1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_directio.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_msgbuf.h" 52 #include "opt_swap.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysproto.h> 57 #include <sys/signalvar.h> 58 #include <sys/kernel.h> 59 #include <sys/linker.h> 60 #include <sys/malloc.h> 61 #include <sys/proc.h> 62 #include <sys/priv.h> 63 #include <sys/buf.h> 64 #include <sys/reboot.h> 65 #include <sys/mbuf.h> 66 #include <sys/msgbuf.h> 67 #include <sys/sysent.h> 68 #include <sys/sysctl.h> 69 #include <sys/vmmeter.h> 70 #include <sys/bus.h> 71 #include <sys/usched.h> 72 #include <sys/reg.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <sys/lock.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_page.h> 80 #include <vm/vm_map.h> 81 #include <vm/vm_pager.h> 82 #include <vm/vm_extern.h> 83 84 #include <sys/thread2.h> 85 #include <sys/mplock2.h> 86 #include <sys/mutex2.h> 87 88 #include <sys/user.h> 89 #include <sys/exec.h> 90 #include <sys/cons.h> 91 92 #include <ddb/ddb.h> 93 94 #include <machine/cpu.h> 95 #include <machine/clock.h> 96 #include <machine/specialreg.h> 97 #if JG 98 #include <machine/bootinfo.h> 99 #endif 100 #include <machine/md_var.h> 101 #include <machine/metadata.h> 102 #include <machine/pc/bios.h> 103 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 104 #include <machine/globaldata.h> /* CPU_prvspace */ 105 #include <machine/smp.h> 106 #ifdef PERFMON 107 #include <machine/perfmon.h> 108 #endif 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 112 #ifdef OLD_BUS_ARCH 113 #include <bus/isa/isa_device.h> 114 #endif 115 #include <machine_base/isa/isa_intr.h> 116 #include <bus/isa/rtc.h> 117 #include <sys/random.h> 118 #include <sys/ptrace.h> 119 #include <machine/sigframe.h> 120 121 #include <sys/machintr.h> 122 #include <machine_base/icu/icu_abi.h> 123 #include <machine_base/icu/elcr_var.h> 124 #include <machine_base/apic/lapic.h> 125 #include <machine_base/apic/ioapic.h> 126 #include <machine_base/apic/ioapic_abi.h> 127 #include <machine/mptable.h> 128 129 #define PHYSMAP_ENTRIES 10 130 131 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 132 133 extern void printcpuinfo(void); /* XXX header file */ 134 extern void identify_cpu(void); 135 #if JG 136 extern void finishidentcpu(void); 137 #endif 138 extern void panicifcpuunsupported(void); 139 140 static void cpu_startup(void *); 141 static void pic_finish(void *); 142 static void cpu_finish(void *); 143 144 #ifndef CPU_DISABLE_SSE 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 #endif /* CPU_DISABLE_SSE */ 148 #ifdef DIRECTIO 149 extern void ffs_rawread_setup(void); 150 #endif /* DIRECTIO */ 151 static void init_locks(void); 152 153 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL) 154 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL) 155 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL) 156 157 #ifdef DDB 158 extern vm_offset_t ksym_start, ksym_end; 159 #endif 160 161 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */ 162 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 int cpu_mwait_halt; 167 168 #if defined(SWTCH_OPTIM_STATS) 169 extern int swtch_optim_stats; 170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 171 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 173 CTLFLAG_RD, &tlb_flush_count, 0, ""); 174 #endif 175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 176 CTLFLAG_RW, &cpu_mwait_halt, 0, ""); 177 178 long physmem = 0; 179 180 u_long ebda_addr = 0; 181 182 int imcr_present = 0; 183 184 int naps = 0; /* # of Applications processors */ 185 186 u_int base_memory; 187 struct mtx dt_lock; /* lock for GDT and LDT */ 188 189 static int 190 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 191 { 192 u_long pmem = ctob(physmem); 193 194 int error = sysctl_handle_long(oidp, &pmem, 0, req); 195 return (error); 196 } 197 198 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 199 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 200 201 static int 202 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 203 { 204 int error = sysctl_handle_int(oidp, 0, 205 ctob(physmem - vmstats.v_wire_count), req); 206 return (error); 207 } 208 209 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 210 0, 0, sysctl_hw_usermem, "IU", ""); 211 212 static int 213 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 214 { 215 int error = sysctl_handle_int(oidp, 0, 216 x86_64_btop(avail_end - avail_start), req); 217 return (error); 218 } 219 220 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 221 0, 0, sysctl_hw_availpages, "I", ""); 222 223 vm_paddr_t Maxmem; 224 vm_paddr_t Realmem; 225 226 /* 227 * The number of PHYSMAP entries must be one less than the number of 228 * PHYSSEG entries because the PHYSMAP entry that spans the largest 229 * physical address that is accessible by ISA DMA is split into two 230 * PHYSSEG entries. 231 */ 232 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 233 234 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 235 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 236 237 /* must be 2 less so 0 0 can signal end of chunks */ 238 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2) 239 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2) 240 241 static vm_offset_t buffer_sva, buffer_eva; 242 vm_offset_t clean_sva, clean_eva; 243 static vm_offset_t pager_sva, pager_eva; 244 static struct trapframe proc0_tf; 245 246 static void 247 cpu_startup(void *dummy) 248 { 249 caddr_t v; 250 vm_size_t size = 0; 251 vm_offset_t firstaddr; 252 253 /* 254 * Good {morning,afternoon,evening,night}. 255 */ 256 kprintf("%s", version); 257 startrtclock(); 258 printcpuinfo(); 259 panicifcpuunsupported(); 260 #ifdef PERFMON 261 perfmon_init(); 262 #endif 263 kprintf("real memory = %ju (%ju MB)\n", 264 (intmax_t)Realmem, 265 (intmax_t)Realmem / 1024 / 1024); 266 /* 267 * Display any holes after the first chunk of extended memory. 268 */ 269 if (bootverbose) { 270 int indx; 271 272 kprintf("Physical memory chunk(s):\n"); 273 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 274 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx]; 275 276 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 277 (intmax_t)phys_avail[indx], 278 (intmax_t)phys_avail[indx + 1] - 1, 279 (intmax_t)size1, 280 (intmax_t)(size1 / PAGE_SIZE)); 281 } 282 } 283 284 /* 285 * Allocate space for system data structures. 286 * The first available kernel virtual address is in "v". 287 * As pages of kernel virtual memory are allocated, "v" is incremented. 288 * As pages of memory are allocated and cleared, 289 * "firstaddr" is incremented. 290 * An index into the kernel page table corresponding to the 291 * virtual memory address maintained in "v" is kept in "mapaddr". 292 */ 293 294 /* 295 * Make two passes. The first pass calculates how much memory is 296 * needed and allocates it. The second pass assigns virtual 297 * addresses to the various data structures. 298 */ 299 firstaddr = 0; 300 again: 301 v = (caddr_t)firstaddr; 302 303 #define valloc(name, type, num) \ 304 (name) = (type *)v; v = (caddr_t)((name)+(num)) 305 #define valloclim(name, type, num, lim) \ 306 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 307 308 /* 309 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE. 310 * For the first 64MB of ram nominally allocate sufficient buffers to 311 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 312 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 313 * the buffer cache we limit the eventual kva reservation to 314 * maxbcache bytes. 315 * 316 * factor represents the 1/4 x ram conversion. 317 */ 318 if (nbuf == 0) { 319 long factor = 4 * BKVASIZE / 1024; 320 long kbytes = physmem * (PAGE_SIZE / 1024); 321 322 nbuf = 50; 323 if (kbytes > 4096) 324 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 325 if (kbytes > 65536) 326 nbuf += (kbytes - 65536) * 2 / (factor * 5); 327 if (maxbcache && nbuf > maxbcache / BKVASIZE) 328 nbuf = maxbcache / BKVASIZE; 329 } 330 331 /* 332 * Do not allow the buffer_map to be more then 1/2 the size of the 333 * kernel_map. 334 */ 335 if (nbuf > (virtual_end - virtual_start + 336 virtual2_end - virtual2_start) / (BKVASIZE * 2)) { 337 nbuf = (virtual_end - virtual_start + 338 virtual2_end - virtual2_start) / (BKVASIZE * 2); 339 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 340 } 341 342 /* 343 * Do not allow the buffer_map to use more than 50% of available 344 * physical-equivalent memory. Since the VM pages which back 345 * individual buffers are typically wired, having too many bufs 346 * can prevent the system from paging properly. 347 */ 348 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) { 349 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2); 350 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 351 } 352 353 /* 354 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 355 * the valloc space which is just the virtual_end - virtual_start 356 * section. We use valloc() to allocate the buf header array. 357 */ 358 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 359 nbuf = (virtual_end - virtual_start) / 360 sizeof(struct buf) / 2; 361 kprintf("Warning: nbufs capped at %ld due to valloc " 362 "considerations", nbuf); 363 } 364 365 nswbuf = lmax(lmin(nbuf / 4, 256), 16); 366 #ifdef NSWBUF_MIN 367 if (nswbuf < NSWBUF_MIN) 368 nswbuf = NSWBUF_MIN; 369 #endif 370 #ifdef DIRECTIO 371 ffs_rawread_setup(); 372 #endif 373 374 valloc(swbuf, struct buf, nswbuf); 375 valloc(buf, struct buf, nbuf); 376 377 /* 378 * End of first pass, size has been calculated so allocate memory 379 */ 380 if (firstaddr == 0) { 381 size = (vm_size_t)(v - firstaddr); 382 firstaddr = kmem_alloc(&kernel_map, round_page(size)); 383 if (firstaddr == 0) 384 panic("startup: no room for tables"); 385 goto again; 386 } 387 388 /* 389 * End of second pass, addresses have been assigned 390 * 391 * nbuf is an int, make sure we don't overflow the field. 392 * 393 * On 64-bit systems we always reserve maximal allocations for 394 * buffer cache buffers and there are no fragmentation issues, 395 * so the KVA segment does not have to be excessively oversized. 396 */ 397 if ((vm_size_t)(v - firstaddr) != size) 398 panic("startup: table size inconsistency"); 399 400 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 401 ((vm_offset_t)(nbuf + 16) * BKVASIZE) + 402 (nswbuf * MAXPHYS) + pager_map_size); 403 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 404 ((vm_offset_t)(nbuf + 16) * BKVASIZE)); 405 buffer_map.system_map = 1; 406 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 407 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size); 408 pager_map.system_map = 1; 409 410 #if defined(USERCONFIG) 411 userconfig(); 412 cninit(); /* the preferred console may have changed */ 413 #endif 414 415 kprintf("avail memory = %ju (%ju MB)\n", 416 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 417 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 418 1024 / 1024); 419 } 420 421 static void 422 cpu_finish(void *dummy __unused) 423 { 424 cpu_setregs(); 425 } 426 427 static void 428 pic_finish(void *dummy __unused) 429 { 430 /* Log ELCR information */ 431 elcr_dump(); 432 433 /* Log MPTABLE information */ 434 mptable_pci_int_dump(); 435 436 /* Finalize PCI */ 437 MachIntrABI.finalize(); 438 } 439 440 /* 441 * Send an interrupt to process. 442 * 443 * Stack is set up to allow sigcode stored 444 * at top to call routine, followed by kcall 445 * to sigreturn routine below. After sigreturn 446 * resets the signal mask, the stack, and the 447 * frame pointer, it returns to the user 448 * specified pc, psl. 449 */ 450 void 451 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 452 { 453 struct lwp *lp = curthread->td_lwp; 454 struct proc *p = lp->lwp_proc; 455 struct trapframe *regs; 456 struct sigacts *psp = p->p_sigacts; 457 struct sigframe sf, *sfp; 458 int oonstack; 459 char *sp; 460 461 regs = lp->lwp_md.md_regs; 462 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 463 464 /* Save user context */ 465 bzero(&sf, sizeof(struct sigframe)); 466 sf.sf_uc.uc_sigmask = *mask; 467 sf.sf_uc.uc_stack = lp->lwp_sigstk; 468 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 469 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 470 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 471 472 /* Make the size of the saved context visible to userland */ 473 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 474 475 /* Allocate and validate space for the signal handler context. */ 476 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 477 SIGISMEMBER(psp->ps_sigonstack, sig)) { 478 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 479 sizeof(struct sigframe)); 480 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 481 } else { 482 /* We take red zone into account */ 483 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 484 } 485 486 /* 487 * XXX AVX needs 64-byte alignment but sigframe has other fields and 488 * the embedded ucontext is not at the front, so aligning this won't 489 * help us. Fortunately we bcopy in/out of the sigframe, so the 490 * kernel is ok. 491 * 492 * The problem though is if userland winds up trying to use the 493 * context directly. 494 */ 495 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 496 497 /* Translate the signal is appropriate */ 498 if (p->p_sysent->sv_sigtbl) { 499 if (sig <= p->p_sysent->sv_sigsize) 500 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 501 } 502 503 /* 504 * Build the argument list for the signal handler. 505 * 506 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 507 */ 508 regs->tf_rdi = sig; /* argument 1 */ 509 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 510 511 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 512 /* 513 * Signal handler installed with SA_SIGINFO. 514 * 515 * action(signo, siginfo, ucontext) 516 */ 517 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 518 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 519 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 520 521 /* fill siginfo structure */ 522 sf.sf_si.si_signo = sig; 523 sf.sf_si.si_code = code; 524 sf.sf_si.si_addr = (void *)regs->tf_addr; 525 } else { 526 /* 527 * Old FreeBSD-style arguments. 528 * 529 * handler (signo, code, [uc], addr) 530 */ 531 regs->tf_rsi = (register_t)code; /* argument 2 */ 532 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 533 sf.sf_ahu.sf_handler = catcher; 534 } 535 536 /* 537 * If we're a vm86 process, we want to save the segment registers. 538 * We also change eflags to be our emulated eflags, not the actual 539 * eflags. 540 */ 541 #if JG 542 if (regs->tf_eflags & PSL_VM) { 543 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 544 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 545 546 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 547 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 548 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 549 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 550 551 if (vm86->vm86_has_vme == 0) 552 sf.sf_uc.uc_mcontext.mc_eflags = 553 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 554 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 555 556 /* 557 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 558 * syscalls made by the signal handler. This just avoids 559 * wasting time for our lazy fixup of such faults. PSL_NT 560 * does nothing in vm86 mode, but vm86 programs can set it 561 * almost legitimately in probes for old cpu types. 562 */ 563 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 564 } 565 #endif 566 567 /* 568 * Save the FPU state and reinit the FP unit 569 */ 570 npxpush(&sf.sf_uc.uc_mcontext); 571 572 /* 573 * Copy the sigframe out to the user's stack. 574 */ 575 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 576 /* 577 * Something is wrong with the stack pointer. 578 * ...Kill the process. 579 */ 580 sigexit(lp, SIGILL); 581 } 582 583 regs->tf_rsp = (register_t)sfp; 584 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 585 586 /* 587 * i386 abi specifies that the direction flag must be cleared 588 * on function entry 589 */ 590 regs->tf_rflags &= ~(PSL_T|PSL_D); 591 592 /* 593 * 64 bit mode has a code and stack selector but 594 * no data or extra selector. %fs and %gs are not 595 * stored in-context. 596 */ 597 regs->tf_cs = _ucodesel; 598 regs->tf_ss = _udatasel; 599 clear_quickret(); 600 } 601 602 /* 603 * Sanitize the trapframe for a virtual kernel passing control to a custom 604 * VM context. Remove any items that would otherwise create a privilage 605 * issue. 606 * 607 * XXX at the moment we allow userland to set the resume flag. Is this a 608 * bad idea? 609 */ 610 int 611 cpu_sanitize_frame(struct trapframe *frame) 612 { 613 frame->tf_cs = _ucodesel; 614 frame->tf_ss = _udatasel; 615 /* XXX VM (8086) mode not supported? */ 616 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 617 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 618 619 return(0); 620 } 621 622 /* 623 * Sanitize the tls so loading the descriptor does not blow up 624 * on us. For x86_64 we don't have to do anything. 625 */ 626 int 627 cpu_sanitize_tls(struct savetls *tls) 628 { 629 return(0); 630 } 631 632 /* 633 * sigreturn(ucontext_t *sigcntxp) 634 * 635 * System call to cleanup state after a signal 636 * has been taken. Reset signal mask and 637 * stack state from context left by sendsig (above). 638 * Return to previous pc and psl as specified by 639 * context left by sendsig. Check carefully to 640 * make sure that the user has not modified the 641 * state to gain improper privileges. 642 * 643 * MPSAFE 644 */ 645 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 646 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 647 648 int 649 sys_sigreturn(struct sigreturn_args *uap) 650 { 651 struct lwp *lp = curthread->td_lwp; 652 struct trapframe *regs; 653 ucontext_t uc; 654 ucontext_t *ucp; 655 register_t rflags; 656 int cs; 657 int error; 658 659 /* 660 * We have to copy the information into kernel space so userland 661 * can't modify it while we are sniffing it. 662 */ 663 regs = lp->lwp_md.md_regs; 664 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 665 if (error) 666 return (error); 667 ucp = &uc; 668 rflags = ucp->uc_mcontext.mc_rflags; 669 670 /* VM (8086) mode not supported */ 671 rflags &= ~PSL_VM_UNSUPP; 672 673 #if JG 674 if (eflags & PSL_VM) { 675 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 676 struct vm86_kernel *vm86; 677 678 /* 679 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 680 * set up the vm86 area, and we can't enter vm86 mode. 681 */ 682 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 683 return (EINVAL); 684 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 685 if (vm86->vm86_inited == 0) 686 return (EINVAL); 687 688 /* go back to user mode if both flags are set */ 689 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 690 trapsignal(lp, SIGBUS, 0); 691 692 if (vm86->vm86_has_vme) { 693 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 694 (eflags & VME_USERCHANGE) | PSL_VM; 695 } else { 696 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 697 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 698 (eflags & VM_USERCHANGE) | PSL_VM; 699 } 700 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 701 tf->tf_eflags = eflags; 702 tf->tf_vm86_ds = tf->tf_ds; 703 tf->tf_vm86_es = tf->tf_es; 704 tf->tf_vm86_fs = tf->tf_fs; 705 tf->tf_vm86_gs = tf->tf_gs; 706 tf->tf_ds = _udatasel; 707 tf->tf_es = _udatasel; 708 tf->tf_fs = _udatasel; 709 tf->tf_gs = _udatasel; 710 } else 711 #endif 712 { 713 /* 714 * Don't allow users to change privileged or reserved flags. 715 */ 716 /* 717 * XXX do allow users to change the privileged flag PSL_RF. 718 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 719 * should sometimes set it there too. tf_eflags is kept in 720 * the signal context during signal handling and there is no 721 * other place to remember it, so the PSL_RF bit may be 722 * corrupted by the signal handler without us knowing. 723 * Corruption of the PSL_RF bit at worst causes one more or 724 * one less debugger trap, so allowing it is fairly harmless. 725 */ 726 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 727 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 728 return(EINVAL); 729 } 730 731 /* 732 * Don't allow users to load a valid privileged %cs. Let the 733 * hardware check for invalid selectors, excess privilege in 734 * other selectors, invalid %eip's and invalid %esp's. 735 */ 736 cs = ucp->uc_mcontext.mc_cs; 737 if (!CS_SECURE(cs)) { 738 kprintf("sigreturn: cs = 0x%x\n", cs); 739 trapsignal(lp, SIGBUS, T_PROTFLT); 740 return(EINVAL); 741 } 742 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 743 } 744 745 /* 746 * Restore the FPU state from the frame 747 */ 748 crit_enter(); 749 npxpop(&ucp->uc_mcontext); 750 751 if (ucp->uc_mcontext.mc_onstack & 1) 752 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 753 else 754 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 755 756 lp->lwp_sigmask = ucp->uc_sigmask; 757 SIG_CANTMASK(lp->lwp_sigmask); 758 clear_quickret(); 759 crit_exit(); 760 return(EJUSTRETURN); 761 } 762 763 /* 764 * Machine dependent boot() routine 765 * 766 * I haven't seen anything to put here yet 767 * Possibly some stuff might be grafted back here from boot() 768 */ 769 void 770 cpu_boot(int howto) 771 { 772 } 773 774 /* 775 * Shutdown the CPU as much as possible 776 */ 777 void 778 cpu_halt(void) 779 { 780 for (;;) 781 __asm__ __volatile("hlt"); 782 } 783 784 /* 785 * cpu_idle() represents the idle LWKT. You cannot return from this function 786 * (unless you want to blow things up!). Instead we look for runnable threads 787 * and loop or halt as appropriate. Giant is not held on entry to the thread. 788 * 789 * The main loop is entered with a critical section held, we must release 790 * the critical section before doing anything else. lwkt_switch() will 791 * check for pending interrupts due to entering and exiting its own 792 * critical section. 793 * 794 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 795 * However, there are cases where the idlethread will be entered with 796 * the possibility that no IPI will occur and in such cases 797 * lwkt_switch() sets TDF_IDLE_NOHLT. 798 * 799 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to 800 * 1 to just use hlt and for debugging purposes. 801 * 802 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 803 * must occur before it starts using ACPI halt. 804 */ 805 static int cpu_idle_hlt = 2; 806 static int cpu_idle_hltcnt; 807 static int cpu_idle_spincnt; 808 static u_int cpu_idle_repeat = 750; 809 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 810 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 811 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW, 812 &cpu_idle_hltcnt, 0, "Idle loop entry halts"); 813 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW, 814 &cpu_idle_spincnt, 0, "Idle loop entry spins"); 815 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 816 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 817 818 static void 819 cpu_idle_default_hook(void) 820 { 821 /* 822 * We must guarentee that hlt is exactly the instruction 823 * following the sti. 824 */ 825 __asm __volatile("sti; hlt"); 826 } 827 828 /* Other subsystems (e.g., ACPI) can hook this later. */ 829 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 830 831 void 832 cpu_idle(void) 833 { 834 globaldata_t gd = mycpu; 835 struct thread *td __debugvar = gd->gd_curthread; 836 int reqflags; 837 int quick; 838 839 crit_exit(); 840 KKASSERT(td->td_critcount == 0); 841 for (;;) { 842 /* 843 * See if there are any LWKTs ready to go. 844 */ 845 lwkt_switch(); 846 847 /* 848 * When halting inside a cli we must check for reqflags 849 * races, particularly [re]schedule requests. Running 850 * splz() does the job. 851 * 852 * cpu_idle_hlt: 853 * 0 Never halt, just spin 854 * 855 * 1 Always use HLT (or MONITOR/MWAIT if avail). 856 * This typically eats more power than the 857 * ACPI halt. 858 * 859 * 2 Use HLT/MONITOR/MWAIT up to a point and then 860 * use the ACPI halt (default). This is a hybrid 861 * approach. See machdep.cpu_idle_repeat. 862 * 863 * 3 Always use the ACPI halt. This typically 864 * eats the least amount of power but the cpu 865 * will be slow waking up. Slows down e.g. 866 * compiles and other pipe/event oriented stuff. 867 * 868 * NOTE: Interrupts are enabled and we are not in a critical 869 * section. 870 * 871 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 872 * don't bother capping gd_idle_repeat, it is ok if 873 * it overflows. 874 */ 875 ++gd->gd_idle_repeat; 876 reqflags = gd->gd_reqflags; 877 quick = (cpu_idle_hlt == 1) || 878 (cpu_idle_hlt < 3 && 879 gd->gd_idle_repeat < cpu_idle_repeat); 880 881 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 882 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 883 splz(); /* XXX */ 884 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 885 cpu_mwait_halt); 886 ++cpu_idle_hltcnt; 887 } else if (cpu_idle_hlt) { 888 __asm __volatile("cli"); 889 splz(); 890 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 891 if (quick) 892 cpu_idle_default_hook(); 893 else 894 cpu_idle_hook(); 895 } 896 __asm __volatile("sti"); 897 ++cpu_idle_hltcnt; 898 } else { 899 splz(); 900 __asm __volatile("sti"); 901 ++cpu_idle_spincnt; 902 } 903 } 904 } 905 906 /* 907 * This routine is called if a spinlock has been held through the 908 * exponential backoff period and is seriously contested. On a real cpu 909 * we let it spin. 910 */ 911 void 912 cpu_spinlock_contested(void) 913 { 914 cpu_pause(); 915 } 916 917 /* 918 * Clear registers on exec 919 */ 920 void 921 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 922 { 923 struct thread *td = curthread; 924 struct lwp *lp = td->td_lwp; 925 struct pcb *pcb = td->td_pcb; 926 struct trapframe *regs = lp->lwp_md.md_regs; 927 928 /* was i386_user_cleanup() in NetBSD */ 929 user_ldt_free(pcb); 930 931 clear_quickret(); 932 bzero((char *)regs, sizeof(struct trapframe)); 933 regs->tf_rip = entry; 934 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 935 regs->tf_rdi = stack; /* argv */ 936 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 937 regs->tf_ss = _udatasel; 938 regs->tf_cs = _ucodesel; 939 regs->tf_rbx = ps_strings; 940 941 /* 942 * Reset the hardware debug registers if they were in use. 943 * They won't have any meaning for the newly exec'd process. 944 */ 945 if (pcb->pcb_flags & PCB_DBREGS) { 946 pcb->pcb_dr0 = 0; 947 pcb->pcb_dr1 = 0; 948 pcb->pcb_dr2 = 0; 949 pcb->pcb_dr3 = 0; 950 pcb->pcb_dr6 = 0; 951 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 952 if (pcb == td->td_pcb) { 953 /* 954 * Clear the debug registers on the running 955 * CPU, otherwise they will end up affecting 956 * the next process we switch to. 957 */ 958 reset_dbregs(); 959 } 960 pcb->pcb_flags &= ~PCB_DBREGS; 961 } 962 963 /* 964 * Initialize the math emulator (if any) for the current process. 965 * Actually, just clear the bit that says that the emulator has 966 * been initialized. Initialization is delayed until the process 967 * traps to the emulator (if it is done at all) mainly because 968 * emulators don't provide an entry point for initialization. 969 */ 970 pcb->pcb_flags &= ~FP_SOFTFP; 971 972 /* 973 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 974 * gd_npxthread. Otherwise a preemptive interrupt thread 975 * may panic in npxdna(). 976 */ 977 crit_enter(); 978 load_cr0(rcr0() | CR0_MP); 979 980 /* 981 * NOTE: The MSR values must be correct so we can return to 982 * userland. gd_user_fs/gs must be correct so the switch 983 * code knows what the current MSR values are. 984 */ 985 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 986 pcb->pcb_gsbase = 0; 987 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 988 mdcpu->gd_user_gs = 0; 989 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 990 wrmsr(MSR_KGSBASE, 0); 991 992 /* Initialize the npx (if any) for the current process. */ 993 npxinit(__INITIAL_FPUCW__); 994 crit_exit(); 995 996 pcb->pcb_ds = _udatasel; 997 pcb->pcb_es = _udatasel; 998 pcb->pcb_fs = _udatasel; 999 pcb->pcb_gs = _udatasel; 1000 } 1001 1002 void 1003 cpu_setregs(void) 1004 { 1005 register_t cr0; 1006 1007 cr0 = rcr0(); 1008 cr0 |= CR0_NE; /* Done by npxinit() */ 1009 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1010 cr0 |= CR0_WP | CR0_AM; 1011 load_cr0(cr0); 1012 load_gs(_udatasel); 1013 } 1014 1015 static int 1016 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1017 { 1018 int error; 1019 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1020 req); 1021 if (!error && req->newptr) 1022 resettodr(); 1023 return (error); 1024 } 1025 1026 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1027 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1028 1029 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1030 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1031 1032 #if JG 1033 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1034 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1035 #endif 1036 1037 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1038 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1039 1040 extern u_long bootdev; /* not a cdev_t - encoding is different */ 1041 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, 1042 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)"); 1043 1044 /* 1045 * Initialize 386 and configure to run kernel 1046 */ 1047 1048 /* 1049 * Initialize segments & interrupt table 1050 */ 1051 1052 int _default_ldt; 1053 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1054 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1055 #if JG 1056 union descriptor ldt[NLDT]; /* local descriptor table */ 1057 #endif 1058 1059 /* table descriptors - used to load tables by cpu */ 1060 struct region_descriptor r_gdt; 1061 struct region_descriptor r_idt_arr[MAXCPU]; 1062 1063 /* JG proc0paddr is a virtual address */ 1064 void *proc0paddr; 1065 /* JG alignment? */ 1066 char proc0paddr_buff[LWKT_THREAD_STACK]; 1067 1068 1069 /* software prototypes -- in more palatable form */ 1070 struct soft_segment_descriptor gdt_segs[] = { 1071 /* GNULL_SEL 0 Null Descriptor */ 1072 { 0x0, /* segment base address */ 1073 0x0, /* length */ 1074 0, /* segment type */ 1075 0, /* segment descriptor priority level */ 1076 0, /* segment descriptor present */ 1077 0, /* long */ 1078 0, /* default 32 vs 16 bit size */ 1079 0 /* limit granularity (byte/page units)*/ }, 1080 /* GCODE_SEL 1 Code Descriptor for kernel */ 1081 { 0x0, /* segment base address */ 1082 0xfffff, /* length - all address space */ 1083 SDT_MEMERA, /* segment type */ 1084 SEL_KPL, /* segment descriptor priority level */ 1085 1, /* segment descriptor present */ 1086 1, /* long */ 1087 0, /* default 32 vs 16 bit size */ 1088 1 /* limit granularity (byte/page units)*/ }, 1089 /* GDATA_SEL 2 Data Descriptor for kernel */ 1090 { 0x0, /* segment base address */ 1091 0xfffff, /* length - all address space */ 1092 SDT_MEMRWA, /* segment type */ 1093 SEL_KPL, /* segment descriptor priority level */ 1094 1, /* segment descriptor present */ 1095 1, /* long */ 1096 0, /* default 32 vs 16 bit size */ 1097 1 /* limit granularity (byte/page units)*/ }, 1098 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1099 { 0x0, /* segment base address */ 1100 0xfffff, /* length - all address space */ 1101 SDT_MEMERA, /* segment type */ 1102 SEL_UPL, /* segment descriptor priority level */ 1103 1, /* segment descriptor present */ 1104 0, /* long */ 1105 1, /* default 32 vs 16 bit size */ 1106 1 /* limit granularity (byte/page units)*/ }, 1107 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1108 { 0x0, /* segment base address */ 1109 0xfffff, /* length - all address space */ 1110 SDT_MEMRWA, /* segment type */ 1111 SEL_UPL, /* segment descriptor priority level */ 1112 1, /* segment descriptor present */ 1113 0, /* long */ 1114 1, /* default 32 vs 16 bit size */ 1115 1 /* limit granularity (byte/page units)*/ }, 1116 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1117 { 0x0, /* segment base address */ 1118 0xfffff, /* length - all address space */ 1119 SDT_MEMERA, /* segment type */ 1120 SEL_UPL, /* segment descriptor priority level */ 1121 1, /* segment descriptor present */ 1122 1, /* long */ 1123 0, /* default 32 vs 16 bit size */ 1124 1 /* limit granularity (byte/page units)*/ }, 1125 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1126 { 1127 0x0, /* segment base address */ 1128 sizeof(struct x86_64tss)-1,/* length - all address space */ 1129 SDT_SYSTSS, /* segment type */ 1130 SEL_KPL, /* segment descriptor priority level */ 1131 1, /* segment descriptor present */ 1132 0, /* long */ 1133 0, /* unused - default 32 vs 16 bit size */ 1134 0 /* limit granularity (byte/page units)*/ }, 1135 /* Actually, the TSS is a system descriptor which is double size */ 1136 { 0x0, /* segment base address */ 1137 0x0, /* length */ 1138 0, /* segment type */ 1139 0, /* segment descriptor priority level */ 1140 0, /* segment descriptor present */ 1141 0, /* long */ 1142 0, /* default 32 vs 16 bit size */ 1143 0 /* limit granularity (byte/page units)*/ }, 1144 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1145 { 0x0, /* segment base address */ 1146 0xfffff, /* length - all address space */ 1147 SDT_MEMRWA, /* segment type */ 1148 SEL_UPL, /* segment descriptor priority level */ 1149 1, /* segment descriptor present */ 1150 0, /* long */ 1151 1, /* default 32 vs 16 bit size */ 1152 1 /* limit granularity (byte/page units)*/ }, 1153 }; 1154 1155 void 1156 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1157 { 1158 int cpu; 1159 1160 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1161 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1162 1163 ip->gd_looffset = (uintptr_t)func; 1164 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1165 ip->gd_ist = ist; 1166 ip->gd_xx = 0; 1167 ip->gd_type = typ; 1168 ip->gd_dpl = dpl; 1169 ip->gd_p = 1; 1170 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1171 } 1172 } 1173 1174 void 1175 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1176 { 1177 struct gate_descriptor *ip; 1178 1179 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1180 1181 ip = &idt_arr[cpu][idx]; 1182 ip->gd_looffset = (uintptr_t)func; 1183 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1184 ip->gd_ist = ist; 1185 ip->gd_xx = 0; 1186 ip->gd_type = typ; 1187 ip->gd_dpl = dpl; 1188 ip->gd_p = 1; 1189 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1190 } 1191 1192 #define IDTVEC(name) __CONCAT(X,name) 1193 1194 extern inthand_t 1195 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1196 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1197 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1198 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1199 IDTVEC(xmm), IDTVEC(dblfault), 1200 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1201 1202 #ifdef DEBUG_INTERRUPTS 1203 extern inthand_t *Xrsvdary[256]; 1204 #endif 1205 1206 void 1207 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1208 { 1209 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1210 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1211 ssd->ssd_type = sd->sd_type; 1212 ssd->ssd_dpl = sd->sd_dpl; 1213 ssd->ssd_p = sd->sd_p; 1214 ssd->ssd_def32 = sd->sd_def32; 1215 ssd->ssd_gran = sd->sd_gran; 1216 } 1217 1218 void 1219 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1220 { 1221 1222 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1223 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1224 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1225 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1226 sd->sd_type = ssd->ssd_type; 1227 sd->sd_dpl = ssd->ssd_dpl; 1228 sd->sd_p = ssd->ssd_p; 1229 sd->sd_long = ssd->ssd_long; 1230 sd->sd_def32 = ssd->ssd_def32; 1231 sd->sd_gran = ssd->ssd_gran; 1232 } 1233 1234 void 1235 ssdtosyssd(struct soft_segment_descriptor *ssd, 1236 struct system_segment_descriptor *sd) 1237 { 1238 1239 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1240 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1241 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1242 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1243 sd->sd_type = ssd->ssd_type; 1244 sd->sd_dpl = ssd->ssd_dpl; 1245 sd->sd_p = ssd->ssd_p; 1246 sd->sd_gran = ssd->ssd_gran; 1247 } 1248 1249 /* 1250 * Populate the (physmap) array with base/bound pairs describing the 1251 * available physical memory in the system, then test this memory and 1252 * build the phys_avail array describing the actually-available memory. 1253 * 1254 * If we cannot accurately determine the physical memory map, then use 1255 * value from the 0xE801 call, and failing that, the RTC. 1256 * 1257 * Total memory size may be set by the kernel environment variable 1258 * hw.physmem or the compile-time define MAXMEM. 1259 * 1260 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1261 * of PAGE_SIZE. This also greatly reduces the memory test time 1262 * which would otherwise be excessive on machines with > 8G of ram. 1263 * 1264 * XXX first should be vm_paddr_t. 1265 */ 1266 1267 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1268 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1269 1270 static void 1271 getmemsize(caddr_t kmdp, u_int64_t first) 1272 { 1273 int off, physmap_idx, pa_indx, da_indx; 1274 int i, j; 1275 vm_paddr_t physmap[PHYSMAP_SIZE]; 1276 vm_paddr_t pa; 1277 vm_paddr_t msgbuf_size; 1278 u_long physmem_tunable; 1279 pt_entry_t *pte; 1280 struct bios_smap *smapbase, *smap, *smapend; 1281 u_int32_t smapsize; 1282 quad_t dcons_addr, dcons_size; 1283 1284 bzero(physmap, sizeof(physmap)); 1285 physmap_idx = 0; 1286 1287 /* 1288 * get memory map from INT 15:E820, kindly supplied by the loader. 1289 * 1290 * subr_module.c says: 1291 * "Consumer may safely assume that size value precedes data." 1292 * ie: an int32_t immediately precedes smap. 1293 */ 1294 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1295 MODINFO_METADATA | MODINFOMD_SMAP); 1296 if (smapbase == NULL) 1297 panic("No BIOS smap info from loader!"); 1298 1299 smapsize = *((u_int32_t *)smapbase - 1); 1300 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1301 1302 for (smap = smapbase; smap < smapend; smap++) { 1303 if (boothowto & RB_VERBOSE) 1304 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1305 smap->type, smap->base, smap->length); 1306 1307 if (smap->type != SMAP_TYPE_MEMORY) 1308 continue; 1309 1310 if (smap->length == 0) 1311 continue; 1312 1313 for (i = 0; i <= physmap_idx; i += 2) { 1314 if (smap->base < physmap[i + 1]) { 1315 if (boothowto & RB_VERBOSE) { 1316 kprintf("Overlapping or non-monotonic " 1317 "memory region, ignoring " 1318 "second region\n"); 1319 } 1320 break; 1321 } 1322 } 1323 if (i <= physmap_idx) 1324 continue; 1325 1326 Realmem += smap->length; 1327 1328 if (smap->base == physmap[physmap_idx + 1]) { 1329 physmap[physmap_idx + 1] += smap->length; 1330 continue; 1331 } 1332 1333 physmap_idx += 2; 1334 if (physmap_idx == PHYSMAP_SIZE) { 1335 kprintf("Too many segments in the physical " 1336 "address map, giving up\n"); 1337 break; 1338 } 1339 physmap[physmap_idx] = smap->base; 1340 physmap[physmap_idx + 1] = smap->base + smap->length; 1341 } 1342 1343 base_memory = physmap[1] / 1024; 1344 /* make hole for AP bootstrap code */ 1345 physmap[1] = mp_bootaddress(base_memory); 1346 1347 /* Save EBDA address, if any */ 1348 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1349 ebda_addr <<= 4; 1350 1351 /* 1352 * Maxmem isn't the "maximum memory", it's one larger than the 1353 * highest page of the physical address space. It should be 1354 * called something like "Maxphyspage". We may adjust this 1355 * based on ``hw.physmem'' and the results of the memory test. 1356 */ 1357 Maxmem = atop(physmap[physmap_idx + 1]); 1358 1359 #ifdef MAXMEM 1360 Maxmem = MAXMEM / 4; 1361 #endif 1362 1363 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1364 Maxmem = atop(physmem_tunable); 1365 1366 /* 1367 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1368 * in the system. 1369 */ 1370 if (Maxmem > atop(physmap[physmap_idx + 1])) 1371 Maxmem = atop(physmap[physmap_idx + 1]); 1372 1373 /* 1374 * Blowing out the DMAP will blow up the system. 1375 */ 1376 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1377 kprintf("Limiting Maxmem due to DMAP size\n"); 1378 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1379 } 1380 1381 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1382 (boothowto & RB_VERBOSE)) { 1383 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1384 } 1385 1386 /* 1387 * Call pmap initialization to make new kernel address space 1388 * 1389 * Mask off page 0. 1390 */ 1391 pmap_bootstrap(&first); 1392 physmap[0] = PAGE_SIZE; 1393 1394 /* 1395 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1396 * exceeding Maxmem. 1397 */ 1398 for (i = j = 0; i <= physmap_idx; i += 2) { 1399 if (physmap[i+1] > ptoa(Maxmem)) 1400 physmap[i+1] = ptoa(Maxmem); 1401 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1402 ~PHYSMAP_ALIGN_MASK; 1403 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1404 1405 physmap[j] = physmap[i]; 1406 physmap[j+1] = physmap[i+1]; 1407 1408 if (physmap[i] < physmap[i+1]) 1409 j += 2; 1410 } 1411 physmap_idx = j - 2; 1412 1413 /* 1414 * Align anything else used in the validation loop. 1415 */ 1416 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1417 1418 /* 1419 * Size up each available chunk of physical memory. 1420 */ 1421 pa_indx = 0; 1422 da_indx = 1; 1423 phys_avail[pa_indx++] = physmap[0]; 1424 phys_avail[pa_indx] = physmap[0]; 1425 dump_avail[da_indx] = physmap[0]; 1426 pte = CMAP1; 1427 1428 /* 1429 * Get dcons buffer address 1430 */ 1431 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 1432 kgetenv_quad("dcons.size", &dcons_size) == 0) 1433 dcons_addr = 0; 1434 1435 /* 1436 * Validate the physical memory. The physical memory segments 1437 * have already been aligned to PHYSMAP_ALIGN which is a multiple 1438 * of PAGE_SIZE. 1439 */ 1440 for (i = 0; i <= physmap_idx; i += 2) { 1441 vm_paddr_t end; 1442 1443 end = physmap[i + 1]; 1444 1445 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) { 1446 int tmp, page_bad, full; 1447 int *ptr = (int *)CADDR1; 1448 1449 full = FALSE; 1450 /* 1451 * block out kernel memory as not available. 1452 */ 1453 if (pa >= 0x200000 && pa < first) 1454 goto do_dump_avail; 1455 1456 /* 1457 * block out dcons buffer 1458 */ 1459 if (dcons_addr > 0 1460 && pa >= trunc_page(dcons_addr) 1461 && pa < dcons_addr + dcons_size) { 1462 goto do_dump_avail; 1463 } 1464 1465 page_bad = FALSE; 1466 1467 /* 1468 * map page into kernel: valid, read/write,non-cacheable 1469 */ 1470 *pte = pa | 1471 kernel_pmap.pmap_bits[PG_V_IDX] | 1472 kernel_pmap.pmap_bits[PG_RW_IDX] | 1473 kernel_pmap.pmap_bits[PG_N_IDX]; 1474 cpu_invltlb(); 1475 1476 tmp = *ptr; 1477 /* 1478 * Test for alternating 1's and 0's 1479 */ 1480 *(volatile int *)ptr = 0xaaaaaaaa; 1481 cpu_mfence(); 1482 if (*(volatile int *)ptr != 0xaaaaaaaa) 1483 page_bad = TRUE; 1484 /* 1485 * Test for alternating 0's and 1's 1486 */ 1487 *(volatile int *)ptr = 0x55555555; 1488 cpu_mfence(); 1489 if (*(volatile int *)ptr != 0x55555555) 1490 page_bad = TRUE; 1491 /* 1492 * Test for all 1's 1493 */ 1494 *(volatile int *)ptr = 0xffffffff; 1495 cpu_mfence(); 1496 if (*(volatile int *)ptr != 0xffffffff) 1497 page_bad = TRUE; 1498 /* 1499 * Test for all 0's 1500 */ 1501 *(volatile int *)ptr = 0x0; 1502 cpu_mfence(); 1503 if (*(volatile int *)ptr != 0x0) 1504 page_bad = TRUE; 1505 /* 1506 * Restore original value. 1507 */ 1508 *ptr = tmp; 1509 1510 /* 1511 * Adjust array of valid/good pages. 1512 */ 1513 if (page_bad == TRUE) 1514 continue; 1515 /* 1516 * If this good page is a continuation of the 1517 * previous set of good pages, then just increase 1518 * the end pointer. Otherwise start a new chunk. 1519 * Note that "end" points one higher than end, 1520 * making the range >= start and < end. 1521 * If we're also doing a speculative memory 1522 * test and we at or past the end, bump up Maxmem 1523 * so that we keep going. The first bad page 1524 * will terminate the loop. 1525 */ 1526 if (phys_avail[pa_indx] == pa) { 1527 phys_avail[pa_indx] += PHYSMAP_ALIGN; 1528 } else { 1529 pa_indx++; 1530 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1531 kprintf( 1532 "Too many holes in the physical address space, giving up\n"); 1533 pa_indx--; 1534 full = TRUE; 1535 goto do_dump_avail; 1536 } 1537 phys_avail[pa_indx++] = pa; 1538 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN; 1539 } 1540 physmem += PHYSMAP_ALIGN / PAGE_SIZE; 1541 do_dump_avail: 1542 if (dump_avail[da_indx] == pa) { 1543 dump_avail[da_indx] += PHYSMAP_ALIGN; 1544 } else { 1545 da_indx++; 1546 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1547 da_indx--; 1548 goto do_next; 1549 } 1550 dump_avail[da_indx++] = pa; 1551 dump_avail[da_indx] = pa + PHYSMAP_ALIGN; 1552 } 1553 do_next: 1554 if (full) 1555 break; 1556 } 1557 } 1558 *pte = 0; 1559 cpu_invltlb(); 1560 1561 /* 1562 * The last chunk must contain at least one page plus the message 1563 * buffer to avoid complicating other code (message buffer address 1564 * calculation, etc.). 1565 */ 1566 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 1567 1568 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN + 1569 msgbuf_size >= phys_avail[pa_indx]) { 1570 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1571 phys_avail[pa_indx--] = 0; 1572 phys_avail[pa_indx--] = 0; 1573 } 1574 1575 Maxmem = atop(phys_avail[pa_indx]); 1576 1577 /* Trim off space for the message buffer. */ 1578 phys_avail[pa_indx] -= msgbuf_size; 1579 1580 avail_end = phys_avail[pa_indx]; 1581 1582 /* Map the message buffer. */ 1583 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 1584 pmap_kenter((vm_offset_t)msgbufp + off, 1585 phys_avail[pa_indx] + off); 1586 } 1587 } 1588 1589 struct machintr_abi MachIntrABI; 1590 1591 /* 1592 * IDT VECTORS: 1593 * 0 Divide by zero 1594 * 1 Debug 1595 * 2 NMI 1596 * 3 BreakPoint 1597 * 4 OverFlow 1598 * 5 Bound-Range 1599 * 6 Invalid OpCode 1600 * 7 Device Not Available (x87) 1601 * 8 Double-Fault 1602 * 9 Coprocessor Segment overrun (unsupported, reserved) 1603 * 10 Invalid-TSS 1604 * 11 Segment not present 1605 * 12 Stack 1606 * 13 General Protection 1607 * 14 Page Fault 1608 * 15 Reserved 1609 * 16 x87 FP Exception pending 1610 * 17 Alignment Check 1611 * 18 Machine Check 1612 * 19 SIMD floating point 1613 * 20-31 reserved 1614 * 32-255 INTn/external sources 1615 */ 1616 u_int64_t 1617 hammer_time(u_int64_t modulep, u_int64_t physfree) 1618 { 1619 caddr_t kmdp; 1620 int gsel_tss, x, cpu; 1621 #if JG 1622 int metadata_missing, off; 1623 #endif 1624 struct mdglobaldata *gd; 1625 u_int64_t msr; 1626 1627 /* 1628 * Prevent lowering of the ipl if we call tsleep() early. 1629 */ 1630 gd = &CPU_prvspace[0].mdglobaldata; 1631 bzero(gd, sizeof(*gd)); 1632 1633 /* 1634 * Note: on both UP and SMP curthread must be set non-NULL 1635 * early in the boot sequence because the system assumes 1636 * that 'curthread' is never NULL. 1637 */ 1638 1639 gd->mi.gd_curthread = &thread0; 1640 thread0.td_gd = &gd->mi; 1641 1642 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 1643 1644 #if JG 1645 metadata_missing = 0; 1646 if (bootinfo.bi_modulep) { 1647 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 1648 preload_bootstrap_relocate(KERNBASE); 1649 } else { 1650 metadata_missing = 1; 1651 } 1652 if (bootinfo.bi_envp) 1653 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 1654 #endif 1655 1656 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 1657 preload_bootstrap_relocate(PTOV_OFFSET); 1658 kmdp = preload_search_by_type("elf kernel"); 1659 if (kmdp == NULL) 1660 kmdp = preload_search_by_type("elf64 kernel"); 1661 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1662 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 1663 #ifdef DDB 1664 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1665 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1666 #endif 1667 1668 if (boothowto & RB_VERBOSE) 1669 bootverbose++; 1670 1671 /* 1672 * Default MachIntrABI to ICU 1673 */ 1674 MachIntrABI = MachIntrABI_ICU; 1675 1676 /* 1677 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask, 1678 * and ncpus_fit_mask remain 0. 1679 */ 1680 ncpus = 1; 1681 ncpus2 = 1; 1682 ncpus_fit = 1; 1683 /* Init basic tunables, hz etc */ 1684 init_param1(); 1685 1686 /* 1687 * make gdt memory segments 1688 */ 1689 gdt_segs[GPROC0_SEL].ssd_base = 1690 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss; 1691 1692 gd->mi.gd_prvspace = &CPU_prvspace[0]; 1693 1694 for (x = 0; x < NGDT; x++) { 1695 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 1696 ssdtosd(&gdt_segs[x], &gdt[x]); 1697 } 1698 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1699 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1700 1701 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1702 r_gdt.rd_base = (long) gdt; 1703 lgdt(&r_gdt); 1704 1705 wrmsr(MSR_FSBASE, 0); /* User value */ 1706 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 1707 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1708 1709 mi_gdinit(&gd->mi, 0); 1710 cpu_gdinit(gd, 0); 1711 proc0paddr = proc0paddr_buff; 1712 mi_proc0init(&gd->mi, proc0paddr); 1713 safepri = TDPRI_MAX; 1714 1715 /* spinlocks and the BGL */ 1716 init_locks(); 1717 1718 /* exceptions */ 1719 for (x = 0; x < NIDT; x++) 1720 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1721 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1722 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1723 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 1724 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1725 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1726 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1727 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1728 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1729 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1730 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1731 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1732 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1733 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1734 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1735 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1736 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1737 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1738 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1739 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1740 1741 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1742 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 1743 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 1744 } 1745 1746 lidt(&r_idt_arr[0]); 1747 1748 /* 1749 * Initialize the console before we print anything out. 1750 */ 1751 cninit(); 1752 1753 #if JG 1754 if (metadata_missing) 1755 kprintf("WARNING: loader(8) metadata is missing!\n"); 1756 #endif 1757 1758 #if NISA >0 1759 elcr_probe(); 1760 isa_defaultirq(); 1761 #endif 1762 rand_initialize(); 1763 1764 /* 1765 * Initialize IRQ mapping 1766 * 1767 * NOTE: 1768 * SHOULD be after elcr_probe() 1769 */ 1770 MachIntrABI_ICU.initmap(); 1771 MachIntrABI_IOAPIC.initmap(); 1772 1773 #ifdef DDB 1774 kdb_init(); 1775 if (boothowto & RB_KDB) 1776 Debugger("Boot flags requested debugger"); 1777 #endif 1778 1779 #if JG 1780 finishidentcpu(); /* Final stage of CPU initialization */ 1781 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1782 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 1783 #endif 1784 identify_cpu(); /* Final stage of CPU initialization */ 1785 initializecpu(0); /* Initialize CPU registers */ 1786 1787 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 1788 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 1789 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 1790 1791 /* 1792 * Some of the virtual machines do not work w/ I/O APIC 1793 * enabled. If the user does not explicitly enable or 1794 * disable the I/O APIC (ioapic_enable < 0), then we 1795 * disable I/O APIC on all virtual machines. 1796 * 1797 * NOTE: 1798 * This must be done after identify_cpu(), which sets 1799 * 'cpu_feature2' 1800 */ 1801 if (ioapic_enable < 0) { 1802 if (cpu_feature2 & CPUID2_VMM) 1803 ioapic_enable = 0; 1804 else 1805 ioapic_enable = 1; 1806 } 1807 1808 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1809 gd->gd_common_tss.tss_rsp0 = 1810 (register_t)(thread0.td_kstack + 1811 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 1812 /* Ensure the stack is aligned to 16 bytes */ 1813 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 1814 1815 /* double fault stack */ 1816 gd->gd_common_tss.tss_ist1 = 1817 (long)&gd->mi.gd_prvspace->idlestack[ 1818 sizeof(gd->mi.gd_prvspace->idlestack)]; 1819 1820 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1821 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 1822 1823 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1824 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 1825 gd->gd_common_tssd = *gd->gd_tss_gdt; 1826 ltr(gsel_tss); 1827 1828 /* Set up the fast syscall stuff */ 1829 msr = rdmsr(MSR_EFER) | EFER_SCE; 1830 wrmsr(MSR_EFER, msr); 1831 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1832 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1833 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1834 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1835 wrmsr(MSR_STAR, msr); 1836 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 1837 1838 getmemsize(kmdp, physfree); 1839 init_param2(physmem); 1840 1841 /* now running on new page tables, configured,and u/iom is accessible */ 1842 1843 /* Map the message buffer. */ 1844 #if JG 1845 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1846 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 1847 #endif 1848 1849 msgbufinit(msgbufp, MSGBUF_SIZE); 1850 1851 1852 /* transfer to user mode */ 1853 1854 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1855 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1856 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1857 1858 load_ds(_udatasel); 1859 load_es(_udatasel); 1860 load_fs(_udatasel); 1861 1862 /* setup proc 0's pcb */ 1863 thread0.td_pcb->pcb_flags = 0; 1864 thread0.td_pcb->pcb_cr3 = KPML4phys; 1865 thread0.td_pcb->pcb_ext = NULL; 1866 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 1867 1868 /* Location of kernel stack for locore */ 1869 return ((u_int64_t)thread0.td_pcb); 1870 } 1871 1872 /* 1873 * Initialize machine-dependant portions of the global data structure. 1874 * Note that the global data area and cpu0's idlestack in the private 1875 * data space were allocated in locore. 1876 * 1877 * Note: the idlethread's cpl is 0 1878 * 1879 * WARNING! Called from early boot, 'mycpu' may not work yet. 1880 */ 1881 void 1882 cpu_gdinit(struct mdglobaldata *gd, int cpu) 1883 { 1884 if (cpu) 1885 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 1886 1887 lwkt_init_thread(&gd->mi.gd_idlethread, 1888 gd->mi.gd_prvspace->idlestack, 1889 sizeof(gd->mi.gd_prvspace->idlestack), 1890 0, &gd->mi); 1891 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 1892 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 1893 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 1894 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 1895 } 1896 1897 int 1898 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 1899 { 1900 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 1901 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 1902 return (TRUE); 1903 } 1904 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 1905 return (TRUE); 1906 return (FALSE); 1907 } 1908 1909 struct globaldata * 1910 globaldata_find(int cpu) 1911 { 1912 KKASSERT(cpu >= 0 && cpu < ncpus); 1913 return(&CPU_prvspace[cpu].mdglobaldata.mi); 1914 } 1915 1916 int 1917 ptrace_set_pc(struct lwp *lp, unsigned long addr) 1918 { 1919 lp->lwp_md.md_regs->tf_rip = addr; 1920 return (0); 1921 } 1922 1923 int 1924 ptrace_single_step(struct lwp *lp) 1925 { 1926 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 1927 return (0); 1928 } 1929 1930 int 1931 fill_regs(struct lwp *lp, struct reg *regs) 1932 { 1933 struct trapframe *tp; 1934 1935 if ((tp = lp->lwp_md.md_regs) == NULL) 1936 return EINVAL; 1937 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 1938 return (0); 1939 } 1940 1941 int 1942 set_regs(struct lwp *lp, struct reg *regs) 1943 { 1944 struct trapframe *tp; 1945 1946 tp = lp->lwp_md.md_regs; 1947 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 1948 !CS_SECURE(regs->r_cs)) 1949 return (EINVAL); 1950 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 1951 clear_quickret(); 1952 return (0); 1953 } 1954 1955 #ifndef CPU_DISABLE_SSE 1956 static void 1957 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1958 { 1959 struct env87 *penv_87 = &sv_87->sv_env; 1960 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1961 int i; 1962 1963 /* FPU control/status */ 1964 penv_87->en_cw = penv_xmm->en_cw; 1965 penv_87->en_sw = penv_xmm->en_sw; 1966 penv_87->en_tw = penv_xmm->en_tw; 1967 penv_87->en_fip = penv_xmm->en_fip; 1968 penv_87->en_fcs = penv_xmm->en_fcs; 1969 penv_87->en_opcode = penv_xmm->en_opcode; 1970 penv_87->en_foo = penv_xmm->en_foo; 1971 penv_87->en_fos = penv_xmm->en_fos; 1972 1973 /* FPU registers */ 1974 for (i = 0; i < 8; ++i) 1975 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 1976 } 1977 1978 static void 1979 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1980 { 1981 struct env87 *penv_87 = &sv_87->sv_env; 1982 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1983 int i; 1984 1985 /* FPU control/status */ 1986 penv_xmm->en_cw = penv_87->en_cw; 1987 penv_xmm->en_sw = penv_87->en_sw; 1988 penv_xmm->en_tw = penv_87->en_tw; 1989 penv_xmm->en_fip = penv_87->en_fip; 1990 penv_xmm->en_fcs = penv_87->en_fcs; 1991 penv_xmm->en_opcode = penv_87->en_opcode; 1992 penv_xmm->en_foo = penv_87->en_foo; 1993 penv_xmm->en_fos = penv_87->en_fos; 1994 1995 /* FPU registers */ 1996 for (i = 0; i < 8; ++i) 1997 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 1998 } 1999 #endif /* CPU_DISABLE_SSE */ 2000 2001 int 2002 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2003 { 2004 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2005 return EINVAL; 2006 #ifndef CPU_DISABLE_SSE 2007 if (cpu_fxsr) { 2008 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2009 (struct save87 *)fpregs); 2010 return (0); 2011 } 2012 #endif /* CPU_DISABLE_SSE */ 2013 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2014 return (0); 2015 } 2016 2017 int 2018 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2019 { 2020 #ifndef CPU_DISABLE_SSE 2021 if (cpu_fxsr) { 2022 set_fpregs_xmm((struct save87 *)fpregs, 2023 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2024 return (0); 2025 } 2026 #endif /* CPU_DISABLE_SSE */ 2027 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2028 return (0); 2029 } 2030 2031 int 2032 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2033 { 2034 struct pcb *pcb; 2035 2036 if (lp == NULL) { 2037 dbregs->dr[0] = rdr0(); 2038 dbregs->dr[1] = rdr1(); 2039 dbregs->dr[2] = rdr2(); 2040 dbregs->dr[3] = rdr3(); 2041 dbregs->dr[4] = rdr4(); 2042 dbregs->dr[5] = rdr5(); 2043 dbregs->dr[6] = rdr6(); 2044 dbregs->dr[7] = rdr7(); 2045 return (0); 2046 } 2047 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2048 return EINVAL; 2049 dbregs->dr[0] = pcb->pcb_dr0; 2050 dbregs->dr[1] = pcb->pcb_dr1; 2051 dbregs->dr[2] = pcb->pcb_dr2; 2052 dbregs->dr[3] = pcb->pcb_dr3; 2053 dbregs->dr[4] = 0; 2054 dbregs->dr[5] = 0; 2055 dbregs->dr[6] = pcb->pcb_dr6; 2056 dbregs->dr[7] = pcb->pcb_dr7; 2057 return (0); 2058 } 2059 2060 int 2061 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2062 { 2063 if (lp == NULL) { 2064 load_dr0(dbregs->dr[0]); 2065 load_dr1(dbregs->dr[1]); 2066 load_dr2(dbregs->dr[2]); 2067 load_dr3(dbregs->dr[3]); 2068 load_dr4(dbregs->dr[4]); 2069 load_dr5(dbregs->dr[5]); 2070 load_dr6(dbregs->dr[6]); 2071 load_dr7(dbregs->dr[7]); 2072 } else { 2073 struct pcb *pcb; 2074 struct ucred *ucred; 2075 int i; 2076 uint64_t mask1, mask2; 2077 2078 /* 2079 * Don't let an illegal value for dr7 get set. Specifically, 2080 * check for undefined settings. Setting these bit patterns 2081 * result in undefined behaviour and can lead to an unexpected 2082 * TRCTRAP. 2083 */ 2084 /* JG this loop looks unreadable */ 2085 /* Check 4 2-bit fields for invalid patterns. 2086 * These fields are R/Wi, for i = 0..3 2087 */ 2088 /* Is 10 in LENi allowed when running in compatibility mode? */ 2089 /* Pattern 10 in R/Wi might be used to indicate 2090 * breakpoint on I/O. Further analysis should be 2091 * carried to decide if it is safe and useful to 2092 * provide access to that capability 2093 */ 2094 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2095 i++, mask1 <<= 4, mask2 <<= 4) 2096 if ((dbregs->dr[7] & mask1) == mask2) 2097 return (EINVAL); 2098 2099 pcb = lp->lwp_thread->td_pcb; 2100 ucred = lp->lwp_proc->p_ucred; 2101 2102 /* 2103 * Don't let a process set a breakpoint that is not within the 2104 * process's address space. If a process could do this, it 2105 * could halt the system by setting a breakpoint in the kernel 2106 * (if ddb was enabled). Thus, we need to check to make sure 2107 * that no breakpoints are being enabled for addresses outside 2108 * process's address space, unless, perhaps, we were called by 2109 * uid 0. 2110 * 2111 * XXX - what about when the watched area of the user's 2112 * address space is written into from within the kernel 2113 * ... wouldn't that still cause a breakpoint to be generated 2114 * from within kernel mode? 2115 */ 2116 2117 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2118 if (dbregs->dr[7] & 0x3) { 2119 /* dr0 is enabled */ 2120 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2121 return (EINVAL); 2122 } 2123 2124 if (dbregs->dr[7] & (0x3<<2)) { 2125 /* dr1 is enabled */ 2126 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2127 return (EINVAL); 2128 } 2129 2130 if (dbregs->dr[7] & (0x3<<4)) { 2131 /* dr2 is enabled */ 2132 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2133 return (EINVAL); 2134 } 2135 2136 if (dbregs->dr[7] & (0x3<<6)) { 2137 /* dr3 is enabled */ 2138 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2139 return (EINVAL); 2140 } 2141 } 2142 2143 pcb->pcb_dr0 = dbregs->dr[0]; 2144 pcb->pcb_dr1 = dbregs->dr[1]; 2145 pcb->pcb_dr2 = dbregs->dr[2]; 2146 pcb->pcb_dr3 = dbregs->dr[3]; 2147 pcb->pcb_dr6 = dbregs->dr[6]; 2148 pcb->pcb_dr7 = dbregs->dr[7]; 2149 2150 pcb->pcb_flags |= PCB_DBREGS; 2151 } 2152 2153 return (0); 2154 } 2155 2156 /* 2157 * Return > 0 if a hardware breakpoint has been hit, and the 2158 * breakpoint was in user space. Return 0, otherwise. 2159 */ 2160 int 2161 user_dbreg_trap(void) 2162 { 2163 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2164 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2165 int nbp; /* number of breakpoints that triggered */ 2166 caddr_t addr[4]; /* breakpoint addresses */ 2167 int i; 2168 2169 dr7 = rdr7(); 2170 if ((dr7 & 0xff) == 0) { 2171 /* 2172 * all GE and LE bits in the dr7 register are zero, 2173 * thus the trap couldn't have been caused by the 2174 * hardware debug registers 2175 */ 2176 return 0; 2177 } 2178 2179 nbp = 0; 2180 dr6 = rdr6(); 2181 bp = dr6 & 0xf; 2182 2183 if (bp == 0) { 2184 /* 2185 * None of the breakpoint bits are set meaning this 2186 * trap was not caused by any of the debug registers 2187 */ 2188 return 0; 2189 } 2190 2191 /* 2192 * at least one of the breakpoints were hit, check to see 2193 * which ones and if any of them are user space addresses 2194 */ 2195 2196 if (bp & 0x01) { 2197 addr[nbp++] = (caddr_t)rdr0(); 2198 } 2199 if (bp & 0x02) { 2200 addr[nbp++] = (caddr_t)rdr1(); 2201 } 2202 if (bp & 0x04) { 2203 addr[nbp++] = (caddr_t)rdr2(); 2204 } 2205 if (bp & 0x08) { 2206 addr[nbp++] = (caddr_t)rdr3(); 2207 } 2208 2209 for (i=0; i<nbp; i++) { 2210 if (addr[i] < 2211 (caddr_t)VM_MAX_USER_ADDRESS) { 2212 /* 2213 * addr[i] is in user space 2214 */ 2215 return nbp; 2216 } 2217 } 2218 2219 /* 2220 * None of the breakpoints are in user space. 2221 */ 2222 return 0; 2223 } 2224 2225 2226 #ifndef DDB 2227 void 2228 Debugger(const char *msg) 2229 { 2230 kprintf("Debugger(\"%s\") called.\n", msg); 2231 } 2232 #endif /* no DDB */ 2233 2234 #ifdef DDB 2235 2236 /* 2237 * Provide inb() and outb() as functions. They are normally only 2238 * available as macros calling inlined functions, thus cannot be 2239 * called inside DDB. 2240 * 2241 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2242 */ 2243 2244 #undef inb 2245 #undef outb 2246 2247 /* silence compiler warnings */ 2248 u_char inb(u_int); 2249 void outb(u_int, u_char); 2250 2251 u_char 2252 inb(u_int port) 2253 { 2254 u_char data; 2255 /* 2256 * We use %%dx and not %1 here because i/o is done at %dx and not at 2257 * %edx, while gcc generates inferior code (movw instead of movl) 2258 * if we tell it to load (u_short) port. 2259 */ 2260 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2261 return (data); 2262 } 2263 2264 void 2265 outb(u_int port, u_char data) 2266 { 2267 u_char al; 2268 /* 2269 * Use an unnecessary assignment to help gcc's register allocator. 2270 * This make a large difference for gcc-1.40 and a tiny difference 2271 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2272 * best results. gcc-2.6.0 can't handle this. 2273 */ 2274 al = data; 2275 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2276 } 2277 2278 #endif /* DDB */ 2279 2280 2281 2282 /* 2283 * initialize all the SMP locks 2284 */ 2285 2286 /* critical region when masking or unmasking interupts */ 2287 struct spinlock_deprecated imen_spinlock; 2288 2289 /* critical region for old style disable_intr/enable_intr */ 2290 struct spinlock_deprecated mpintr_spinlock; 2291 2292 /* critical region around INTR() routines */ 2293 struct spinlock_deprecated intr_spinlock; 2294 2295 /* lock region used by kernel profiling */ 2296 struct spinlock_deprecated mcount_spinlock; 2297 2298 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2299 struct spinlock_deprecated com_spinlock; 2300 2301 /* lock regions around the clock hardware */ 2302 struct spinlock_deprecated clock_spinlock; 2303 2304 static void 2305 init_locks(void) 2306 { 2307 /* 2308 * Get the initial mplock with a count of 1 for the BSP. 2309 * This uses a LOGICAL cpu ID, ie BSP == 0. 2310 */ 2311 cpu_get_initial_mplock(); 2312 /* DEPRECATED */ 2313 spin_lock_init(&mcount_spinlock); 2314 spin_lock_init(&intr_spinlock); 2315 spin_lock_init(&mpintr_spinlock); 2316 spin_lock_init(&imen_spinlock); 2317 spin_lock_init(&com_spinlock); 2318 spin_lock_init(&clock_spinlock); 2319 2320 /* our token pool needs to work early */ 2321 lwkt_token_pool_init(); 2322 } 2323 2324