1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008-2017 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 #if 0 /* JG */ 137 extern void finishidentcpu(void); 138 #endif 139 extern void panicifcpuunsupported(void); 140 141 static void cpu_startup(void *); 142 static void pic_finish(void *); 143 static void cpu_finish(void *); 144 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 static void init_locks(void); 148 149 extern void pcpu_timer_always(struct intrframe *); 150 151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 154 155 #ifdef DDB 156 extern vm_offset_t ksym_start, ksym_end; 157 #endif 158 159 struct privatespace CPU_prvspace_bsp __aligned(4096); 160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 161 162 vm_paddr_t efi_systbl_phys; 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 cpumask_t smp_idleinvl_mask; 167 cpumask_t smp_idleinvl_reqs; 168 169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 181 "monitor/mwait target state"); 182 183 #define CPU_MWAIT_HAS_CX \ 184 ((cpu_feature2 & CPUID2_MON) && \ 185 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 186 187 #define CPU_MWAIT_CX_NAMELEN 16 188 189 #define CPU_MWAIT_C1 1 190 #define CPU_MWAIT_C2 2 191 #define CPU_MWAIT_C3 3 192 #define CPU_MWAIT_CX_MAX 8 193 194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 196 197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 199 200 struct cpu_mwait_cx { 201 int subcnt; 202 char name[4]; 203 struct sysctl_ctx_list sysctl_ctx; 204 struct sysctl_oid *sysctl_tree; 205 }; 206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 207 static char cpu_mwait_cx_supported[256]; 208 209 static int cpu_mwait_c1_hints_cnt; 210 static int cpu_mwait_hints_cnt; 211 static int *cpu_mwait_hints; 212 213 static int cpu_mwait_deep_hints_cnt; 214 static int *cpu_mwait_deep_hints; 215 216 #define CPU_IDLE_REPEAT_DEFAULT 750 217 218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 220 static u_int cpu_mwait_repeat_shift = 1; 221 222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 224 225 static int cpu_mwait_c3_preamble = 226 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 227 CPU_MWAIT_C3_PREAMBLE_BM_STS; 228 229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 230 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 233 234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 235 int *, boolean_t); 236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 239 240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 245 &cpu_mwait_repeat_shift, 0, ""); 246 247 long physmem = 0; 248 249 u_long ebda_addr = 0; 250 251 int imcr_present = 0; 252 253 int naps = 0; /* # of Applications processors */ 254 255 u_int base_memory; 256 257 static int 258 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 259 { 260 u_long pmem = ctob(physmem); 261 int error; 262 263 error = sysctl_handle_long(oidp, &pmem, 0, req); 264 265 return (error); 266 } 267 268 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 269 0, 0, sysctl_hw_physmem, "LU", 270 "Total system memory in bytes (number of pages * page size)"); 271 272 static int 273 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 274 { 275 u_long usermem = ctob(physmem - vmstats.v_wire_count); 276 int error; 277 278 error = sysctl_handle_long(oidp, &usermem, 0, req); 279 280 return (error); 281 } 282 283 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_ULONG|CTLFLAG_RD, 284 0, 0, sysctl_hw_usermem, "LU", ""); 285 286 static int 287 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 288 { 289 int error; 290 u_long availpages; 291 292 availpages = x86_64_btop(avail_end - avail_start); 293 error = sysctl_handle_long(oidp, &availpages, 0, req); 294 295 return (error); 296 } 297 298 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_ULONG|CTLFLAG_RD, 299 0, 0, sysctl_hw_availpages, "LU", ""); 300 301 vm_paddr_t Maxmem; 302 vm_paddr_t Realmem; 303 304 /* 305 * The number of PHYSMAP entries must be one less than the number of 306 * PHYSSEG entries because the PHYSMAP entry that spans the largest 307 * physical address that is accessible by ISA DMA is split into two 308 * PHYSSEG entries. 309 */ 310 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 311 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 312 313 /* must be 1 less so 0 0 can signal end of chunks */ 314 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 315 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 316 317 static vm_offset_t buffer_sva, buffer_eva; 318 vm_offset_t clean_sva, clean_eva; 319 static vm_offset_t pager_sva, pager_eva; 320 static struct trapframe proc0_tf; 321 322 static void 323 cpu_startup(void *dummy) 324 { 325 caddr_t v; 326 vm_size_t size = 0; 327 vm_offset_t firstaddr; 328 329 /* 330 * Good {morning,afternoon,evening,night}. 331 */ 332 kprintf("%s", version); 333 startrtclock(); 334 printcpuinfo(); 335 panicifcpuunsupported(); 336 kprintf("real memory = %ju (%ju MB)\n", 337 (intmax_t)Realmem, 338 (intmax_t)Realmem / 1024 / 1024); 339 /* 340 * Display any holes after the first chunk of extended memory. 341 */ 342 if (bootverbose) { 343 int indx; 344 345 kprintf("Physical memory chunk(s):\n"); 346 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 347 vm_paddr_t size1; 348 349 size1 = phys_avail[indx].phys_end - 350 phys_avail[indx].phys_beg; 351 352 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 353 (intmax_t)phys_avail[indx].phys_beg, 354 (intmax_t)phys_avail[indx].phys_end - 1, 355 (intmax_t)size1, 356 (intmax_t)(size1 / PAGE_SIZE)); 357 } 358 } 359 360 /* 361 * Allocate space for system data structures. 362 * The first available kernel virtual address is in "v". 363 * As pages of kernel virtual memory are allocated, "v" is incremented. 364 * As pages of memory are allocated and cleared, 365 * "firstaddr" is incremented. 366 * An index into the kernel page table corresponding to the 367 * virtual memory address maintained in "v" is kept in "mapaddr". 368 */ 369 370 /* 371 * Make two passes. The first pass calculates how much memory is 372 * needed and allocates it. The second pass assigns virtual 373 * addresses to the various data structures. 374 */ 375 firstaddr = 0; 376 again: 377 v = (caddr_t)firstaddr; 378 379 #define valloc(name, type, num) \ 380 (name) = (type *)v; v = (caddr_t)((name)+(num)) 381 #define valloclim(name, type, num, lim) \ 382 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 383 384 /* 385 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 386 * For the first 64MB of ram nominally allocate sufficient buffers to 387 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 388 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 389 * the buffer cache we limit the eventual kva reservation to 390 * maxbcache bytes. 391 * 392 * factor represents the 1/4 x ram conversion. 393 */ 394 if (nbuf == 0) { 395 long factor = 4 * NBUFCALCSIZE / 1024; 396 long kbytes = physmem * (PAGE_SIZE / 1024); 397 398 nbuf = 50; 399 if (kbytes > 4096) 400 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 401 if (kbytes > 65536) 402 nbuf += (kbytes - 65536) * 2 / (factor * 5); 403 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 404 nbuf = maxbcache / NBUFCALCSIZE; 405 } 406 407 /* 408 * Do not allow the buffer_map to be more then 1/2 the size of the 409 * kernel_map. 410 */ 411 if (nbuf > (virtual_end - virtual_start + 412 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 413 nbuf = (virtual_end - virtual_start + 414 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 415 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 416 } 417 418 /* 419 * Do not allow the buffer_map to use more than 50% of available 420 * physical-equivalent memory. Since the VM pages which back 421 * individual buffers are typically wired, having too many bufs 422 * can prevent the system from paging properly. 423 */ 424 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 425 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 426 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 427 } 428 429 /* 430 * Do not allow the sizeof(struct buf) * nbuf to exceed 1/4 of 431 * the valloc space which is just the virtual_end - virtual_start 432 * section. This is typically ~2GB regardless of the amount of 433 * memory, so we use 500MB as a metric. 434 * 435 * This is because we use valloc() to allocate the buf header array. 436 * 437 * NOTE: buffer space in bytes is limited by vfs.*bufspace sysctls. 438 */ 439 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 4) { 440 nbuf = (virtual_end - virtual_start) / 441 sizeof(struct buf) / 2; 442 kprintf("Warning: nbufs capped at %ld due to " 443 "valloc considerations\n", 444 nbuf); 445 } 446 447 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 448 #ifdef NSWBUF_MIN 449 if (nswbuf_mem < NSWBUF_MIN) 450 nswbuf_mem = NSWBUF_MIN; 451 #endif 452 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 453 #ifdef NSWBUF_MIN 454 if (nswbuf_kva < NSWBUF_MIN) 455 nswbuf_kva = NSWBUF_MIN; 456 #endif 457 458 valloc(swbuf_mem, struct buf, nswbuf_mem); 459 valloc(swbuf_kva, struct buf, nswbuf_kva); 460 valloc(buf, struct buf, nbuf); 461 462 /* 463 * End of first pass, size has been calculated so allocate memory 464 */ 465 if (firstaddr == 0) { 466 size = (vm_size_t)(v - firstaddr); 467 firstaddr = kmem_alloc(&kernel_map, round_page(size), 468 VM_SUBSYS_BUF); 469 if (firstaddr == 0) 470 panic("startup: no room for tables"); 471 goto again; 472 } 473 474 /* 475 * End of second pass, addresses have been assigned 476 * 477 * nbuf is an int, make sure we don't overflow the field. 478 * 479 * On 64-bit systems we always reserve maximal allocations for 480 * buffer cache buffers and there are no fragmentation issues, 481 * so the KVA segment does not have to be excessively oversized. 482 */ 483 if ((vm_size_t)(v - firstaddr) != size) 484 panic("startup: table size inconsistency"); 485 486 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 487 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 488 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 489 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 490 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 491 buffer_map.system_map = 1; 492 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 493 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 494 pager_map_size); 495 pager_map.system_map = 1; 496 kprintf("avail memory = %ju (%ju MB)\n", 497 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 498 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 499 1024 / 1024); 500 } 501 502 struct cpu_idle_stat { 503 int hint; 504 int reserved; 505 u_long halt; 506 u_long spin; 507 u_long repeat; 508 u_long repeat_last; 509 u_long repeat_delta; 510 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 511 } __cachealign; 512 513 #define CPU_IDLE_STAT_HALT -1 514 #define CPU_IDLE_STAT_SPIN -2 515 516 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 517 518 static int 519 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 520 { 521 int idx = arg2, cpu, error; 522 u_long val = 0; 523 524 if (idx == CPU_IDLE_STAT_HALT) { 525 for (cpu = 0; cpu < ncpus; ++cpu) 526 val += cpu_idle_stats[cpu].halt; 527 } else if (idx == CPU_IDLE_STAT_SPIN) { 528 for (cpu = 0; cpu < ncpus; ++cpu) 529 val += cpu_idle_stats[cpu].spin; 530 } else { 531 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 532 ("invalid index %d", idx)); 533 for (cpu = 0; cpu < ncpus; ++cpu) 534 val += cpu_idle_stats[cpu].mwait_cx[idx]; 535 } 536 537 error = sysctl_handle_quad(oidp, &val, 0, req); 538 if (error || req->newptr == NULL) 539 return error; 540 541 if (idx == CPU_IDLE_STAT_HALT) { 542 for (cpu = 0; cpu < ncpus; ++cpu) 543 cpu_idle_stats[cpu].halt = 0; 544 cpu_idle_stats[0].halt = val; 545 } else if (idx == CPU_IDLE_STAT_SPIN) { 546 for (cpu = 0; cpu < ncpus; ++cpu) 547 cpu_idle_stats[cpu].spin = 0; 548 cpu_idle_stats[0].spin = val; 549 } else { 550 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 551 ("invalid index %d", idx)); 552 for (cpu = 0; cpu < ncpus; ++cpu) 553 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 554 cpu_idle_stats[0].mwait_cx[idx] = val; 555 } 556 return 0; 557 } 558 559 static void 560 cpu_mwait_attach(void) 561 { 562 struct sbuf sb; 563 int hint_idx, i; 564 565 if (!CPU_MWAIT_HAS_CX) 566 return; 567 568 if (cpu_vendor_id == CPU_VENDOR_INTEL && 569 (CPUID_TO_FAMILY(cpu_id) > 0xf || 570 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 571 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 572 int bm_sts = 1; 573 574 /* 575 * Pentium dual-core, Core 2 and beyond do not need any 576 * additional activities to enter deep C-state, i.e. C3(+). 577 */ 578 cpu_mwait_cx_no_bmarb(); 579 580 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 581 if (!bm_sts) 582 cpu_mwait_cx_no_bmsts(); 583 } 584 585 sbuf_new(&sb, cpu_mwait_cx_supported, 586 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 587 588 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 589 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 590 int sub; 591 592 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 593 594 sysctl_ctx_init(&cx->sysctl_ctx); 595 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 596 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 597 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 598 if (cx->sysctl_tree == NULL) 599 continue; 600 601 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 602 SYSCTL_ADD_INT(&cx->sysctl_ctx, 603 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 604 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 605 "sub-state count"); 606 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 607 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 608 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 609 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 610 611 for (sub = 0; sub < cx->subcnt; ++sub) 612 sbuf_printf(&sb, "C%d/%d ", i, sub); 613 } 614 sbuf_trim(&sb); 615 sbuf_finish(&sb); 616 617 /* 618 * Non-deep C-states 619 */ 620 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 621 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 622 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 623 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 624 M_DEVBUF, M_WAITOK); 625 626 hint_idx = 0; 627 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 628 int j, subcnt; 629 630 subcnt = cpu_mwait_cx_info[i].subcnt; 631 for (j = 0; j < subcnt; ++j) { 632 KASSERT(hint_idx < cpu_mwait_hints_cnt, 633 ("invalid mwait hint index %d", hint_idx)); 634 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 635 ++hint_idx; 636 } 637 } 638 KASSERT(hint_idx == cpu_mwait_hints_cnt, 639 ("mwait hint count %d != index %d", 640 cpu_mwait_hints_cnt, hint_idx)); 641 642 if (bootverbose) { 643 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 644 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 645 int hint = cpu_mwait_hints[i]; 646 647 kprintf(" C%d/%d hint 0x%04x\n", 648 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 649 hint); 650 } 651 } 652 653 /* 654 * Deep C-states 655 */ 656 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 657 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 658 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 659 M_DEVBUF, M_WAITOK); 660 661 hint_idx = 0; 662 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 663 int j, subcnt; 664 665 subcnt = cpu_mwait_cx_info[i].subcnt; 666 for (j = 0; j < subcnt; ++j) { 667 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 668 ("invalid mwait deep hint index %d", hint_idx)); 669 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 670 ++hint_idx; 671 } 672 } 673 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 674 ("mwait deep hint count %d != index %d", 675 cpu_mwait_deep_hints_cnt, hint_idx)); 676 677 if (bootverbose) { 678 kprintf("MWAIT deep hints:\n"); 679 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 680 int hint = cpu_mwait_deep_hints[i]; 681 682 kprintf(" C%d/%d hint 0x%04x\n", 683 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 684 hint); 685 } 686 } 687 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 688 689 for (i = 0; i < ncpus; ++i) { 690 char name[16]; 691 692 ksnprintf(name, sizeof(name), "idle%d", i); 693 SYSCTL_ADD_PROC(NULL, 694 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 695 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 696 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 697 } 698 } 699 700 static void 701 cpu_finish(void *dummy __unused) 702 { 703 cpu_setregs(); 704 cpu_mwait_attach(); 705 } 706 707 static void 708 pic_finish(void *dummy __unused) 709 { 710 /* Log ELCR information */ 711 elcr_dump(); 712 713 /* Log MPTABLE information */ 714 mptable_pci_int_dump(); 715 716 /* Finalize PCI */ 717 MachIntrABI.finalize(); 718 } 719 720 /* 721 * Send an interrupt to process. 722 * 723 * Stack is set up to allow sigcode stored 724 * at top to call routine, followed by kcall 725 * to sigreturn routine below. After sigreturn 726 * resets the signal mask, the stack, and the 727 * frame pointer, it returns to the user 728 * specified pc, psl. 729 */ 730 void 731 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 732 { 733 struct lwp *lp = curthread->td_lwp; 734 struct proc *p = lp->lwp_proc; 735 struct trapframe *regs; 736 struct sigacts *psp = p->p_sigacts; 737 struct sigframe sf, *sfp; 738 int oonstack; 739 char *sp; 740 741 regs = lp->lwp_md.md_regs; 742 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 743 744 /* Save user context */ 745 bzero(&sf, sizeof(struct sigframe)); 746 sf.sf_uc.uc_sigmask = *mask; 747 sf.sf_uc.uc_stack = lp->lwp_sigstk; 748 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 749 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 750 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 751 752 /* Make the size of the saved context visible to userland */ 753 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 754 755 /* Allocate and validate space for the signal handler context. */ 756 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 757 SIGISMEMBER(psp->ps_sigonstack, sig)) { 758 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 759 sizeof(struct sigframe)); 760 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 761 } else { 762 /* We take red zone into account */ 763 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 764 } 765 766 /* 767 * XXX AVX needs 64-byte alignment but sigframe has other fields and 768 * the embedded ucontext is not at the front, so aligning this won't 769 * help us. Fortunately we bcopy in/out of the sigframe, so the 770 * kernel is ok. 771 * 772 * The problem though is if userland winds up trying to use the 773 * context directly. 774 */ 775 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 776 777 /* Translate the signal is appropriate */ 778 if (p->p_sysent->sv_sigtbl) { 779 if (sig <= p->p_sysent->sv_sigsize) 780 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 781 } 782 783 /* 784 * Build the argument list for the signal handler. 785 * 786 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 787 */ 788 regs->tf_rdi = sig; /* argument 1 */ 789 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 790 791 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 792 /* 793 * Signal handler installed with SA_SIGINFO. 794 * 795 * action(signo, siginfo, ucontext) 796 */ 797 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 798 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 799 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 800 801 /* fill siginfo structure */ 802 sf.sf_si.si_signo = sig; 803 sf.sf_si.si_code = code; 804 sf.sf_si.si_addr = (void *)regs->tf_addr; 805 } else { 806 /* 807 * Old FreeBSD-style arguments. 808 * 809 * handler (signo, code, [uc], addr) 810 */ 811 regs->tf_rsi = (register_t)code; /* argument 2 */ 812 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 813 sf.sf_ahu.sf_handler = catcher; 814 } 815 816 /* 817 * If we're a vm86 process, we want to save the segment registers. 818 * We also change eflags to be our emulated eflags, not the actual 819 * eflags. 820 */ 821 #if 0 /* JG */ 822 if (regs->tf_eflags & PSL_VM) { 823 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 824 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 825 826 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 827 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 828 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 829 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 830 831 if (vm86->vm86_has_vme == 0) 832 sf.sf_uc.uc_mcontext.mc_eflags = 833 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 834 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 835 836 /* 837 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 838 * syscalls made by the signal handler. This just avoids 839 * wasting time for our lazy fixup of such faults. PSL_NT 840 * does nothing in vm86 mode, but vm86 programs can set it 841 * almost legitimately in probes for old cpu types. 842 */ 843 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 844 } 845 #endif 846 847 /* 848 * Save the FPU state and reinit the FP unit 849 */ 850 npxpush(&sf.sf_uc.uc_mcontext); 851 852 /* 853 * Copy the sigframe out to the user's stack. 854 */ 855 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 856 /* 857 * Something is wrong with the stack pointer. 858 * ...Kill the process. 859 */ 860 sigexit(lp, SIGILL); 861 } 862 863 regs->tf_rsp = (register_t)sfp; 864 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 865 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 866 867 /* 868 * x86 abi specifies that the direction flag must be cleared 869 * on function entry 870 */ 871 regs->tf_rflags &= ~(PSL_T | PSL_D); 872 873 /* 874 * 64 bit mode has a code and stack selector but 875 * no data or extra selector. %fs and %gs are not 876 * stored in-context. 877 */ 878 regs->tf_cs = _ucodesel; 879 regs->tf_ss = _udatasel; 880 clear_quickret(); 881 } 882 883 /* 884 * Sanitize the trapframe for a virtual kernel passing control to a custom 885 * VM context. Remove any items that would otherwise create a privilage 886 * issue. 887 * 888 * XXX at the moment we allow userland to set the resume flag. Is this a 889 * bad idea? 890 */ 891 int 892 cpu_sanitize_frame(struct trapframe *frame) 893 { 894 frame->tf_cs = _ucodesel; 895 frame->tf_ss = _udatasel; 896 /* XXX VM (8086) mode not supported? */ 897 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 898 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 899 900 return(0); 901 } 902 903 /* 904 * Sanitize the tls so loading the descriptor does not blow up 905 * on us. For x86_64 we don't have to do anything. 906 */ 907 int 908 cpu_sanitize_tls(struct savetls *tls) 909 { 910 return(0); 911 } 912 913 /* 914 * sigreturn(ucontext_t *sigcntxp) 915 * 916 * System call to cleanup state after a signal 917 * has been taken. Reset signal mask and 918 * stack state from context left by sendsig (above). 919 * Return to previous pc and psl as specified by 920 * context left by sendsig. Check carefully to 921 * make sure that the user has not modified the 922 * state to gain improper privileges. 923 * 924 * MPSAFE 925 */ 926 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 927 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 928 929 int 930 sys_sigreturn(struct sigreturn_args *uap) 931 { 932 struct lwp *lp = curthread->td_lwp; 933 struct trapframe *regs; 934 ucontext_t uc; 935 ucontext_t *ucp; 936 register_t rflags; 937 int cs; 938 int error; 939 940 /* 941 * We have to copy the information into kernel space so userland 942 * can't modify it while we are sniffing it. 943 */ 944 regs = lp->lwp_md.md_regs; 945 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 946 if (error) 947 return (error); 948 ucp = &uc; 949 rflags = ucp->uc_mcontext.mc_rflags; 950 951 /* VM (8086) mode not supported */ 952 rflags &= ~PSL_VM_UNSUPP; 953 954 #if 0 /* JG */ 955 if (eflags & PSL_VM) { 956 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 957 struct vm86_kernel *vm86; 958 959 /* 960 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 961 * set up the vm86 area, and we can't enter vm86 mode. 962 */ 963 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 964 return (EINVAL); 965 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 966 if (vm86->vm86_inited == 0) 967 return (EINVAL); 968 969 /* go back to user mode if both flags are set */ 970 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 971 trapsignal(lp, SIGBUS, 0); 972 973 if (vm86->vm86_has_vme) { 974 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 975 (eflags & VME_USERCHANGE) | PSL_VM; 976 } else { 977 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 978 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 979 (eflags & VM_USERCHANGE) | PSL_VM; 980 } 981 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 982 tf->tf_eflags = eflags; 983 tf->tf_vm86_ds = tf->tf_ds; 984 tf->tf_vm86_es = tf->tf_es; 985 tf->tf_vm86_fs = tf->tf_fs; 986 tf->tf_vm86_gs = tf->tf_gs; 987 tf->tf_ds = _udatasel; 988 tf->tf_es = _udatasel; 989 tf->tf_fs = _udatasel; 990 tf->tf_gs = _udatasel; 991 } else 992 #endif 993 { 994 /* 995 * Don't allow users to change privileged or reserved flags. 996 */ 997 /* 998 * XXX do allow users to change the privileged flag PSL_RF. 999 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 1000 * should sometimes set it there too. tf_eflags is kept in 1001 * the signal context during signal handling and there is no 1002 * other place to remember it, so the PSL_RF bit may be 1003 * corrupted by the signal handler without us knowing. 1004 * Corruption of the PSL_RF bit at worst causes one more or 1005 * one less debugger trap, so allowing it is fairly harmless. 1006 */ 1007 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 1008 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 1009 return(EINVAL); 1010 } 1011 1012 /* 1013 * Don't allow users to load a valid privileged %cs. Let the 1014 * hardware check for invalid selectors, excess privilege in 1015 * other selectors, invalid %eip's and invalid %esp's. 1016 */ 1017 cs = ucp->uc_mcontext.mc_cs; 1018 if (!CS_SECURE(cs)) { 1019 kprintf("sigreturn: cs = 0x%x\n", cs); 1020 trapsignal(lp, SIGBUS, T_PROTFLT); 1021 return(EINVAL); 1022 } 1023 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1024 } 1025 1026 /* 1027 * Restore the FPU state from the frame 1028 */ 1029 crit_enter(); 1030 npxpop(&ucp->uc_mcontext); 1031 1032 if (ucp->uc_mcontext.mc_onstack & 1) 1033 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1034 else 1035 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1036 1037 lp->lwp_sigmask = ucp->uc_sigmask; 1038 SIG_CANTMASK(lp->lwp_sigmask); 1039 clear_quickret(); 1040 crit_exit(); 1041 return(EJUSTRETURN); 1042 } 1043 1044 /* 1045 * Machine dependent boot() routine 1046 * 1047 * I haven't seen anything to put here yet 1048 * Possibly some stuff might be grafted back here from boot() 1049 */ 1050 void 1051 cpu_boot(int howto) 1052 { 1053 } 1054 1055 /* 1056 * Shutdown the CPU as much as possible 1057 */ 1058 void 1059 cpu_halt(void) 1060 { 1061 for (;;) 1062 __asm__ __volatile("hlt"); 1063 } 1064 1065 /* 1066 * cpu_idle() represents the idle LWKT. You cannot return from this function 1067 * (unless you want to blow things up!). Instead we look for runnable threads 1068 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1069 * 1070 * The main loop is entered with a critical section held, we must release 1071 * the critical section before doing anything else. lwkt_switch() will 1072 * check for pending interrupts due to entering and exiting its own 1073 * critical section. 1074 * 1075 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1076 * However, there are cases where the idlethread will be entered with 1077 * the possibility that no IPI will occur and in such cases 1078 * lwkt_switch() sets TDF_IDLE_NOHLT. 1079 * 1080 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1081 * must occur before it starts using ACPI halt. 1082 * 1083 * NOTE: Value overridden in hammer_time(). 1084 */ 1085 static int cpu_idle_hlt = 2; 1086 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1087 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1088 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1089 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1090 1091 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1092 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1093 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1094 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1095 1096 static void 1097 cpu_idle_default_hook(void) 1098 { 1099 /* 1100 * We must guarentee that hlt is exactly the instruction 1101 * following the sti. 1102 */ 1103 __asm __volatile("sti; hlt"); 1104 } 1105 1106 /* Other subsystems (e.g., ACPI) can hook this later. */ 1107 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1108 1109 static __inline int 1110 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1111 { 1112 int hint, cx_idx; 1113 u_int idx; 1114 1115 hint = stat->hint; 1116 if (hint >= 0) 1117 goto done; 1118 1119 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1120 cpu_mwait_repeat_shift; 1121 if (idx >= cpu_mwait_c1_hints_cnt) { 1122 /* Step up faster, once we walked through all C1 states */ 1123 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1124 } 1125 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1126 if (idx >= cpu_mwait_deep_hints_cnt) 1127 idx = cpu_mwait_deep_hints_cnt - 1; 1128 hint = cpu_mwait_deep_hints[idx]; 1129 } else { 1130 if (idx >= cpu_mwait_hints_cnt) 1131 idx = cpu_mwait_hints_cnt - 1; 1132 hint = cpu_mwait_hints[idx]; 1133 } 1134 done: 1135 cx_idx = MWAIT_EAX_TO_CX(hint); 1136 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1137 stat->mwait_cx[cx_idx]++; 1138 return hint; 1139 } 1140 1141 void 1142 cpu_idle(void) 1143 { 1144 globaldata_t gd = mycpu; 1145 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1146 struct thread *td __debugvar = gd->gd_curthread; 1147 int reqflags; 1148 int quick; 1149 1150 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1151 1152 crit_exit(); 1153 KKASSERT(td->td_critcount == 0); 1154 1155 for (;;) { 1156 /* 1157 * See if there are any LWKTs ready to go. 1158 */ 1159 lwkt_switch(); 1160 1161 /* 1162 * When halting inside a cli we must check for reqflags 1163 * races, particularly [re]schedule requests. Running 1164 * splz() does the job. 1165 * 1166 * cpu_idle_hlt: 1167 * 0 Never halt, just spin 1168 * 1169 * 1 Always use MONITOR/MWAIT if avail, HLT 1170 * otherwise. 1171 * 1172 * Better default for modern (Haswell+) Intel 1173 * cpus. 1174 * 1175 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1176 * use the ACPI halt (default). This is a hybrid 1177 * approach. See machdep.cpu_idle_repeat. 1178 * 1179 * Better default for modern AMD cpus and older 1180 * Intel cpus. 1181 * 1182 * 3 Always use the ACPI halt. This typically 1183 * eats the least amount of power but the cpu 1184 * will be slow waking up. Slows down e.g. 1185 * compiles and other pipe/event oriented stuff. 1186 * 1187 * Usually the best default for AMD cpus. 1188 * 1189 * 4 Always use HLT. 1190 * 1191 * 5 Always spin. 1192 * 1193 * NOTE: Interrupts are enabled and we are not in a critical 1194 * section. 1195 * 1196 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1197 * don't bother capping gd_idle_repeat, it is ok if 1198 * it overflows. 1199 * 1200 * Implement optimized invltlb operations when halted 1201 * in idle. By setting the bit in smp_idleinvl_mask 1202 * we inform other cpus that they can set _reqs to 1203 * request an invltlb. Current the code to do that 1204 * sets the bits in _reqs anyway, but then check _mask 1205 * to determine if they can assume the invltlb will execute. 1206 * 1207 * A critical section is required to ensure that interrupts 1208 * do not fully run until after we've had a chance to execute 1209 * the request. 1210 */ 1211 if (gd->gd_idle_repeat == 0) { 1212 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1213 if (stat->repeat > cpu_idle_repeat_max) 1214 stat->repeat = cpu_idle_repeat_max; 1215 stat->repeat_last = 0; 1216 stat->repeat_delta = 0; 1217 } 1218 ++stat->repeat_last; 1219 1220 ++gd->gd_idle_repeat; 1221 reqflags = gd->gd_reqflags; 1222 quick = (cpu_idle_hlt == 1) || 1223 (cpu_idle_hlt == 2 && 1224 gd->gd_idle_repeat < cpu_idle_repeat); 1225 1226 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1227 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1228 splz(); /* XXX */ 1229 crit_enter_gd(gd); 1230 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1231 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1232 cpu_mwait_cx_hint(stat), 0); 1233 stat->halt++; 1234 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1235 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1236 gd->gd_cpuid)) { 1237 cpu_invltlb(); 1238 cpu_mfence(); 1239 } 1240 crit_exit_gd(gd); 1241 } else if (cpu_idle_hlt) { 1242 __asm __volatile("cli"); 1243 splz(); 1244 crit_enter_gd(gd); 1245 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1246 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1247 if (cpu_idle_hlt == 5) { 1248 __asm __volatile("sti"); 1249 } else if (quick || cpu_idle_hlt == 4) { 1250 cpu_idle_default_hook(); 1251 } else { 1252 cpu_idle_hook(); 1253 } 1254 } 1255 __asm __volatile("sti"); 1256 stat->halt++; 1257 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1258 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1259 gd->gd_cpuid)) { 1260 cpu_invltlb(); 1261 cpu_mfence(); 1262 } 1263 crit_exit_gd(gd); 1264 } else { 1265 splz(); 1266 __asm __volatile("sti"); 1267 stat->spin++; 1268 crit_enter_gd(gd); 1269 crit_exit_gd(gd); 1270 } 1271 } 1272 } 1273 1274 /* 1275 * Called in a loop indirectly via Xcpustop 1276 */ 1277 void 1278 cpu_smp_stopped(void) 1279 { 1280 globaldata_t gd = mycpu; 1281 volatile __uint64_t *ptr; 1282 __uint64_t ovalue; 1283 1284 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1285 ovalue = *ptr; 1286 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1287 if (cpu_mi_feature & CPU_MI_MONITOR) { 1288 if (cpu_mwait_hints) { 1289 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1290 ovalue, 1291 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1292 } else { 1293 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1294 ovalue, 0, 0); 1295 } 1296 } else { 1297 cpu_halt(); /* depend on lapic timer */ 1298 } 1299 } 1300 } 1301 1302 /* 1303 * This routine is called if a spinlock has been held through the 1304 * exponential backoff period and is seriously contested. On a real cpu 1305 * we let it spin. 1306 */ 1307 void 1308 cpu_spinlock_contested(void) 1309 { 1310 cpu_pause(); 1311 } 1312 1313 /* 1314 * Clear registers on exec 1315 */ 1316 void 1317 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1318 { 1319 struct thread *td = curthread; 1320 struct lwp *lp = td->td_lwp; 1321 struct pcb *pcb = td->td_pcb; 1322 struct trapframe *regs = lp->lwp_md.md_regs; 1323 1324 user_ldt_free(pcb); 1325 1326 clear_quickret(); 1327 bzero((char *)regs, sizeof(struct trapframe)); 1328 regs->tf_rip = entry; 1329 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1330 regs->tf_rdi = stack; /* argv */ 1331 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1332 regs->tf_ss = _udatasel; 1333 regs->tf_cs = _ucodesel; 1334 regs->tf_rbx = ps_strings; 1335 1336 /* 1337 * Reset the hardware debug registers if they were in use. 1338 * They won't have any meaning for the newly exec'd process. 1339 */ 1340 if (pcb->pcb_flags & PCB_DBREGS) { 1341 pcb->pcb_dr0 = 0; 1342 pcb->pcb_dr1 = 0; 1343 pcb->pcb_dr2 = 0; 1344 pcb->pcb_dr3 = 0; 1345 pcb->pcb_dr6 = 0; 1346 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1347 if (pcb == td->td_pcb) { 1348 /* 1349 * Clear the debug registers on the running 1350 * CPU, otherwise they will end up affecting 1351 * the next process we switch to. 1352 */ 1353 reset_dbregs(); 1354 } 1355 pcb->pcb_flags &= ~PCB_DBREGS; 1356 } 1357 1358 /* 1359 * Initialize the math emulator (if any) for the current process. 1360 * Actually, just clear the bit that says that the emulator has 1361 * been initialized. Initialization is delayed until the process 1362 * traps to the emulator (if it is done at all) mainly because 1363 * emulators don't provide an entry point for initialization. 1364 */ 1365 pcb->pcb_flags &= ~FP_SOFTFP; 1366 1367 /* 1368 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1369 * gd_npxthread. Otherwise a preemptive interrupt thread 1370 * may panic in npxdna(). 1371 */ 1372 crit_enter(); 1373 load_cr0(rcr0() | CR0_MP); 1374 1375 /* 1376 * NOTE: The MSR values must be correct so we can return to 1377 * userland. gd_user_fs/gs must be correct so the switch 1378 * code knows what the current MSR values are. 1379 */ 1380 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1381 pcb->pcb_gsbase = 0; 1382 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1383 mdcpu->gd_user_gs = 0; 1384 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1385 wrmsr(MSR_KGSBASE, 0); 1386 1387 /* Initialize the npx (if any) for the current process. */ 1388 npxinit(); 1389 crit_exit(); 1390 1391 pcb->pcb_ds = _udatasel; 1392 pcb->pcb_es = _udatasel; 1393 pcb->pcb_fs = _udatasel; 1394 pcb->pcb_gs = _udatasel; 1395 } 1396 1397 void 1398 cpu_setregs(void) 1399 { 1400 register_t cr0; 1401 1402 cr0 = rcr0(); 1403 cr0 |= CR0_NE; /* Done by npxinit() */ 1404 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1405 cr0 |= CR0_WP | CR0_AM; 1406 load_cr0(cr0); 1407 load_gs(_udatasel); 1408 } 1409 1410 static int 1411 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1412 { 1413 int error; 1414 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1415 req); 1416 if (!error && req->newptr) 1417 resettodr(); 1418 return (error); 1419 } 1420 1421 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1422 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1423 1424 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1425 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1426 1427 #if 0 /* JG */ 1428 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1429 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1430 #endif 1431 1432 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1433 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1434 1435 static int 1436 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1437 { 1438 struct efi_map_header *efihdr; 1439 caddr_t kmdp; 1440 uint32_t efisize; 1441 1442 kmdp = preload_search_by_type("elf kernel"); 1443 if (kmdp == NULL) 1444 kmdp = preload_search_by_type("elf64 kernel"); 1445 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1446 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1447 if (efihdr == NULL) 1448 return (0); 1449 efisize = *((uint32_t *)efihdr - 1); 1450 return (SYSCTL_OUT(req, efihdr, efisize)); 1451 } 1452 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1453 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1454 1455 /* 1456 * Initialize x86 and configure to run kernel 1457 */ 1458 1459 /* 1460 * Initialize segments & interrupt table 1461 */ 1462 1463 int _default_ldt; 1464 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1465 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1466 #if 0 /* JG */ 1467 union descriptor ldt[NLDT]; /* local descriptor table */ 1468 #endif 1469 1470 /* table descriptors - used to load tables by cpu */ 1471 struct region_descriptor r_gdt; 1472 struct region_descriptor r_idt_arr[MAXCPU]; 1473 1474 /* JG proc0paddr is a virtual address */ 1475 void *proc0paddr; 1476 /* JG alignment? */ 1477 char proc0paddr_buff[LWKT_THREAD_STACK]; 1478 1479 1480 /* software prototypes -- in more palatable form */ 1481 struct soft_segment_descriptor gdt_segs[] = { 1482 /* GNULL_SEL 0 Null Descriptor */ 1483 { 0x0, /* segment base address */ 1484 0x0, /* length */ 1485 0, /* segment type */ 1486 0, /* segment descriptor priority level */ 1487 0, /* segment descriptor present */ 1488 0, /* long */ 1489 0, /* default 32 vs 16 bit size */ 1490 0 /* limit granularity (byte/page units)*/ }, 1491 /* GCODE_SEL 1 Code Descriptor for kernel */ 1492 { 0x0, /* segment base address */ 1493 0xfffff, /* length - all address space */ 1494 SDT_MEMERA, /* segment type */ 1495 SEL_KPL, /* segment descriptor priority level */ 1496 1, /* segment descriptor present */ 1497 1, /* long */ 1498 0, /* default 32 vs 16 bit size */ 1499 1 /* limit granularity (byte/page units)*/ }, 1500 /* GDATA_SEL 2 Data Descriptor for kernel */ 1501 { 0x0, /* segment base address */ 1502 0xfffff, /* length - all address space */ 1503 SDT_MEMRWA, /* segment type */ 1504 SEL_KPL, /* segment descriptor priority level */ 1505 1, /* segment descriptor present */ 1506 1, /* long */ 1507 0, /* default 32 vs 16 bit size */ 1508 1 /* limit granularity (byte/page units)*/ }, 1509 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1510 { 0x0, /* segment base address */ 1511 0xfffff, /* length - all address space */ 1512 SDT_MEMERA, /* segment type */ 1513 SEL_UPL, /* segment descriptor priority level */ 1514 1, /* segment descriptor present */ 1515 0, /* long */ 1516 1, /* default 32 vs 16 bit size */ 1517 1 /* limit granularity (byte/page units)*/ }, 1518 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1519 { 0x0, /* segment base address */ 1520 0xfffff, /* length - all address space */ 1521 SDT_MEMRWA, /* segment type */ 1522 SEL_UPL, /* segment descriptor priority level */ 1523 1, /* segment descriptor present */ 1524 0, /* long */ 1525 1, /* default 32 vs 16 bit size */ 1526 1 /* limit granularity (byte/page units)*/ }, 1527 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1528 { 0x0, /* segment base address */ 1529 0xfffff, /* length - all address space */ 1530 SDT_MEMERA, /* segment type */ 1531 SEL_UPL, /* segment descriptor priority level */ 1532 1, /* segment descriptor present */ 1533 1, /* long */ 1534 0, /* default 32 vs 16 bit size */ 1535 1 /* limit granularity (byte/page units)*/ }, 1536 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1537 { 1538 0x0, /* segment base address */ 1539 sizeof(struct x86_64tss)-1,/* length - all address space */ 1540 SDT_SYSTSS, /* segment type */ 1541 SEL_KPL, /* segment descriptor priority level */ 1542 1, /* segment descriptor present */ 1543 0, /* long */ 1544 0, /* unused - default 32 vs 16 bit size */ 1545 0 /* limit granularity (byte/page units)*/ }, 1546 /* Actually, the TSS is a system descriptor which is double size */ 1547 { 0x0, /* segment base address */ 1548 0x0, /* length */ 1549 0, /* segment type */ 1550 0, /* segment descriptor priority level */ 1551 0, /* segment descriptor present */ 1552 0, /* long */ 1553 0, /* default 32 vs 16 bit size */ 1554 0 /* limit granularity (byte/page units)*/ }, 1555 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1556 { 0x0, /* segment base address */ 1557 0xfffff, /* length - all address space */ 1558 SDT_MEMRWA, /* segment type */ 1559 SEL_UPL, /* segment descriptor priority level */ 1560 1, /* segment descriptor present */ 1561 0, /* long */ 1562 1, /* default 32 vs 16 bit size */ 1563 1 /* limit granularity (byte/page units)*/ }, 1564 }; 1565 1566 void 1567 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1568 { 1569 int cpu; 1570 1571 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1572 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1573 1574 ip->gd_looffset = (uintptr_t)func; 1575 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1576 ip->gd_ist = ist; 1577 ip->gd_xx = 0; 1578 ip->gd_type = typ; 1579 ip->gd_dpl = dpl; 1580 ip->gd_p = 1; 1581 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1582 } 1583 } 1584 1585 void 1586 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1587 { 1588 struct gate_descriptor *ip; 1589 1590 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1591 1592 ip = &idt_arr[cpu][idx]; 1593 ip->gd_looffset = (uintptr_t)func; 1594 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1595 ip->gd_ist = ist; 1596 ip->gd_xx = 0; 1597 ip->gd_type = typ; 1598 ip->gd_dpl = dpl; 1599 ip->gd_p = 1; 1600 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1601 } 1602 1603 #define IDTVEC(name) __CONCAT(X,name) 1604 1605 extern inthand_t 1606 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1607 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1608 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1609 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1610 IDTVEC(xmm), IDTVEC(dblfault), 1611 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1612 1613 void 1614 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1615 { 1616 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1617 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1618 ssd->ssd_type = sd->sd_type; 1619 ssd->ssd_dpl = sd->sd_dpl; 1620 ssd->ssd_p = sd->sd_p; 1621 ssd->ssd_def32 = sd->sd_def32; 1622 ssd->ssd_gran = sd->sd_gran; 1623 } 1624 1625 void 1626 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1627 { 1628 1629 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1630 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1631 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1632 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1633 sd->sd_type = ssd->ssd_type; 1634 sd->sd_dpl = ssd->ssd_dpl; 1635 sd->sd_p = ssd->ssd_p; 1636 sd->sd_long = ssd->ssd_long; 1637 sd->sd_def32 = ssd->ssd_def32; 1638 sd->sd_gran = ssd->ssd_gran; 1639 } 1640 1641 void 1642 ssdtosyssd(struct soft_segment_descriptor *ssd, 1643 struct system_segment_descriptor *sd) 1644 { 1645 1646 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1647 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1648 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1649 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1650 sd->sd_type = ssd->ssd_type; 1651 sd->sd_dpl = ssd->ssd_dpl; 1652 sd->sd_p = ssd->ssd_p; 1653 sd->sd_gran = ssd->ssd_gran; 1654 } 1655 1656 /* 1657 * Populate the (physmap) array with base/bound pairs describing the 1658 * available physical memory in the system, then test this memory and 1659 * build the phys_avail array describing the actually-available memory. 1660 * 1661 * If we cannot accurately determine the physical memory map, then use 1662 * value from the 0xE801 call, and failing that, the RTC. 1663 * 1664 * Total memory size may be set by the kernel environment variable 1665 * hw.physmem or the compile-time define MAXMEM. 1666 * 1667 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1668 * of PAGE_SIZE. This also greatly reduces the memory test time 1669 * which would otherwise be excessive on machines with > 8G of ram. 1670 * 1671 * XXX first should be vm_paddr_t. 1672 */ 1673 1674 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1675 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1676 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1677 1678 vm_paddr_t physmap[PHYSMAP_SIZE]; 1679 struct bios_smap *smapbase, *smap, *smapend; 1680 struct efi_map_header *efihdrbase; 1681 u_int32_t smapsize; 1682 1683 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1684 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1685 1686 static void 1687 add_smap_entries(int *physmap_idx) 1688 { 1689 int i; 1690 1691 smapsize = *((u_int32_t *)smapbase - 1); 1692 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1693 1694 for (smap = smapbase; smap < smapend; smap++) { 1695 if (boothowto & RB_VERBOSE) 1696 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1697 smap->type, smap->base, smap->length); 1698 1699 if (smap->type != SMAP_TYPE_MEMORY) 1700 continue; 1701 1702 if (smap->length == 0) 1703 continue; 1704 1705 for (i = 0; i <= *physmap_idx; i += 2) { 1706 if (smap->base < physmap[i + 1]) { 1707 if (boothowto & RB_VERBOSE) { 1708 kprintf("Overlapping or non-monotonic " 1709 "memory region, ignoring " 1710 "second region\n"); 1711 } 1712 break; 1713 } 1714 } 1715 if (i <= *physmap_idx) 1716 continue; 1717 1718 Realmem += smap->length; 1719 1720 if (smap->base == physmap[*physmap_idx + 1]) { 1721 physmap[*physmap_idx + 1] += smap->length; 1722 continue; 1723 } 1724 1725 *physmap_idx += 2; 1726 if (*physmap_idx == PHYSMAP_SIZE) { 1727 kprintf("Too many segments in the physical " 1728 "address map, giving up\n"); 1729 break; 1730 } 1731 physmap[*physmap_idx] = smap->base; 1732 physmap[*physmap_idx + 1] = smap->base + smap->length; 1733 } 1734 } 1735 1736 static void 1737 add_efi_map_entries(int *physmap_idx) 1738 { 1739 struct efi_md *map, *p; 1740 const char *type; 1741 size_t efisz; 1742 int i, ndesc; 1743 1744 static const char *types[] = { 1745 "Reserved", 1746 "LoaderCode", 1747 "LoaderData", 1748 "BootServicesCode", 1749 "BootServicesData", 1750 "RuntimeServicesCode", 1751 "RuntimeServicesData", 1752 "ConventionalMemory", 1753 "UnusableMemory", 1754 "ACPIReclaimMemory", 1755 "ACPIMemoryNVS", 1756 "MemoryMappedIO", 1757 "MemoryMappedIOPortSpace", 1758 "PalCode" 1759 }; 1760 1761 /* 1762 * Memory map data provided by UEFI via the GetMemoryMap 1763 * Boot Services API. 1764 */ 1765 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1766 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1767 1768 if (efihdrbase->descriptor_size == 0) 1769 return; 1770 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1771 1772 if (boothowto & RB_VERBOSE) 1773 kprintf("%23s %12s %12s %8s %4s\n", 1774 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1775 1776 for (i = 0, p = map; i < ndesc; i++, 1777 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1778 if (boothowto & RB_VERBOSE) { 1779 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1780 type = types[p->md_type]; 1781 else 1782 type = "<INVALID>"; 1783 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1784 p->md_virt, p->md_pages); 1785 if (p->md_attr & EFI_MD_ATTR_UC) 1786 kprintf("UC "); 1787 if (p->md_attr & EFI_MD_ATTR_WC) 1788 kprintf("WC "); 1789 if (p->md_attr & EFI_MD_ATTR_WT) 1790 kprintf("WT "); 1791 if (p->md_attr & EFI_MD_ATTR_WB) 1792 kprintf("WB "); 1793 if (p->md_attr & EFI_MD_ATTR_UCE) 1794 kprintf("UCE "); 1795 if (p->md_attr & EFI_MD_ATTR_WP) 1796 kprintf("WP "); 1797 if (p->md_attr & EFI_MD_ATTR_RP) 1798 kprintf("RP "); 1799 if (p->md_attr & EFI_MD_ATTR_XP) 1800 kprintf("XP "); 1801 if (p->md_attr & EFI_MD_ATTR_RT) 1802 kprintf("RUNTIME"); 1803 kprintf("\n"); 1804 } 1805 1806 switch (p->md_type) { 1807 case EFI_MD_TYPE_CODE: 1808 case EFI_MD_TYPE_DATA: 1809 case EFI_MD_TYPE_BS_CODE: 1810 case EFI_MD_TYPE_BS_DATA: 1811 case EFI_MD_TYPE_FREE: 1812 /* 1813 * We're allowed to use any entry with these types. 1814 */ 1815 break; 1816 default: 1817 continue; 1818 } 1819 1820 Realmem += p->md_pages * PAGE_SIZE; 1821 1822 if (p->md_phys == physmap[*physmap_idx + 1]) { 1823 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1824 continue; 1825 } 1826 1827 *physmap_idx += 2; 1828 if (*physmap_idx == PHYSMAP_SIZE) { 1829 kprintf("Too many segments in the physical " 1830 "address map, giving up\n"); 1831 break; 1832 } 1833 physmap[*physmap_idx] = p->md_phys; 1834 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1835 } 1836 } 1837 1838 struct fb_info efi_fb_info; 1839 static int have_efi_framebuffer = 0; 1840 1841 static void 1842 efi_fb_init_vaddr(int direct_map) 1843 { 1844 uint64_t sz; 1845 vm_offset_t addr, v; 1846 1847 v = efi_fb_info.vaddr; 1848 sz = efi_fb_info.stride * efi_fb_info.height; 1849 1850 if (direct_map) { 1851 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1852 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1853 efi_fb_info.vaddr = addr; 1854 } else { 1855 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1856 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1857 } 1858 } 1859 1860 static u_int 1861 efifb_color_depth(struct efi_fb *efifb) 1862 { 1863 uint32_t mask; 1864 u_int depth; 1865 1866 mask = efifb->fb_mask_red | efifb->fb_mask_green | 1867 efifb->fb_mask_blue | efifb->fb_mask_reserved; 1868 if (mask == 0) 1869 return (0); 1870 for (depth = 1; mask != 1; depth++) 1871 mask >>= 1; 1872 return (depth); 1873 } 1874 1875 int 1876 probe_efi_fb(int early) 1877 { 1878 struct efi_fb *efifb; 1879 caddr_t kmdp; 1880 u_int depth; 1881 1882 if (have_efi_framebuffer) { 1883 if (!early && 1884 (efi_fb_info.vaddr == 0 || 1885 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1886 efi_fb_init_vaddr(0); 1887 return 0; 1888 } 1889 1890 kmdp = preload_search_by_type("elf kernel"); 1891 if (kmdp == NULL) 1892 kmdp = preload_search_by_type("elf64 kernel"); 1893 efifb = (struct efi_fb *)preload_search_info(kmdp, 1894 MODINFO_METADATA | MODINFOMD_EFI_FB); 1895 if (efifb == NULL) 1896 return 1; 1897 1898 depth = efifb_color_depth(efifb); 1899 /* 1900 * Our bootloader should already notice, when we won't be able to 1901 * use the UEFI framebuffer. 1902 */ 1903 if (depth != 24 && depth != 32) 1904 return 1; 1905 1906 have_efi_framebuffer = 1; 1907 1908 efi_fb_info.is_vga_boot_display = 1; 1909 efi_fb_info.width = efifb->fb_width; 1910 efi_fb_info.height = efifb->fb_height; 1911 efi_fb_info.depth = depth; 1912 efi_fb_info.stride = efifb->fb_stride * (depth / 8); 1913 efi_fb_info.paddr = efifb->fb_addr; 1914 if (early) { 1915 efi_fb_info.vaddr = 0; 1916 } else { 1917 efi_fb_init_vaddr(0); 1918 } 1919 efi_fb_info.fbops.fb_set_par = NULL; 1920 efi_fb_info.fbops.fb_blank = NULL; 1921 efi_fb_info.fbops.fb_debug_enter = NULL; 1922 efi_fb_info.device = NULL; 1923 1924 return 0; 1925 } 1926 1927 static void 1928 efifb_startup(void *arg) 1929 { 1930 probe_efi_fb(0); 1931 } 1932 1933 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1934 1935 static void 1936 getmemsize(caddr_t kmdp, u_int64_t first) 1937 { 1938 int off, physmap_idx, pa_indx, da_indx; 1939 int i, j; 1940 vm_paddr_t pa; 1941 vm_paddr_t msgbuf_size; 1942 u_long physmem_tunable; 1943 pt_entry_t *pte; 1944 quad_t dcons_addr, dcons_size; 1945 1946 bzero(physmap, sizeof(physmap)); 1947 physmap_idx = 0; 1948 1949 /* 1950 * get memory map from INT 15:E820, kindly supplied by the loader. 1951 * 1952 * subr_module.c says: 1953 * "Consumer may safely assume that size value precedes data." 1954 * ie: an int32_t immediately precedes smap. 1955 */ 1956 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1957 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1958 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1959 MODINFO_METADATA | MODINFOMD_SMAP); 1960 if (smapbase == NULL && efihdrbase == NULL) 1961 panic("No BIOS smap or EFI map info from loader!"); 1962 1963 if (efihdrbase == NULL) 1964 add_smap_entries(&physmap_idx); 1965 else 1966 add_efi_map_entries(&physmap_idx); 1967 1968 base_memory = physmap[1] / 1024; 1969 /* make hole for AP bootstrap code */ 1970 physmap[1] = mp_bootaddress(base_memory); 1971 1972 /* Save EBDA address, if any */ 1973 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1974 ebda_addr <<= 4; 1975 1976 /* 1977 * Maxmem isn't the "maximum memory", it's one larger than the 1978 * highest page of the physical address space. It should be 1979 * called something like "Maxphyspage". We may adjust this 1980 * based on ``hw.physmem'' and the results of the memory test. 1981 */ 1982 Maxmem = atop(physmap[physmap_idx + 1]); 1983 1984 #ifdef MAXMEM 1985 Maxmem = MAXMEM / 4; 1986 #endif 1987 1988 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1989 Maxmem = atop(physmem_tunable); 1990 1991 /* 1992 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1993 * in the system. 1994 */ 1995 if (Maxmem > atop(physmap[physmap_idx + 1])) 1996 Maxmem = atop(physmap[physmap_idx + 1]); 1997 1998 /* 1999 * Blowing out the DMAP will blow up the system. 2000 */ 2001 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 2002 kprintf("Limiting Maxmem due to DMAP size\n"); 2003 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 2004 } 2005 2006 if (atop(physmap[physmap_idx + 1]) != Maxmem && 2007 (boothowto & RB_VERBOSE)) { 2008 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 2009 } 2010 2011 /* 2012 * Call pmap initialization to make new kernel address space 2013 * 2014 * Mask off page 0. 2015 */ 2016 pmap_bootstrap(&first); 2017 physmap[0] = PAGE_SIZE; 2018 2019 /* 2020 * Align the physmap to PHYSMAP_ALIGN and cut out anything 2021 * exceeding Maxmem. 2022 */ 2023 for (i = j = 0; i <= physmap_idx; i += 2) { 2024 if (physmap[i+1] > ptoa(Maxmem)) 2025 physmap[i+1] = ptoa(Maxmem); 2026 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 2027 ~PHYSMAP_ALIGN_MASK; 2028 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 2029 2030 physmap[j] = physmap[i]; 2031 physmap[j+1] = physmap[i+1]; 2032 2033 if (physmap[i] < physmap[i+1]) 2034 j += 2; 2035 } 2036 physmap_idx = j - 2; 2037 2038 /* 2039 * Align anything else used in the validation loop. 2040 * 2041 * Also make sure that our 2MB kernel text+data+bss mappings 2042 * do not overlap potentially allocatable space. 2043 */ 2044 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2045 2046 /* 2047 * Size up each available chunk of physical memory. 2048 */ 2049 pa_indx = 0; 2050 da_indx = 0; 2051 phys_avail[pa_indx].phys_beg = physmap[0]; 2052 phys_avail[pa_indx].phys_end = physmap[0]; 2053 dump_avail[da_indx].phys_beg = 0; 2054 dump_avail[da_indx].phys_end = physmap[0]; 2055 pte = CMAP1; 2056 2057 /* 2058 * Get dcons buffer address 2059 */ 2060 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2061 kgetenv_quad("dcons.size", &dcons_size) == 0) 2062 dcons_addr = 0; 2063 2064 /* 2065 * Validate the physical memory. The physical memory segments 2066 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2067 * of PAGE_SIZE. 2068 * 2069 * We no longer perform an exhaustive memory test. Instead we 2070 * simply test the first and last word in each physmap[] 2071 * segment. 2072 */ 2073 for (i = 0; i <= physmap_idx; i += 2) { 2074 vm_paddr_t end; 2075 vm_paddr_t incr; 2076 2077 end = physmap[i + 1]; 2078 2079 for (pa = physmap[i]; pa < end; pa += incr) { 2080 int page_bad, full; 2081 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2082 uint64_t tmp; 2083 2084 full = FALSE; 2085 2086 /* 2087 * Calculate incr. Just test the first and 2088 * last page in each physmap[] segment. 2089 */ 2090 if (pa == end - PAGE_SIZE) 2091 incr = PAGE_SIZE; 2092 else 2093 incr = end - pa - PAGE_SIZE; 2094 2095 /* 2096 * Make sure we don't skip blacked out areas. 2097 */ 2098 if (pa < 0x200000 && 0x200000 < end) { 2099 incr = 0x200000 - pa; 2100 } 2101 if (dcons_addr > 0 && 2102 pa < dcons_addr && 2103 dcons_addr < end) { 2104 incr = dcons_addr - pa; 2105 } 2106 2107 /* 2108 * Block out kernel memory as not available. 2109 */ 2110 if (pa >= 0x200000 && pa < first) { 2111 incr = first - pa; 2112 if (pa + incr > end) 2113 incr = end - pa; 2114 goto do_dump_avail; 2115 } 2116 2117 /* 2118 * Block out the dcons buffer if it exists. 2119 */ 2120 if (dcons_addr > 0 && 2121 pa >= trunc_page(dcons_addr) && 2122 pa < dcons_addr + dcons_size) { 2123 incr = dcons_addr + dcons_size - pa; 2124 incr = (incr + PAGE_MASK) & 2125 ~(vm_paddr_t)PAGE_MASK; 2126 if (pa + incr > end) 2127 incr = end - pa; 2128 goto do_dump_avail; 2129 } 2130 2131 page_bad = FALSE; 2132 2133 /* 2134 * Map the page non-cacheable for the memory 2135 * test. 2136 */ 2137 *pte = pa | 2138 kernel_pmap.pmap_bits[PG_V_IDX] | 2139 kernel_pmap.pmap_bits[PG_RW_IDX] | 2140 kernel_pmap.pmap_bits[PG_N_IDX]; 2141 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2142 cpu_mfence(); 2143 2144 /* 2145 * Save original value for restoration later. 2146 */ 2147 tmp = *ptr; 2148 2149 /* 2150 * Test for alternating 1's and 0's 2151 */ 2152 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2153 cpu_mfence(); 2154 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2155 page_bad = TRUE; 2156 /* 2157 * Test for alternating 0's and 1's 2158 */ 2159 *ptr = 0x5555555555555555LLU; 2160 cpu_mfence(); 2161 if (*ptr != 0x5555555555555555LLU) 2162 page_bad = TRUE; 2163 /* 2164 * Test for all 1's 2165 */ 2166 *ptr = 0xffffffffffffffffLLU; 2167 cpu_mfence(); 2168 if (*ptr != 0xffffffffffffffffLLU) 2169 page_bad = TRUE; 2170 /* 2171 * Test for all 0's 2172 */ 2173 *ptr = 0x0; 2174 cpu_mfence(); 2175 if (*ptr != 0x0) 2176 page_bad = TRUE; 2177 2178 /* 2179 * Restore original value. 2180 */ 2181 *ptr = tmp; 2182 2183 /* 2184 * Adjust array of valid/good pages. 2185 */ 2186 if (page_bad == TRUE) { 2187 incr = PAGE_SIZE; 2188 continue; 2189 } 2190 2191 /* 2192 * Collapse page address into phys_avail[]. Do a 2193 * continuation of the current phys_avail[] index 2194 * when possible. 2195 */ 2196 if (phys_avail[pa_indx].phys_end == pa) { 2197 /* 2198 * Continuation 2199 */ 2200 phys_avail[pa_indx].phys_end += incr; 2201 } else if (phys_avail[pa_indx].phys_beg == 2202 phys_avail[pa_indx].phys_end) { 2203 /* 2204 * Current phys_avail is completely empty, 2205 * reuse the index. 2206 */ 2207 phys_avail[pa_indx].phys_beg = pa; 2208 phys_avail[pa_indx].phys_end = pa + incr; 2209 } else { 2210 /* 2211 * Allocate next phys_avail index. 2212 */ 2213 ++pa_indx; 2214 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2215 kprintf( 2216 "Too many holes in the physical address space, giving up\n"); 2217 --pa_indx; 2218 full = TRUE; 2219 goto do_dump_avail; 2220 } 2221 phys_avail[pa_indx].phys_beg = pa; 2222 phys_avail[pa_indx].phys_end = pa + incr; 2223 } 2224 physmem += incr / PAGE_SIZE; 2225 2226 /* 2227 * pa available for dumping 2228 */ 2229 do_dump_avail: 2230 if (dump_avail[da_indx].phys_end == pa) { 2231 dump_avail[da_indx].phys_end += incr; 2232 } else { 2233 ++da_indx; 2234 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2235 --da_indx; 2236 goto do_next; 2237 } 2238 dump_avail[da_indx].phys_beg = pa; 2239 dump_avail[da_indx].phys_end = pa + incr; 2240 } 2241 do_next: 2242 if (full) 2243 break; 2244 } 2245 } 2246 *pte = 0; 2247 cpu_invltlb(); 2248 cpu_mfence(); 2249 2250 /* 2251 * The last chunk must contain at least one page plus the message 2252 * buffer to avoid complicating other code (message buffer address 2253 * calculation, etc.). 2254 */ 2255 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2256 2257 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2258 phys_avail[pa_indx].phys_end) { 2259 physmem -= atop(phys_avail[pa_indx].phys_end - 2260 phys_avail[pa_indx].phys_beg); 2261 phys_avail[pa_indx].phys_beg = 0; 2262 phys_avail[pa_indx].phys_end = 0; 2263 --pa_indx; 2264 } 2265 2266 Maxmem = atop(phys_avail[pa_indx].phys_end); 2267 2268 /* Trim off space for the message buffer. */ 2269 phys_avail[pa_indx].phys_end -= msgbuf_size; 2270 2271 avail_end = phys_avail[pa_indx].phys_end; 2272 2273 /* Map the message buffer. */ 2274 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2275 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2276 } 2277 /* Try to get EFI framebuffer working as early as possible */ 2278 if (have_efi_framebuffer) 2279 efi_fb_init_vaddr(1); 2280 } 2281 2282 struct machintr_abi MachIntrABI; 2283 2284 /* 2285 * IDT VECTORS: 2286 * 0 Divide by zero 2287 * 1 Debug 2288 * 2 NMI 2289 * 3 BreakPoint 2290 * 4 OverFlow 2291 * 5 Bound-Range 2292 * 6 Invalid OpCode 2293 * 7 Device Not Available (x87) 2294 * 8 Double-Fault 2295 * 9 Coprocessor Segment overrun (unsupported, reserved) 2296 * 10 Invalid-TSS 2297 * 11 Segment not present 2298 * 12 Stack 2299 * 13 General Protection 2300 * 14 Page Fault 2301 * 15 Reserved 2302 * 16 x87 FP Exception pending 2303 * 17 Alignment Check 2304 * 18 Machine Check 2305 * 19 SIMD floating point 2306 * 20-31 reserved 2307 * 32-255 INTn/external sources 2308 */ 2309 u_int64_t 2310 hammer_time(u_int64_t modulep, u_int64_t physfree) 2311 { 2312 caddr_t kmdp; 2313 int gsel_tss, x, cpu; 2314 #if 0 /* JG */ 2315 int metadata_missing, off; 2316 #endif 2317 struct mdglobaldata *gd; 2318 u_int64_t msr; 2319 2320 /* 2321 * Prevent lowering of the ipl if we call tsleep() early. 2322 */ 2323 gd = &CPU_prvspace[0]->mdglobaldata; 2324 bzero(gd, sizeof(*gd)); 2325 2326 /* 2327 * Note: on both UP and SMP curthread must be set non-NULL 2328 * early in the boot sequence because the system assumes 2329 * that 'curthread' is never NULL. 2330 */ 2331 2332 gd->mi.gd_curthread = &thread0; 2333 thread0.td_gd = &gd->mi; 2334 2335 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2336 2337 #if 0 /* JG */ 2338 metadata_missing = 0; 2339 if (bootinfo.bi_modulep) { 2340 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2341 preload_bootstrap_relocate(KERNBASE); 2342 } else { 2343 metadata_missing = 1; 2344 } 2345 if (bootinfo.bi_envp) 2346 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2347 #endif 2348 2349 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2350 preload_bootstrap_relocate(PTOV_OFFSET); 2351 kmdp = preload_search_by_type("elf kernel"); 2352 if (kmdp == NULL) 2353 kmdp = preload_search_by_type("elf64 kernel"); 2354 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2355 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2356 #ifdef DDB 2357 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2358 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2359 #endif 2360 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2361 2362 if (boothowto & RB_VERBOSE) 2363 bootverbose++; 2364 2365 /* 2366 * Default MachIntrABI to ICU 2367 */ 2368 MachIntrABI = MachIntrABI_ICU; 2369 2370 /* 2371 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2372 */ 2373 ncpus = 1; 2374 ncpus_fit = 1; 2375 /* Init basic tunables, hz etc */ 2376 init_param1(); 2377 2378 /* 2379 * make gdt memory segments 2380 */ 2381 gdt_segs[GPROC0_SEL].ssd_base = 2382 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 2383 2384 gd->mi.gd_prvspace = CPU_prvspace[0]; 2385 2386 for (x = 0; x < NGDT; x++) { 2387 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2388 ssdtosd(&gdt_segs[x], &gdt[x]); 2389 } 2390 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2391 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2392 2393 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2394 r_gdt.rd_base = (long) gdt; 2395 lgdt(&r_gdt); 2396 2397 wrmsr(MSR_FSBASE, 0); /* User value */ 2398 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2399 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2400 2401 mi_gdinit(&gd->mi, 0); 2402 cpu_gdinit(gd, 0); 2403 proc0paddr = proc0paddr_buff; 2404 mi_proc0init(&gd->mi, proc0paddr); 2405 safepri = TDPRI_MAX; 2406 2407 /* spinlocks and the BGL */ 2408 init_locks(); 2409 2410 /* exceptions */ 2411 for (x = 0; x < NIDT; x++) 2412 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2413 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2414 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2415 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2416 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2417 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2418 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2419 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2420 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2421 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2422 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2423 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2424 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2425 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2426 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2427 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2428 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2429 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2430 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2431 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2432 2433 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2434 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2435 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2436 } 2437 2438 lidt(&r_idt_arr[0]); 2439 2440 /* 2441 * Initialize the console before we print anything out. 2442 */ 2443 cninit(); 2444 2445 #if 0 /* JG */ 2446 if (metadata_missing) 2447 kprintf("WARNING: loader(8) metadata is missing!\n"); 2448 #endif 2449 2450 #if NISA >0 2451 elcr_probe(); 2452 isa_defaultirq(); 2453 #endif 2454 rand_initialize(); 2455 2456 /* 2457 * Initialize IRQ mapping 2458 * 2459 * NOTE: 2460 * SHOULD be after elcr_probe() 2461 */ 2462 MachIntrABI_ICU.initmap(); 2463 MachIntrABI_IOAPIC.initmap(); 2464 2465 #ifdef DDB 2466 kdb_init(); 2467 if (boothowto & RB_KDB) 2468 Debugger("Boot flags requested debugger"); 2469 #endif 2470 2471 identify_cpu(); /* Final stage of CPU initialization */ 2472 initializecpu(0); /* Initialize CPU registers */ 2473 2474 /* 2475 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2476 * because the cpu does significant power management in MWAIT 2477 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2478 * 2479 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2480 * significant power management only when using ACPI halt mode. 2481 * 2482 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2483 * is needed to reduce power consumption, but wakeup times are often 2484 * too long longer. 2485 */ 2486 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2487 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2488 cpu_idle_hlt = 1; 2489 } 2490 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2491 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2492 /* Ryzen or later */ 2493 cpu_idle_hlt = 3; 2494 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2495 /* Bobcat or later */ 2496 cpu_idle_hlt = 3; 2497 } 2498 } 2499 2500 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2501 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2502 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2503 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2504 2505 /* 2506 * Some of the virtual machines do not work w/ I/O APIC 2507 * enabled. If the user does not explicitly enable or 2508 * disable the I/O APIC (ioapic_enable < 0), then we 2509 * disable I/O APIC on all virtual machines. 2510 * 2511 * NOTE: 2512 * This must be done after identify_cpu(), which sets 2513 * 'cpu_feature2' 2514 */ 2515 if (ioapic_enable < 0) { 2516 if (cpu_feature2 & CPUID2_VMM) 2517 ioapic_enable = 0; 2518 else 2519 ioapic_enable = 1; 2520 } 2521 2522 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2523 gd->gd_common_tss.tss_rsp0 = 2524 (register_t)(thread0.td_kstack + 2525 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2526 /* Ensure the stack is aligned to 16 bytes */ 2527 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2528 2529 /* double fault stack */ 2530 gd->gd_common_tss.tss_ist1 = 2531 (long)&gd->mi.gd_prvspace->idlestack[ 2532 sizeof(gd->mi.gd_prvspace->idlestack)]; 2533 2534 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2535 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2536 2537 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2538 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2539 gd->gd_common_tssd = *gd->gd_tss_gdt; 2540 ltr(gsel_tss); 2541 2542 /* Set up the fast syscall stuff */ 2543 msr = rdmsr(MSR_EFER) | EFER_SCE; 2544 wrmsr(MSR_EFER, msr); 2545 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2546 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2547 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2548 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2549 wrmsr(MSR_STAR, msr); 2550 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2551 2552 getmemsize(kmdp, physfree); 2553 init_param2(physmem); 2554 2555 /* now running on new page tables, configured,and u/iom is accessible */ 2556 2557 /* Map the message buffer. */ 2558 #if 0 /* JG */ 2559 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2560 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2561 #endif 2562 2563 msgbufinit(msgbufp, MSGBUF_SIZE); 2564 2565 2566 /* transfer to user mode */ 2567 2568 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2569 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2570 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2571 2572 load_ds(_udatasel); 2573 load_es(_udatasel); 2574 load_fs(_udatasel); 2575 2576 /* setup proc 0's pcb */ 2577 thread0.td_pcb->pcb_flags = 0; 2578 thread0.td_pcb->pcb_cr3 = KPML4phys; 2579 thread0.td_pcb->pcb_ext = NULL; 2580 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2581 2582 /* Location of kernel stack for locore */ 2583 return ((u_int64_t)thread0.td_pcb); 2584 } 2585 2586 /* 2587 * Initialize machine-dependant portions of the global data structure. 2588 * Note that the global data area and cpu0's idlestack in the private 2589 * data space were allocated in locore. 2590 * 2591 * Note: the idlethread's cpl is 0 2592 * 2593 * WARNING! Called from early boot, 'mycpu' may not work yet. 2594 */ 2595 void 2596 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2597 { 2598 if (cpu) 2599 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2600 2601 lwkt_init_thread(&gd->mi.gd_idlethread, 2602 gd->mi.gd_prvspace->idlestack, 2603 sizeof(gd->mi.gd_prvspace->idlestack), 2604 0, &gd->mi); 2605 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2606 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2607 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2608 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2609 } 2610 2611 /* 2612 * We only have to check for DMAP bounds, the globaldata space is 2613 * actually part of the kernel_map so we don't have to waste time 2614 * checking CPU_prvspace[*]. 2615 */ 2616 int 2617 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2618 { 2619 #if 0 2620 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2621 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2622 return (TRUE); 2623 } 2624 #endif 2625 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2626 return (TRUE); 2627 return (FALSE); 2628 } 2629 2630 struct globaldata * 2631 globaldata_find(int cpu) 2632 { 2633 KKASSERT(cpu >= 0 && cpu < ncpus); 2634 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2635 } 2636 2637 /* 2638 * This path should be safe from the SYSRET issue because only stopped threads 2639 * can have their %rip adjusted this way (and all heavy weight thread switches 2640 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2641 * convoluted so add a safety by forcing %rip to be cannonical. 2642 */ 2643 int 2644 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2645 { 2646 if (addr & 0x0000800000000000LLU) 2647 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2648 else 2649 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2650 return (0); 2651 } 2652 2653 int 2654 ptrace_single_step(struct lwp *lp) 2655 { 2656 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2657 return (0); 2658 } 2659 2660 int 2661 fill_regs(struct lwp *lp, struct reg *regs) 2662 { 2663 struct trapframe *tp; 2664 2665 if ((tp = lp->lwp_md.md_regs) == NULL) 2666 return EINVAL; 2667 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2668 return (0); 2669 } 2670 2671 int 2672 set_regs(struct lwp *lp, struct reg *regs) 2673 { 2674 struct trapframe *tp; 2675 2676 tp = lp->lwp_md.md_regs; 2677 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2678 !CS_SECURE(regs->r_cs)) 2679 return (EINVAL); 2680 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2681 clear_quickret(); 2682 return (0); 2683 } 2684 2685 static void 2686 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2687 { 2688 struct env87 *penv_87 = &sv_87->sv_env; 2689 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2690 int i; 2691 2692 /* FPU control/status */ 2693 penv_87->en_cw = penv_xmm->en_cw; 2694 penv_87->en_sw = penv_xmm->en_sw; 2695 penv_87->en_tw = penv_xmm->en_tw; 2696 penv_87->en_fip = penv_xmm->en_fip; 2697 penv_87->en_fcs = penv_xmm->en_fcs; 2698 penv_87->en_opcode = penv_xmm->en_opcode; 2699 penv_87->en_foo = penv_xmm->en_foo; 2700 penv_87->en_fos = penv_xmm->en_fos; 2701 2702 /* FPU registers */ 2703 for (i = 0; i < 8; ++i) 2704 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2705 } 2706 2707 static void 2708 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2709 { 2710 struct env87 *penv_87 = &sv_87->sv_env; 2711 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2712 int i; 2713 2714 /* FPU control/status */ 2715 penv_xmm->en_cw = penv_87->en_cw; 2716 penv_xmm->en_sw = penv_87->en_sw; 2717 penv_xmm->en_tw = penv_87->en_tw; 2718 penv_xmm->en_fip = penv_87->en_fip; 2719 penv_xmm->en_fcs = penv_87->en_fcs; 2720 penv_xmm->en_opcode = penv_87->en_opcode; 2721 penv_xmm->en_foo = penv_87->en_foo; 2722 penv_xmm->en_fos = penv_87->en_fos; 2723 2724 /* FPU registers */ 2725 for (i = 0; i < 8; ++i) 2726 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2727 } 2728 2729 int 2730 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2731 { 2732 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2733 return EINVAL; 2734 if (cpu_fxsr) { 2735 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2736 (struct save87 *)fpregs); 2737 return (0); 2738 } 2739 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2740 return (0); 2741 } 2742 2743 int 2744 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2745 { 2746 if (cpu_fxsr) { 2747 set_fpregs_xmm((struct save87 *)fpregs, 2748 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2749 return (0); 2750 } 2751 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2752 return (0); 2753 } 2754 2755 int 2756 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2757 { 2758 struct pcb *pcb; 2759 2760 if (lp == NULL) { 2761 dbregs->dr[0] = rdr0(); 2762 dbregs->dr[1] = rdr1(); 2763 dbregs->dr[2] = rdr2(); 2764 dbregs->dr[3] = rdr3(); 2765 dbregs->dr[4] = rdr4(); 2766 dbregs->dr[5] = rdr5(); 2767 dbregs->dr[6] = rdr6(); 2768 dbregs->dr[7] = rdr7(); 2769 return (0); 2770 } 2771 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2772 return EINVAL; 2773 dbregs->dr[0] = pcb->pcb_dr0; 2774 dbregs->dr[1] = pcb->pcb_dr1; 2775 dbregs->dr[2] = pcb->pcb_dr2; 2776 dbregs->dr[3] = pcb->pcb_dr3; 2777 dbregs->dr[4] = 0; 2778 dbregs->dr[5] = 0; 2779 dbregs->dr[6] = pcb->pcb_dr6; 2780 dbregs->dr[7] = pcb->pcb_dr7; 2781 return (0); 2782 } 2783 2784 int 2785 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2786 { 2787 if (lp == NULL) { 2788 load_dr0(dbregs->dr[0]); 2789 load_dr1(dbregs->dr[1]); 2790 load_dr2(dbregs->dr[2]); 2791 load_dr3(dbregs->dr[3]); 2792 load_dr4(dbregs->dr[4]); 2793 load_dr5(dbregs->dr[5]); 2794 load_dr6(dbregs->dr[6]); 2795 load_dr7(dbregs->dr[7]); 2796 } else { 2797 struct pcb *pcb; 2798 struct ucred *ucred; 2799 int i; 2800 uint64_t mask1, mask2; 2801 2802 /* 2803 * Don't let an illegal value for dr7 get set. Specifically, 2804 * check for undefined settings. Setting these bit patterns 2805 * result in undefined behaviour and can lead to an unexpected 2806 * TRCTRAP. 2807 */ 2808 /* JG this loop looks unreadable */ 2809 /* Check 4 2-bit fields for invalid patterns. 2810 * These fields are R/Wi, for i = 0..3 2811 */ 2812 /* Is 10 in LENi allowed when running in compatibility mode? */ 2813 /* Pattern 10 in R/Wi might be used to indicate 2814 * breakpoint on I/O. Further analysis should be 2815 * carried to decide if it is safe and useful to 2816 * provide access to that capability 2817 */ 2818 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2819 i++, mask1 <<= 4, mask2 <<= 4) 2820 if ((dbregs->dr[7] & mask1) == mask2) 2821 return (EINVAL); 2822 2823 pcb = lp->lwp_thread->td_pcb; 2824 ucred = lp->lwp_proc->p_ucred; 2825 2826 /* 2827 * Don't let a process set a breakpoint that is not within the 2828 * process's address space. If a process could do this, it 2829 * could halt the system by setting a breakpoint in the kernel 2830 * (if ddb was enabled). Thus, we need to check to make sure 2831 * that no breakpoints are being enabled for addresses outside 2832 * process's address space, unless, perhaps, we were called by 2833 * uid 0. 2834 * 2835 * XXX - what about when the watched area of the user's 2836 * address space is written into from within the kernel 2837 * ... wouldn't that still cause a breakpoint to be generated 2838 * from within kernel mode? 2839 */ 2840 2841 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2842 if (dbregs->dr[7] & 0x3) { 2843 /* dr0 is enabled */ 2844 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2845 return (EINVAL); 2846 } 2847 2848 if (dbregs->dr[7] & (0x3<<2)) { 2849 /* dr1 is enabled */ 2850 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2851 return (EINVAL); 2852 } 2853 2854 if (dbregs->dr[7] & (0x3<<4)) { 2855 /* dr2 is enabled */ 2856 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2857 return (EINVAL); 2858 } 2859 2860 if (dbregs->dr[7] & (0x3<<6)) { 2861 /* dr3 is enabled */ 2862 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2863 return (EINVAL); 2864 } 2865 } 2866 2867 pcb->pcb_dr0 = dbregs->dr[0]; 2868 pcb->pcb_dr1 = dbregs->dr[1]; 2869 pcb->pcb_dr2 = dbregs->dr[2]; 2870 pcb->pcb_dr3 = dbregs->dr[3]; 2871 pcb->pcb_dr6 = dbregs->dr[6]; 2872 pcb->pcb_dr7 = dbregs->dr[7]; 2873 2874 pcb->pcb_flags |= PCB_DBREGS; 2875 } 2876 2877 return (0); 2878 } 2879 2880 /* 2881 * Return > 0 if a hardware breakpoint has been hit, and the 2882 * breakpoint was in user space. Return 0, otherwise. 2883 */ 2884 int 2885 user_dbreg_trap(void) 2886 { 2887 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2888 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2889 int nbp; /* number of breakpoints that triggered */ 2890 caddr_t addr[4]; /* breakpoint addresses */ 2891 int i; 2892 2893 dr7 = rdr7(); 2894 if ((dr7 & 0xff) == 0) { 2895 /* 2896 * all GE and LE bits in the dr7 register are zero, 2897 * thus the trap couldn't have been caused by the 2898 * hardware debug registers 2899 */ 2900 return 0; 2901 } 2902 2903 nbp = 0; 2904 dr6 = rdr6(); 2905 bp = dr6 & 0xf; 2906 2907 if (bp == 0) { 2908 /* 2909 * None of the breakpoint bits are set meaning this 2910 * trap was not caused by any of the debug registers 2911 */ 2912 return 0; 2913 } 2914 2915 /* 2916 * at least one of the breakpoints were hit, check to see 2917 * which ones and if any of them are user space addresses 2918 */ 2919 2920 if (bp & 0x01) { 2921 addr[nbp++] = (caddr_t)rdr0(); 2922 } 2923 if (bp & 0x02) { 2924 addr[nbp++] = (caddr_t)rdr1(); 2925 } 2926 if (bp & 0x04) { 2927 addr[nbp++] = (caddr_t)rdr2(); 2928 } 2929 if (bp & 0x08) { 2930 addr[nbp++] = (caddr_t)rdr3(); 2931 } 2932 2933 for (i=0; i<nbp; i++) { 2934 if (addr[i] < 2935 (caddr_t)VM_MAX_USER_ADDRESS) { 2936 /* 2937 * addr[i] is in user space 2938 */ 2939 return nbp; 2940 } 2941 } 2942 2943 /* 2944 * None of the breakpoints are in user space. 2945 */ 2946 return 0; 2947 } 2948 2949 2950 #ifndef DDB 2951 void 2952 Debugger(const char *msg) 2953 { 2954 kprintf("Debugger(\"%s\") called.\n", msg); 2955 } 2956 #endif /* no DDB */ 2957 2958 #ifdef DDB 2959 2960 /* 2961 * Provide inb() and outb() as functions. They are normally only 2962 * available as macros calling inlined functions, thus cannot be 2963 * called inside DDB. 2964 * 2965 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2966 */ 2967 2968 #undef inb 2969 #undef outb 2970 2971 /* silence compiler warnings */ 2972 u_char inb(u_int); 2973 void outb(u_int, u_char); 2974 2975 u_char 2976 inb(u_int port) 2977 { 2978 u_char data; 2979 /* 2980 * We use %%dx and not %1 here because i/o is done at %dx and not at 2981 * %edx, while gcc generates inferior code (movw instead of movl) 2982 * if we tell it to load (u_short) port. 2983 */ 2984 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2985 return (data); 2986 } 2987 2988 void 2989 outb(u_int port, u_char data) 2990 { 2991 u_char al; 2992 /* 2993 * Use an unnecessary assignment to help gcc's register allocator. 2994 * This make a large difference for gcc-1.40 and a tiny difference 2995 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2996 * best results. gcc-2.6.0 can't handle this. 2997 */ 2998 al = data; 2999 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 3000 } 3001 3002 #endif /* DDB */ 3003 3004 3005 3006 /* 3007 * initialize all the SMP locks 3008 */ 3009 3010 /* critical region when masking or unmasking interupts */ 3011 struct spinlock_deprecated imen_spinlock; 3012 3013 /* lock region used by kernel profiling */ 3014 struct spinlock_deprecated mcount_spinlock; 3015 3016 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 3017 struct spinlock_deprecated com_spinlock; 3018 3019 /* lock regions around the clock hardware */ 3020 struct spinlock_deprecated clock_spinlock; 3021 3022 static void 3023 init_locks(void) 3024 { 3025 /* 3026 * Get the initial mplock with a count of 1 for the BSP. 3027 * This uses a LOGICAL cpu ID, ie BSP == 0. 3028 */ 3029 cpu_get_initial_mplock(); 3030 /* DEPRECATED */ 3031 spin_init_deprecated(&mcount_spinlock); 3032 spin_init_deprecated(&imen_spinlock); 3033 spin_init_deprecated(&com_spinlock); 3034 spin_init_deprecated(&clock_spinlock); 3035 3036 /* our token pool needs to work early */ 3037 lwkt_token_pool_init(); 3038 } 3039 3040 boolean_t 3041 cpu_mwait_hint_valid(uint32_t hint) 3042 { 3043 int cx_idx, sub; 3044 3045 cx_idx = MWAIT_EAX_TO_CX(hint); 3046 if (cx_idx >= CPU_MWAIT_CX_MAX) 3047 return FALSE; 3048 3049 sub = MWAIT_EAX_TO_CX_SUB(hint); 3050 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3051 return FALSE; 3052 3053 return TRUE; 3054 } 3055 3056 void 3057 cpu_mwait_cx_no_bmsts(void) 3058 { 3059 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 3060 } 3061 3062 void 3063 cpu_mwait_cx_no_bmarb(void) 3064 { 3065 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 3066 } 3067 3068 static int 3069 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 3070 { 3071 int old_cx_idx, sub = 0; 3072 3073 if (hint >= 0) { 3074 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3075 sub = MWAIT_EAX_TO_CX_SUB(hint); 3076 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3077 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3078 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3079 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3080 } else { 3081 old_cx_idx = CPU_MWAIT_CX_MAX; 3082 } 3083 3084 if (!CPU_MWAIT_HAS_CX) 3085 strlcpy(name, "NONE", namelen); 3086 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3087 strlcpy(name, "AUTO", namelen); 3088 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3089 strlcpy(name, "AUTODEEP", namelen); 3090 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3091 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3092 strlcpy(name, "INVALID", namelen); 3093 else 3094 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3095 3096 return old_cx_idx; 3097 } 3098 3099 static int 3100 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3101 { 3102 int cx_idx, sub, hint; 3103 char *ptr, *start; 3104 3105 if (allow_auto && strcmp(name, "AUTO") == 0) { 3106 hint = CPU_MWAIT_HINT_AUTO; 3107 cx_idx = CPU_MWAIT_C2; 3108 goto done; 3109 } 3110 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3111 hint = CPU_MWAIT_HINT_AUTODEEP; 3112 cx_idx = CPU_MWAIT_C3; 3113 goto done; 3114 } 3115 3116 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3117 return -1; 3118 start = &name[1]; 3119 ptr = NULL; 3120 3121 cx_idx = strtol(start, &ptr, 10); 3122 if (ptr == start || *ptr != '/') 3123 return -1; 3124 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3125 return -1; 3126 3127 start = ptr + 1; 3128 ptr = NULL; 3129 3130 sub = strtol(start, &ptr, 10); 3131 if (*ptr != '\0') 3132 return -1; 3133 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3134 return -1; 3135 3136 hint = MWAIT_EAX_HINT(cx_idx, sub); 3137 done: 3138 *hint0 = hint; 3139 return cx_idx; 3140 } 3141 3142 static int 3143 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3144 { 3145 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3146 return EOPNOTSUPP; 3147 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3148 int error; 3149 3150 error = cputimer_intr_powersave_addreq(); 3151 if (error) 3152 return error; 3153 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3154 cputimer_intr_powersave_remreq(); 3155 } 3156 return 0; 3157 } 3158 3159 static int 3160 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3161 boolean_t allow_auto) 3162 { 3163 int error, cx_idx, old_cx_idx, hint; 3164 char name[CPU_MWAIT_CX_NAMELEN]; 3165 3166 hint = *hint0; 3167 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3168 allow_auto); 3169 3170 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3171 if (error != 0 || req->newptr == NULL) 3172 return error; 3173 3174 if (!CPU_MWAIT_HAS_CX) 3175 return EOPNOTSUPP; 3176 3177 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3178 if (cx_idx < 0) 3179 return EINVAL; 3180 3181 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3182 if (error) 3183 return error; 3184 3185 *hint0 = hint; 3186 return 0; 3187 } 3188 3189 static int 3190 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3191 { 3192 int error, cx_idx, old_cx_idx, hint; 3193 char name[CPU_MWAIT_CX_NAMELEN]; 3194 3195 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3196 3197 hint = stat->hint; 3198 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3199 3200 strlcpy(name, cx_name, sizeof(name)); 3201 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3202 if (cx_idx < 0) 3203 return EINVAL; 3204 3205 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3206 if (error) 3207 return error; 3208 3209 stat->hint = hint; 3210 return 0; 3211 } 3212 3213 static int 3214 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3215 { 3216 int hint = cpu_mwait_halt_global; 3217 int error, cx_idx, cpu; 3218 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3219 3220 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3221 3222 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3223 if (error != 0 || req->newptr == NULL) 3224 return error; 3225 3226 if (!CPU_MWAIT_HAS_CX) 3227 return EOPNOTSUPP; 3228 3229 /* Save name for later per-cpu CX configuration */ 3230 strlcpy(cx_name, name, sizeof(cx_name)); 3231 3232 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3233 if (cx_idx < 0) 3234 return EINVAL; 3235 3236 /* Change per-cpu CX configuration */ 3237 for (cpu = 0; cpu < ncpus; ++cpu) { 3238 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3239 if (error) 3240 return error; 3241 } 3242 3243 cpu_mwait_halt_global = hint; 3244 return 0; 3245 } 3246 3247 static int 3248 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3249 { 3250 struct cpu_idle_stat *stat = arg1; 3251 int error; 3252 3253 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3254 &stat->hint, TRUE); 3255 return error; 3256 } 3257 3258 static int 3259 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3260 { 3261 int error; 3262 3263 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3264 &cpu_mwait_spin, FALSE); 3265 return error; 3266 } 3267 3268 /* 3269 * This manual debugging code is called unconditionally from Xtimer 3270 * (the per-cpu timer interrupt) whether the current thread is in a 3271 * critical section or not) and can be useful in tracking down lockups. 3272 * 3273 * NOTE: MANUAL DEBUG CODE 3274 */ 3275 #if 0 3276 static int saveticks[SMP_MAXCPU]; 3277 static int savecounts[SMP_MAXCPU]; 3278 #endif 3279 3280 void 3281 pcpu_timer_always(struct intrframe *frame) 3282 { 3283 #if 0 3284 globaldata_t gd = mycpu; 3285 int cpu = gd->gd_cpuid; 3286 char buf[64]; 3287 short *gptr; 3288 int i; 3289 3290 if (cpu <= 20) { 3291 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3292 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3293 ++gptr; 3294 3295 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3296 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3297 gd->gd_infomsg); 3298 for (i = 0; buf[i]; ++i) { 3299 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3300 } 3301 } 3302 #if 0 3303 if (saveticks[gd->gd_cpuid] != ticks) { 3304 saveticks[gd->gd_cpuid] = ticks; 3305 savecounts[gd->gd_cpuid] = 0; 3306 } 3307 ++savecounts[gd->gd_cpuid]; 3308 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3309 panic("cpud %d panicing on ticks failure", 3310 gd->gd_cpuid); 3311 } 3312 for (i = 0; i < ncpus; ++i) { 3313 int delta; 3314 if (saveticks[i] && panicstr == NULL) { 3315 delta = saveticks[i] - ticks; 3316 if (delta < -10 || delta > 10) { 3317 panic("cpu %d panicing on cpu %d watchdog", 3318 gd->gd_cpuid, i); 3319 } 3320 } 3321 } 3322 #endif 3323 #endif 3324 } 3325