1 /*- 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 2008 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * William Jolitz. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $ 41 */ 42 43 //#include "use_npx.h" 44 #include "use_isa.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_msgbuf.h" 49 #include "opt_swap.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysproto.h> 54 #include <sys/signalvar.h> 55 #include <sys/kernel.h> 56 #include <sys/linker.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/priv.h> 60 #include <sys/buf.h> 61 #include <sys/reboot.h> 62 #include <sys/mbuf.h> 63 #include <sys/msgbuf.h> 64 #include <sys/sysent.h> 65 #include <sys/sysctl.h> 66 #include <sys/vmmeter.h> 67 #include <sys/bus.h> 68 #include <sys/usched.h> 69 #include <sys/reg.h> 70 #include <sys/sbuf.h> 71 #include <sys/ctype.h> 72 #include <sys/serialize.h> 73 #include <sys/systimer.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_param.h> 77 #include <sys/lock.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_page.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_pager.h> 83 #include <vm/vm_extern.h> 84 85 #include <sys/thread2.h> 86 #include <sys/mplock2.h> 87 #include <sys/mutex2.h> 88 89 #include <sys/user.h> 90 #include <sys/exec.h> 91 #include <sys/cons.h> 92 93 #include <sys/efi.h> 94 95 #include <ddb/ddb.h> 96 97 #include <machine/cpu.h> 98 #include <machine/clock.h> 99 #include <machine/specialreg.h> 100 #if 0 /* JG */ 101 #include <machine/bootinfo.h> 102 #endif 103 #include <machine/md_var.h> 104 #include <machine/metadata.h> 105 #include <machine/pc/bios.h> 106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */ 107 #include <machine/globaldata.h> /* CPU_prvspace */ 108 #include <machine/smp.h> 109 #include <machine/cputypes.h> 110 #include <machine/intr_machdep.h> 111 #include <machine/framebuffer.h> 112 113 #ifdef OLD_BUS_ARCH 114 #include <bus/isa/isa_device.h> 115 #endif 116 #include <machine_base/isa/isa_intr.h> 117 #include <bus/isa/rtc.h> 118 #include <sys/random.h> 119 #include <sys/ptrace.h> 120 #include <machine/sigframe.h> 121 122 #include <sys/machintr.h> 123 #include <machine_base/icu/icu_abi.h> 124 #include <machine_base/icu/elcr_var.h> 125 #include <machine_base/apic/lapic.h> 126 #include <machine_base/apic/ioapic.h> 127 #include <machine_base/apic/ioapic_abi.h> 128 #include <machine/mptable.h> 129 130 #define PHYSMAP_ENTRIES 10 131 132 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 133 134 extern void printcpuinfo(void); /* XXX header file */ 135 extern void identify_cpu(void); 136 #if 0 /* JG */ 137 extern void finishidentcpu(void); 138 #endif 139 extern void panicifcpuunsupported(void); 140 141 static void cpu_startup(void *); 142 static void pic_finish(void *); 143 static void cpu_finish(void *); 144 145 static void set_fpregs_xmm(struct save87 *, struct savexmm *); 146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *); 147 static void init_locks(void); 148 149 extern void pcpu_timer_always(struct intrframe *); 150 151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL); 153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL); 154 155 #ifdef DDB 156 extern vm_offset_t ksym_start, ksym_end; 157 #endif 158 159 struct privatespace CPU_prvspace_bsp __aligned(4096); 160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp }; 161 162 vm_paddr_t efi_systbl_phys; 163 int _udatasel, _ucodesel, _ucode32sel; 164 u_long atdevbase; 165 int64_t tsc_offsets[MAXCPU]; 166 cpumask_t smp_idleinvl_mask; 167 cpumask_t smp_idleinvl_reqs; 168 169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */ 170 171 #if defined(SWTCH_OPTIM_STATS) 172 extern int swtch_optim_stats; 173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats, 174 CTLFLAG_RD, &swtch_optim_stats, 0, ""); 175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count, 176 CTLFLAG_RD, &tlb_flush_count, 0, ""); 177 #endif 178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt, 179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, ""); 180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0, 181 "monitor/mwait target state"); 182 183 #define CPU_MWAIT_HAS_CX \ 184 ((cpu_feature2 & CPUID2_MON) && \ 185 (cpu_mwait_feature & CPUID_MWAIT_EXT)) 186 187 #define CPU_MWAIT_CX_NAMELEN 16 188 189 #define CPU_MWAIT_C1 1 190 #define CPU_MWAIT_C2 2 191 #define CPU_MWAIT_C3 3 192 #define CPU_MWAIT_CX_MAX 8 193 194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */ 195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */ 196 197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features"); 198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings"); 199 200 struct cpu_mwait_cx { 201 int subcnt; 202 char name[4]; 203 struct sysctl_ctx_list sysctl_ctx; 204 struct sysctl_oid *sysctl_tree; 205 }; 206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX]; 207 static char cpu_mwait_cx_supported[256]; 208 209 static int cpu_mwait_c1_hints_cnt; 210 static int cpu_mwait_hints_cnt; 211 static int *cpu_mwait_hints; 212 213 static int cpu_mwait_deep_hints_cnt; 214 static int *cpu_mwait_deep_hints; 215 216 #define CPU_IDLE_REPEAT_DEFAULT 750 217 218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT; 219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT; 220 static u_int cpu_mwait_repeat_shift = 1; 221 222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1 223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2 224 225 static int cpu_mwait_c3_preamble = 226 CPU_MWAIT_C3_PREAMBLE_BM_ARB | 227 CPU_MWAIT_C3_PREAMBLE_BM_STS; 228 229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD, 230 cpu_mwait_cx_supported, 0, "MWAIT supported C states"); 231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD, 232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask"); 233 234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, 235 int *, boolean_t); 236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS); 237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS); 238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS); 239 240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW, 241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", ""); 242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW, 243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", ""); 244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW, 245 &cpu_mwait_repeat_shift, 0, ""); 246 247 long physmem = 0; 248 249 u_long ebda_addr = 0; 250 251 int imcr_present = 0; 252 253 int naps = 0; /* # of Applications processors */ 254 255 u_int base_memory; 256 struct mtx dt_lock; /* lock for GDT and LDT */ 257 258 static int 259 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS) 260 { 261 u_long pmem = ctob(physmem); 262 263 int error = sysctl_handle_long(oidp, &pmem, 0, req); 264 return (error); 265 } 266 267 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD, 268 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)"); 269 270 static int 271 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS) 272 { 273 int error = sysctl_handle_int(oidp, 0, 274 ctob(physmem - vmstats.v_wire_count), req); 275 return (error); 276 } 277 278 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD, 279 0, 0, sysctl_hw_usermem, "IU", ""); 280 281 static int 282 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS) 283 { 284 int error = sysctl_handle_int(oidp, 0, 285 x86_64_btop(avail_end - avail_start), req); 286 return (error); 287 } 288 289 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD, 290 0, 0, sysctl_hw_availpages, "I", ""); 291 292 vm_paddr_t Maxmem; 293 vm_paddr_t Realmem; 294 295 /* 296 * The number of PHYSMAP entries must be one less than the number of 297 * PHYSSEG entries because the PHYSMAP entry that spans the largest 298 * physical address that is accessible by ISA DMA is split into two 299 * PHYSSEG entries. 300 */ 301 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1]; 302 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1]; 303 304 /* must be 1 less so 0 0 can signal end of chunks */ 305 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1) 306 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1) 307 308 static vm_offset_t buffer_sva, buffer_eva; 309 vm_offset_t clean_sva, clean_eva; 310 static vm_offset_t pager_sva, pager_eva; 311 static struct trapframe proc0_tf; 312 313 static void 314 cpu_startup(void *dummy) 315 { 316 caddr_t v; 317 vm_size_t size = 0; 318 vm_offset_t firstaddr; 319 320 /* 321 * Good {morning,afternoon,evening,night}. 322 */ 323 kprintf("%s", version); 324 startrtclock(); 325 printcpuinfo(); 326 panicifcpuunsupported(); 327 kprintf("real memory = %ju (%ju MB)\n", 328 (intmax_t)Realmem, 329 (intmax_t)Realmem / 1024 / 1024); 330 /* 331 * Display any holes after the first chunk of extended memory. 332 */ 333 if (bootverbose) { 334 int indx; 335 336 kprintf("Physical memory chunk(s):\n"); 337 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) { 338 vm_paddr_t size1; 339 340 size1 = phys_avail[indx].phys_end - 341 phys_avail[indx].phys_beg; 342 343 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n", 344 (intmax_t)phys_avail[indx].phys_beg, 345 (intmax_t)phys_avail[indx].phys_end - 1, 346 (intmax_t)size1, 347 (intmax_t)(size1 / PAGE_SIZE)); 348 } 349 } 350 351 /* 352 * Allocate space for system data structures. 353 * The first available kernel virtual address is in "v". 354 * As pages of kernel virtual memory are allocated, "v" is incremented. 355 * As pages of memory are allocated and cleared, 356 * "firstaddr" is incremented. 357 * An index into the kernel page table corresponding to the 358 * virtual memory address maintained in "v" is kept in "mapaddr". 359 */ 360 361 /* 362 * Make two passes. The first pass calculates how much memory is 363 * needed and allocates it. The second pass assigns virtual 364 * addresses to the various data structures. 365 */ 366 firstaddr = 0; 367 again: 368 v = (caddr_t)firstaddr; 369 370 #define valloc(name, type, num) \ 371 (name) = (type *)v; v = (caddr_t)((name)+(num)) 372 #define valloclim(name, type, num, lim) \ 373 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num))) 374 375 /* 376 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE. 377 * For the first 64MB of ram nominally allocate sufficient buffers to 378 * cover 1/4 of our ram. Beyond the first 64MB allocate additional 379 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing 380 * the buffer cache we limit the eventual kva reservation to 381 * maxbcache bytes. 382 * 383 * factor represents the 1/4 x ram conversion. 384 */ 385 if (nbuf == 0) { 386 long factor = 4 * NBUFCALCSIZE / 1024; 387 long kbytes = physmem * (PAGE_SIZE / 1024); 388 389 nbuf = 50; 390 if (kbytes > 4096) 391 nbuf += min((kbytes - 4096) / factor, 65536 / factor); 392 if (kbytes > 65536) 393 nbuf += (kbytes - 65536) * 2 / (factor * 5); 394 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE) 395 nbuf = maxbcache / NBUFCALCSIZE; 396 } 397 398 /* 399 * Do not allow the buffer_map to be more then 1/2 the size of the 400 * kernel_map. 401 */ 402 if (nbuf > (virtual_end - virtual_start + 403 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) { 404 nbuf = (virtual_end - virtual_start + 405 virtual2_end - virtual2_start) / (MAXBSIZE * 2); 406 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf); 407 } 408 409 /* 410 * Do not allow the buffer_map to use more than 50% of available 411 * physical-equivalent memory. Since the VM pages which back 412 * individual buffers are typically wired, having too many bufs 413 * can prevent the system from paging properly. 414 */ 415 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) { 416 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2); 417 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf); 418 } 419 420 /* 421 * Do not allow the sizeof(struct buf) * nbuf to exceed half of 422 * the valloc space which is just the virtual_end - virtual_start 423 * section. We use valloc() to allocate the buf header array. 424 */ 425 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) { 426 nbuf = (virtual_end - virtual_start) / 427 sizeof(struct buf) / 2; 428 kprintf("Warning: nbufs capped at %ld due to valloc " 429 "considerations\n", nbuf); 430 } 431 432 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8); 433 #ifdef NSWBUF_MIN 434 if (nswbuf_mem < NSWBUF_MIN) 435 nswbuf_mem = NSWBUF_MIN; 436 #endif 437 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16); 438 #ifdef NSWBUF_MIN 439 if (nswbuf_kva < NSWBUF_MIN) 440 nswbuf_kva = NSWBUF_MIN; 441 #endif 442 443 valloc(swbuf_mem, struct buf, nswbuf_mem); 444 valloc(swbuf_kva, struct buf, nswbuf_kva); 445 valloc(buf, struct buf, nbuf); 446 447 /* 448 * End of first pass, size has been calculated so allocate memory 449 */ 450 if (firstaddr == 0) { 451 size = (vm_size_t)(v - firstaddr); 452 firstaddr = kmem_alloc(&kernel_map, round_page(size), 453 VM_SUBSYS_BUF); 454 if (firstaddr == 0) 455 panic("startup: no room for tables"); 456 goto again; 457 } 458 459 /* 460 * End of second pass, addresses have been assigned 461 * 462 * nbuf is an int, make sure we don't overflow the field. 463 * 464 * On 64-bit systems we always reserve maximal allocations for 465 * buffer cache buffers and there are no fragmentation issues, 466 * so the KVA segment does not have to be excessively oversized. 467 */ 468 if ((vm_size_t)(v - firstaddr) != size) 469 panic("startup: table size inconsistency"); 470 471 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva, 472 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) + 473 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size); 474 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva, 475 ((vm_offset_t)(nbuf + 16) * MAXBSIZE)); 476 buffer_map.system_map = 1; 477 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva, 478 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) + 479 pager_map_size); 480 pager_map.system_map = 1; 481 kprintf("avail memory = %ju (%ju MB)\n", 482 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages), 483 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) / 484 1024 / 1024); 485 } 486 487 struct cpu_idle_stat { 488 int hint; 489 int reserved; 490 u_long halt; 491 u_long spin; 492 u_long repeat; 493 u_long repeat_last; 494 u_long repeat_delta; 495 u_long mwait_cx[CPU_MWAIT_CX_MAX]; 496 } __cachealign; 497 498 #define CPU_IDLE_STAT_HALT -1 499 #define CPU_IDLE_STAT_SPIN -2 500 501 static struct cpu_idle_stat cpu_idle_stats[MAXCPU]; 502 503 static int 504 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS) 505 { 506 int idx = arg2, cpu, error; 507 u_long val = 0; 508 509 if (idx == CPU_IDLE_STAT_HALT) { 510 for (cpu = 0; cpu < ncpus; ++cpu) 511 val += cpu_idle_stats[cpu].halt; 512 } else if (idx == CPU_IDLE_STAT_SPIN) { 513 for (cpu = 0; cpu < ncpus; ++cpu) 514 val += cpu_idle_stats[cpu].spin; 515 } else { 516 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 517 ("invalid index %d", idx)); 518 for (cpu = 0; cpu < ncpus; ++cpu) 519 val += cpu_idle_stats[cpu].mwait_cx[idx]; 520 } 521 522 error = sysctl_handle_quad(oidp, &val, 0, req); 523 if (error || req->newptr == NULL) 524 return error; 525 526 if (idx == CPU_IDLE_STAT_HALT) { 527 for (cpu = 0; cpu < ncpus; ++cpu) 528 cpu_idle_stats[cpu].halt = 0; 529 cpu_idle_stats[0].halt = val; 530 } else if (idx == CPU_IDLE_STAT_SPIN) { 531 for (cpu = 0; cpu < ncpus; ++cpu) 532 cpu_idle_stats[cpu].spin = 0; 533 cpu_idle_stats[0].spin = val; 534 } else { 535 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX, 536 ("invalid index %d", idx)); 537 for (cpu = 0; cpu < ncpus; ++cpu) 538 cpu_idle_stats[cpu].mwait_cx[idx] = 0; 539 cpu_idle_stats[0].mwait_cx[idx] = val; 540 } 541 return 0; 542 } 543 544 static void 545 cpu_mwait_attach(void) 546 { 547 struct sbuf sb; 548 int hint_idx, i; 549 550 if (!CPU_MWAIT_HAS_CX) 551 return; 552 553 if (cpu_vendor_id == CPU_VENDOR_INTEL && 554 (CPUID_TO_FAMILY(cpu_id) > 0xf || 555 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 556 CPUID_TO_MODEL(cpu_id) >= 0xf))) { 557 int bm_sts = 1; 558 559 /* 560 * Pentium dual-core, Core 2 and beyond do not need any 561 * additional activities to enter deep C-state, i.e. C3(+). 562 */ 563 cpu_mwait_cx_no_bmarb(); 564 565 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts); 566 if (!bm_sts) 567 cpu_mwait_cx_no_bmsts(); 568 } 569 570 sbuf_new(&sb, cpu_mwait_cx_supported, 571 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN); 572 573 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) { 574 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i]; 575 int sub; 576 577 ksnprintf(cx->name, sizeof(cx->name), "C%d", i); 578 579 sysctl_ctx_init(&cx->sysctl_ctx); 580 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx, 581 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO, 582 cx->name, CTLFLAG_RW, NULL, "Cx control/info"); 583 if (cx->sysctl_tree == NULL) 584 continue; 585 586 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i); 587 SYSCTL_ADD_INT(&cx->sysctl_ctx, 588 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 589 "subcnt", CTLFLAG_RD, &cx->subcnt, 0, 590 "sub-state count"); 591 SYSCTL_ADD_PROC(&cx->sysctl_ctx, 592 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO, 593 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0, 594 i, sysctl_cpu_idle_cnt, "Q", "# of times entered"); 595 596 for (sub = 0; sub < cx->subcnt; ++sub) 597 sbuf_printf(&sb, "C%d/%d ", i, sub); 598 } 599 sbuf_trim(&sb); 600 sbuf_finish(&sb); 601 602 /* 603 * Non-deep C-states 604 */ 605 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt; 606 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) 607 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt; 608 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt, 609 M_DEVBUF, M_WAITOK); 610 611 hint_idx = 0; 612 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) { 613 int j, subcnt; 614 615 subcnt = cpu_mwait_cx_info[i].subcnt; 616 for (j = 0; j < subcnt; ++j) { 617 KASSERT(hint_idx < cpu_mwait_hints_cnt, 618 ("invalid mwait hint index %d", hint_idx)); 619 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 620 ++hint_idx; 621 } 622 } 623 KASSERT(hint_idx == cpu_mwait_hints_cnt, 624 ("mwait hint count %d != index %d", 625 cpu_mwait_hints_cnt, hint_idx)); 626 627 if (bootverbose) { 628 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt); 629 for (i = 0; i < cpu_mwait_hints_cnt; ++i) { 630 int hint = cpu_mwait_hints[i]; 631 632 kprintf(" C%d/%d hint 0x%04x\n", 633 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 634 hint); 635 } 636 } 637 638 /* 639 * Deep C-states 640 */ 641 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) 642 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt; 643 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt, 644 M_DEVBUF, M_WAITOK); 645 646 hint_idx = 0; 647 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) { 648 int j, subcnt; 649 650 subcnt = cpu_mwait_cx_info[i].subcnt; 651 for (j = 0; j < subcnt; ++j) { 652 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt, 653 ("invalid mwait deep hint index %d", hint_idx)); 654 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j); 655 ++hint_idx; 656 } 657 } 658 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt, 659 ("mwait deep hint count %d != index %d", 660 cpu_mwait_deep_hints_cnt, hint_idx)); 661 662 if (bootverbose) { 663 kprintf("MWAIT deep hints:\n"); 664 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) { 665 int hint = cpu_mwait_deep_hints[i]; 666 667 kprintf(" C%d/%d hint 0x%04x\n", 668 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint), 669 hint); 670 } 671 } 672 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt; 673 674 for (i = 0; i < ncpus; ++i) { 675 char name[16]; 676 677 ksnprintf(name, sizeof(name), "idle%d", i); 678 SYSCTL_ADD_PROC(NULL, 679 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO, 680 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i], 681 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", ""); 682 } 683 } 684 685 static void 686 cpu_finish(void *dummy __unused) 687 { 688 cpu_setregs(); 689 cpu_mwait_attach(); 690 } 691 692 static void 693 pic_finish(void *dummy __unused) 694 { 695 /* Log ELCR information */ 696 elcr_dump(); 697 698 /* Log MPTABLE information */ 699 mptable_pci_int_dump(); 700 701 /* Finalize PCI */ 702 MachIntrABI.finalize(); 703 } 704 705 /* 706 * Send an interrupt to process. 707 * 708 * Stack is set up to allow sigcode stored 709 * at top to call routine, followed by kcall 710 * to sigreturn routine below. After sigreturn 711 * resets the signal mask, the stack, and the 712 * frame pointer, it returns to the user 713 * specified pc, psl. 714 */ 715 void 716 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code) 717 { 718 struct lwp *lp = curthread->td_lwp; 719 struct proc *p = lp->lwp_proc; 720 struct trapframe *regs; 721 struct sigacts *psp = p->p_sigacts; 722 struct sigframe sf, *sfp; 723 int oonstack; 724 char *sp; 725 726 regs = lp->lwp_md.md_regs; 727 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0; 728 729 /* Save user context */ 730 bzero(&sf, sizeof(struct sigframe)); 731 sf.sf_uc.uc_sigmask = *mask; 732 sf.sf_uc.uc_stack = lp->lwp_sigstk; 733 sf.sf_uc.uc_mcontext.mc_onstack = oonstack; 734 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0); 735 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe)); 736 737 /* Make the size of the saved context visible to userland */ 738 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); 739 740 /* Allocate and validate space for the signal handler context. */ 741 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack && 742 SIGISMEMBER(psp->ps_sigonstack, sig)) { 743 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size - 744 sizeof(struct sigframe)); 745 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 746 } else { 747 /* We take red zone into account */ 748 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 749 } 750 751 /* 752 * XXX AVX needs 64-byte alignment but sigframe has other fields and 753 * the embedded ucontext is not at the front, so aligning this won't 754 * help us. Fortunately we bcopy in/out of the sigframe, so the 755 * kernel is ok. 756 * 757 * The problem though is if userland winds up trying to use the 758 * context directly. 759 */ 760 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF); 761 762 /* Translate the signal is appropriate */ 763 if (p->p_sysent->sv_sigtbl) { 764 if (sig <= p->p_sysent->sv_sigsize) 765 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 766 } 767 768 /* 769 * Build the argument list for the signal handler. 770 * 771 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx) 772 */ 773 regs->tf_rdi = sig; /* argument 1 */ 774 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */ 775 776 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 777 /* 778 * Signal handler installed with SA_SIGINFO. 779 * 780 * action(signo, siginfo, ucontext) 781 */ 782 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */ 783 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 784 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 785 786 /* fill siginfo structure */ 787 sf.sf_si.si_signo = sig; 788 sf.sf_si.si_code = code; 789 sf.sf_si.si_addr = (void *)regs->tf_addr; 790 } else { 791 /* 792 * Old FreeBSD-style arguments. 793 * 794 * handler (signo, code, [uc], addr) 795 */ 796 regs->tf_rsi = (register_t)code; /* argument 2 */ 797 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */ 798 sf.sf_ahu.sf_handler = catcher; 799 } 800 801 /* 802 * If we're a vm86 process, we want to save the segment registers. 803 * We also change eflags to be our emulated eflags, not the actual 804 * eflags. 805 */ 806 #if 0 /* JG */ 807 if (regs->tf_eflags & PSL_VM) { 808 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 809 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 810 811 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs; 812 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs; 813 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es; 814 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds; 815 816 if (vm86->vm86_has_vme == 0) 817 sf.sf_uc.uc_mcontext.mc_eflags = 818 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) | 819 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP)); 820 821 /* 822 * Clear PSL_NT to inhibit T_TSSFLT faults on return from 823 * syscalls made by the signal handler. This just avoids 824 * wasting time for our lazy fixup of such faults. PSL_NT 825 * does nothing in vm86 mode, but vm86 programs can set it 826 * almost legitimately in probes for old cpu types. 827 */ 828 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP); 829 } 830 #endif 831 832 /* 833 * Save the FPU state and reinit the FP unit 834 */ 835 npxpush(&sf.sf_uc.uc_mcontext); 836 837 /* 838 * Copy the sigframe out to the user's stack. 839 */ 840 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) { 841 /* 842 * Something is wrong with the stack pointer. 843 * ...Kill the process. 844 */ 845 sigexit(lp, SIGILL); 846 } 847 848 regs->tf_rsp = (register_t)sfp; 849 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); 850 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES; 851 852 /* 853 * i386 abi specifies that the direction flag must be cleared 854 * on function entry 855 */ 856 regs->tf_rflags &= ~(PSL_T | PSL_D); 857 858 /* 859 * 64 bit mode has a code and stack selector but 860 * no data or extra selector. %fs and %gs are not 861 * stored in-context. 862 */ 863 regs->tf_cs = _ucodesel; 864 regs->tf_ss = _udatasel; 865 clear_quickret(); 866 } 867 868 /* 869 * Sanitize the trapframe for a virtual kernel passing control to a custom 870 * VM context. Remove any items that would otherwise create a privilage 871 * issue. 872 * 873 * XXX at the moment we allow userland to set the resume flag. Is this a 874 * bad idea? 875 */ 876 int 877 cpu_sanitize_frame(struct trapframe *frame) 878 { 879 frame->tf_cs = _ucodesel; 880 frame->tf_ss = _udatasel; 881 /* XXX VM (8086) mode not supported? */ 882 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP); 883 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I; 884 885 return(0); 886 } 887 888 /* 889 * Sanitize the tls so loading the descriptor does not blow up 890 * on us. For x86_64 we don't have to do anything. 891 */ 892 int 893 cpu_sanitize_tls(struct savetls *tls) 894 { 895 return(0); 896 } 897 898 /* 899 * sigreturn(ucontext_t *sigcntxp) 900 * 901 * System call to cleanup state after a signal 902 * has been taken. Reset signal mask and 903 * stack state from context left by sendsig (above). 904 * Return to previous pc and psl as specified by 905 * context left by sendsig. Check carefully to 906 * make sure that the user has not modified the 907 * state to gain improper privileges. 908 * 909 * MPSAFE 910 */ 911 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 912 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 913 914 int 915 sys_sigreturn(struct sigreturn_args *uap) 916 { 917 struct lwp *lp = curthread->td_lwp; 918 struct trapframe *regs; 919 ucontext_t uc; 920 ucontext_t *ucp; 921 register_t rflags; 922 int cs; 923 int error; 924 925 /* 926 * We have to copy the information into kernel space so userland 927 * can't modify it while we are sniffing it. 928 */ 929 regs = lp->lwp_md.md_regs; 930 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 931 if (error) 932 return (error); 933 ucp = &uc; 934 rflags = ucp->uc_mcontext.mc_rflags; 935 936 /* VM (8086) mode not supported */ 937 rflags &= ~PSL_VM_UNSUPP; 938 939 #if 0 /* JG */ 940 if (eflags & PSL_VM) { 941 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs; 942 struct vm86_kernel *vm86; 943 944 /* 945 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't 946 * set up the vm86 area, and we can't enter vm86 mode. 947 */ 948 if (lp->lwp_thread->td_pcb->pcb_ext == 0) 949 return (EINVAL); 950 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86; 951 if (vm86->vm86_inited == 0) 952 return (EINVAL); 953 954 /* go back to user mode if both flags are set */ 955 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) 956 trapsignal(lp, SIGBUS, 0); 957 958 if (vm86->vm86_has_vme) { 959 eflags = (tf->tf_eflags & ~VME_USERCHANGE) | 960 (eflags & VME_USERCHANGE) | PSL_VM; 961 } else { 962 vm86->vm86_eflags = eflags; /* save VIF, VIP */ 963 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | 964 (eflags & VM_USERCHANGE) | PSL_VM; 965 } 966 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe)); 967 tf->tf_eflags = eflags; 968 tf->tf_vm86_ds = tf->tf_ds; 969 tf->tf_vm86_es = tf->tf_es; 970 tf->tf_vm86_fs = tf->tf_fs; 971 tf->tf_vm86_gs = tf->tf_gs; 972 tf->tf_ds = _udatasel; 973 tf->tf_es = _udatasel; 974 tf->tf_fs = _udatasel; 975 tf->tf_gs = _udatasel; 976 } else 977 #endif 978 { 979 /* 980 * Don't allow users to change privileged or reserved flags. 981 */ 982 /* 983 * XXX do allow users to change the privileged flag PSL_RF. 984 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers 985 * should sometimes set it there too. tf_eflags is kept in 986 * the signal context during signal handling and there is no 987 * other place to remember it, so the PSL_RF bit may be 988 * corrupted by the signal handler without us knowing. 989 * Corruption of the PSL_RF bit at worst causes one more or 990 * one less debugger trap, so allowing it is fairly harmless. 991 */ 992 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 993 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags); 994 return(EINVAL); 995 } 996 997 /* 998 * Don't allow users to load a valid privileged %cs. Let the 999 * hardware check for invalid selectors, excess privilege in 1000 * other selectors, invalid %eip's and invalid %esp's. 1001 */ 1002 cs = ucp->uc_mcontext.mc_cs; 1003 if (!CS_SECURE(cs)) { 1004 kprintf("sigreturn: cs = 0x%x\n", cs); 1005 trapsignal(lp, SIGBUS, T_PROTFLT); 1006 return(EINVAL); 1007 } 1008 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe)); 1009 } 1010 1011 /* 1012 * Restore the FPU state from the frame 1013 */ 1014 crit_enter(); 1015 npxpop(&ucp->uc_mcontext); 1016 1017 if (ucp->uc_mcontext.mc_onstack & 1) 1018 lp->lwp_sigstk.ss_flags |= SS_ONSTACK; 1019 else 1020 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK; 1021 1022 lp->lwp_sigmask = ucp->uc_sigmask; 1023 SIG_CANTMASK(lp->lwp_sigmask); 1024 clear_quickret(); 1025 crit_exit(); 1026 return(EJUSTRETURN); 1027 } 1028 1029 /* 1030 * Machine dependent boot() routine 1031 * 1032 * I haven't seen anything to put here yet 1033 * Possibly some stuff might be grafted back here from boot() 1034 */ 1035 void 1036 cpu_boot(int howto) 1037 { 1038 } 1039 1040 /* 1041 * Shutdown the CPU as much as possible 1042 */ 1043 void 1044 cpu_halt(void) 1045 { 1046 for (;;) 1047 __asm__ __volatile("hlt"); 1048 } 1049 1050 /* 1051 * cpu_idle() represents the idle LWKT. You cannot return from this function 1052 * (unless you want to blow things up!). Instead we look for runnable threads 1053 * and loop or halt as appropriate. Giant is not held on entry to the thread. 1054 * 1055 * The main loop is entered with a critical section held, we must release 1056 * the critical section before doing anything else. lwkt_switch() will 1057 * check for pending interrupts due to entering and exiting its own 1058 * critical section. 1059 * 1060 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up. 1061 * However, there are cases where the idlethread will be entered with 1062 * the possibility that no IPI will occur and in such cases 1063 * lwkt_switch() sets TDF_IDLE_NOHLT. 1064 * 1065 * NOTE: cpu_idle_repeat determines how many entries into the idle thread 1066 * must occur before it starts using ACPI halt. 1067 * 1068 * NOTE: Value overridden in hammer_time(). 1069 */ 1070 static int cpu_idle_hlt = 2; 1071 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 1072 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 1073 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW, 1074 &cpu_idle_repeat, 0, "Idle entries before acpi hlt"); 1075 1076 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1077 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts"); 1078 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW), 1079 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins"); 1080 1081 static void 1082 cpu_idle_default_hook(void) 1083 { 1084 /* 1085 * We must guarentee that hlt is exactly the instruction 1086 * following the sti. 1087 */ 1088 __asm __volatile("sti; hlt"); 1089 } 1090 1091 /* Other subsystems (e.g., ACPI) can hook this later. */ 1092 void (*cpu_idle_hook)(void) = cpu_idle_default_hook; 1093 1094 static __inline int 1095 cpu_mwait_cx_hint(struct cpu_idle_stat *stat) 1096 { 1097 int hint, cx_idx; 1098 u_int idx; 1099 1100 hint = stat->hint; 1101 if (hint >= 0) 1102 goto done; 1103 1104 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >> 1105 cpu_mwait_repeat_shift; 1106 if (idx >= cpu_mwait_c1_hints_cnt) { 1107 /* Step up faster, once we walked through all C1 states */ 1108 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1); 1109 } 1110 if (hint == CPU_MWAIT_HINT_AUTODEEP) { 1111 if (idx >= cpu_mwait_deep_hints_cnt) 1112 idx = cpu_mwait_deep_hints_cnt - 1; 1113 hint = cpu_mwait_deep_hints[idx]; 1114 } else { 1115 if (idx >= cpu_mwait_hints_cnt) 1116 idx = cpu_mwait_hints_cnt - 1; 1117 hint = cpu_mwait_hints[idx]; 1118 } 1119 done: 1120 cx_idx = MWAIT_EAX_TO_CX(hint); 1121 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX) 1122 stat->mwait_cx[cx_idx]++; 1123 return hint; 1124 } 1125 1126 void 1127 cpu_idle(void) 1128 { 1129 globaldata_t gd = mycpu; 1130 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid]; 1131 struct thread *td __debugvar = gd->gd_curthread; 1132 int reqflags; 1133 int quick; 1134 1135 stat->repeat = stat->repeat_last = cpu_idle_repeat_max; 1136 1137 crit_exit(); 1138 KKASSERT(td->td_critcount == 0); 1139 1140 for (;;) { 1141 /* 1142 * See if there are any LWKTs ready to go. 1143 */ 1144 lwkt_switch(); 1145 1146 /* 1147 * When halting inside a cli we must check for reqflags 1148 * races, particularly [re]schedule requests. Running 1149 * splz() does the job. 1150 * 1151 * cpu_idle_hlt: 1152 * 0 Never halt, just spin 1153 * 1154 * 1 Always use MONITOR/MWAIT if avail, HLT 1155 * otherwise. 1156 * 1157 * Better default for modern (Haswell+) Intel 1158 * cpus. 1159 * 1160 * 2 Use HLT/MONITOR/MWAIT up to a point and then 1161 * use the ACPI halt (default). This is a hybrid 1162 * approach. See machdep.cpu_idle_repeat. 1163 * 1164 * Better default for modern AMD cpus and older 1165 * Intel cpus. 1166 * 1167 * 3 Always use the ACPI halt. This typically 1168 * eats the least amount of power but the cpu 1169 * will be slow waking up. Slows down e.g. 1170 * compiles and other pipe/event oriented stuff. 1171 * 1172 * Usually the best default for AMD cpus. 1173 * 1174 * 4 Always use HLT. 1175 * 1176 * 5 Always spin. 1177 * 1178 * NOTE: Interrupts are enabled and we are not in a critical 1179 * section. 1180 * 1181 * NOTE: Preemptions do not reset gd_idle_repeat. Also we 1182 * don't bother capping gd_idle_repeat, it is ok if 1183 * it overflows. 1184 * 1185 * Implement optimized invltlb operations when halted 1186 * in idle. By setting the bit in smp_idleinvl_mask 1187 * we inform other cpus that they can set _reqs to 1188 * request an invltlb. Current the code to do that 1189 * sets the bits in _reqs anyway, but then check _mask 1190 * to determine if they can assume the invltlb will execute. 1191 * 1192 * A critical section is required to ensure that interrupts 1193 * do not fully run until after we've had a chance to execute 1194 * the request. 1195 */ 1196 if (gd->gd_idle_repeat == 0) { 1197 stat->repeat = (stat->repeat + stat->repeat_last) >> 1; 1198 if (stat->repeat > cpu_idle_repeat_max) 1199 stat->repeat = cpu_idle_repeat_max; 1200 stat->repeat_last = 0; 1201 stat->repeat_delta = 0; 1202 } 1203 ++stat->repeat_last; 1204 1205 ++gd->gd_idle_repeat; 1206 reqflags = gd->gd_reqflags; 1207 quick = (cpu_idle_hlt == 1) || 1208 (cpu_idle_hlt == 2 && 1209 gd->gd_idle_repeat < cpu_idle_repeat); 1210 1211 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) && 1212 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1213 splz(); /* XXX */ 1214 crit_enter_gd(gd); 1215 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1216 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags, 1217 cpu_mwait_cx_hint(stat), 0); 1218 stat->halt++; 1219 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1220 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1221 gd->gd_cpuid)) { 1222 cpu_invltlb(); 1223 cpu_mfence(); 1224 } 1225 crit_exit_gd(gd); 1226 } else if (cpu_idle_hlt) { 1227 __asm __volatile("cli"); 1228 splz(); 1229 crit_enter_gd(gd); 1230 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid); 1231 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) { 1232 if (cpu_idle_hlt == 5) { 1233 __asm __volatile("sti"); 1234 } else if (quick || cpu_idle_hlt == 4) { 1235 cpu_idle_default_hook(); 1236 } else { 1237 cpu_idle_hook(); 1238 } 1239 } 1240 __asm __volatile("sti"); 1241 stat->halt++; 1242 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid); 1243 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, 1244 gd->gd_cpuid)) { 1245 cpu_invltlb(); 1246 cpu_mfence(); 1247 } 1248 crit_exit_gd(gd); 1249 } else { 1250 splz(); 1251 __asm __volatile("sti"); 1252 stat->spin++; 1253 crit_enter_gd(gd); 1254 crit_exit_gd(gd); 1255 } 1256 } 1257 } 1258 1259 /* 1260 * Called in a loop indirectly via Xcpustop 1261 */ 1262 void 1263 cpu_smp_stopped(void) 1264 { 1265 globaldata_t gd = mycpu; 1266 volatile __uint64_t *ptr; 1267 __uint64_t ovalue; 1268 1269 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid); 1270 ovalue = *ptr; 1271 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) { 1272 if (cpu_mi_feature & CPU_MI_MONITOR) { 1273 if (cpu_mwait_hints) { 1274 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1275 ovalue, 1276 cpu_mwait_hints[CPU_MWAIT_C1], 0); 1277 } else { 1278 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr), 1279 ovalue, 0, 0); 1280 } 1281 } else { 1282 cpu_halt(); /* depend on lapic timer */ 1283 } 1284 } 1285 } 1286 1287 /* 1288 * This routine is called if a spinlock has been held through the 1289 * exponential backoff period and is seriously contested. On a real cpu 1290 * we let it spin. 1291 */ 1292 void 1293 cpu_spinlock_contested(void) 1294 { 1295 cpu_pause(); 1296 } 1297 1298 /* 1299 * Clear registers on exec 1300 */ 1301 void 1302 exec_setregs(u_long entry, u_long stack, u_long ps_strings) 1303 { 1304 struct thread *td = curthread; 1305 struct lwp *lp = td->td_lwp; 1306 struct pcb *pcb = td->td_pcb; 1307 struct trapframe *regs = lp->lwp_md.md_regs; 1308 1309 /* was i386_user_cleanup() in NetBSD */ 1310 user_ldt_free(pcb); 1311 1312 clear_quickret(); 1313 bzero((char *)regs, sizeof(struct trapframe)); 1314 regs->tf_rip = entry; 1315 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */ 1316 regs->tf_rdi = stack; /* argv */ 1317 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 1318 regs->tf_ss = _udatasel; 1319 regs->tf_cs = _ucodesel; 1320 regs->tf_rbx = ps_strings; 1321 1322 /* 1323 * Reset the hardware debug registers if they were in use. 1324 * They won't have any meaning for the newly exec'd process. 1325 */ 1326 if (pcb->pcb_flags & PCB_DBREGS) { 1327 pcb->pcb_dr0 = 0; 1328 pcb->pcb_dr1 = 0; 1329 pcb->pcb_dr2 = 0; 1330 pcb->pcb_dr3 = 0; 1331 pcb->pcb_dr6 = 0; 1332 pcb->pcb_dr7 = 0; /* JG set bit 10? */ 1333 if (pcb == td->td_pcb) { 1334 /* 1335 * Clear the debug registers on the running 1336 * CPU, otherwise they will end up affecting 1337 * the next process we switch to. 1338 */ 1339 reset_dbregs(); 1340 } 1341 pcb->pcb_flags &= ~PCB_DBREGS; 1342 } 1343 1344 /* 1345 * Initialize the math emulator (if any) for the current process. 1346 * Actually, just clear the bit that says that the emulator has 1347 * been initialized. Initialization is delayed until the process 1348 * traps to the emulator (if it is done at all) mainly because 1349 * emulators don't provide an entry point for initialization. 1350 */ 1351 pcb->pcb_flags &= ~FP_SOFTFP; 1352 1353 /* 1354 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing 1355 * gd_npxthread. Otherwise a preemptive interrupt thread 1356 * may panic in npxdna(). 1357 */ 1358 crit_enter(); 1359 load_cr0(rcr0() | CR0_MP); 1360 1361 /* 1362 * NOTE: The MSR values must be correct so we can return to 1363 * userland. gd_user_fs/gs must be correct so the switch 1364 * code knows what the current MSR values are. 1365 */ 1366 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */ 1367 pcb->pcb_gsbase = 0; 1368 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */ 1369 mdcpu->gd_user_gs = 0; 1370 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */ 1371 wrmsr(MSR_KGSBASE, 0); 1372 1373 /* Initialize the npx (if any) for the current process. */ 1374 npxinit(); 1375 crit_exit(); 1376 1377 pcb->pcb_ds = _udatasel; 1378 pcb->pcb_es = _udatasel; 1379 pcb->pcb_fs = _udatasel; 1380 pcb->pcb_gs = _udatasel; 1381 } 1382 1383 void 1384 cpu_setregs(void) 1385 { 1386 register_t cr0; 1387 1388 cr0 = rcr0(); 1389 cr0 |= CR0_NE; /* Done by npxinit() */ 1390 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */ 1391 cr0 |= CR0_WP | CR0_AM; 1392 load_cr0(cr0); 1393 load_gs(_udatasel); 1394 } 1395 1396 static int 1397 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS) 1398 { 1399 int error; 1400 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, 1401 req); 1402 if (!error && req->newptr) 1403 resettodr(); 1404 return (error); 1405 } 1406 1407 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW, 1408 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", ""); 1409 1410 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set, 1411 CTLFLAG_RW, &disable_rtc_set, 0, ""); 1412 1413 #if 0 /* JG */ 1414 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo, 1415 CTLFLAG_RD, &bootinfo, bootinfo, ""); 1416 #endif 1417 1418 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock, 1419 CTLFLAG_RW, &wall_cmos_clock, 0, ""); 1420 1421 static int 1422 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 1423 { 1424 struct efi_map_header *efihdr; 1425 caddr_t kmdp; 1426 uint32_t efisize; 1427 1428 kmdp = preload_search_by_type("elf kernel"); 1429 if (kmdp == NULL) 1430 kmdp = preload_search_by_type("elf64 kernel"); 1431 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1432 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1433 if (efihdr == NULL) 1434 return (0); 1435 efisize = *((uint32_t *)efihdr - 1); 1436 return (SYSCTL_OUT(req, efihdr, efisize)); 1437 } 1438 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 1439 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 1440 1441 /* 1442 * Initialize 386 and configure to run kernel 1443 */ 1444 1445 /* 1446 * Initialize segments & interrupt table 1447 */ 1448 1449 int _default_ldt; 1450 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */ 1451 struct gate_descriptor idt_arr[MAXCPU][NIDT]; 1452 #if 0 /* JG */ 1453 union descriptor ldt[NLDT]; /* local descriptor table */ 1454 #endif 1455 1456 /* table descriptors - used to load tables by cpu */ 1457 struct region_descriptor r_gdt; 1458 struct region_descriptor r_idt_arr[MAXCPU]; 1459 1460 /* JG proc0paddr is a virtual address */ 1461 void *proc0paddr; 1462 /* JG alignment? */ 1463 char proc0paddr_buff[LWKT_THREAD_STACK]; 1464 1465 1466 /* software prototypes -- in more palatable form */ 1467 struct soft_segment_descriptor gdt_segs[] = { 1468 /* GNULL_SEL 0 Null Descriptor */ 1469 { 0x0, /* segment base address */ 1470 0x0, /* length */ 1471 0, /* segment type */ 1472 0, /* segment descriptor priority level */ 1473 0, /* segment descriptor present */ 1474 0, /* long */ 1475 0, /* default 32 vs 16 bit size */ 1476 0 /* limit granularity (byte/page units)*/ }, 1477 /* GCODE_SEL 1 Code Descriptor for kernel */ 1478 { 0x0, /* segment base address */ 1479 0xfffff, /* length - all address space */ 1480 SDT_MEMERA, /* segment type */ 1481 SEL_KPL, /* segment descriptor priority level */ 1482 1, /* segment descriptor present */ 1483 1, /* long */ 1484 0, /* default 32 vs 16 bit size */ 1485 1 /* limit granularity (byte/page units)*/ }, 1486 /* GDATA_SEL 2 Data Descriptor for kernel */ 1487 { 0x0, /* segment base address */ 1488 0xfffff, /* length - all address space */ 1489 SDT_MEMRWA, /* segment type */ 1490 SEL_KPL, /* segment descriptor priority level */ 1491 1, /* segment descriptor present */ 1492 1, /* long */ 1493 0, /* default 32 vs 16 bit size */ 1494 1 /* limit granularity (byte/page units)*/ }, 1495 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 1496 { 0x0, /* segment base address */ 1497 0xfffff, /* length - all address space */ 1498 SDT_MEMERA, /* segment type */ 1499 SEL_UPL, /* segment descriptor priority level */ 1500 1, /* segment descriptor present */ 1501 0, /* long */ 1502 1, /* default 32 vs 16 bit size */ 1503 1 /* limit granularity (byte/page units)*/ }, 1504 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 1505 { 0x0, /* segment base address */ 1506 0xfffff, /* length - all address space */ 1507 SDT_MEMRWA, /* segment type */ 1508 SEL_UPL, /* segment descriptor priority level */ 1509 1, /* segment descriptor present */ 1510 0, /* long */ 1511 1, /* default 32 vs 16 bit size */ 1512 1 /* limit granularity (byte/page units)*/ }, 1513 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 1514 { 0x0, /* segment base address */ 1515 0xfffff, /* length - all address space */ 1516 SDT_MEMERA, /* segment type */ 1517 SEL_UPL, /* segment descriptor priority level */ 1518 1, /* segment descriptor present */ 1519 1, /* long */ 1520 0, /* default 32 vs 16 bit size */ 1521 1 /* limit granularity (byte/page units)*/ }, 1522 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 1523 { 1524 0x0, /* segment base address */ 1525 sizeof(struct x86_64tss)-1,/* length - all address space */ 1526 SDT_SYSTSS, /* segment type */ 1527 SEL_KPL, /* segment descriptor priority level */ 1528 1, /* segment descriptor present */ 1529 0, /* long */ 1530 0, /* unused - default 32 vs 16 bit size */ 1531 0 /* limit granularity (byte/page units)*/ }, 1532 /* Actually, the TSS is a system descriptor which is double size */ 1533 { 0x0, /* segment base address */ 1534 0x0, /* length */ 1535 0, /* segment type */ 1536 0, /* segment descriptor priority level */ 1537 0, /* segment descriptor present */ 1538 0, /* long */ 1539 0, /* default 32 vs 16 bit size */ 1540 0 /* limit granularity (byte/page units)*/ }, 1541 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 1542 { 0x0, /* segment base address */ 1543 0xfffff, /* length - all address space */ 1544 SDT_MEMRWA, /* segment type */ 1545 SEL_UPL, /* segment descriptor priority level */ 1546 1, /* segment descriptor present */ 1547 0, /* long */ 1548 1, /* default 32 vs 16 bit size */ 1549 1 /* limit granularity (byte/page units)*/ }, 1550 }; 1551 1552 void 1553 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist) 1554 { 1555 int cpu; 1556 1557 for (cpu = 0; cpu < MAXCPU; ++cpu) { 1558 struct gate_descriptor *ip = &idt_arr[cpu][idx]; 1559 1560 ip->gd_looffset = (uintptr_t)func; 1561 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1562 ip->gd_ist = ist; 1563 ip->gd_xx = 0; 1564 ip->gd_type = typ; 1565 ip->gd_dpl = dpl; 1566 ip->gd_p = 1; 1567 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1568 } 1569 } 1570 1571 void 1572 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu) 1573 { 1574 struct gate_descriptor *ip; 1575 1576 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu)); 1577 1578 ip = &idt_arr[cpu][idx]; 1579 ip->gd_looffset = (uintptr_t)func; 1580 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1581 ip->gd_ist = ist; 1582 ip->gd_xx = 0; 1583 ip->gd_type = typ; 1584 ip->gd_dpl = dpl; 1585 ip->gd_p = 1; 1586 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1587 } 1588 1589 #define IDTVEC(name) __CONCAT(X,name) 1590 1591 extern inthand_t 1592 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1593 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1594 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1595 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1596 IDTVEC(xmm), IDTVEC(dblfault), 1597 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1598 1599 void 1600 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd) 1601 { 1602 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1603 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1604 ssd->ssd_type = sd->sd_type; 1605 ssd->ssd_dpl = sd->sd_dpl; 1606 ssd->ssd_p = sd->sd_p; 1607 ssd->ssd_def32 = sd->sd_def32; 1608 ssd->ssd_gran = sd->sd_gran; 1609 } 1610 1611 void 1612 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd) 1613 { 1614 1615 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1616 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1617 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1618 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1619 sd->sd_type = ssd->ssd_type; 1620 sd->sd_dpl = ssd->ssd_dpl; 1621 sd->sd_p = ssd->ssd_p; 1622 sd->sd_long = ssd->ssd_long; 1623 sd->sd_def32 = ssd->ssd_def32; 1624 sd->sd_gran = ssd->ssd_gran; 1625 } 1626 1627 void 1628 ssdtosyssd(struct soft_segment_descriptor *ssd, 1629 struct system_segment_descriptor *sd) 1630 { 1631 1632 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1633 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1634 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1635 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1636 sd->sd_type = ssd->ssd_type; 1637 sd->sd_dpl = ssd->ssd_dpl; 1638 sd->sd_p = ssd->ssd_p; 1639 sd->sd_gran = ssd->ssd_gran; 1640 } 1641 1642 /* 1643 * Populate the (physmap) array with base/bound pairs describing the 1644 * available physical memory in the system, then test this memory and 1645 * build the phys_avail array describing the actually-available memory. 1646 * 1647 * If we cannot accurately determine the physical memory map, then use 1648 * value from the 0xE801 call, and failing that, the RTC. 1649 * 1650 * Total memory size may be set by the kernel environment variable 1651 * hw.physmem or the compile-time define MAXMEM. 1652 * 1653 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple 1654 * of PAGE_SIZE. This also greatly reduces the memory test time 1655 * which would otherwise be excessive on machines with > 8G of ram. 1656 * 1657 * XXX first should be vm_paddr_t. 1658 */ 1659 1660 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024) 1661 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1) 1662 #define PHYSMAP_SIZE VM_PHYSSEG_MAX 1663 1664 vm_paddr_t physmap[PHYSMAP_SIZE]; 1665 struct bios_smap *smapbase, *smap, *smapend; 1666 struct efi_map_header *efihdrbase; 1667 u_int32_t smapsize; 1668 1669 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024) 1670 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1) 1671 1672 static void 1673 add_smap_entries(int *physmap_idx) 1674 { 1675 int i; 1676 1677 smapsize = *((u_int32_t *)smapbase - 1); 1678 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1679 1680 for (smap = smapbase; smap < smapend; smap++) { 1681 if (boothowto & RB_VERBOSE) 1682 kprintf("SMAP type=%02x base=%016lx len=%016lx\n", 1683 smap->type, smap->base, smap->length); 1684 1685 if (smap->type != SMAP_TYPE_MEMORY) 1686 continue; 1687 1688 if (smap->length == 0) 1689 continue; 1690 1691 for (i = 0; i <= *physmap_idx; i += 2) { 1692 if (smap->base < physmap[i + 1]) { 1693 if (boothowto & RB_VERBOSE) { 1694 kprintf("Overlapping or non-monotonic " 1695 "memory region, ignoring " 1696 "second region\n"); 1697 } 1698 break; 1699 } 1700 } 1701 if (i <= *physmap_idx) 1702 continue; 1703 1704 Realmem += smap->length; 1705 1706 if (smap->base == physmap[*physmap_idx + 1]) { 1707 physmap[*physmap_idx + 1] += smap->length; 1708 continue; 1709 } 1710 1711 *physmap_idx += 2; 1712 if (*physmap_idx == PHYSMAP_SIZE) { 1713 kprintf("Too many segments in the physical " 1714 "address map, giving up\n"); 1715 break; 1716 } 1717 physmap[*physmap_idx] = smap->base; 1718 physmap[*physmap_idx + 1] = smap->base + smap->length; 1719 } 1720 } 1721 1722 static void 1723 add_efi_map_entries(int *physmap_idx) 1724 { 1725 struct efi_md *map, *p; 1726 const char *type; 1727 size_t efisz; 1728 int i, ndesc; 1729 1730 static const char *types[] = { 1731 "Reserved", 1732 "LoaderCode", 1733 "LoaderData", 1734 "BootServicesCode", 1735 "BootServicesData", 1736 "RuntimeServicesCode", 1737 "RuntimeServicesData", 1738 "ConventionalMemory", 1739 "UnusableMemory", 1740 "ACPIReclaimMemory", 1741 "ACPIMemoryNVS", 1742 "MemoryMappedIO", 1743 "MemoryMappedIOPortSpace", 1744 "PalCode" 1745 }; 1746 1747 /* 1748 * Memory map data provided by UEFI via the GetMemoryMap 1749 * Boot Services API. 1750 */ 1751 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1752 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz); 1753 1754 if (efihdrbase->descriptor_size == 0) 1755 return; 1756 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size; 1757 1758 if (boothowto & RB_VERBOSE) 1759 kprintf("%23s %12s %12s %8s %4s\n", 1760 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1761 1762 for (i = 0, p = map; i < ndesc; i++, 1763 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) { 1764 if (boothowto & RB_VERBOSE) { 1765 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1766 type = types[p->md_type]; 1767 else 1768 type = "<INVALID>"; 1769 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys, 1770 p->md_virt, p->md_pages); 1771 if (p->md_attr & EFI_MD_ATTR_UC) 1772 kprintf("UC "); 1773 if (p->md_attr & EFI_MD_ATTR_WC) 1774 kprintf("WC "); 1775 if (p->md_attr & EFI_MD_ATTR_WT) 1776 kprintf("WT "); 1777 if (p->md_attr & EFI_MD_ATTR_WB) 1778 kprintf("WB "); 1779 if (p->md_attr & EFI_MD_ATTR_UCE) 1780 kprintf("UCE "); 1781 if (p->md_attr & EFI_MD_ATTR_WP) 1782 kprintf("WP "); 1783 if (p->md_attr & EFI_MD_ATTR_RP) 1784 kprintf("RP "); 1785 if (p->md_attr & EFI_MD_ATTR_XP) 1786 kprintf("XP "); 1787 if (p->md_attr & EFI_MD_ATTR_RT) 1788 kprintf("RUNTIME"); 1789 kprintf("\n"); 1790 } 1791 1792 switch (p->md_type) { 1793 case EFI_MD_TYPE_CODE: 1794 case EFI_MD_TYPE_DATA: 1795 case EFI_MD_TYPE_BS_CODE: 1796 case EFI_MD_TYPE_BS_DATA: 1797 case EFI_MD_TYPE_FREE: 1798 /* 1799 * We're allowed to use any entry with these types. 1800 */ 1801 break; 1802 default: 1803 continue; 1804 } 1805 1806 Realmem += p->md_pages * PAGE_SIZE; 1807 1808 if (p->md_phys == physmap[*physmap_idx + 1]) { 1809 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE; 1810 continue; 1811 } 1812 1813 *physmap_idx += 2; 1814 if (*physmap_idx == PHYSMAP_SIZE) { 1815 kprintf("Too many segments in the physical " 1816 "address map, giving up\n"); 1817 break; 1818 } 1819 physmap[*physmap_idx] = p->md_phys; 1820 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE; 1821 } 1822 } 1823 1824 struct fb_info efi_fb_info; 1825 static int have_efi_framebuffer = 0; 1826 1827 static void 1828 efi_fb_init_vaddr(int direct_map) 1829 { 1830 uint64_t sz; 1831 vm_offset_t addr, v; 1832 1833 v = efi_fb_info.vaddr; 1834 sz = efi_fb_info.stride * efi_fb_info.height; 1835 1836 if (direct_map) { 1837 addr = PHYS_TO_DMAP(efi_fb_info.paddr); 1838 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS) 1839 efi_fb_info.vaddr = addr; 1840 } else { 1841 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr( 1842 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING); 1843 } 1844 } 1845 1846 int 1847 probe_efi_fb(int early) 1848 { 1849 struct efi_fb *efifb; 1850 caddr_t kmdp; 1851 1852 if (have_efi_framebuffer) { 1853 if (!early && 1854 (efi_fb_info.vaddr == 0 || 1855 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr))) 1856 efi_fb_init_vaddr(0); 1857 return 0; 1858 } 1859 1860 kmdp = preload_search_by_type("elf kernel"); 1861 if (kmdp == NULL) 1862 kmdp = preload_search_by_type("elf64 kernel"); 1863 efifb = (struct efi_fb *)preload_search_info(kmdp, 1864 MODINFO_METADATA | MODINFOMD_EFI_FB); 1865 if (efifb == NULL) 1866 return 1; 1867 1868 have_efi_framebuffer = 1; 1869 1870 efi_fb_info.is_vga_boot_display = 1; 1871 efi_fb_info.width = efifb->fb_width; 1872 efi_fb_info.height = efifb->fb_height; 1873 efi_fb_info.stride = efifb->fb_stride * 4; 1874 efi_fb_info.depth = 32; 1875 efi_fb_info.paddr = efifb->fb_addr; 1876 if (early) { 1877 efi_fb_info.vaddr = 0; 1878 } else { 1879 efi_fb_init_vaddr(0); 1880 } 1881 efi_fb_info.fbops.fb_set_par = NULL; 1882 efi_fb_info.fbops.fb_blank = NULL; 1883 efi_fb_info.fbops.fb_debug_enter = NULL; 1884 efi_fb_info.device = NULL; 1885 1886 return 0; 1887 } 1888 1889 static void 1890 efifb_startup(void *arg) 1891 { 1892 probe_efi_fb(0); 1893 } 1894 1895 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL); 1896 1897 static void 1898 getmemsize(caddr_t kmdp, u_int64_t first) 1899 { 1900 int off, physmap_idx, pa_indx, da_indx; 1901 int i, j; 1902 vm_paddr_t pa; 1903 vm_paddr_t msgbuf_size; 1904 u_long physmem_tunable; 1905 pt_entry_t *pte; 1906 quad_t dcons_addr, dcons_size; 1907 1908 bzero(physmap, sizeof(physmap)); 1909 physmap_idx = 0; 1910 1911 /* 1912 * get memory map from INT 15:E820, kindly supplied by the loader. 1913 * 1914 * subr_module.c says: 1915 * "Consumer may safely assume that size value precedes data." 1916 * ie: an int32_t immediately precedes smap. 1917 */ 1918 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp, 1919 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1920 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1921 MODINFO_METADATA | MODINFOMD_SMAP); 1922 if (smapbase == NULL && efihdrbase == NULL) 1923 panic("No BIOS smap or EFI map info from loader!"); 1924 1925 if (efihdrbase == NULL) 1926 add_smap_entries(&physmap_idx); 1927 else 1928 add_efi_map_entries(&physmap_idx); 1929 1930 base_memory = physmap[1] / 1024; 1931 /* make hole for AP bootstrap code */ 1932 physmap[1] = mp_bootaddress(base_memory); 1933 1934 /* Save EBDA address, if any */ 1935 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e)); 1936 ebda_addr <<= 4; 1937 1938 /* 1939 * Maxmem isn't the "maximum memory", it's one larger than the 1940 * highest page of the physical address space. It should be 1941 * called something like "Maxphyspage". We may adjust this 1942 * based on ``hw.physmem'' and the results of the memory test. 1943 */ 1944 Maxmem = atop(physmap[physmap_idx + 1]); 1945 1946 #ifdef MAXMEM 1947 Maxmem = MAXMEM / 4; 1948 #endif 1949 1950 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1951 Maxmem = atop(physmem_tunable); 1952 1953 /* 1954 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1955 * in the system. 1956 */ 1957 if (Maxmem > atop(physmap[physmap_idx + 1])) 1958 Maxmem = atop(physmap[physmap_idx + 1]); 1959 1960 /* 1961 * Blowing out the DMAP will blow up the system. 1962 */ 1963 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) { 1964 kprintf("Limiting Maxmem due to DMAP size\n"); 1965 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS); 1966 } 1967 1968 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1969 (boothowto & RB_VERBOSE)) { 1970 kprintf("Physical memory use set to %ldK\n", Maxmem * 4); 1971 } 1972 1973 /* 1974 * Call pmap initialization to make new kernel address space 1975 * 1976 * Mask off page 0. 1977 */ 1978 pmap_bootstrap(&first); 1979 physmap[0] = PAGE_SIZE; 1980 1981 /* 1982 * Align the physmap to PHYSMAP_ALIGN and cut out anything 1983 * exceeding Maxmem. 1984 */ 1985 for (i = j = 0; i <= physmap_idx; i += 2) { 1986 if (physmap[i+1] > ptoa(Maxmem)) 1987 physmap[i+1] = ptoa(Maxmem); 1988 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) & 1989 ~PHYSMAP_ALIGN_MASK; 1990 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK; 1991 1992 physmap[j] = physmap[i]; 1993 physmap[j+1] = physmap[i+1]; 1994 1995 if (physmap[i] < physmap[i+1]) 1996 j += 2; 1997 } 1998 physmap_idx = j - 2; 1999 2000 /* 2001 * Align anything else used in the validation loop. 2002 */ 2003 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2004 2005 /* 2006 * Size up each available chunk of physical memory. 2007 */ 2008 pa_indx = 0; 2009 da_indx = 0; 2010 phys_avail[pa_indx].phys_beg = physmap[0]; 2011 phys_avail[pa_indx].phys_end = physmap[0]; 2012 dump_avail[da_indx].phys_beg = 0; 2013 dump_avail[da_indx].phys_end = physmap[0]; 2014 pte = CMAP1; 2015 2016 /* 2017 * Get dcons buffer address 2018 */ 2019 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 || 2020 kgetenv_quad("dcons.size", &dcons_size) == 0) 2021 dcons_addr = 0; 2022 2023 /* 2024 * Validate the physical memory. The physical memory segments 2025 * have already been aligned to PHYSMAP_ALIGN which is a multiple 2026 * of PAGE_SIZE. 2027 */ 2028 for (i = 0; i <= physmap_idx; i += 2) { 2029 vm_paddr_t end; 2030 vm_paddr_t incr = PHYSMAP_ALIGN; 2031 2032 end = physmap[i + 1]; 2033 2034 for (pa = physmap[i]; pa < end; pa += incr) { 2035 int page_bad, full; 2036 volatile uint64_t *ptr = (uint64_t *)CADDR1; 2037 uint64_t tmp; 2038 2039 incr = PHYSMAP_ALIGN; 2040 full = FALSE; 2041 2042 /* 2043 * block out kernel memory as not available. 2044 */ 2045 if (pa >= 0x200000 && pa < first) 2046 goto do_dump_avail; 2047 2048 /* 2049 * block out dcons buffer 2050 */ 2051 if (dcons_addr > 0 2052 && pa >= trunc_page(dcons_addr) 2053 && pa < dcons_addr + dcons_size) { 2054 goto do_dump_avail; 2055 } 2056 2057 page_bad = FALSE; 2058 2059 /* 2060 * Always test the first and last block supplied in 2061 * the map entry, but it just takes too long to run 2062 * the test these days and we already have to skip 2063 * pages. Handwave it on PHYSMAP_HANDWAVE boundaries. 2064 */ 2065 if (pa != physmap[i]) { 2066 vm_paddr_t bytes = end - pa; 2067 if ((pa & PHYSMAP_HANDWAVE_MASK) == 0 && 2068 bytes >= PHYSMAP_HANDWAVE + PHYSMAP_ALIGN) { 2069 incr = PHYSMAP_HANDWAVE; 2070 goto handwaved; 2071 } 2072 } 2073 2074 /* 2075 * map page into kernel: valid, read/write,non-cacheable 2076 */ 2077 *pte = pa | 2078 kernel_pmap.pmap_bits[PG_V_IDX] | 2079 kernel_pmap.pmap_bits[PG_RW_IDX] | 2080 kernel_pmap.pmap_bits[PG_N_IDX]; 2081 cpu_invlpg(__DEVOLATILE(void *, ptr)); 2082 cpu_mfence(); 2083 2084 tmp = *ptr; 2085 /* 2086 * Test for alternating 1's and 0's 2087 */ 2088 *ptr = 0xaaaaaaaaaaaaaaaaLLU; 2089 cpu_mfence(); 2090 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU) 2091 page_bad = TRUE; 2092 /* 2093 * Test for alternating 0's and 1's 2094 */ 2095 *ptr = 0x5555555555555555LLU; 2096 cpu_mfence(); 2097 if (*ptr != 0x5555555555555555LLU) 2098 page_bad = TRUE; 2099 /* 2100 * Test for all 1's 2101 */ 2102 *ptr = 0xffffffffffffffffLLU; 2103 cpu_mfence(); 2104 if (*ptr != 0xffffffffffffffffLLU) 2105 page_bad = TRUE; 2106 /* 2107 * Test for all 0's 2108 */ 2109 *ptr = 0x0; 2110 cpu_mfence(); 2111 if (*ptr != 0x0) 2112 page_bad = TRUE; 2113 /* 2114 * Restore original value. 2115 */ 2116 *ptr = tmp; 2117 handwaved: 2118 2119 /* 2120 * Adjust array of valid/good pages. 2121 */ 2122 if (page_bad == TRUE) 2123 continue; 2124 2125 /* 2126 * If this good page is a continuation of the 2127 * previous set of good pages, then just increase 2128 * the end pointer. Otherwise start a new chunk. 2129 * Note that "end" points one higher than end, 2130 * making the range >= start and < end. 2131 * If we're also doing a speculative memory 2132 * test and we at or past the end, bump up Maxmem 2133 * so that we keep going. The first bad page 2134 * will terminate the loop. 2135 */ 2136 if (phys_avail[pa_indx].phys_end == pa) { 2137 phys_avail[pa_indx].phys_end += incr; 2138 } else { 2139 ++pa_indx; 2140 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 2141 kprintf( 2142 "Too many holes in the physical address space, giving up\n"); 2143 --pa_indx; 2144 full = TRUE; 2145 goto do_dump_avail; 2146 } 2147 phys_avail[pa_indx].phys_beg = pa; 2148 phys_avail[pa_indx].phys_end = pa + incr; 2149 } 2150 physmem += incr / PAGE_SIZE; 2151 do_dump_avail: 2152 if (dump_avail[da_indx].phys_end == pa) { 2153 dump_avail[da_indx].phys_end += incr; 2154 } else { 2155 ++da_indx; 2156 if (da_indx == DUMP_AVAIL_ARRAY_END) { 2157 --da_indx; 2158 goto do_next; 2159 } 2160 dump_avail[da_indx].phys_beg = pa; 2161 dump_avail[da_indx].phys_end = pa + incr; 2162 } 2163 do_next: 2164 if (full) 2165 break; 2166 } 2167 } 2168 *pte = 0; 2169 cpu_invltlb(); 2170 cpu_mfence(); 2171 2172 /* 2173 * The last chunk must contain at least one page plus the message 2174 * buffer to avoid complicating other code (message buffer address 2175 * calculation, etc.). 2176 */ 2177 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK; 2178 2179 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >= 2180 phys_avail[pa_indx].phys_end) { 2181 physmem -= atop(phys_avail[pa_indx].phys_end - 2182 phys_avail[pa_indx].phys_beg); 2183 phys_avail[pa_indx].phys_beg = 0; 2184 phys_avail[pa_indx].phys_end = 0; 2185 --pa_indx; 2186 } 2187 2188 Maxmem = atop(phys_avail[pa_indx].phys_end); 2189 2190 /* Trim off space for the message buffer. */ 2191 phys_avail[pa_indx].phys_end -= msgbuf_size; 2192 2193 avail_end = phys_avail[pa_indx].phys_end; 2194 2195 /* Map the message buffer. */ 2196 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) { 2197 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2198 } 2199 /* Try to get EFI framebuffer working as early as possible */ 2200 if (have_efi_framebuffer) 2201 efi_fb_init_vaddr(1); 2202 } 2203 2204 struct machintr_abi MachIntrABI; 2205 2206 /* 2207 * IDT VECTORS: 2208 * 0 Divide by zero 2209 * 1 Debug 2210 * 2 NMI 2211 * 3 BreakPoint 2212 * 4 OverFlow 2213 * 5 Bound-Range 2214 * 6 Invalid OpCode 2215 * 7 Device Not Available (x87) 2216 * 8 Double-Fault 2217 * 9 Coprocessor Segment overrun (unsupported, reserved) 2218 * 10 Invalid-TSS 2219 * 11 Segment not present 2220 * 12 Stack 2221 * 13 General Protection 2222 * 14 Page Fault 2223 * 15 Reserved 2224 * 16 x87 FP Exception pending 2225 * 17 Alignment Check 2226 * 18 Machine Check 2227 * 19 SIMD floating point 2228 * 20-31 reserved 2229 * 32-255 INTn/external sources 2230 */ 2231 u_int64_t 2232 hammer_time(u_int64_t modulep, u_int64_t physfree) 2233 { 2234 caddr_t kmdp; 2235 int gsel_tss, x, cpu; 2236 #if 0 /* JG */ 2237 int metadata_missing, off; 2238 #endif 2239 struct mdglobaldata *gd; 2240 u_int64_t msr; 2241 2242 /* 2243 * Prevent lowering of the ipl if we call tsleep() early. 2244 */ 2245 gd = &CPU_prvspace[0]->mdglobaldata; 2246 bzero(gd, sizeof(*gd)); 2247 2248 /* 2249 * Note: on both UP and SMP curthread must be set non-NULL 2250 * early in the boot sequence because the system assumes 2251 * that 'curthread' is never NULL. 2252 */ 2253 2254 gd->mi.gd_curthread = &thread0; 2255 thread0.td_gd = &gd->mi; 2256 2257 atdevbase = ISA_HOLE_START + PTOV_OFFSET; 2258 2259 #if 0 /* JG */ 2260 metadata_missing = 0; 2261 if (bootinfo.bi_modulep) { 2262 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE; 2263 preload_bootstrap_relocate(KERNBASE); 2264 } else { 2265 metadata_missing = 1; 2266 } 2267 if (bootinfo.bi_envp) 2268 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE; 2269 #endif 2270 2271 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET); 2272 preload_bootstrap_relocate(PTOV_OFFSET); 2273 kmdp = preload_search_by_type("elf kernel"); 2274 if (kmdp == NULL) 2275 kmdp = preload_search_by_type("elf64 kernel"); 2276 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 2277 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET; 2278 #ifdef DDB 2279 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 2280 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 2281 #endif 2282 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t); 2283 2284 if (boothowto & RB_VERBOSE) 2285 bootverbose++; 2286 2287 /* 2288 * Default MachIntrABI to ICU 2289 */ 2290 MachIntrABI = MachIntrABI_ICU; 2291 2292 /* 2293 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0. 2294 */ 2295 ncpus = 1; 2296 ncpus_fit = 1; 2297 /* Init basic tunables, hz etc */ 2298 init_param1(); 2299 2300 /* 2301 * make gdt memory segments 2302 */ 2303 gdt_segs[GPROC0_SEL].ssd_base = 2304 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss; 2305 2306 gd->mi.gd_prvspace = CPU_prvspace[0]; 2307 2308 for (x = 0; x < NGDT; x++) { 2309 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 2310 ssdtosd(&gdt_segs[x], &gdt[x]); 2311 } 2312 ssdtosyssd(&gdt_segs[GPROC0_SEL], 2313 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 2314 2315 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 2316 r_gdt.rd_base = (long) gdt; 2317 lgdt(&r_gdt); 2318 2319 wrmsr(MSR_FSBASE, 0); /* User value */ 2320 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi); 2321 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 2322 2323 mi_gdinit(&gd->mi, 0); 2324 cpu_gdinit(gd, 0); 2325 proc0paddr = proc0paddr_buff; 2326 mi_proc0init(&gd->mi, proc0paddr); 2327 safepri = TDPRI_MAX; 2328 2329 /* spinlocks and the BGL */ 2330 init_locks(); 2331 2332 /* exceptions */ 2333 for (x = 0; x < NIDT; x++) 2334 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 2335 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 2336 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 2337 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 2338 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 2339 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 2340 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 2341 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 2342 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 2343 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 2344 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 2345 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 2346 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 2347 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 2348 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 2349 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 2350 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 2351 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 2352 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 2353 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 2354 2355 for (cpu = 0; cpu < MAXCPU; ++cpu) { 2356 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1; 2357 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0]; 2358 } 2359 2360 lidt(&r_idt_arr[0]); 2361 2362 /* 2363 * Initialize the console before we print anything out. 2364 */ 2365 cninit(); 2366 2367 #if 0 /* JG */ 2368 if (metadata_missing) 2369 kprintf("WARNING: loader(8) metadata is missing!\n"); 2370 #endif 2371 2372 #if NISA >0 2373 elcr_probe(); 2374 isa_defaultirq(); 2375 #endif 2376 rand_initialize(); 2377 2378 /* 2379 * Initialize IRQ mapping 2380 * 2381 * NOTE: 2382 * SHOULD be after elcr_probe() 2383 */ 2384 MachIntrABI_ICU.initmap(); 2385 MachIntrABI_IOAPIC.initmap(); 2386 2387 #ifdef DDB 2388 kdb_init(); 2389 if (boothowto & RB_KDB) 2390 Debugger("Boot flags requested debugger"); 2391 #endif 2392 2393 #if 0 /* JG */ 2394 finishidentcpu(); /* Final stage of CPU initialization */ 2395 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2396 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 2397 #endif 2398 identify_cpu(); /* Final stage of CPU initialization */ 2399 initializecpu(0); /* Initialize CPU registers */ 2400 2401 /* 2402 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better 2403 * because the cpu does significant power management in MWAIT 2404 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP). 2405 * 2406 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does 2407 * significant power management only when using ACPI halt mode. 2408 * 2409 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI 2410 * is needed to reduce power consumption, but wakeup times are often 2411 * too long longer. 2412 */ 2413 if (cpu_vendor_id == CPU_VENDOR_INTEL && 2414 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */ 2415 cpu_idle_hlt = 1; 2416 } 2417 if (cpu_vendor_id == CPU_VENDOR_AMD) { 2418 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) { 2419 /* Ryzen or later */ 2420 cpu_idle_hlt = 3; 2421 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) { 2422 /* Bobcat or later */ 2423 cpu_idle_hlt = 3; 2424 } 2425 } 2426 2427 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */ 2428 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable); 2429 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable); 2430 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt); 2431 2432 /* 2433 * Some of the virtual machines do not work w/ I/O APIC 2434 * enabled. If the user does not explicitly enable or 2435 * disable the I/O APIC (ioapic_enable < 0), then we 2436 * disable I/O APIC on all virtual machines. 2437 * 2438 * NOTE: 2439 * This must be done after identify_cpu(), which sets 2440 * 'cpu_feature2' 2441 */ 2442 if (ioapic_enable < 0) { 2443 if (cpu_feature2 & CPUID2_VMM) 2444 ioapic_enable = 0; 2445 else 2446 ioapic_enable = 1; 2447 } 2448 2449 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2450 gd->gd_common_tss.tss_rsp0 = 2451 (register_t)(thread0.td_kstack + 2452 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb)); 2453 /* Ensure the stack is aligned to 16 bytes */ 2454 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF; 2455 2456 /* double fault stack */ 2457 gd->gd_common_tss.tss_ist1 = 2458 (long)&gd->mi.gd_prvspace->idlestack[ 2459 sizeof(gd->mi.gd_prvspace->idlestack)]; 2460 2461 /* Set the IO permission bitmap (empty due to tss seg limit) */ 2462 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss); 2463 2464 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 2465 gd->gd_tss_gdt = &gdt[GPROC0_SEL]; 2466 gd->gd_common_tssd = *gd->gd_tss_gdt; 2467 ltr(gsel_tss); 2468 2469 /* Set up the fast syscall stuff */ 2470 msr = rdmsr(MSR_EFER) | EFER_SCE; 2471 wrmsr(MSR_EFER, msr); 2472 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 2473 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 2474 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 2475 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 2476 wrmsr(MSR_STAR, msr); 2477 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 2478 2479 getmemsize(kmdp, physfree); 2480 init_param2(physmem); 2481 2482 /* now running on new page tables, configured,and u/iom is accessible */ 2483 2484 /* Map the message buffer. */ 2485 #if 0 /* JG */ 2486 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 2487 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off); 2488 #endif 2489 2490 msgbufinit(msgbufp, MSGBUF_SIZE); 2491 2492 2493 /* transfer to user mode */ 2494 2495 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2496 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2497 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2498 2499 load_ds(_udatasel); 2500 load_es(_udatasel); 2501 load_fs(_udatasel); 2502 2503 /* setup proc 0's pcb */ 2504 thread0.td_pcb->pcb_flags = 0; 2505 thread0.td_pcb->pcb_cr3 = KPML4phys; 2506 thread0.td_pcb->pcb_ext = NULL; 2507 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */ 2508 2509 /* Location of kernel stack for locore */ 2510 return ((u_int64_t)thread0.td_pcb); 2511 } 2512 2513 /* 2514 * Initialize machine-dependant portions of the global data structure. 2515 * Note that the global data area and cpu0's idlestack in the private 2516 * data space were allocated in locore. 2517 * 2518 * Note: the idlethread's cpl is 0 2519 * 2520 * WARNING! Called from early boot, 'mycpu' may not work yet. 2521 */ 2522 void 2523 cpu_gdinit(struct mdglobaldata *gd, int cpu) 2524 { 2525 if (cpu) 2526 gd->mi.gd_curthread = &gd->mi.gd_idlethread; 2527 2528 lwkt_init_thread(&gd->mi.gd_idlethread, 2529 gd->mi.gd_prvspace->idlestack, 2530 sizeof(gd->mi.gd_prvspace->idlestack), 2531 0, &gd->mi); 2532 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu); 2533 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch; 2534 gd->mi.gd_idlethread.td_sp -= sizeof(void *); 2535 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore; 2536 } 2537 2538 /* 2539 * We only have to check for DMAP bounds, the globaldata space is 2540 * actually part of the kernel_map so we don't have to waste time 2541 * checking CPU_prvspace[*]. 2542 */ 2543 int 2544 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr) 2545 { 2546 #if 0 2547 if (saddr >= (vm_offset_t)&CPU_prvspace[0] && 2548 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) { 2549 return (TRUE); 2550 } 2551 #endif 2552 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS) 2553 return (TRUE); 2554 return (FALSE); 2555 } 2556 2557 struct globaldata * 2558 globaldata_find(int cpu) 2559 { 2560 KKASSERT(cpu >= 0 && cpu < ncpus); 2561 return(&CPU_prvspace[cpu]->mdglobaldata.mi); 2562 } 2563 2564 /* 2565 * This path should be safe from the SYSRET issue because only stopped threads 2566 * can have their %rip adjusted this way (and all heavy weight thread switches 2567 * clear QUICKREF and thus do not use SYSRET). However, the code path is 2568 * convoluted so add a safety by forcing %rip to be cannonical. 2569 */ 2570 int 2571 ptrace_set_pc(struct lwp *lp, unsigned long addr) 2572 { 2573 if (addr & 0x0000800000000000LLU) 2574 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU; 2575 else 2576 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU; 2577 return (0); 2578 } 2579 2580 int 2581 ptrace_single_step(struct lwp *lp) 2582 { 2583 lp->lwp_md.md_regs->tf_rflags |= PSL_T; 2584 return (0); 2585 } 2586 2587 int 2588 fill_regs(struct lwp *lp, struct reg *regs) 2589 { 2590 struct trapframe *tp; 2591 2592 if ((tp = lp->lwp_md.md_regs) == NULL) 2593 return EINVAL; 2594 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs)); 2595 return (0); 2596 } 2597 2598 int 2599 set_regs(struct lwp *lp, struct reg *regs) 2600 { 2601 struct trapframe *tp; 2602 2603 tp = lp->lwp_md.md_regs; 2604 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) || 2605 !CS_SECURE(regs->r_cs)) 2606 return (EINVAL); 2607 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs)); 2608 clear_quickret(); 2609 return (0); 2610 } 2611 2612 static void 2613 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 2614 { 2615 struct env87 *penv_87 = &sv_87->sv_env; 2616 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2617 int i; 2618 2619 /* FPU control/status */ 2620 penv_87->en_cw = penv_xmm->en_cw; 2621 penv_87->en_sw = penv_xmm->en_sw; 2622 penv_87->en_tw = penv_xmm->en_tw; 2623 penv_87->en_fip = penv_xmm->en_fip; 2624 penv_87->en_fcs = penv_xmm->en_fcs; 2625 penv_87->en_opcode = penv_xmm->en_opcode; 2626 penv_87->en_foo = penv_xmm->en_foo; 2627 penv_87->en_fos = penv_xmm->en_fos; 2628 2629 /* FPU registers */ 2630 for (i = 0; i < 8; ++i) 2631 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 2632 } 2633 2634 static void 2635 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 2636 { 2637 struct env87 *penv_87 = &sv_87->sv_env; 2638 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2639 int i; 2640 2641 /* FPU control/status */ 2642 penv_xmm->en_cw = penv_87->en_cw; 2643 penv_xmm->en_sw = penv_87->en_sw; 2644 penv_xmm->en_tw = penv_87->en_tw; 2645 penv_xmm->en_fip = penv_87->en_fip; 2646 penv_xmm->en_fcs = penv_87->en_fcs; 2647 penv_xmm->en_opcode = penv_87->en_opcode; 2648 penv_xmm->en_foo = penv_87->en_foo; 2649 penv_xmm->en_fos = penv_87->en_fos; 2650 2651 /* FPU registers */ 2652 for (i = 0; i < 8; ++i) 2653 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 2654 } 2655 2656 int 2657 fill_fpregs(struct lwp *lp, struct fpreg *fpregs) 2658 { 2659 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL) 2660 return EINVAL; 2661 if (cpu_fxsr) { 2662 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm, 2663 (struct save87 *)fpregs); 2664 return (0); 2665 } 2666 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs); 2667 return (0); 2668 } 2669 2670 int 2671 set_fpregs(struct lwp *lp, struct fpreg *fpregs) 2672 { 2673 if (cpu_fxsr) { 2674 set_fpregs_xmm((struct save87 *)fpregs, 2675 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm); 2676 return (0); 2677 } 2678 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs); 2679 return (0); 2680 } 2681 2682 int 2683 fill_dbregs(struct lwp *lp, struct dbreg *dbregs) 2684 { 2685 struct pcb *pcb; 2686 2687 if (lp == NULL) { 2688 dbregs->dr[0] = rdr0(); 2689 dbregs->dr[1] = rdr1(); 2690 dbregs->dr[2] = rdr2(); 2691 dbregs->dr[3] = rdr3(); 2692 dbregs->dr[4] = rdr4(); 2693 dbregs->dr[5] = rdr5(); 2694 dbregs->dr[6] = rdr6(); 2695 dbregs->dr[7] = rdr7(); 2696 return (0); 2697 } 2698 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL) 2699 return EINVAL; 2700 dbregs->dr[0] = pcb->pcb_dr0; 2701 dbregs->dr[1] = pcb->pcb_dr1; 2702 dbregs->dr[2] = pcb->pcb_dr2; 2703 dbregs->dr[3] = pcb->pcb_dr3; 2704 dbregs->dr[4] = 0; 2705 dbregs->dr[5] = 0; 2706 dbregs->dr[6] = pcb->pcb_dr6; 2707 dbregs->dr[7] = pcb->pcb_dr7; 2708 return (0); 2709 } 2710 2711 int 2712 set_dbregs(struct lwp *lp, struct dbreg *dbregs) 2713 { 2714 if (lp == NULL) { 2715 load_dr0(dbregs->dr[0]); 2716 load_dr1(dbregs->dr[1]); 2717 load_dr2(dbregs->dr[2]); 2718 load_dr3(dbregs->dr[3]); 2719 load_dr4(dbregs->dr[4]); 2720 load_dr5(dbregs->dr[5]); 2721 load_dr6(dbregs->dr[6]); 2722 load_dr7(dbregs->dr[7]); 2723 } else { 2724 struct pcb *pcb; 2725 struct ucred *ucred; 2726 int i; 2727 uint64_t mask1, mask2; 2728 2729 /* 2730 * Don't let an illegal value for dr7 get set. Specifically, 2731 * check for undefined settings. Setting these bit patterns 2732 * result in undefined behaviour and can lead to an unexpected 2733 * TRCTRAP. 2734 */ 2735 /* JG this loop looks unreadable */ 2736 /* Check 4 2-bit fields for invalid patterns. 2737 * These fields are R/Wi, for i = 0..3 2738 */ 2739 /* Is 10 in LENi allowed when running in compatibility mode? */ 2740 /* Pattern 10 in R/Wi might be used to indicate 2741 * breakpoint on I/O. Further analysis should be 2742 * carried to decide if it is safe and useful to 2743 * provide access to that capability 2744 */ 2745 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4; 2746 i++, mask1 <<= 4, mask2 <<= 4) 2747 if ((dbregs->dr[7] & mask1) == mask2) 2748 return (EINVAL); 2749 2750 pcb = lp->lwp_thread->td_pcb; 2751 ucred = lp->lwp_proc->p_ucred; 2752 2753 /* 2754 * Don't let a process set a breakpoint that is not within the 2755 * process's address space. If a process could do this, it 2756 * could halt the system by setting a breakpoint in the kernel 2757 * (if ddb was enabled). Thus, we need to check to make sure 2758 * that no breakpoints are being enabled for addresses outside 2759 * process's address space, unless, perhaps, we were called by 2760 * uid 0. 2761 * 2762 * XXX - what about when the watched area of the user's 2763 * address space is written into from within the kernel 2764 * ... wouldn't that still cause a breakpoint to be generated 2765 * from within kernel mode? 2766 */ 2767 2768 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) { 2769 if (dbregs->dr[7] & 0x3) { 2770 /* dr0 is enabled */ 2771 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS) 2772 return (EINVAL); 2773 } 2774 2775 if (dbregs->dr[7] & (0x3<<2)) { 2776 /* dr1 is enabled */ 2777 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS) 2778 return (EINVAL); 2779 } 2780 2781 if (dbregs->dr[7] & (0x3<<4)) { 2782 /* dr2 is enabled */ 2783 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS) 2784 return (EINVAL); 2785 } 2786 2787 if (dbregs->dr[7] & (0x3<<6)) { 2788 /* dr3 is enabled */ 2789 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS) 2790 return (EINVAL); 2791 } 2792 } 2793 2794 pcb->pcb_dr0 = dbregs->dr[0]; 2795 pcb->pcb_dr1 = dbregs->dr[1]; 2796 pcb->pcb_dr2 = dbregs->dr[2]; 2797 pcb->pcb_dr3 = dbregs->dr[3]; 2798 pcb->pcb_dr6 = dbregs->dr[6]; 2799 pcb->pcb_dr7 = dbregs->dr[7]; 2800 2801 pcb->pcb_flags |= PCB_DBREGS; 2802 } 2803 2804 return (0); 2805 } 2806 2807 /* 2808 * Return > 0 if a hardware breakpoint has been hit, and the 2809 * breakpoint was in user space. Return 0, otherwise. 2810 */ 2811 int 2812 user_dbreg_trap(void) 2813 { 2814 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2815 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2816 int nbp; /* number of breakpoints that triggered */ 2817 caddr_t addr[4]; /* breakpoint addresses */ 2818 int i; 2819 2820 dr7 = rdr7(); 2821 if ((dr7 & 0xff) == 0) { 2822 /* 2823 * all GE and LE bits in the dr7 register are zero, 2824 * thus the trap couldn't have been caused by the 2825 * hardware debug registers 2826 */ 2827 return 0; 2828 } 2829 2830 nbp = 0; 2831 dr6 = rdr6(); 2832 bp = dr6 & 0xf; 2833 2834 if (bp == 0) { 2835 /* 2836 * None of the breakpoint bits are set meaning this 2837 * trap was not caused by any of the debug registers 2838 */ 2839 return 0; 2840 } 2841 2842 /* 2843 * at least one of the breakpoints were hit, check to see 2844 * which ones and if any of them are user space addresses 2845 */ 2846 2847 if (bp & 0x01) { 2848 addr[nbp++] = (caddr_t)rdr0(); 2849 } 2850 if (bp & 0x02) { 2851 addr[nbp++] = (caddr_t)rdr1(); 2852 } 2853 if (bp & 0x04) { 2854 addr[nbp++] = (caddr_t)rdr2(); 2855 } 2856 if (bp & 0x08) { 2857 addr[nbp++] = (caddr_t)rdr3(); 2858 } 2859 2860 for (i=0; i<nbp; i++) { 2861 if (addr[i] < 2862 (caddr_t)VM_MAX_USER_ADDRESS) { 2863 /* 2864 * addr[i] is in user space 2865 */ 2866 return nbp; 2867 } 2868 } 2869 2870 /* 2871 * None of the breakpoints are in user space. 2872 */ 2873 return 0; 2874 } 2875 2876 2877 #ifndef DDB 2878 void 2879 Debugger(const char *msg) 2880 { 2881 kprintf("Debugger(\"%s\") called.\n", msg); 2882 } 2883 #endif /* no DDB */ 2884 2885 #ifdef DDB 2886 2887 /* 2888 * Provide inb() and outb() as functions. They are normally only 2889 * available as macros calling inlined functions, thus cannot be 2890 * called inside DDB. 2891 * 2892 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 2893 */ 2894 2895 #undef inb 2896 #undef outb 2897 2898 /* silence compiler warnings */ 2899 u_char inb(u_int); 2900 void outb(u_int, u_char); 2901 2902 u_char 2903 inb(u_int port) 2904 { 2905 u_char data; 2906 /* 2907 * We use %%dx and not %1 here because i/o is done at %dx and not at 2908 * %edx, while gcc generates inferior code (movw instead of movl) 2909 * if we tell it to load (u_short) port. 2910 */ 2911 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 2912 return (data); 2913 } 2914 2915 void 2916 outb(u_int port, u_char data) 2917 { 2918 u_char al; 2919 /* 2920 * Use an unnecessary assignment to help gcc's register allocator. 2921 * This make a large difference for gcc-1.40 and a tiny difference 2922 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 2923 * best results. gcc-2.6.0 can't handle this. 2924 */ 2925 al = data; 2926 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 2927 } 2928 2929 #endif /* DDB */ 2930 2931 2932 2933 /* 2934 * initialize all the SMP locks 2935 */ 2936 2937 /* critical region when masking or unmasking interupts */ 2938 struct spinlock_deprecated imen_spinlock; 2939 2940 /* lock region used by kernel profiling */ 2941 struct spinlock_deprecated mcount_spinlock; 2942 2943 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 2944 struct spinlock_deprecated com_spinlock; 2945 2946 /* lock regions around the clock hardware */ 2947 struct spinlock_deprecated clock_spinlock; 2948 2949 static void 2950 init_locks(void) 2951 { 2952 /* 2953 * Get the initial mplock with a count of 1 for the BSP. 2954 * This uses a LOGICAL cpu ID, ie BSP == 0. 2955 */ 2956 cpu_get_initial_mplock(); 2957 /* DEPRECATED */ 2958 spin_init_deprecated(&mcount_spinlock); 2959 spin_init_deprecated(&imen_spinlock); 2960 spin_init_deprecated(&com_spinlock); 2961 spin_init_deprecated(&clock_spinlock); 2962 2963 /* our token pool needs to work early */ 2964 lwkt_token_pool_init(); 2965 } 2966 2967 boolean_t 2968 cpu_mwait_hint_valid(uint32_t hint) 2969 { 2970 int cx_idx, sub; 2971 2972 cx_idx = MWAIT_EAX_TO_CX(hint); 2973 if (cx_idx >= CPU_MWAIT_CX_MAX) 2974 return FALSE; 2975 2976 sub = MWAIT_EAX_TO_CX_SUB(hint); 2977 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt) 2978 return FALSE; 2979 2980 return TRUE; 2981 } 2982 2983 void 2984 cpu_mwait_cx_no_bmsts(void) 2985 { 2986 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS); 2987 } 2988 2989 void 2990 cpu_mwait_cx_no_bmarb(void) 2991 { 2992 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB); 2993 } 2994 2995 static int 2996 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto) 2997 { 2998 int old_cx_idx, sub = 0; 2999 3000 if (hint >= 0) { 3001 old_cx_idx = MWAIT_EAX_TO_CX(hint); 3002 sub = MWAIT_EAX_TO_CX_SUB(hint); 3003 } else if (hint == CPU_MWAIT_HINT_AUTO) { 3004 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX; 3005 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) { 3006 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX; 3007 } else { 3008 old_cx_idx = CPU_MWAIT_CX_MAX; 3009 } 3010 3011 if (!CPU_MWAIT_HAS_CX) 3012 strlcpy(name, "NONE", namelen); 3013 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO) 3014 strlcpy(name, "AUTO", namelen); 3015 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP) 3016 strlcpy(name, "AUTODEEP", namelen); 3017 else if (old_cx_idx >= CPU_MWAIT_CX_MAX || 3018 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt) 3019 strlcpy(name, "INVALID", namelen); 3020 else 3021 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub); 3022 3023 return old_cx_idx; 3024 } 3025 3026 static int 3027 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto) 3028 { 3029 int cx_idx, sub, hint; 3030 char *ptr, *start; 3031 3032 if (allow_auto && strcmp(name, "AUTO") == 0) { 3033 hint = CPU_MWAIT_HINT_AUTO; 3034 cx_idx = CPU_MWAIT_C2; 3035 goto done; 3036 } 3037 if (allow_auto && strcmp(name, "AUTODEEP") == 0) { 3038 hint = CPU_MWAIT_HINT_AUTODEEP; 3039 cx_idx = CPU_MWAIT_C3; 3040 goto done; 3041 } 3042 3043 if (strlen(name) < 4 || toupper(name[0]) != 'C') 3044 return -1; 3045 start = &name[1]; 3046 ptr = NULL; 3047 3048 cx_idx = strtol(start, &ptr, 10); 3049 if (ptr == start || *ptr != '/') 3050 return -1; 3051 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX) 3052 return -1; 3053 3054 start = ptr + 1; 3055 ptr = NULL; 3056 3057 sub = strtol(start, &ptr, 10); 3058 if (*ptr != '\0') 3059 return -1; 3060 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt) 3061 return -1; 3062 3063 hint = MWAIT_EAX_HINT(cx_idx, sub); 3064 done: 3065 *hint0 = hint; 3066 return cx_idx; 3067 } 3068 3069 static int 3070 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx) 3071 { 3072 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble) 3073 return EOPNOTSUPP; 3074 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) { 3075 int error; 3076 3077 error = cputimer_intr_powersave_addreq(); 3078 if (error) 3079 return error; 3080 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) { 3081 cputimer_intr_powersave_remreq(); 3082 } 3083 return 0; 3084 } 3085 3086 static int 3087 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0, 3088 boolean_t allow_auto) 3089 { 3090 int error, cx_idx, old_cx_idx, hint; 3091 char name[CPU_MWAIT_CX_NAMELEN]; 3092 3093 hint = *hint0; 3094 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), 3095 allow_auto); 3096 3097 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3098 if (error != 0 || req->newptr == NULL) 3099 return error; 3100 3101 if (!CPU_MWAIT_HAS_CX) 3102 return EOPNOTSUPP; 3103 3104 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto); 3105 if (cx_idx < 0) 3106 return EINVAL; 3107 3108 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3109 if (error) 3110 return error; 3111 3112 *hint0 = hint; 3113 return 0; 3114 } 3115 3116 static int 3117 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name) 3118 { 3119 int error, cx_idx, old_cx_idx, hint; 3120 char name[CPU_MWAIT_CX_NAMELEN]; 3121 3122 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension")); 3123 3124 hint = stat->hint; 3125 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3126 3127 strlcpy(name, cx_name, sizeof(name)); 3128 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3129 if (cx_idx < 0) 3130 return EINVAL; 3131 3132 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx); 3133 if (error) 3134 return error; 3135 3136 stat->hint = hint; 3137 return 0; 3138 } 3139 3140 static int 3141 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS) 3142 { 3143 int hint = cpu_mwait_halt_global; 3144 int error, cx_idx, cpu; 3145 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN]; 3146 3147 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE); 3148 3149 error = sysctl_handle_string(oidp, name, sizeof(name), req); 3150 if (error != 0 || req->newptr == NULL) 3151 return error; 3152 3153 if (!CPU_MWAIT_HAS_CX) 3154 return EOPNOTSUPP; 3155 3156 /* Save name for later per-cpu CX configuration */ 3157 strlcpy(cx_name, name, sizeof(cx_name)); 3158 3159 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE); 3160 if (cx_idx < 0) 3161 return EINVAL; 3162 3163 /* Change per-cpu CX configuration */ 3164 for (cpu = 0; cpu < ncpus; ++cpu) { 3165 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name); 3166 if (error) 3167 return error; 3168 } 3169 3170 cpu_mwait_halt_global = hint; 3171 return 0; 3172 } 3173 3174 static int 3175 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 3176 { 3177 struct cpu_idle_stat *stat = arg1; 3178 int error; 3179 3180 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3181 &stat->hint, TRUE); 3182 return error; 3183 } 3184 3185 static int 3186 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS) 3187 { 3188 int error; 3189 3190 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req, 3191 &cpu_mwait_spin, FALSE); 3192 return error; 3193 } 3194 3195 /* 3196 * This manual debugging code is called unconditionally from Xtimer 3197 * (the per-cpu timer interrupt) whether the current thread is in a 3198 * critical section or not) and can be useful in tracking down lockups. 3199 * 3200 * NOTE: MANUAL DEBUG CODE 3201 */ 3202 #if 0 3203 static int saveticks[SMP_MAXCPU]; 3204 static int savecounts[SMP_MAXCPU]; 3205 #endif 3206 3207 void 3208 pcpu_timer_always(struct intrframe *frame) 3209 { 3210 #if 0 3211 globaldata_t gd = mycpu; 3212 int cpu = gd->gd_cpuid; 3213 char buf[64]; 3214 short *gptr; 3215 int i; 3216 3217 if (cpu <= 20) { 3218 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu; 3219 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700; 3220 ++gptr; 3221 3222 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ", 3223 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks, 3224 gd->gd_infomsg); 3225 for (i = 0; buf[i]; ++i) { 3226 gptr[i] = 0x0700 | (unsigned char)buf[i]; 3227 } 3228 } 3229 #if 0 3230 if (saveticks[gd->gd_cpuid] != ticks) { 3231 saveticks[gd->gd_cpuid] = ticks; 3232 savecounts[gd->gd_cpuid] = 0; 3233 } 3234 ++savecounts[gd->gd_cpuid]; 3235 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) { 3236 panic("cpud %d panicing on ticks failure", 3237 gd->gd_cpuid); 3238 } 3239 for (i = 0; i < ncpus; ++i) { 3240 int delta; 3241 if (saveticks[i] && panicstr == NULL) { 3242 delta = saveticks[i] - ticks; 3243 if (delta < -10 || delta > 10) { 3244 panic("cpu %d panicing on cpu %d watchdog", 3245 gd->gd_cpuid, i); 3246 } 3247 } 3248 } 3249 #endif 3250 #endif 3251 } 3252