1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 #include <sys/cpu_topology.h> 39 40 #include <sys/mplock2.h> 41 42 #include <vm/vm.h> 43 #include <vm/vm_param.h> 44 #include <vm/pmap.h> 45 #include <vm/vm_kern.h> 46 #include <vm/vm_extern.h> 47 #include <sys/lock.h> 48 #include <vm/vm_map.h> 49 #include <sys/user.h> 50 #ifdef GPROF 51 #include <sys/gmon.h> 52 #endif 53 54 #include <machine/smp.h> 55 #include <machine_base/apic/apicreg.h> 56 #include <machine/atomic.h> 57 #include <machine/cpufunc.h> 58 #include <machine/cputypes.h> 59 #include <machine_base/apic/lapic.h> 60 #include <machine_base/apic/ioapic.h> 61 #include <machine_base/acpica/acpi_md_cpu.h> 62 #include <machine/psl.h> 63 #include <machine/segments.h> 64 #include <machine/tss.h> 65 #include <machine/specialreg.h> 66 #include <machine/globaldata.h> 67 #include <machine/pmap_inval.h> 68 #include <machine/clock.h> 69 70 #include <machine/md_var.h> /* setidt() */ 71 #include <machine_base/icu/icu.h> /* IPIs */ 72 #include <machine_base/icu/icu_var.h> 73 #include <machine_base/apic/ioapic_abi.h> 74 #include <machine/intr_machdep.h> /* IPIs */ 75 76 #define WARMBOOT_TARGET 0 77 #define WARMBOOT_OFF (KERNBASE + 0x0467) 78 #define WARMBOOT_SEG (KERNBASE + 0x0469) 79 80 #define CMOS_REG (0x70) 81 #define CMOS_DATA (0x71) 82 #define BIOS_RESET (0x0f) 83 #define BIOS_WARM (0x0a) 84 85 /* 86 * this code MUST be enabled here and in mpboot.s. 87 * it follows the very early stages of AP boot by placing values in CMOS ram. 88 * it NORMALLY will never be needed and thus the primitive method for enabling. 89 * 90 */ 91 #if defined(CHECK_POINTS) 92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 94 95 #define CHECK_INIT(D); \ 96 CHECK_WRITE(0x34, (D)); \ 97 CHECK_WRITE(0x35, (D)); \ 98 CHECK_WRITE(0x36, (D)); \ 99 CHECK_WRITE(0x37, (D)); \ 100 CHECK_WRITE(0x38, (D)); \ 101 CHECK_WRITE(0x39, (D)); 102 103 #define CHECK_PRINT(S); \ 104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 105 (S), \ 106 CHECK_READ(0x34), \ 107 CHECK_READ(0x35), \ 108 CHECK_READ(0x36), \ 109 CHECK_READ(0x37), \ 110 CHECK_READ(0x38), \ 111 CHECK_READ(0x39)); 112 113 #else /* CHECK_POINTS */ 114 115 #define CHECK_INIT(D) 116 #define CHECK_PRINT(S) 117 118 #endif /* CHECK_POINTS */ 119 120 /* 121 * Values to send to the POST hardware. 122 */ 123 #define MP_BOOTADDRESS_POST 0x10 124 #define MP_PROBE_POST 0x11 125 #define MPTABLE_PASS1_POST 0x12 126 127 #define MP_START_POST 0x13 128 #define MP_ENABLE_POST 0x14 129 #define MPTABLE_PASS2_POST 0x15 130 131 #define START_ALL_APS_POST 0x16 132 #define INSTALL_AP_TRAMP_POST 0x17 133 #define START_AP_POST 0x18 134 135 #define MP_ANNOUNCE_POST 0x19 136 137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 138 int current_postcode; 139 140 /** XXX FIXME: what system files declare these??? */ 141 extern struct region_descriptor r_gdt; 142 143 extern int nkpt; 144 extern int naps; 145 146 int64_t tsc0_offset; 147 extern int64_t tsc_offsets[]; 148 149 /* AP uses this during bootstrap. Do not staticize. */ 150 char *bootSTK; 151 static int bootAP; 152 153 struct pcb stoppcbs[MAXCPU]; 154 155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 156 157 /* 158 * Local data and functions. 159 */ 160 161 static u_int boot_address; 162 static int mp_finish; 163 static int mp_finish_lapic; 164 165 static int start_all_aps(u_int boot_addr); 166 #if 0 167 static void install_ap_tramp(u_int boot_addr); 168 #endif 169 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 170 static int smitest(void); 171 static void mp_bsp_simple_setup(void); 172 173 /* which cpus have been started */ 174 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE; 175 /* which cpus have lapic been inited */ 176 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE; 177 /* which cpus are ready for IPIs etc? */ 178 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE; 179 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE; 180 181 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, ""); 182 static u_int bootMP_size; 183 static u_int report_invlpg_src; 184 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW, 185 &report_invlpg_src, 0, ""); 186 static u_int report_invltlb_src; 187 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW, 188 &report_invltlb_src, 0, ""); 189 static int optimized_invltlb; 190 SYSCTL_INT(_machdep, OID_AUTO, optimized_invltlb, CTLFLAG_RW, 191 &optimized_invltlb, 0, ""); 192 static int all_but_self_ipi_enable = 1; 193 SYSCTL_INT(_machdep, OID_AUTO, all_but_self_ipi_enable, CTLFLAG_RW, 194 &all_but_self_ipi_enable, 0, ""); 195 196 /* Local data for detecting CPU TOPOLOGY */ 197 static int core_bits = 0; 198 static int logical_CPU_bits = 0; 199 200 201 /* 202 * Calculate usable address in base memory for AP trampoline code. 203 */ 204 u_int 205 mp_bootaddress(u_int basemem) 206 { 207 POSTCODE(MP_BOOTADDRESS_POST); 208 209 bootMP_size = mptramp_end - mptramp_start; 210 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 211 if (((basemem * 1024) - boot_address) < bootMP_size) 212 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 213 /* 3 levels of page table pages */ 214 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 215 216 return mptramp_pagetables; 217 } 218 219 /* 220 * Print various information about the SMP system hardware and setup. 221 */ 222 void 223 mp_announce(void) 224 { 225 int x; 226 227 POSTCODE(MP_ANNOUNCE_POST); 228 229 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 230 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 231 for (x = 1; x <= naps; ++x) 232 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 233 234 if (!ioapic_enable) 235 kprintf(" Warning: APIC I/O disabled\n"); 236 } 237 238 /* 239 * AP cpu's call this to sync up protected mode. 240 * 241 * WARNING! %gs is not set up on entry. This routine sets up %gs. 242 */ 243 void 244 init_secondary(void) 245 { 246 int gsel_tss; 247 int x, myid = bootAP; 248 u_int64_t msr, cr0; 249 struct mdglobaldata *md; 250 struct privatespace *ps; 251 252 ps = CPU_prvspace[myid]; 253 254 gdt_segs[GPROC0_SEL].ssd_base = 255 (long) &ps->mdglobaldata.gd_common_tss; 256 ps->mdglobaldata.mi.gd_prvspace = ps; 257 258 /* We fill the 32-bit segment descriptors */ 259 for (x = 0; x < NGDT; x++) { 260 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 261 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 262 } 263 /* And now a 64-bit one */ 264 ssdtosyssd(&gdt_segs[GPROC0_SEL], 265 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 266 267 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 268 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 269 lgdt(&r_gdt); /* does magic intra-segment return */ 270 271 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 272 wrmsr(MSR_FSBASE, 0); /* User value */ 273 wrmsr(MSR_GSBASE, (u_int64_t)ps); 274 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 275 276 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 277 278 #if 0 279 lldt(_default_ldt); 280 mdcpu->gd_currentldt = _default_ldt; 281 #endif 282 283 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 284 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 285 286 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 287 288 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 289 #if 0 /* JG XXX */ 290 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 291 #endif 292 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 293 md->gd_common_tssd = *md->gd_tss_gdt; 294 295 /* double fault stack */ 296 md->gd_common_tss.tss_ist1 = 297 (long)&md->mi.gd_prvspace->idlestack[ 298 sizeof(md->mi.gd_prvspace->idlestack)]; 299 300 ltr(gsel_tss); 301 302 /* 303 * Set to a known state: 304 * Set by mpboot.s: CR0_PG, CR0_PE 305 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 306 */ 307 cr0 = rcr0(); 308 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 309 load_cr0(cr0); 310 311 /* Set up the fast syscall stuff */ 312 msr = rdmsr(MSR_EFER) | EFER_SCE; 313 wrmsr(MSR_EFER, msr); 314 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 315 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 316 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 317 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 318 wrmsr(MSR_STAR, msr); 319 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 320 321 pmap_set_opt(); /* PSE/4MB pages, etc */ 322 pmap_init_pat(); /* Page Attribute Table */ 323 324 /* set up CPU registers and state */ 325 cpu_setregs(); 326 327 /* set up SSE/NX registers */ 328 initializecpu(myid); 329 330 /* set up FPU state on the AP */ 331 npxinit(); 332 333 /* disable the APIC, just to be SURE */ 334 lapic->svr &= ~APIC_SVR_ENABLE; 335 } 336 337 /******************************************************************* 338 * local functions and data 339 */ 340 341 /* 342 * Start the SMP system 343 */ 344 static void 345 mp_start_aps(void *dummy __unused) 346 { 347 if (lapic_enable) { 348 /* start each Application Processor */ 349 start_all_aps(boot_address); 350 } else { 351 mp_bsp_simple_setup(); 352 } 353 } 354 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL); 355 356 /* 357 * start each AP in our list 358 */ 359 static int 360 start_all_aps(u_int boot_addr) 361 { 362 vm_offset_t va = boot_address + KERNBASE; 363 u_int64_t *pt4, *pt3, *pt2; 364 int pssize; 365 int x, i; 366 int shift; 367 int smicount; 368 int smibest; 369 int smilast; 370 u_char mpbiosreason; 371 u_long mpbioswarmvec; 372 struct mdglobaldata *gd; 373 struct privatespace *ps; 374 size_t ipiq_size; 375 376 POSTCODE(START_ALL_APS_POST); 377 378 /* install the AP 1st level boot code */ 379 pmap_kenter(va, boot_address); 380 cpu_invlpg((void *)va); /* JG XXX */ 381 bcopy(mptramp_start, (void *)va, bootMP_size); 382 383 /* Locate the page tables, they'll be below the trampoline */ 384 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 385 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 386 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 387 388 /* Create the initial 1GB replicated page tables */ 389 for (i = 0; i < 512; i++) { 390 /* Each slot of the level 4 pages points to the same level 3 page */ 391 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 392 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 393 kernel_pmap.pmap_bits[PG_RW_IDX] | 394 kernel_pmap.pmap_bits[PG_U_IDX]; 395 396 /* Each slot of the level 3 pages points to the same level 2 page */ 397 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 398 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 399 kernel_pmap.pmap_bits[PG_RW_IDX] | 400 kernel_pmap.pmap_bits[PG_U_IDX]; 401 402 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 403 pt2[i] = i * (2 * 1024 * 1024); 404 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 405 kernel_pmap.pmap_bits[PG_RW_IDX] | 406 kernel_pmap.pmap_bits[PG_PS_IDX] | 407 kernel_pmap.pmap_bits[PG_U_IDX]; 408 } 409 410 /* save the current value of the warm-start vector */ 411 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 412 outb(CMOS_REG, BIOS_RESET); 413 mpbiosreason = inb(CMOS_DATA); 414 415 /* setup a vector to our boot code */ 416 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 417 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 418 outb(CMOS_REG, BIOS_RESET); 419 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 420 421 /* 422 * If we have a TSC we can figure out the SMI interrupt rate. 423 * The SMI does not necessarily use a constant rate. Spend 424 * up to 250ms trying to figure it out. 425 */ 426 smibest = 0; 427 if (cpu_feature & CPUID_TSC) { 428 set_apic_timer(275000); 429 smilast = read_apic_timer(); 430 for (x = 0; x < 20 && read_apic_timer(); ++x) { 431 smicount = smitest(); 432 if (smibest == 0 || smilast - smicount < smibest) 433 smibest = smilast - smicount; 434 smilast = smicount; 435 } 436 if (smibest > 250000) 437 smibest = 0; 438 if (smibest) { 439 smibest = smibest * (int64_t)1000000 / 440 get_apic_timer_frequency(); 441 } 442 } 443 if (smibest) 444 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 445 1000000 / smibest, smibest); 446 447 /* start each AP */ 448 for (x = 1; x <= naps; ++x) { 449 /* This is a bit verbose, it will go away soon. */ 450 451 pssize = sizeof(struct privatespace); 452 ps = (void *)kmem_alloc(&kernel_map, pssize); 453 CPU_prvspace[x] = ps; 454 #if 0 455 kprintf("ps %d %p %d\n", x, ps, pssize); 456 #endif 457 bzero(ps, pssize); 458 gd = &ps->mdglobaldata; 459 gd->mi.gd_prvspace = ps; 460 461 /* prime data page for it to use */ 462 mi_gdinit(&gd->mi, x); 463 cpu_gdinit(gd, x); 464 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1); 465 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size); 466 bzero(gd->mi.gd_ipiq, ipiq_size); 467 468 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid); 469 470 /* setup a vector to our boot code */ 471 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 472 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 473 outb(CMOS_REG, BIOS_RESET); 474 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 475 476 /* 477 * Setup the AP boot stack 478 */ 479 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE]; 480 bootAP = x; 481 482 /* attempt to start the Application Processor */ 483 CHECK_INIT(99); /* setup checkpoints */ 484 if (!start_ap(gd, boot_addr, smibest)) { 485 kprintf("\nAP #%d (PHY# %d) failed!\n", 486 x, CPUID_TO_APICID(x)); 487 CHECK_PRINT("trace"); /* show checkpoints */ 488 /* better panic as the AP may be running loose */ 489 kprintf("panic y/n? [y] "); 490 cnpoll(TRUE); 491 if (cngetc() != 'n') 492 panic("bye-bye"); 493 cnpoll(FALSE); 494 } 495 CHECK_PRINT("trace"); /* show checkpoints */ 496 } 497 498 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 499 ncpus = x; 500 501 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */ 502 for (shift = 0; (1 << shift) <= ncpus; ++shift) 503 ; 504 --shift; 505 ncpus2_shift = shift; 506 ncpus2 = 1 << shift; 507 ncpus2_mask = ncpus2 - 1; 508 509 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 510 if ((1 << shift) < ncpus) 511 ++shift; 512 ncpus_fit = 1 << shift; 513 ncpus_fit_mask = ncpus_fit - 1; 514 515 /* build our map of 'other' CPUs */ 516 mycpu->gd_other_cpus = smp_startup_mask; 517 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 518 519 gd = (struct mdglobaldata *)mycpu; 520 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid); 521 522 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus; 523 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size); 524 bzero(mycpu->gd_ipiq, ipiq_size); 525 526 /* restore the warmstart vector */ 527 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 528 outb(CMOS_REG, BIOS_RESET); 529 outb(CMOS_DATA, mpbiosreason); 530 531 /* 532 * NOTE! The idlestack for the BSP was setup by locore. Finish 533 * up, clean out the P==V mapping we did earlier. 534 */ 535 pmap_set_opt(); 536 537 /* 538 * Wait all APs to finish initializing LAPIC 539 */ 540 if (bootverbose) 541 kprintf("SMP: Waiting APs LAPIC initialization\n"); 542 if (cpu_feature & CPUID_TSC) 543 tsc0_offset = rdtsc(); 544 tsc_offsets[0] = 0; 545 mp_finish_lapic = 1; 546 rel_mplock(); 547 548 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) { 549 cpu_pause(); 550 cpu_lfence(); 551 if (cpu_feature & CPUID_TSC) 552 tsc0_offset = rdtsc(); 553 } 554 while (try_mplock() == 0) { 555 cpu_pause(); 556 cpu_lfence(); 557 } 558 559 /* number of APs actually started */ 560 return ncpus - 1; 561 } 562 563 564 /* 565 * load the 1st level AP boot code into base memory. 566 */ 567 568 /* targets for relocation */ 569 extern void bigJump(void); 570 extern void bootCodeSeg(void); 571 extern void bootDataSeg(void); 572 extern void MPentry(void); 573 extern u_int MP_GDT; 574 extern u_int mp_gdtbase; 575 576 #if 0 577 578 static void 579 install_ap_tramp(u_int boot_addr) 580 { 581 int x; 582 int size = *(int *) ((u_long) & bootMP_size); 583 u_char *src = (u_char *) ((u_long) bootMP); 584 u_char *dst = (u_char *) boot_addr + KERNBASE; 585 u_int boot_base = (u_int) bootMP; 586 u_int8_t *dst8; 587 u_int16_t *dst16; 588 u_int32_t *dst32; 589 590 POSTCODE(INSTALL_AP_TRAMP_POST); 591 592 for (x = 0; x < size; ++x) 593 *dst++ = *src++; 594 595 /* 596 * modify addresses in code we just moved to basemem. unfortunately we 597 * need fairly detailed info about mpboot.s for this to work. changes 598 * to mpboot.s might require changes here. 599 */ 600 601 /* boot code is located in KERNEL space */ 602 dst = (u_char *) boot_addr + KERNBASE; 603 604 /* modify the lgdt arg */ 605 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 606 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 607 608 /* modify the ljmp target for MPentry() */ 609 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 610 *dst32 = ((u_int) MPentry - KERNBASE); 611 612 /* modify the target for boot code segment */ 613 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 614 dst8 = (u_int8_t *) (dst16 + 1); 615 *dst16 = (u_int) boot_addr & 0xffff; 616 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 617 618 /* modify the target for boot data segment */ 619 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 620 dst8 = (u_int8_t *) (dst16 + 1); 621 *dst16 = (u_int) boot_addr & 0xffff; 622 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 623 } 624 625 #endif 626 627 /* 628 * This function starts the AP (application processor) identified 629 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 630 * to accomplish this. This is necessary because of the nuances 631 * of the different hardware we might encounter. It ain't pretty, 632 * but it seems to work. 633 * 634 * NOTE: eventually an AP gets to ap_init(), which is called just 635 * before the AP goes into the LWKT scheduler's idle loop. 636 */ 637 static int 638 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 639 { 640 int physical_cpu; 641 int vector; 642 u_long icr_lo, icr_hi; 643 644 POSTCODE(START_AP_POST); 645 646 /* get the PHYSICAL APIC ID# */ 647 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 648 649 /* calculate the vector */ 650 vector = (boot_addr >> 12) & 0xff; 651 652 /* We don't want anything interfering */ 653 cpu_disable_intr(); 654 655 /* Make sure the target cpu sees everything */ 656 wbinvd(); 657 658 /* 659 * Try to detect when a SMI has occurred, wait up to 200ms. 660 * 661 * If a SMI occurs during an AP reset but before we issue 662 * the STARTUP command, the AP may brick. To work around 663 * this problem we hold off doing the AP startup until 664 * after we have detected the SMI. Hopefully another SMI 665 * will not occur before we finish the AP startup. 666 * 667 * Retries don't seem to help. SMIs have a window of opportunity 668 * and if USB->legacy keyboard emulation is enabled in the BIOS 669 * the interrupt rate can be quite high. 670 * 671 * NOTE: Don't worry about the L1 cache load, it might bloat 672 * ldelta a little but ndelta will be so huge when the SMI 673 * occurs the detection logic will still work fine. 674 */ 675 if (smibest) { 676 set_apic_timer(200000); 677 smitest(); 678 } 679 680 /* 681 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 682 * and running the target CPU. OR this INIT IPI might be latched (P5 683 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 684 * ignored. 685 * 686 * see apic/apicreg.h for icr bit definitions. 687 * 688 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 689 */ 690 691 /* 692 * Setup the address for the target AP. We can setup 693 * icr_hi once and then just trigger operations with 694 * icr_lo. 695 */ 696 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 697 icr_hi |= (physical_cpu << 24); 698 icr_lo = lapic->icr_lo & 0xfff00000; 699 lapic->icr_hi = icr_hi; 700 701 /* 702 * Do an INIT IPI: assert RESET 703 * 704 * Use edge triggered mode to assert INIT 705 */ 706 lapic->icr_lo = icr_lo | 0x00004500; 707 while (lapic->icr_lo & APIC_DELSTAT_MASK) 708 /* spin */ ; 709 710 /* 711 * The spec calls for a 10ms delay but we may have to use a 712 * MUCH lower delay to avoid bricking an AP due to a fast SMI 713 * interrupt. We have other loops here too and dividing by 2 714 * doesn't seem to be enough even after subtracting 350us, 715 * so we divide by 4. 716 * 717 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 718 * interrupt was detected we use the full 10ms. 719 */ 720 if (smibest == 0) 721 u_sleep(10000); 722 else if (smibest < 150 * 4 + 350) 723 u_sleep(150); 724 else if ((smibest - 350) / 4 < 10000) 725 u_sleep((smibest - 350) / 4); 726 else 727 u_sleep(10000); 728 729 /* 730 * Do an INIT IPI: deassert RESET 731 * 732 * Use level triggered mode to deassert. It is unclear 733 * why we need to do this. 734 */ 735 lapic->icr_lo = icr_lo | 0x00008500; 736 while (lapic->icr_lo & APIC_DELSTAT_MASK) 737 /* spin */ ; 738 u_sleep(150); /* wait 150us */ 739 740 /* 741 * Next we do a STARTUP IPI: the previous INIT IPI might still be 742 * latched, (P5 bug) this 1st STARTUP would then terminate 743 * immediately, and the previously started INIT IPI would continue. OR 744 * the previous INIT IPI has already run. and this STARTUP IPI will 745 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 746 * will run. 747 */ 748 lapic->icr_lo = icr_lo | 0x00000600 | vector; 749 while (lapic->icr_lo & APIC_DELSTAT_MASK) 750 /* spin */ ; 751 u_sleep(200); /* wait ~200uS */ 752 753 /* 754 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 755 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 756 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 757 * recognized after hardware RESET or INIT IPI. 758 */ 759 lapic->icr_lo = icr_lo | 0x00000600 | vector; 760 while (lapic->icr_lo & APIC_DELSTAT_MASK) 761 /* spin */ ; 762 763 /* Resume normal operation */ 764 cpu_enable_intr(); 765 766 /* wait for it to start, see ap_init() */ 767 set_apic_timer(5000000);/* == 5 seconds */ 768 while (read_apic_timer()) { 769 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid)) 770 return 1; /* return SUCCESS */ 771 } 772 773 return 0; /* return FAILURE */ 774 } 775 776 static 777 int 778 smitest(void) 779 { 780 int64_t ltsc; 781 int64_t ntsc; 782 int64_t ldelta; 783 int64_t ndelta; 784 int count; 785 786 ldelta = 0; 787 ndelta = 0; 788 while (read_apic_timer()) { 789 ltsc = rdtsc(); 790 for (count = 0; count < 100; ++count) 791 ntsc = rdtsc(); /* force loop to occur */ 792 if (ldelta) { 793 ndelta = ntsc - ltsc; 794 if (ldelta > ndelta) 795 ldelta = ndelta; 796 if (ndelta > ldelta * 2) 797 break; 798 } else { 799 ldelta = ntsc - ltsc; 800 } 801 } 802 return(read_apic_timer()); 803 } 804 805 /* 806 * Synchronously flush the TLB on all other CPU's. The current cpu's 807 * TLB is not flushed. If the caller wishes to flush the current cpu's 808 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 809 * 810 * This routine may be called concurrently from multiple cpus. When this 811 * happens, smp_invltlb() can wind up sticking around in the confirmation 812 * while() loop at the end as additional cpus are added to the global 813 * cpumask, until they are acknowledged by another IPI. 814 * 815 * NOTE: If for some reason we were unable to start all cpus we cannot 816 * safely use broadcast IPIs. 817 */ 818 819 cpumask_t smp_smurf_mask; 820 static cpumask_t smp_invltlb_mask; 821 #define LOOPRECOVER 822 #ifdef LOOPMASK_IN 823 cpumask_t smp_in_mask; 824 #endif 825 cpumask_t smp_invmask; 826 extern cpumask_t smp_idleinvl_mask; 827 extern cpumask_t smp_idleinvl_reqs; 828 829 /* 830 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove 831 * bits that do not need to be IPId. These bits are still part of the command, 832 * but the target cpus have already been signalled and do not need to be 833 * sigalled again. 834 */ 835 #include <sys/spinlock.h> 836 #include <sys/spinlock2.h> 837 838 static __noinline 839 void 840 smp_smurf_fetchset(cpumask_t *mask) 841 { 842 cpumask_t omask; 843 int i; 844 __uint64_t obits; 845 __uint64_t nbits; 846 847 i = 0; 848 while (i < CPUMASK_ELEMENTS) { 849 obits = smp_smurf_mask.ary[i]; 850 cpu_ccfence(); 851 nbits = obits | mask->ary[i]; 852 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) { 853 omask.ary[i] = obits; 854 ++i; 855 } 856 } 857 CPUMASK_NANDMASK(*mask, omask); 858 } 859 860 /* 861 * This is a mechanism which guarantees that cpu_invltlb() will be executed 862 * on idle cpus without having to signal or wake them up. The invltlb will be 863 * executed when they wake up, prior to any scheduling or interrupt thread. 864 * 865 * (*mask) is modified to remove the cpus we successfully negotiate this 866 * function with. This function may only be used with semi-synchronous 867 * commands (typically invltlb's or semi-synchronous invalidations which 868 * are usually associated only with kernel memory). 869 */ 870 void 871 smp_smurf_idleinvlclr(cpumask_t *mask) 872 { 873 if (optimized_invltlb) { 874 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask); 875 /* cpu_lfence() not needed */ 876 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask); 877 } 878 } 879 880 /* 881 * Issue cpu_invltlb() across all cpus except the current cpu. 882 * 883 * This function will arrange to avoid idle cpus, but still gurantee that 884 * invltlb is run on them when they wake up prior to any scheduling or 885 * nominal interrupt. 886 */ 887 void 888 smp_invltlb(void) 889 { 890 struct mdglobaldata *md = mdcpu; 891 cpumask_t mask; 892 unsigned long rflags; 893 #ifdef LOOPRECOVER 894 uint64_t tsc_base = rdtsc(); 895 int repeats = 0; 896 #endif 897 898 if (report_invltlb_src > 0) { 899 if (--report_invltlb_src <= 0) 900 print_backtrace(8); 901 } 902 903 /* 904 * Disallow normal interrupts, set all active cpus except our own 905 * in the global smp_invltlb_mask. 906 */ 907 ++md->mi.gd_cnt.v_smpinvltlb; 908 crit_enter_gd(&md->mi); 909 910 /* 911 * Bits we want to set in smp_invltlb_mask. We do not want to signal 912 * our own cpu. Also try to remove bits associated with idle cpus 913 * that we can flag for auto-invltlb. 914 */ 915 mask = smp_active_mask; 916 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid); 917 smp_smurf_idleinvlclr(&mask); 918 919 rflags = read_rflags(); 920 cpu_disable_intr(); 921 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask); 922 923 /* 924 * IPI non-idle cpus represented by mask. The omask calculation 925 * removes cpus from the mask which already have a Xinvltlb IPI 926 * pending (avoid double-queueing the IPI). 927 * 928 * We must disable real interrupts when setting the smurf flags or 929 * we might race a XINVLTLB before we manage to send the ipi's for 930 * the bits we set. 931 * 932 * NOTE: We are not signalling ourselves, mask already does NOT 933 * include our own cpu. 934 */ 935 smp_smurf_fetchset(&mask); 936 937 /* 938 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of 939 * the critical section count on the target cpus. 940 */ 941 CPUMASK_ORMASK(mask, md->mi.gd_cpumask); 942 if (all_but_self_ipi_enable && 943 CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) { 944 all_but_self_ipi(XINVLTLB_OFFSET); 945 } else { 946 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask); 947 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 948 } 949 950 /* 951 * Wait for acknowledgement by all cpus. smp_inval_intr() will 952 * temporarily enable interrupts to avoid deadlocking the lapic, 953 * and will also handle running cpu_invltlb() and remote invlpg 954 * command son our cpu if some other cpu requests it of us. 955 * 956 * WARNING! I originally tried to implement this as a hard loop 957 * checking only smp_invltlb_mask (and issuing a local 958 * cpu_invltlb() if requested), with interrupts enabled 959 * and without calling smp_inval_intr(). This DID NOT WORK. 960 * It resulted in weird races where smurf bits would get 961 * cleared without any action being taken. 962 */ 963 smp_inval_intr(); 964 CPUMASK_ASSZERO(mask); 965 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) { 966 smp_inval_intr(); 967 cpu_pause(); 968 #ifdef LOOPRECOVER 969 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) { 970 kprintf("smp_invltlb %d: waited too long %08jx " 971 "dbg=%08jx %08jx\n", 972 md->mi.gd_cpuid, 973 smp_invltlb_mask.ary[0], 974 smp_idleinvl_mask.ary[0], 975 smp_idleinvl_reqs.ary[0]); 976 mdcpu->gd_xinvaltlb = 0; 977 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask, 978 smp_invltlb_mask); 979 smp_invlpg(&smp_active_mask); 980 tsc_base = rdtsc(); 981 if (++repeats > 10) { 982 kprintf("smp_invltlb: giving up\n"); 983 CPUMASK_ASSZERO(smp_invltlb_mask); 984 } 985 } 986 #endif 987 } 988 write_rflags(rflags); 989 crit_exit_gd(&md->mi); 990 } 991 992 /* 993 * Called from a critical section with interrupts hard-disabled. 994 * This function issues an XINVLTLB IPI and then executes any pending 995 * command on the current cpu before returning. 996 */ 997 void 998 smp_invlpg(cpumask_t *cmdmask) 999 { 1000 struct mdglobaldata *md = mdcpu; 1001 cpumask_t mask; 1002 1003 if (report_invlpg_src > 0) { 1004 if (--report_invlpg_src <= 0) 1005 print_backtrace(8); 1006 } 1007 1008 /* 1009 * Disallow normal interrupts, set all active cpus in the pmap, 1010 * plus our own for completion processing (it might or might not 1011 * be part of the set). 1012 */ 1013 mask = smp_active_mask; 1014 CPUMASK_ANDMASK(mask, *cmdmask); 1015 CPUMASK_ORMASK(mask, md->mi.gd_cpumask); 1016 1017 /* 1018 * Avoid double-queuing IPIs, which can deadlock us. We must disable 1019 * real interrupts when setting the smurf flags or we might race a 1020 * XINVLTLB before we manage to send the ipi's for the bits we set. 1021 * 1022 * NOTE: We might be including our own cpu in the smurf mask. 1023 */ 1024 smp_smurf_fetchset(&mask); 1025 1026 /* 1027 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of 1028 * the critical section count on the target cpus. 1029 * 1030 * We do not include our own cpu when issuing the IPI. 1031 */ 1032 if (all_but_self_ipi_enable && 1033 CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) { 1034 all_but_self_ipi(XINVLTLB_OFFSET); 1035 } else { 1036 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask); 1037 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 1038 } 1039 1040 /* 1041 * This will synchronously wait for our command to complete, 1042 * as well as process commands from other cpus. It also handles 1043 * reentrancy. 1044 * 1045 * (interrupts are disabled and we are in a critical section here) 1046 */ 1047 smp_inval_intr(); 1048 } 1049 1050 void 1051 smp_sniff(void) 1052 { 1053 globaldata_t gd = mycpu; 1054 int dummy; 1055 1056 /* 1057 * Ignore all_but_self_ipi_enable here and just use it. 1058 */ 1059 all_but_self_ipi(XSNIFF_OFFSET); 1060 gd->gd_sample_pc = smp_sniff; 1061 gd->gd_sample_sp = &dummy; 1062 } 1063 1064 /* 1065 * Called from Xinvltlb assembly with interrupts hard-disabled and in a 1066 * critical section. gd_intr_nesting_level may or may not be bumped 1067 * depending on entry. 1068 * 1069 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT. 1070 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE 1071 * IS IN A CRITICAL SECTION. 1072 */ 1073 void 1074 smp_inval_intr(void) 1075 { 1076 struct mdglobaldata *md = mdcpu; 1077 cpumask_t cpumask; 1078 #ifdef LOOPRECOVER 1079 uint64_t tsc_base = rdtsc(); 1080 #endif 1081 1082 #if 0 1083 /* 1084 * The idle code is in a critical section, but that doesn't stop 1085 * Xinvltlb from executing, so deal with the race which can occur 1086 * in that situation. Otherwise r-m-w operations by pmap_inval_intr() 1087 * may have problems. 1088 */ 1089 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, md->mi.gd_cpuid)) { 1090 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, md->mi.gd_cpuid); 1091 cpu_invltlb(); 1092 cpu_mfence(); 1093 } 1094 #endif 1095 1096 /* 1097 * This is a real mess. I'd like to just leave interrupts disabled 1098 * but it can cause the lapic to deadlock if too many interrupts queue 1099 * to it, due to the idiotic design of the lapic. So instead we have 1100 * to enter a critical section so normal interrupts are made pending 1101 * and track whether this one was reentered. 1102 */ 1103 if (md->gd_xinvaltlb) { /* reentrant on cpu */ 1104 md->gd_xinvaltlb = 2; 1105 return; 1106 } 1107 md->gd_xinvaltlb = 1; 1108 1109 /* 1110 * Check only those cpus with active Xinvl* commands pending. 1111 * 1112 * We are going to enable interrupts so make sure we are in a 1113 * critical section. This is necessary to avoid deadlocking 1114 * the lapic and to ensure that we execute our commands prior to 1115 * any nominal interrupt or preemption. 1116 * 1117 * WARNING! It is very important that we only clear out but in 1118 * smp_smurf_mask once for each interrupt we take. In 1119 * this case, we clear it on initial entry and only loop 1120 * on the reentrancy detect (caused by another interrupt). 1121 */ 1122 cpumask = smp_invmask; 1123 loop: 1124 cpu_enable_intr(); 1125 #ifdef LOOPMASK_IN 1126 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid); 1127 #endif 1128 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid); 1129 1130 /* 1131 * Specific page request(s), and we can't return until all bits 1132 * are zero. 1133 */ 1134 for (;;) { 1135 int toolong; 1136 1137 /* 1138 * Also execute any pending full invalidation request in 1139 * this loop. 1140 */ 1141 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) { 1142 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, 1143 md->mi.gd_cpuid); 1144 cpu_invltlb(); 1145 cpu_mfence(); 1146 } 1147 1148 #ifdef LOOPRECOVER 1149 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) { 1150 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx " 1151 "idle=%08jx/%08jx\n", 1152 md->mi.gd_cpuid, 1153 smp_invmask.ary[0], 1154 smp_invltlb_mask.ary[0], 1155 smp_idleinvl_mask.ary[0], 1156 smp_idleinvl_reqs.ary[0]); 1157 tsc_base = rdtsc(); 1158 toolong = 1; 1159 } else { 1160 toolong = 0; 1161 } 1162 #else 1163 toolong = 0; 1164 #endif 1165 1166 /* 1167 * We can only add bits to the cpumask to test during the 1168 * loop because the smp_invmask bit is cleared once the 1169 * originator completes the command (the targets may still 1170 * be cycling their own completions in this loop, afterwords). 1171 * 1172 * lfence required prior to all tests as this Xinvltlb 1173 * interrupt could race the originator (already be in progress 1174 * wnen the originator decides to issue, due to an issue by 1175 * another cpu). 1176 */ 1177 cpu_lfence(); 1178 CPUMASK_ORMASK(cpumask, smp_invmask); 1179 /*cpumask = smp_active_mask;*/ /* XXX */ 1180 1181 if (pmap_inval_intr(&cpumask, toolong) == 0) { 1182 /* 1183 * Clear our smurf mask to allow new IPIs, but deal 1184 * with potential races. 1185 */ 1186 break; 1187 } 1188 1189 /* 1190 * Test if someone sent us another invalidation IPI, break 1191 * out so we can take it to avoid deadlocking the lapic 1192 * interrupt queue (? stupid intel, amd). 1193 */ 1194 if (md->gd_xinvaltlb == 2) 1195 break; 1196 /* 1197 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid)) 1198 break; 1199 */ 1200 } 1201 1202 /* 1203 * Full invalidation request 1204 */ 1205 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) { 1206 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, 1207 md->mi.gd_cpuid); 1208 cpu_invltlb(); 1209 cpu_mfence(); 1210 } 1211 1212 #ifdef LOOPMASK_IN 1213 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid); 1214 #endif 1215 /* 1216 * Check to see if another Xinvltlb interrupt occurred and loop up 1217 * if it did. 1218 */ 1219 cpu_disable_intr(); 1220 if (md->gd_xinvaltlb == 2) { 1221 md->gd_xinvaltlb = 1; 1222 goto loop; 1223 } 1224 md->gd_xinvaltlb = 0; 1225 } 1226 1227 void 1228 cpu_wbinvd_on_all_cpus_callback(void *arg) 1229 { 1230 wbinvd(); 1231 } 1232 1233 /* 1234 * When called the executing CPU will send an IPI to all other CPUs 1235 * requesting that they halt execution. 1236 * 1237 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1238 * 1239 * - Signals all CPUs in map to stop. 1240 * - Waits for each to stop. 1241 * 1242 * Returns: 1243 * -1: error 1244 * 0: NA 1245 * 1: ok 1246 * 1247 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1248 * from executing at same time. 1249 */ 1250 int 1251 stop_cpus(cpumask_t map) 1252 { 1253 cpumask_t mask; 1254 1255 CPUMASK_ANDMASK(map, smp_active_mask); 1256 1257 /* send the Xcpustop IPI to all CPUs in map */ 1258 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1259 1260 do { 1261 mask = stopped_cpus; 1262 CPUMASK_ANDMASK(mask, map); 1263 /* spin */ 1264 } while (CPUMASK_CMPMASKNEQ(mask, map)); 1265 1266 return 1; 1267 } 1268 1269 1270 /* 1271 * Called by a CPU to restart stopped CPUs. 1272 * 1273 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1274 * 1275 * - Signals all CPUs in map to restart. 1276 * - Waits for each to restart. 1277 * 1278 * Returns: 1279 * -1: error 1280 * 0: NA 1281 * 1: ok 1282 */ 1283 int 1284 restart_cpus(cpumask_t map) 1285 { 1286 cpumask_t mask; 1287 1288 /* signal other cpus to restart */ 1289 mask = map; 1290 CPUMASK_ANDMASK(mask, smp_active_mask); 1291 cpu_ccfence(); 1292 started_cpus = mask; 1293 cpu_ccfence(); 1294 1295 /* wait for each to clear its bit */ 1296 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map)) 1297 cpu_pause(); 1298 1299 return 1; 1300 } 1301 1302 /* 1303 * This is called once the mpboot code has gotten us properly relocated 1304 * and the MMU turned on, etc. ap_init() is actually the idle thread, 1305 * and when it returns the scheduler will call the real cpu_idle() main 1306 * loop for the idlethread. Interrupts are disabled on entry and should 1307 * remain disabled at return. 1308 */ 1309 void 1310 ap_init(void) 1311 { 1312 int cpu_id; 1313 1314 /* 1315 * Adjust smp_startup_mask to signal the BSP that we have started 1316 * up successfully. Note that we do not yet hold the BGL. The BSP 1317 * is waiting for our signal. 1318 * 1319 * We can't set our bit in smp_active_mask yet because we are holding 1320 * interrupts physically disabled and remote cpus could deadlock 1321 * trying to send us an IPI. 1322 */ 1323 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid); 1324 cpu_mfence(); 1325 1326 /* 1327 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 1328 * non-zero, then get the MP lock. 1329 * 1330 * Note: We are in a critical section. 1331 * 1332 * Note: we are the idle thread, we can only spin. 1333 * 1334 * Note: The load fence is memory volatile and prevents the compiler 1335 * from improperly caching mp_finish_lapic, and the cpu from improperly 1336 * caching it. 1337 */ 1338 while (mp_finish_lapic == 0) { 1339 cpu_pause(); 1340 cpu_lfence(); 1341 } 1342 #if 0 1343 while (try_mplock() == 0) { 1344 cpu_pause(); 1345 cpu_lfence(); 1346 } 1347 #endif 1348 1349 if (cpu_feature & CPUID_TSC) { 1350 /* 1351 * The BSP is constantly updating tsc0_offset, figure out 1352 * the relative difference to synchronize ktrdump. 1353 */ 1354 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 1355 } 1356 1357 /* BSP may have changed PTD while we're waiting for the lock */ 1358 cpu_invltlb(); 1359 1360 /* Build our map of 'other' CPUs. */ 1361 mycpu->gd_other_cpus = smp_startup_mask; 1362 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 1363 1364 /* A quick check from sanity claus */ 1365 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 1366 if (mycpu->gd_cpuid != cpu_id) { 1367 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 1368 kprintf("SMP: actual cpuid = %d lapicid %d\n", 1369 cpu_id, (lapic->id & 0xff000000) >> 24); 1370 #if 0 /* JGXXX */ 1371 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 1372 #endif 1373 panic("cpuid mismatch! boom!!"); 1374 } 1375 1376 /* Initialize AP's local APIC for irq's */ 1377 lapic_init(FALSE); 1378 1379 /* LAPIC initialization is done */ 1380 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid); 1381 cpu_mfence(); 1382 1383 #if 0 1384 /* Let BSP move onto the next initialization stage */ 1385 rel_mplock(); 1386 #endif 1387 1388 /* 1389 * Interlock for finalization. Wait until mp_finish is non-zero, 1390 * then get the MP lock. 1391 * 1392 * Note: We are in a critical section. 1393 * 1394 * Note: we are the idle thread, we can only spin. 1395 * 1396 * Note: The load fence is memory volatile and prevents the compiler 1397 * from improperly caching mp_finish, and the cpu from improperly 1398 * caching it. 1399 */ 1400 while (mp_finish == 0) { 1401 cpu_pause(); 1402 cpu_lfence(); 1403 } 1404 1405 /* BSP may have changed PTD while we're waiting for the lock */ 1406 cpu_invltlb(); 1407 1408 /* Set memory range attributes for this CPU to match the BSP */ 1409 mem_range_AP_init(); 1410 1411 /* 1412 * Once we go active we must process any IPIQ messages that may 1413 * have been queued, because no actual IPI will occur until we 1414 * set our bit in the smp_active_mask. If we don't the IPI 1415 * message interlock could be left set which would also prevent 1416 * further IPIs. 1417 * 1418 * The idle loop doesn't expect the BGL to be held and while 1419 * lwkt_switch() normally cleans things up this is a special case 1420 * because we returning almost directly into the idle loop. 1421 * 1422 * The idle thread is never placed on the runq, make sure 1423 * nothing we've done put it there. 1424 */ 1425 1426 /* 1427 * Hold a critical section and allow real interrupts to occur. Zero 1428 * any spurious interrupts which have accumulated, then set our 1429 * smp_active_mask indicating that we are fully operational. 1430 */ 1431 crit_enter(); 1432 __asm __volatile("sti; pause; pause"::); 1433 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1434 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid); 1435 1436 /* 1437 * Wait until all cpus have set their smp_active_mask and have fully 1438 * operational interrupts before proceeding. 1439 * 1440 * We need a final cpu_invltlb() because we would not have received 1441 * any until we set our bit in smp_active_mask. 1442 */ 1443 while (mp_finish == 1) { 1444 cpu_pause(); 1445 cpu_lfence(); 1446 } 1447 cpu_invltlb(); 1448 1449 /* 1450 * Initialize per-cpu clocks and do other per-cpu initialization. 1451 * At this point code is expected to be able to use the full kernel 1452 * API. 1453 */ 1454 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1455 1456 /* 1457 * Since we may have cleaned up the interrupt triggers, manually 1458 * process any pending IPIs before exiting our critical section. 1459 * Once the critical section has exited, normal interrupt processing 1460 * may occur. 1461 */ 1462 atomic_swap_int(&mycpu->gd_npoll, 0); 1463 lwkt_process_ipiq(); 1464 crit_exit(); 1465 1466 /* 1467 * Final final, allow the waiting BSP to resume the boot process, 1468 * return 'into' the idle thread bootstrap. 1469 */ 1470 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid); 1471 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1472 } 1473 1474 /* 1475 * Get SMP fully working before we start initializing devices. 1476 */ 1477 static 1478 void 1479 ap_finish(void) 1480 { 1481 if (bootverbose) 1482 kprintf("Finish MP startup\n"); 1483 rel_mplock(); 1484 1485 /* 1486 * Wait for the active mask to complete, after which all cpus will 1487 * be accepting interrupts. 1488 */ 1489 mp_finish = 1; 1490 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) { 1491 cpu_pause(); 1492 cpu_lfence(); 1493 } 1494 1495 /* 1496 * Wait for the finalization mask to complete, after which all cpus 1497 * have completely finished initializing and are entering or are in 1498 * their idle thread. 1499 * 1500 * BSP should have received all required invltlbs but do another 1501 * one just in case. 1502 */ 1503 cpu_invltlb(); 1504 mp_finish = 2; 1505 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) { 1506 cpu_pause(); 1507 cpu_lfence(); 1508 } 1509 1510 while (try_mplock() == 0) { 1511 cpu_pause(); 1512 cpu_lfence(); 1513 } 1514 1515 if (bootverbose) { 1516 kprintf("Active CPU Mask: %016jx\n", 1517 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask)); 1518 } 1519 } 1520 1521 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL); 1522 1523 void 1524 cpu_send_ipiq(int dcpu) 1525 { 1526 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) 1527 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1528 } 1529 1530 #if 0 /* single_apic_ipi_passive() not working yet */ 1531 /* 1532 * Returns 0 on failure, 1 on success 1533 */ 1534 int 1535 cpu_send_ipiq_passive(int dcpu) 1536 { 1537 int r = 0; 1538 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) { 1539 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1540 APIC_DELMODE_FIXED); 1541 } 1542 return(r); 1543 } 1544 #endif 1545 1546 static void 1547 mp_bsp_simple_setup(void) 1548 { 1549 struct mdglobaldata *gd; 1550 size_t ipiq_size; 1551 1552 /* build our map of 'other' CPUs */ 1553 mycpu->gd_other_cpus = smp_startup_mask; 1554 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 1555 1556 gd = (struct mdglobaldata *)mycpu; 1557 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid); 1558 1559 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus; 1560 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size); 1561 bzero(mycpu->gd_ipiq, ipiq_size); 1562 1563 pmap_set_opt(); 1564 1565 if (cpu_feature & CPUID_TSC) 1566 tsc0_offset = rdtsc(); 1567 } 1568 1569 1570 /* 1571 * CPU TOPOLOGY DETECTION FUNCTIONS 1572 */ 1573 1574 /* Detect intel topology using CPUID 1575 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1576 */ 1577 static void 1578 detect_intel_topology(int count_htt_cores) 1579 { 1580 int shift = 0; 1581 int ecx_index = 0; 1582 int core_plus_logical_bits = 0; 1583 int cores_per_package; 1584 int logical_per_package; 1585 int logical_per_core; 1586 unsigned int p[4]; 1587 1588 if (cpu_high >= 0xb) { 1589 goto FUNC_B; 1590 1591 } else if (cpu_high >= 0x4) { 1592 goto FUNC_4; 1593 1594 } else { 1595 core_bits = 0; 1596 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1597 ; 1598 logical_CPU_bits = 1 << shift; 1599 return; 1600 } 1601 1602 FUNC_B: 1603 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1604 1605 /* if 0xb not supported - fallback to 0x4 */ 1606 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1607 goto FUNC_4; 1608 } 1609 1610 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1611 1612 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1613 do { 1614 cpuid_count(0xb, ecx_index, p); 1615 1616 /* Check for the Core type in the implemented sub leaves. */ 1617 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1618 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1619 break; 1620 } 1621 1622 ecx_index++; 1623 1624 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1625 1626 core_bits = core_plus_logical_bits - logical_CPU_bits; 1627 1628 return; 1629 1630 FUNC_4: 1631 cpuid_count(0x4, 0, p); 1632 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1633 1634 logical_per_package = count_htt_cores; 1635 logical_per_core = logical_per_package / cores_per_package; 1636 1637 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1638 ; 1639 logical_CPU_bits = shift; 1640 1641 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1642 ; 1643 core_bits = shift; 1644 1645 return; 1646 } 1647 1648 /* Detect AMD topology using CPUID 1649 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1650 */ 1651 static void 1652 detect_amd_topology(int count_htt_cores) 1653 { 1654 int shift = 0; 1655 if ((cpu_feature & CPUID_HTT) 1656 && (amd_feature2 & AMDID2_CMP)) { 1657 1658 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1659 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) 1660 >> AMDID_COREID_SIZE_SHIFT; 1661 } else { 1662 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1663 for (shift = 0; (1 << shift) < core_bits; ++shift) 1664 ; 1665 core_bits = shift; 1666 } 1667 1668 logical_CPU_bits = count_htt_cores >> core_bits; 1669 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1670 ; 1671 logical_CPU_bits = shift; 1672 } else { 1673 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1674 ; 1675 core_bits = shift; 1676 logical_CPU_bits = 0; 1677 } 1678 } 1679 1680 static void 1681 amd_get_compute_unit_id(void *arg) 1682 { 1683 u_int regs[4]; 1684 1685 do_cpuid(0x8000001e, regs); 1686 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid); 1687 /* 1688 * AMD - CPUID Specification September 2010 1689 * page 34 - //ComputeUnitID = ebx[0:7]// 1690 */ 1691 mynode->compute_unit_id = regs[1] & 0xff; 1692 } 1693 1694 int 1695 fix_amd_topology(void) 1696 { 1697 cpumask_t mask; 1698 1699 if (cpu_vendor_id != CPU_VENDOR_AMD) 1700 return -1; 1701 if ((amd_feature2 & AMDID2_TOPOEXT) == 0) 1702 return -1; 1703 1704 CPUMASK_ASSALLONES(mask); 1705 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL); 1706 1707 kprintf("Compute unit iDS:\n"); 1708 int i; 1709 for (i = 0; i < ncpus; i++) { 1710 kprintf("%d-%d; \n", 1711 i, get_cpu_node_by_cpuid(i)->compute_unit_id); 1712 } 1713 1714 return 0; 1715 } 1716 1717 /* Calculate 1718 * - logical_CPU_bits 1719 * - core_bits 1720 * With the values above (for AMD or INTEL) we are able to generally 1721 * detect the CPU topology (number of cores for each level): 1722 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1723 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1724 */ 1725 void 1726 detect_cpu_topology(void) 1727 { 1728 static int topology_detected = 0; 1729 int count = 0; 1730 1731 if (topology_detected) 1732 goto OUT; 1733 if ((cpu_feature & CPUID_HTT) == 0) { 1734 core_bits = 0; 1735 logical_CPU_bits = 0; 1736 goto OUT; 1737 } 1738 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT; 1739 1740 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1741 detect_intel_topology(count); 1742 else if (cpu_vendor_id == CPU_VENDOR_AMD) 1743 detect_amd_topology(count); 1744 topology_detected = 1; 1745 1746 OUT: 1747 if (bootverbose) 1748 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n", 1749 logical_CPU_bits, core_bits); 1750 } 1751 1752 /* Interface functions to calculate chip_ID, 1753 * core_number and logical_number 1754 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1755 */ 1756 int 1757 get_chip_ID(int cpuid) 1758 { 1759 return get_apicid_from_cpuid(cpuid) >> 1760 (logical_CPU_bits + core_bits); 1761 } 1762 1763 int 1764 get_core_number_within_chip(int cpuid) 1765 { 1766 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1767 ( (1 << core_bits) -1); 1768 } 1769 1770 int 1771 get_logical_CPU_number_within_core(int cpuid) 1772 { 1773 return get_apicid_from_cpuid(cpuid) & 1774 ( (1 << logical_CPU_bits) -1); 1775 } 1776