1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 39 #include <sys/mplock2.h> 40 41 #include <vm/vm.h> 42 #include <vm/vm_param.h> 43 #include <vm/pmap.h> 44 #include <vm/vm_kern.h> 45 #include <vm/vm_extern.h> 46 #include <sys/lock.h> 47 #include <vm/vm_map.h> 48 #include <sys/user.h> 49 #ifdef GPROF 50 #include <sys/gmon.h> 51 #endif 52 53 #include <machine/smp.h> 54 #include <machine_base/apic/apicreg.h> 55 #include <machine/atomic.h> 56 #include <machine/cpufunc.h> 57 #include <machine/cputypes.h> 58 #include <machine_base/apic/lapic.h> 59 #include <machine_base/apic/ioapic.h> 60 #include <machine/psl.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/specialreg.h> 64 #include <machine/globaldata.h> 65 #include <machine/pmap_inval.h> 66 67 #include <machine/md_var.h> /* setidt() */ 68 #include <machine_base/icu/icu.h> /* IPIs */ 69 #include <machine_base/icu/icu_var.h> 70 #include <machine_base/apic/ioapic_abi.h> 71 #include <machine/intr_machdep.h> /* IPIs */ 72 73 #define WARMBOOT_TARGET 0 74 #define WARMBOOT_OFF (KERNBASE + 0x0467) 75 #define WARMBOOT_SEG (KERNBASE + 0x0469) 76 77 #define CMOS_REG (0x70) 78 #define CMOS_DATA (0x71) 79 #define BIOS_RESET (0x0f) 80 #define BIOS_WARM (0x0a) 81 82 /* 83 * this code MUST be enabled here and in mpboot.s. 84 * it follows the very early stages of AP boot by placing values in CMOS ram. 85 * it NORMALLY will never be needed and thus the primitive method for enabling. 86 * 87 */ 88 #if defined(CHECK_POINTS) 89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 91 92 #define CHECK_INIT(D); \ 93 CHECK_WRITE(0x34, (D)); \ 94 CHECK_WRITE(0x35, (D)); \ 95 CHECK_WRITE(0x36, (D)); \ 96 CHECK_WRITE(0x37, (D)); \ 97 CHECK_WRITE(0x38, (D)); \ 98 CHECK_WRITE(0x39, (D)); 99 100 #define CHECK_PRINT(S); \ 101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 102 (S), \ 103 CHECK_READ(0x34), \ 104 CHECK_READ(0x35), \ 105 CHECK_READ(0x36), \ 106 CHECK_READ(0x37), \ 107 CHECK_READ(0x38), \ 108 CHECK_READ(0x39)); 109 110 #else /* CHECK_POINTS */ 111 112 #define CHECK_INIT(D) 113 #define CHECK_PRINT(S) 114 115 #endif /* CHECK_POINTS */ 116 117 /* 118 * Values to send to the POST hardware. 119 */ 120 #define MP_BOOTADDRESS_POST 0x10 121 #define MP_PROBE_POST 0x11 122 #define MPTABLE_PASS1_POST 0x12 123 124 #define MP_START_POST 0x13 125 #define MP_ENABLE_POST 0x14 126 #define MPTABLE_PASS2_POST 0x15 127 128 #define START_ALL_APS_POST 0x16 129 #define INSTALL_AP_TRAMP_POST 0x17 130 #define START_AP_POST 0x18 131 132 #define MP_ANNOUNCE_POST 0x19 133 134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 135 int current_postcode; 136 137 /** XXX FIXME: what system files declare these??? */ 138 extern struct region_descriptor r_gdt; 139 140 extern int nkpt; 141 extern int naps; 142 143 int64_t tsc0_offset; 144 extern int64_t tsc_offsets[]; 145 146 /* AP uses this during bootstrap. Do not staticize. */ 147 char *bootSTK; 148 static int bootAP; 149 150 struct pcb stoppcbs[MAXCPU]; 151 152 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 153 154 /* 155 * Local data and functions. 156 */ 157 158 static u_int boot_address; 159 static int mp_finish; 160 static int mp_finish_lapic; 161 162 static int start_all_aps(u_int boot_addr); 163 #if 0 164 static void install_ap_tramp(u_int boot_addr); 165 #endif 166 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 167 static int smitest(void); 168 static void mp_bsp_simple_setup(void); 169 170 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */ 171 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */ 172 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */ 173 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, ""); 174 static u_int bootMP_size; 175 176 /* Local data for detecting CPU TOPOLOGY */ 177 static int core_bits = 0; 178 static int logical_CPU_bits = 0; 179 180 181 /* 182 * Calculate usable address in base memory for AP trampoline code. 183 */ 184 u_int 185 mp_bootaddress(u_int basemem) 186 { 187 POSTCODE(MP_BOOTADDRESS_POST); 188 189 bootMP_size = mptramp_end - mptramp_start; 190 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 191 if (((basemem * 1024) - boot_address) < bootMP_size) 192 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 193 /* 3 levels of page table pages */ 194 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 195 196 return mptramp_pagetables; 197 } 198 199 /* 200 * Print various information about the SMP system hardware and setup. 201 */ 202 void 203 mp_announce(void) 204 { 205 int x; 206 207 POSTCODE(MP_ANNOUNCE_POST); 208 209 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 210 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 211 for (x = 1; x <= naps; ++x) 212 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 213 214 if (!ioapic_enable) 215 kprintf(" Warning: APIC I/O disabled\n"); 216 } 217 218 /* 219 * AP cpu's call this to sync up protected mode. 220 * 221 * WARNING! %gs is not set up on entry. This routine sets up %gs. 222 */ 223 void 224 init_secondary(void) 225 { 226 int gsel_tss; 227 int x, myid = bootAP; 228 u_int64_t msr, cr0; 229 struct mdglobaldata *md; 230 struct privatespace *ps; 231 232 ps = &CPU_prvspace[myid]; 233 234 gdt_segs[GPROC0_SEL].ssd_base = 235 (long) &ps->mdglobaldata.gd_common_tss; 236 ps->mdglobaldata.mi.gd_prvspace = ps; 237 238 /* We fill the 32-bit segment descriptors */ 239 for (x = 0; x < NGDT; x++) { 240 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 241 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 242 } 243 /* And now a 64-bit one */ 244 ssdtosyssd(&gdt_segs[GPROC0_SEL], 245 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 246 247 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 248 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 249 lgdt(&r_gdt); /* does magic intra-segment return */ 250 251 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 252 wrmsr(MSR_FSBASE, 0); /* User value */ 253 wrmsr(MSR_GSBASE, (u_int64_t)ps); 254 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 255 256 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 257 258 #if 0 259 lldt(_default_ldt); 260 mdcpu->gd_currentldt = _default_ldt; 261 #endif 262 263 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 264 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 265 266 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 267 268 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 269 #if 0 /* JG XXX */ 270 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 271 #endif 272 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 273 md->gd_common_tssd = *md->gd_tss_gdt; 274 275 /* double fault stack */ 276 md->gd_common_tss.tss_ist1 = 277 (long)&md->mi.gd_prvspace->idlestack[ 278 sizeof(md->mi.gd_prvspace->idlestack)]; 279 280 ltr(gsel_tss); 281 282 /* 283 * Set to a known state: 284 * Set by mpboot.s: CR0_PG, CR0_PE 285 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 286 */ 287 cr0 = rcr0(); 288 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 289 load_cr0(cr0); 290 291 /* Set up the fast syscall stuff */ 292 msr = rdmsr(MSR_EFER) | EFER_SCE; 293 wrmsr(MSR_EFER, msr); 294 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 295 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 296 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 297 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 298 wrmsr(MSR_STAR, msr); 299 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 300 301 pmap_set_opt(); /* PSE/4MB pages, etc */ 302 pmap_init_pat(); /* Page Attribute Table */ 303 304 /* set up CPU registers and state */ 305 cpu_setregs(); 306 307 /* set up SSE/NX registers */ 308 initializecpu(); 309 310 /* set up FPU state on the AP */ 311 npxinit(__INITIAL_FPUCW__); 312 313 /* disable the APIC, just to be SURE */ 314 lapic->svr &= ~APIC_SVR_ENABLE; 315 } 316 317 /******************************************************************* 318 * local functions and data 319 */ 320 321 /* 322 * Start the SMP system 323 */ 324 static void 325 mp_start_aps(void *dummy __unused) 326 { 327 if (lapic_enable) { 328 /* start each Application Processor */ 329 start_all_aps(boot_address); 330 } else { 331 mp_bsp_simple_setup(); 332 } 333 } 334 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL) 335 336 /* 337 * start each AP in our list 338 */ 339 static int 340 start_all_aps(u_int boot_addr) 341 { 342 vm_offset_t va = boot_address + KERNBASE; 343 u_int64_t *pt4, *pt3, *pt2; 344 int x, i; 345 int shift; 346 int smicount; 347 int smibest; 348 int smilast; 349 u_char mpbiosreason; 350 u_long mpbioswarmvec; 351 struct mdglobaldata *gd; 352 struct privatespace *ps; 353 354 POSTCODE(START_ALL_APS_POST); 355 356 /* install the AP 1st level boot code */ 357 pmap_kenter(va, boot_address); 358 cpu_invlpg((void *)va); /* JG XXX */ 359 bcopy(mptramp_start, (void *)va, bootMP_size); 360 361 /* Locate the page tables, they'll be below the trampoline */ 362 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 363 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 364 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 365 366 /* Create the initial 1GB replicated page tables */ 367 for (i = 0; i < 512; i++) { 368 /* Each slot of the level 4 pages points to the same level 3 page */ 369 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 370 pt4[i] |= PG_V | PG_RW | PG_U; 371 372 /* Each slot of the level 3 pages points to the same level 2 page */ 373 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 374 pt3[i] |= PG_V | PG_RW | PG_U; 375 376 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 377 pt2[i] = i * (2 * 1024 * 1024); 378 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 379 } 380 381 /* save the current value of the warm-start vector */ 382 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 383 outb(CMOS_REG, BIOS_RESET); 384 mpbiosreason = inb(CMOS_DATA); 385 386 /* setup a vector to our boot code */ 387 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 388 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 389 outb(CMOS_REG, BIOS_RESET); 390 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 391 392 /* 393 * If we have a TSC we can figure out the SMI interrupt rate. 394 * The SMI does not necessarily use a constant rate. Spend 395 * up to 250ms trying to figure it out. 396 */ 397 smibest = 0; 398 if (cpu_feature & CPUID_TSC) { 399 set_apic_timer(275000); 400 smilast = read_apic_timer(); 401 for (x = 0; x < 20 && read_apic_timer(); ++x) { 402 smicount = smitest(); 403 if (smibest == 0 || smilast - smicount < smibest) 404 smibest = smilast - smicount; 405 smilast = smicount; 406 } 407 if (smibest > 250000) 408 smibest = 0; 409 if (smibest) { 410 smibest = smibest * (int64_t)1000000 / 411 get_apic_timer_frequency(); 412 } 413 } 414 if (smibest) 415 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 416 1000000 / smibest, smibest); 417 418 /* start each AP */ 419 for (x = 1; x <= naps; ++x) { 420 421 /* This is a bit verbose, it will go away soon. */ 422 423 /* allocate new private data page(s) */ 424 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map, 425 MDGLOBALDATA_BASEALLOC_SIZE); 426 427 gd = &CPU_prvspace[x].mdglobaldata; /* official location */ 428 bzero(gd, sizeof(*gd)); 429 gd->mi.gd_prvspace = ps = &CPU_prvspace[x]; 430 431 /* prime data page for it to use */ 432 mi_gdinit(&gd->mi, x); 433 cpu_gdinit(gd, x); 434 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1)); 435 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1)); 436 437 /* setup a vector to our boot code */ 438 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 439 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 440 outb(CMOS_REG, BIOS_RESET); 441 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 442 443 /* 444 * Setup the AP boot stack 445 */ 446 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2]; 447 bootAP = x; 448 449 /* attempt to start the Application Processor */ 450 CHECK_INIT(99); /* setup checkpoints */ 451 if (!start_ap(gd, boot_addr, smibest)) { 452 kprintf("\nAP #%d (PHY# %d) failed!\n", 453 x, CPUID_TO_APICID(x)); 454 CHECK_PRINT("trace"); /* show checkpoints */ 455 /* better panic as the AP may be running loose */ 456 kprintf("panic y/n? [y] "); 457 if (cngetc() != 'n') 458 panic("bye-bye"); 459 } 460 CHECK_PRINT("trace"); /* show checkpoints */ 461 } 462 463 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 464 ncpus = x; 465 466 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */ 467 for (shift = 0; (1 << shift) <= ncpus; ++shift) 468 ; 469 --shift; 470 ncpus2_shift = shift; 471 ncpus2 = 1 << shift; 472 ncpus2_mask = ncpus2 - 1; 473 474 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 475 if ((1 << shift) < ncpus) 476 ++shift; 477 ncpus_fit = 1 << shift; 478 ncpus_fit_mask = ncpus_fit - 1; 479 480 /* build our map of 'other' CPUs */ 481 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 482 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 483 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 484 485 /* restore the warmstart vector */ 486 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 487 outb(CMOS_REG, BIOS_RESET); 488 outb(CMOS_DATA, mpbiosreason); 489 490 /* 491 * NOTE! The idlestack for the BSP was setup by locore. Finish 492 * up, clean out the P==V mapping we did earlier. 493 */ 494 pmap_set_opt(); 495 496 /* 497 * Wait all APs to finish initializing LAPIC 498 */ 499 mp_finish_lapic = 1; 500 if (bootverbose) 501 kprintf("SMP: Waiting APs LAPIC initialization\n"); 502 if (cpu_feature & CPUID_TSC) 503 tsc0_offset = rdtsc(); 504 tsc_offsets[0] = 0; 505 rel_mplock(); 506 while (smp_lapic_mask != smp_startup_mask) { 507 cpu_lfence(); 508 if (cpu_feature & CPUID_TSC) 509 tsc0_offset = rdtsc(); 510 } 511 while (try_mplock() == 0) 512 ; 513 514 /* number of APs actually started */ 515 return ncpus - 1; 516 } 517 518 519 /* 520 * load the 1st level AP boot code into base memory. 521 */ 522 523 /* targets for relocation */ 524 extern void bigJump(void); 525 extern void bootCodeSeg(void); 526 extern void bootDataSeg(void); 527 extern void MPentry(void); 528 extern u_int MP_GDT; 529 extern u_int mp_gdtbase; 530 531 #if 0 532 533 static void 534 install_ap_tramp(u_int boot_addr) 535 { 536 int x; 537 int size = *(int *) ((u_long) & bootMP_size); 538 u_char *src = (u_char *) ((u_long) bootMP); 539 u_char *dst = (u_char *) boot_addr + KERNBASE; 540 u_int boot_base = (u_int) bootMP; 541 u_int8_t *dst8; 542 u_int16_t *dst16; 543 u_int32_t *dst32; 544 545 POSTCODE(INSTALL_AP_TRAMP_POST); 546 547 for (x = 0; x < size; ++x) 548 *dst++ = *src++; 549 550 /* 551 * modify addresses in code we just moved to basemem. unfortunately we 552 * need fairly detailed info about mpboot.s for this to work. changes 553 * to mpboot.s might require changes here. 554 */ 555 556 /* boot code is located in KERNEL space */ 557 dst = (u_char *) boot_addr + KERNBASE; 558 559 /* modify the lgdt arg */ 560 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 561 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 562 563 /* modify the ljmp target for MPentry() */ 564 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 565 *dst32 = ((u_int) MPentry - KERNBASE); 566 567 /* modify the target for boot code segment */ 568 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 569 dst8 = (u_int8_t *) (dst16 + 1); 570 *dst16 = (u_int) boot_addr & 0xffff; 571 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 572 573 /* modify the target for boot data segment */ 574 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 575 dst8 = (u_int8_t *) (dst16 + 1); 576 *dst16 = (u_int) boot_addr & 0xffff; 577 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 578 } 579 580 #endif 581 582 /* 583 * This function starts the AP (application processor) identified 584 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 585 * to accomplish this. This is necessary because of the nuances 586 * of the different hardware we might encounter. It ain't pretty, 587 * but it seems to work. 588 * 589 * NOTE: eventually an AP gets to ap_init(), which is called just 590 * before the AP goes into the LWKT scheduler's idle loop. 591 */ 592 static int 593 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 594 { 595 int physical_cpu; 596 int vector; 597 u_long icr_lo, icr_hi; 598 599 POSTCODE(START_AP_POST); 600 601 /* get the PHYSICAL APIC ID# */ 602 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 603 604 /* calculate the vector */ 605 vector = (boot_addr >> 12) & 0xff; 606 607 /* We don't want anything interfering */ 608 cpu_disable_intr(); 609 610 /* Make sure the target cpu sees everything */ 611 wbinvd(); 612 613 /* 614 * Try to detect when a SMI has occurred, wait up to 200ms. 615 * 616 * If a SMI occurs during an AP reset but before we issue 617 * the STARTUP command, the AP may brick. To work around 618 * this problem we hold off doing the AP startup until 619 * after we have detected the SMI. Hopefully another SMI 620 * will not occur before we finish the AP startup. 621 * 622 * Retries don't seem to help. SMIs have a window of opportunity 623 * and if USB->legacy keyboard emulation is enabled in the BIOS 624 * the interrupt rate can be quite high. 625 * 626 * NOTE: Don't worry about the L1 cache load, it might bloat 627 * ldelta a little but ndelta will be so huge when the SMI 628 * occurs the detection logic will still work fine. 629 */ 630 if (smibest) { 631 set_apic_timer(200000); 632 smitest(); 633 } 634 635 /* 636 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 637 * and running the target CPU. OR this INIT IPI might be latched (P5 638 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 639 * ignored. 640 * 641 * see apic/apicreg.h for icr bit definitions. 642 * 643 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 644 */ 645 646 /* 647 * Setup the address for the target AP. We can setup 648 * icr_hi once and then just trigger operations with 649 * icr_lo. 650 */ 651 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 652 icr_hi |= (physical_cpu << 24); 653 icr_lo = lapic->icr_lo & 0xfff00000; 654 lapic->icr_hi = icr_hi; 655 656 /* 657 * Do an INIT IPI: assert RESET 658 * 659 * Use edge triggered mode to assert INIT 660 */ 661 lapic->icr_lo = icr_lo | 0x00004500; 662 while (lapic->icr_lo & APIC_DELSTAT_MASK) 663 /* spin */ ; 664 665 /* 666 * The spec calls for a 10ms delay but we may have to use a 667 * MUCH lower delay to avoid bricking an AP due to a fast SMI 668 * interrupt. We have other loops here too and dividing by 2 669 * doesn't seem to be enough even after subtracting 350us, 670 * so we divide by 4. 671 * 672 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 673 * interrupt was detected we use the full 10ms. 674 */ 675 if (smibest == 0) 676 u_sleep(10000); 677 else if (smibest < 150 * 4 + 350) 678 u_sleep(150); 679 else if ((smibest - 350) / 4 < 10000) 680 u_sleep((smibest - 350) / 4); 681 else 682 u_sleep(10000); 683 684 /* 685 * Do an INIT IPI: deassert RESET 686 * 687 * Use level triggered mode to deassert. It is unclear 688 * why we need to do this. 689 */ 690 lapic->icr_lo = icr_lo | 0x00008500; 691 while (lapic->icr_lo & APIC_DELSTAT_MASK) 692 /* spin */ ; 693 u_sleep(150); /* wait 150us */ 694 695 /* 696 * Next we do a STARTUP IPI: the previous INIT IPI might still be 697 * latched, (P5 bug) this 1st STARTUP would then terminate 698 * immediately, and the previously started INIT IPI would continue. OR 699 * the previous INIT IPI has already run. and this STARTUP IPI will 700 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 701 * will run. 702 */ 703 lapic->icr_lo = icr_lo | 0x00000600 | vector; 704 while (lapic->icr_lo & APIC_DELSTAT_MASK) 705 /* spin */ ; 706 u_sleep(200); /* wait ~200uS */ 707 708 /* 709 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 710 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 711 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 712 * recognized after hardware RESET or INIT IPI. 713 */ 714 lapic->icr_lo = icr_lo | 0x00000600 | vector; 715 while (lapic->icr_lo & APIC_DELSTAT_MASK) 716 /* spin */ ; 717 718 /* Resume normal operation */ 719 cpu_enable_intr(); 720 721 /* wait for it to start, see ap_init() */ 722 set_apic_timer(5000000);/* == 5 seconds */ 723 while (read_apic_timer()) { 724 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid)) 725 return 1; /* return SUCCESS */ 726 } 727 728 return 0; /* return FAILURE */ 729 } 730 731 static 732 int 733 smitest(void) 734 { 735 int64_t ltsc; 736 int64_t ntsc; 737 int64_t ldelta; 738 int64_t ndelta; 739 int count; 740 741 ldelta = 0; 742 ndelta = 0; 743 while (read_apic_timer()) { 744 ltsc = rdtsc(); 745 for (count = 0; count < 100; ++count) 746 ntsc = rdtsc(); /* force loop to occur */ 747 if (ldelta) { 748 ndelta = ntsc - ltsc; 749 if (ldelta > ndelta) 750 ldelta = ndelta; 751 if (ndelta > ldelta * 2) 752 break; 753 } else { 754 ldelta = ntsc - ltsc; 755 } 756 } 757 return(read_apic_timer()); 758 } 759 760 /* 761 * Synchronously flush the TLB on all other CPU's. The current cpu's 762 * TLB is not flushed. If the caller wishes to flush the current cpu's 763 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 764 * 765 * NOTE: If for some reason we were unable to start all cpus we cannot 766 * safely use broadcast IPIs. 767 */ 768 769 static cpumask_t smp_invltlb_req; 770 771 #define SMP_INVLTLB_DEBUG 772 773 void 774 smp_invltlb(void) 775 { 776 struct mdglobaldata *md = mdcpu; 777 #ifdef SMP_INVLTLB_DEBUG 778 long count = 0; 779 long xcount = 0; 780 #endif 781 782 crit_enter_gd(&md->mi); 783 md->gd_invltlb_ret = 0; 784 ++md->mi.gd_cnt.v_smpinvltlb; 785 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 786 #ifdef SMP_INVLTLB_DEBUG 787 again: 788 #endif 789 if (smp_startup_mask == smp_active_mask) { 790 all_but_self_ipi(XINVLTLB_OFFSET); 791 } else { 792 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask, 793 XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 794 } 795 796 #ifdef SMP_INVLTLB_DEBUG 797 if (xcount) 798 kprintf("smp_invltlb: ipi sent\n"); 799 #endif 800 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) != 801 (smp_active_mask & ~md->mi.gd_cpumask)) { 802 cpu_mfence(); 803 cpu_pause(); 804 #ifdef SMP_INVLTLB_DEBUG 805 /* DEBUGGING */ 806 if (++count == 400000000) { 807 print_backtrace(-1); 808 kprintf("smp_invltlb: endless loop %08lx %08lx, " 809 "rflags %016jx retry", 810 (long)md->gd_invltlb_ret, 811 (long)smp_invltlb_req, 812 (intmax_t)read_rflags()); 813 __asm __volatile ("sti"); 814 ++xcount; 815 if (xcount > 2) 816 lwkt_process_ipiq(); 817 if (xcount > 3) { 818 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret & 819 ~md->mi.gd_cpumask & 820 smp_active_mask); 821 globaldata_t xgd; 822 823 kprintf("bcpu %d\n", bcpu); 824 xgd = globaldata_find(bcpu); 825 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm); 826 } 827 if (xcount > 5) 828 Debugger("giving up"); 829 count = 0; 830 goto again; 831 } 832 #endif 833 } 834 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 835 crit_exit_gd(&md->mi); 836 } 837 838 /* 839 * Called from Xinvltlb assembly with interrupts disabled. We didn't 840 * bother to bump the critical section count or nested interrupt count 841 * so only do very low level operations here. 842 */ 843 void 844 smp_invltlb_intr(void) 845 { 846 struct mdglobaldata *md = mdcpu; 847 struct mdglobaldata *omd; 848 cpumask_t mask; 849 int cpu; 850 851 cpu_mfence(); 852 mask = smp_invltlb_req; 853 cpu_invltlb(); 854 while (mask) { 855 cpu = BSFCPUMASK(mask); 856 mask &= ~CPUMASK(cpu); 857 omd = (struct mdglobaldata *)globaldata_find(cpu); 858 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask); 859 } 860 } 861 862 void 863 cpu_wbinvd_on_all_cpus_callback(void *arg) 864 { 865 wbinvd(); 866 } 867 868 void 869 smp_invlpg_range_cpusync(void *arg) 870 { 871 vm_offset_t eva, sva, addr; 872 sva = ((struct smp_invlpg_range_cpusync_arg *)arg)->sva; 873 eva = ((struct smp_invlpg_range_cpusync_arg *)arg)->eva; 874 875 for (addr = sva; addr < eva; addr += PAGE_SIZE) { 876 cpu_invlpg((void *)addr); 877 } 878 } 879 880 /* 881 * When called the executing CPU will send an IPI to all other CPUs 882 * requesting that they halt execution. 883 * 884 * Usually (but not necessarily) called with 'other_cpus' as its arg. 885 * 886 * - Signals all CPUs in map to stop. 887 * - Waits for each to stop. 888 * 889 * Returns: 890 * -1: error 891 * 0: NA 892 * 1: ok 893 * 894 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 895 * from executing at same time. 896 */ 897 int 898 stop_cpus(cpumask_t map) 899 { 900 map &= smp_active_mask; 901 902 /* send the Xcpustop IPI to all CPUs in map */ 903 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 904 905 while ((stopped_cpus & map) != map) 906 /* spin */ ; 907 908 return 1; 909 } 910 911 912 /* 913 * Called by a CPU to restart stopped CPUs. 914 * 915 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 916 * 917 * - Signals all CPUs in map to restart. 918 * - Waits for each to restart. 919 * 920 * Returns: 921 * -1: error 922 * 0: NA 923 * 1: ok 924 */ 925 int 926 restart_cpus(cpumask_t map) 927 { 928 /* signal other cpus to restart */ 929 started_cpus = map & smp_active_mask; 930 931 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 932 /* spin */ ; 933 934 return 1; 935 } 936 937 /* 938 * This is called once the mpboot code has gotten us properly relocated 939 * and the MMU turned on, etc. ap_init() is actually the idle thread, 940 * and when it returns the scheduler will call the real cpu_idle() main 941 * loop for the idlethread. Interrupts are disabled on entry and should 942 * remain disabled at return. 943 */ 944 void 945 ap_init(void) 946 { 947 int cpu_id; 948 949 /* 950 * Adjust smp_startup_mask to signal the BSP that we have started 951 * up successfully. Note that we do not yet hold the BGL. The BSP 952 * is waiting for our signal. 953 * 954 * We can't set our bit in smp_active_mask yet because we are holding 955 * interrupts physically disabled and remote cpus could deadlock 956 * trying to send us an IPI. 957 */ 958 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid); 959 cpu_mfence(); 960 961 /* 962 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 963 * non-zero, then get the MP lock. 964 * 965 * Note: We are in a critical section. 966 * 967 * Note: we are the idle thread, we can only spin. 968 * 969 * Note: The load fence is memory volatile and prevents the compiler 970 * from improperly caching mp_finish_lapic, and the cpu from improperly 971 * caching it. 972 */ 973 while (mp_finish_lapic == 0) 974 cpu_lfence(); 975 while (try_mplock() == 0) 976 ; 977 978 if (cpu_feature & CPUID_TSC) { 979 /* 980 * The BSP is constantly updating tsc0_offset, figure out 981 * the relative difference to synchronize ktrdump. 982 */ 983 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 984 } 985 986 /* BSP may have changed PTD while we're waiting for the lock */ 987 cpu_invltlb(); 988 989 /* Build our map of 'other' CPUs. */ 990 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 991 992 /* A quick check from sanity claus */ 993 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 994 if (mycpu->gd_cpuid != cpu_id) { 995 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 996 kprintf("SMP: actual cpuid = %d lapicid %d\n", 997 cpu_id, (lapic->id & 0xff000000) >> 24); 998 #if JGXXX 999 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 1000 #endif 1001 panic("cpuid mismatch! boom!!"); 1002 } 1003 1004 /* Initialize AP's local APIC for irq's */ 1005 lapic_init(FALSE); 1006 1007 /* LAPIC initialization is done */ 1008 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid); 1009 cpu_mfence(); 1010 1011 /* Let BSP move onto the next initialization stage */ 1012 rel_mplock(); 1013 1014 /* 1015 * Interlock for finalization. Wait until mp_finish is non-zero, 1016 * then get the MP lock. 1017 * 1018 * Note: We are in a critical section. 1019 * 1020 * Note: we are the idle thread, we can only spin. 1021 * 1022 * Note: The load fence is memory volatile and prevents the compiler 1023 * from improperly caching mp_finish, and the cpu from improperly 1024 * caching it. 1025 */ 1026 while (mp_finish == 0) 1027 cpu_lfence(); 1028 while (try_mplock() == 0) 1029 ; 1030 1031 /* BSP may have changed PTD while we're waiting for the lock */ 1032 cpu_invltlb(); 1033 1034 /* Set memory range attributes for this CPU to match the BSP */ 1035 mem_range_AP_init(); 1036 1037 /* 1038 * Once we go active we must process any IPIQ messages that may 1039 * have been queued, because no actual IPI will occur until we 1040 * set our bit in the smp_active_mask. If we don't the IPI 1041 * message interlock could be left set which would also prevent 1042 * further IPIs. 1043 * 1044 * The idle loop doesn't expect the BGL to be held and while 1045 * lwkt_switch() normally cleans things up this is a special case 1046 * because we returning almost directly into the idle loop. 1047 * 1048 * The idle thread is never placed on the runq, make sure 1049 * nothing we've done put it there. 1050 */ 1051 KKASSERT(get_mplock_count(curthread) == 1); 1052 smp_active_mask |= CPUMASK(mycpu->gd_cpuid); 1053 1054 /* 1055 * Enable interrupts here. idle_restore will also do it, but 1056 * doing it here lets us clean up any strays that got posted to 1057 * the CPU during the AP boot while we are still in a critical 1058 * section. 1059 */ 1060 __asm __volatile("sti; pause; pause"::); 1061 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1062 1063 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1064 lwkt_process_ipiq(); 1065 1066 /* 1067 * Releasing the mp lock lets the BSP finish up the SMP init 1068 */ 1069 rel_mplock(); 1070 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1071 } 1072 1073 /* 1074 * Get SMP fully working before we start initializing devices. 1075 */ 1076 static 1077 void 1078 ap_finish(void) 1079 { 1080 mp_finish = 1; 1081 if (bootverbose) 1082 kprintf("Finish MP startup\n"); 1083 rel_mplock(); 1084 while (smp_active_mask != smp_startup_mask) 1085 cpu_lfence(); 1086 while (try_mplock() == 0) 1087 ; 1088 if (bootverbose) { 1089 kprintf("Active CPU Mask: %016jx\n", 1090 (uintmax_t)smp_active_mask); 1091 } 1092 } 1093 1094 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL) 1095 1096 void 1097 cpu_send_ipiq(int dcpu) 1098 { 1099 if (CPUMASK(dcpu) & smp_active_mask) 1100 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1101 } 1102 1103 #if 0 /* single_apic_ipi_passive() not working yet */ 1104 /* 1105 * Returns 0 on failure, 1 on success 1106 */ 1107 int 1108 cpu_send_ipiq_passive(int dcpu) 1109 { 1110 int r = 0; 1111 if (CPUMASK(dcpu) & smp_active_mask) { 1112 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1113 APIC_DELMODE_FIXED); 1114 } 1115 return(r); 1116 } 1117 #endif 1118 1119 static void 1120 mp_bsp_simple_setup(void) 1121 { 1122 /* build our map of 'other' CPUs */ 1123 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 1124 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 1125 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 1126 1127 pmap_set_opt(); 1128 1129 if (cpu_feature & CPUID_TSC) 1130 tsc0_offset = rdtsc(); 1131 } 1132 1133 1134 /* 1135 * CPU TOPOLOGY DETECTION FUNCTIONS 1136 */ 1137 1138 /* Detect intel topology using CPUID 1139 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1140 */ 1141 static void 1142 detect_intel_topology(int count_htt_cores) 1143 { 1144 int shift = 0; 1145 int ecx_index = 0; 1146 int core_plus_logical_bits = 0; 1147 int cores_per_package; 1148 int logical_per_package; 1149 int logical_per_core; 1150 unsigned int p[4]; 1151 1152 if (cpu_high >= 0xb) { 1153 goto FUNC_B; 1154 1155 } else if (cpu_high >= 0x4) { 1156 goto FUNC_4; 1157 1158 } else { 1159 core_bits = 0; 1160 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1161 ; 1162 logical_CPU_bits = 1 << shift; 1163 return; 1164 } 1165 1166 FUNC_B: 1167 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1168 1169 /* if 0xb not supported - fallback to 0x4 */ 1170 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1171 goto FUNC_4; 1172 } 1173 1174 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1175 1176 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1177 do { 1178 cpuid_count(0xb, ecx_index, p); 1179 1180 /* Check for the Core type in the implemented sub leaves. */ 1181 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1182 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1183 break; 1184 } 1185 1186 ecx_index++; 1187 1188 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1189 1190 core_bits = core_plus_logical_bits - logical_CPU_bits; 1191 1192 return; 1193 1194 FUNC_4: 1195 cpuid_count(0x4, 0, p); 1196 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1197 1198 logical_per_package = count_htt_cores; 1199 logical_per_core = logical_per_package / cores_per_package; 1200 1201 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1202 ; 1203 logical_CPU_bits = shift; 1204 1205 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1206 ; 1207 core_bits = shift; 1208 1209 return; 1210 } 1211 1212 /* Detect AMD topology using CPUID 1213 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1214 */ 1215 static void 1216 detect_amd_topology(int count_htt_cores) 1217 { 1218 int shift = 0; 1219 if ((cpu_feature & CPUID_HTT) 1220 && (amd_feature2 & AMDID2_CMP)) { 1221 1222 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1223 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) 1224 >> AMDID_COREID_SIZE_SHIFT; 1225 } else { 1226 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1227 for (shift = 0; (1 << shift) < core_bits; ++shift) 1228 ; 1229 core_bits = shift; 1230 } 1231 1232 logical_CPU_bits = count_htt_cores >> core_bits; 1233 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1234 ; 1235 logical_CPU_bits = shift; 1236 } else { 1237 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1238 ; 1239 core_bits = shift; 1240 logical_CPU_bits = 0; 1241 } 1242 } 1243 1244 /* Calculate 1245 * - logical_CPU_bits 1246 * - core_bits 1247 * With the values above (for AMD or INTEL) we are able to generally 1248 * detect the CPU topology (number of cores for each level): 1249 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1250 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1251 */ 1252 void 1253 detect_cpu_topology(void) 1254 { 1255 static int topology_detected = 0; 1256 int count = 0; 1257 1258 if (topology_detected) { 1259 goto OUT; 1260 } 1261 1262 if ((cpu_feature & CPUID_HTT) == 0) { 1263 core_bits = 0; 1264 logical_CPU_bits = 0; 1265 goto OUT; 1266 } else { 1267 count = (cpu_procinfo & CPUID_HTT_CORES) 1268 >> CPUID_HTT_CORE_SHIFT; 1269 } 1270 1271 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1272 detect_intel_topology(count); 1273 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 1274 detect_amd_topology(count); 1275 } 1276 1277 OUT: 1278 if (bootverbose) 1279 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n", 1280 logical_CPU_bits, core_bits); 1281 1282 topology_detected = 1; 1283 } 1284 1285 /* Interface functions to calculate chip_ID, 1286 * core_number and logical_number 1287 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1288 */ 1289 int 1290 get_chip_ID(int cpuid) 1291 { 1292 return get_apicid_from_cpuid(cpuid) >> 1293 (logical_CPU_bits + core_bits); 1294 } 1295 1296 int 1297 get_core_number_within_chip(int cpuid) 1298 { 1299 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1300 ( (1 << core_bits) -1); 1301 } 1302 1303 int 1304 get_logical_CPU_number_within_core(int cpuid) 1305 { 1306 return get_apicid_from_cpuid(cpuid) & 1307 ( (1 << logical_CPU_bits) -1); 1308 } 1309