1 /* 2 * Copyright (c) 2003-2011 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * pmap invalidation support code. Certain hardware requirements must 37 * be dealt with when manipulating page table entries and page directory 38 * entries within a pmap. In particular, we cannot safely manipulate 39 * page tables which are in active use by another cpu (even if it is 40 * running in userland) for two reasons: First, TLB writebacks will 41 * race against our own modifications and tests. Second, even if we 42 * were to use bus-locked instruction we can still screw up the 43 * target cpu's instruction pipeline due to Intel cpu errata. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/proc.h> 50 #include <sys/vmmeter.h> 51 #include <sys/thread2.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <vm/vm_object.h> 56 57 #include <machine/cputypes.h> 58 #include <machine/md_var.h> 59 #include <machine/specialreg.h> 60 #include <machine/smp.h> 61 #include <machine/globaldata.h> 62 #include <machine/pmap.h> 63 #include <machine/pmap_inval.h> 64 65 static void pmap_inval_callback(void *arg); 66 67 /* 68 * Initialize for add or flush 69 * 70 * The critical section is required to prevent preemption, allowing us to 71 * set CPUMASK_LOCK on the pmap. The critical section is also assumed 72 * when lwkt_process_ipiq() is called. 73 */ 74 void 75 pmap_inval_init(pmap_inval_info_t info) 76 { 77 info->pir_flags = 0; 78 crit_enter_id("inval"); 79 } 80 81 /* 82 * Add a (pmap, va) pair to the invalidation list and protect access 83 * as appropriate. 84 * 85 * CPUMASK_LOCK is used to interlock thread switchins, otherwise another 86 * cpu can switch in a pmap that we are unaware of and interfere with our 87 * pte operation. 88 */ 89 void 90 pmap_inval_interlock(pmap_inval_info_t info, pmap_t pmap, vm_offset_t va) 91 { 92 cpumask_t oactive; 93 #ifdef SMP 94 cpumask_t nactive; 95 96 DEBUG_PUSH_INFO("pmap_inval_interlock"); 97 for (;;) { 98 oactive = pmap->pm_active; 99 cpu_ccfence(); 100 nactive = oactive | CPUMASK_LOCK; 101 if ((oactive & CPUMASK_LOCK) == 0 && 102 atomic_cmpset_cpumask(&pmap->pm_active, oactive, nactive)) { 103 break; 104 } 105 lwkt_process_ipiq(); 106 cpu_pause(); 107 } 108 DEBUG_POP_INFO(); 109 #else 110 oactive = pmap->pm_active & ~CPUMASK_LOCK; 111 #endif 112 KKASSERT((info->pir_flags & PIRF_CPUSYNC) == 0); 113 info->pir_va = va; 114 info->pir_flags = PIRF_CPUSYNC; 115 lwkt_cpusync_init(&info->pir_cpusync, oactive, pmap_inval_callback, info); 116 lwkt_cpusync_interlock(&info->pir_cpusync); 117 } 118 119 void 120 pmap_inval_deinterlock(pmap_inval_info_t info, pmap_t pmap) 121 { 122 KKASSERT(info->pir_flags & PIRF_CPUSYNC); 123 #ifdef SMP 124 atomic_clear_cpumask(&pmap->pm_active, CPUMASK_LOCK); 125 #endif 126 lwkt_cpusync_deinterlock(&info->pir_cpusync); 127 info->pir_flags = 0; 128 } 129 130 static void 131 pmap_inval_callback(void *arg) 132 { 133 pmap_inval_info_t info = arg; 134 135 if (info->pir_va == (vm_offset_t)-1) 136 cpu_invltlb(); 137 else 138 cpu_invlpg((void *)info->pir_va); 139 } 140 141 void 142 pmap_inval_done(pmap_inval_info_t info) 143 { 144 KKASSERT((info->pir_flags & PIRF_CPUSYNC) == 0); 145 crit_exit_id("inval"); 146 } 147 148