1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 */ 71 72//#include "use_npx.h" 73 74#include <sys/rtprio.h> 75 76#include <machine/asmacros.h> 77#include <machine/segments.h> 78 79#include <machine/pmap.h> 80#if JG 81#include <machine_base/apic/apicreg.h> 82#endif 83#include <machine/lock.h> 84 85#include "assym.s" 86 87#if defined(SMP) 88#define MPLOCKED lock ; 89#else 90#define MPLOCKED 91#endif 92 93 .data 94 95 .globl panic 96 .globl lwkt_switch_return 97 98#if defined(SWTCH_OPTIM_STATS) 99 .globl swtch_optim_stats, tlb_flush_count 100swtch_optim_stats: .long 0 /* number of _swtch_optims */ 101tlb_flush_count: .long 0 102#endif 103 104 .text 105 106 107/* 108 * cpu_heavy_switch(struct thread *next_thread) 109 * 110 * Switch from the current thread to a new thread. This entry 111 * is normally called via the thread->td_switch function, and will 112 * only be called when the current thread is a heavy weight process. 113 * 114 * Some instructions have been reordered to reduce pipeline stalls. 115 * 116 * YYY disable interrupts once giant is removed. 117 */ 118ENTRY(cpu_heavy_switch) 119 /* 120 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 121 */ 122 movq PCPU(curthread),%rcx 123 /* On top of the stack is the return adress. */ 124 movq (%rsp),%rax /* (reorder optimization) */ 125 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 126 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 127 movq %rbx,PCB_RBX(%rdx) 128 movq %rsp,PCB_RSP(%rdx) 129 movq %rbp,PCB_RBP(%rdx) 130 movq %r12,PCB_R12(%rdx) 131 movq %r13,PCB_R13(%rdx) 132 movq %r14,PCB_R14(%rdx) 133 movq %r15,PCB_R15(%rdx) 134 135 /* 136 * Clear the cpu bit in the pmap active mask. The restore 137 * function will set the bit in the pmap active mask. 138 * 139 * Special case: when switching between threads sharing the 140 * same vmspace if we avoid clearing the bit we do not have 141 * to reload %cr3 (if we clear the bit we could race page 142 * table ops done by other threads and would have to reload 143 * %cr3, because those ops will not know to IPI us). 144 */ 145 movq %rcx,%rbx /* RBX = oldthread */ 146 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 147 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 148 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 149 testq %r13,%r13 /* might not be a heavy */ 150 jz 1f 151 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 152 je 2f 1531: 154 movslq PCPU(cpuid), %rax 155 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 1562: 157 158 /* 159 * Push the LWKT switch restore function, which resumes a heavy 160 * weight process. Note that the LWKT switcher is based on 161 * TD_SP, while the heavy weight process switcher is based on 162 * PCB_RSP. TD_SP is usually two ints pushed relative to 163 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 164 */ 165 pushfq 166 movq $cpu_heavy_restore, %rax 167 pushq %rax 168 movq %rsp,TD_SP(%rbx) 169 170 /* 171 * Save debug regs if necessary 172 */ 173 movq PCB_FLAGS(%rdx),%rax 174 andq $PCB_DBREGS,%rax 175 jz 1f /* no, skip over */ 176 movq %dr7,%rax /* yes, do the save */ 177 movq %rax,PCB_DR7(%rdx) 178 /* JG correct value? */ 179 andq $0x0000fc00, %rax /* disable all watchpoints */ 180 movq %rax,%dr7 181 movq %dr6,%rax 182 movq %rax,PCB_DR6(%rdx) 183 movq %dr3,%rax 184 movq %rax,PCB_DR3(%rdx) 185 movq %dr2,%rax 186 movq %rax,PCB_DR2(%rdx) 187 movq %dr1,%rax 188 movq %rax,PCB_DR1(%rdx) 189 movq %dr0,%rax 190 movq %rax,PCB_DR0(%rdx) 1911: 192 193#if 1 194 /* 195 * Save the FP state if we have used the FP. Note that calling 196 * npxsave will NULL out PCPU(npxthread). 197 */ 198 cmpq %rbx,PCPU(npxthread) 199 jne 1f 200 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 201 movq TD_SAVEFPU(%rbx),%rdi 202 call npxsave /* do it in a big C function */ 203 movq %r12,%rdi /* restore %rdi */ 2041: 205#endif 206 207 /* 208 * Switch to the next thread, which was passed as an argument 209 * to cpu_heavy_switch(). The argument is in %rdi. 210 * Set the current thread, load the stack pointer, 211 * and 'ret' into the switch-restore function. 212 * 213 * The switch restore function expects the new thread to be in %rax 214 * and the old one to be in %rbx. 215 * 216 * There is a one-instruction window where curthread is the new 217 * thread but %rsp still points to the old thread's stack, but 218 * we are protected by a critical section so it is ok. 219 */ 220 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 221 movq %rax,PCPU(curthread) 222 movq TD_SP(%rax),%rsp 223 ret 224 225/* 226 * cpu_exit_switch(struct thread *next) 227 * 228 * The switch function is changed to this when a thread is going away 229 * for good. We have to ensure that the MMU state is not cached, and 230 * we don't bother saving the existing thread state before switching. 231 * 232 * At this point we are in a critical section and this cpu owns the 233 * thread's token, which serves as an interlock until the switchout is 234 * complete. 235 */ 236ENTRY(cpu_exit_switch) 237 /* 238 * Get us out of the vmspace 239 */ 240 movq KPML4phys,%rcx 241 movq %cr3,%rax 242#if 1 243 cmpq %rcx,%rax 244 je 1f 245#endif 246 /* JG no increment of statistics counters? see cpu_heavy_restore */ 247 movq %rcx,%cr3 2481: 249 movq PCPU(curthread),%rbx 250 251 /* 252 * If this is a process/lwp, deactivate the pmap after we've 253 * switched it out. 254 */ 255 movq TD_LWP(%rbx),%rcx 256 testq %rcx,%rcx 257 jz 2f 258 movslq PCPU(cpuid), %rax 259 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 260 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 2612: 262 /* 263 * Switch to the next thread. RET into the restore function, which 264 * expects the new thread in RAX and the old in RBX. 265 * 266 * There is a one-instruction window where curthread is the new 267 * thread but %rsp still points to the old thread's stack, but 268 * we are protected by a critical section so it is ok. 269 */ 270 movq %rdi,%rax 271 movq %rax,PCPU(curthread) 272 movq TD_SP(%rax),%rsp 273 ret 274 275/* 276 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx) 277 * 278 * Restore the thread after an LWKT switch. This entry is normally 279 * called via the LWKT switch restore function, which was pulled 280 * off the thread stack and jumped to. 281 * 282 * This entry is only called if the thread was previously saved 283 * using cpu_heavy_switch() (the heavy weight process thread switcher), 284 * or when a new process is initially scheduled. 285 * 286 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 287 * a preemption switch may interrupt the process and then return via 288 * cpu_heavy_restore. 289 * 290 * YYY theoretically we do not have to restore everything here, a lot 291 * of this junk can wait until we return to usermode. But for now 292 * we restore everything. 293 * 294 * YYY the PCB crap is really crap, it makes startup a bitch because 295 * we can't switch away. 296 * 297 * YYY note: spl check is done in mi_switch when it splx()'s. 298 */ 299 300ENTRY(cpu_heavy_restore) 301 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 302 movq %rdx, PCPU(common_tss) + TSS_RSP0 303 popfq 304 305#if defined(SWTCH_OPTIM_STATS) 306 incl _swtch_optim_stats 307#endif 308 /* 309 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 310 * safely test/reload %cr3 until after we have set the bit in the 311 * pmap. 312 * 313 * We must do an interlocked test of the CPUMASK_BIT at the same 314 * time. If found to be set we will have to wait for it to clear 315 * and then do a forced reload of %cr3 (even if the value matches). 316 * 317 * XXX When switching between two LWPs sharing the same vmspace 318 * the cpu_heavy_switch() code currently avoids clearing the 319 * cpu bit in PM_ACTIVE. So if the bit is already set we can 320 * avoid checking for the interlock via CPUMASK_BIT. We currently 321 * do not perform this optimization. 322 * 323 * %rax is needed for the cmpxchgl so store newthread in %r12 324 * temporarily. 325 */ 326 movq TD_LWP(%rax),%rcx 327 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */ 328#ifdef SMP 329 movq %rax,%r12 /* save newthread ptr */ 3301: 331 movq VM_PMAP+PM_ACTIVE(%rcx),%rax /* old contents */ 332 movq PCPU(cpumask),%rsi /* new contents */ 333 orq %rax,%rsi 334 MPLOCKED cmpxchgq %rsi,VM_PMAP+PM_ACTIVE(%rcx) 335 jnz 1b 336 337 /* 338 * Check CPUMASK_BIT 339 */ 340 btq $CPUMASK_BIT,%rax /* test interlock */ 341 jnc 1f 342 343#if 0 344 movq TD_PCB(%r12),%rdx /* XXX debugging unconditional */ 345 movq PCB_CR3(%rdx),%rdx /* reloading of %cr3 */ 346 movq %rdx,%cr3 347#endif 348 349 movq %rcx,%rdi /* (found to be set) */ 350 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 351 352 /* 353 * Need unconditional load cr3 354 */ 355 movq %r12,%rax 356 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 357 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 358 jmp 2f /* unconditional reload */ 3591: 360 movq %r12,%rax /* restore RAX = newthread */ 361#else 362 movq PCPU(cpumask),%rsi 363 orq %rsi,VM_PMAP+PM_ACTIVE(%rcx) 364#endif 365 /* 366 * Restore the MMU address space. If it is the same as the last 367 * thread we don't have to invalidate the tlb (i.e. reload cr3). 368 * YYY which naturally also means that the PM_ACTIVE bit had better 369 * already have been set before we set it above, check? YYY 370 */ 371 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 372 movq %cr3,%rsi /* RSI = current CR3 */ 373 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 374 cmpq %rsi,%rcx 375 je 4f 3762: 377#if defined(SWTCH_OPTIM_STATS) 378 decl _swtch_optim_stats 379 incl _tlb_flush_count 380#endif 381 movq %rcx,%cr3 3824: 383 384 /* 385 * NOTE: %rbx is the previous thread and %rax is the new thread. 386 * %rbx is retained throughout so we can return it. 387 * 388 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 389 */ 390 391 /* 392 * Deal with the PCB extension, restore the private tss 393 */ 394 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 395 movq $1,%rcx /* maybe mark use of a private tss */ 396 testq %rdi,%rdi 397#if JG 398 jnz 2f 399#endif 400 401 /* 402 * Going back to the common_tss. We may need to update TSS_RSP0 403 * which sets the top of the supervisor stack when entering from 404 * usermode. The PCB is at the top of the stack but we need another 405 * 16 bytes to take vm86 into account. 406 */ 407 movq %rdx,%rcx 408 /*leaq -TF_SIZE(%rdx),%rcx*/ 409 movq %rcx, PCPU(common_tss) + TSS_RSP0 410 411#if JG 412 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 413 je 3f /* already using the common TSS */ 414 415 /* JG? */ 416 subq %rcx,%rcx /* unmark use of private tss */ 417 418 /* 419 * Get the address of the common TSS descriptor for the ltr. 420 * There is no way to get the address of a segment-accessed variable 421 * so we store a self-referential pointer at the base of the per-cpu 422 * data area and add the appropriate offset. 423 */ 424 /* JG movl? */ 425 movq $gd_common_tssd, %rdi 426 /* JG name for "%gs:0"? */ 427 addq %gs:0, %rdi 428 429 /* 430 * Move the correct TSS descriptor into the GDT slot, then reload 431 * ltr. 432 */ 4332: 434 /* JG */ 435 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 436 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 437 movq 0(%rdi), %rax 438 movq %rax, 0(%rbx) 439 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 440 ltr %si 441#endif 442 4433: 444 /* 445 * Restore the user %gs and %fs 446 */ 447 movq PCB_FSBASE(%rdx),%r9 448 cmpq PCPU(user_fs),%r9 449 je 4f 450 movq %rdx,%r10 451 movq %r9,PCPU(user_fs) 452 movl $MSR_FSBASE,%ecx 453 movl PCB_FSBASE(%r10),%eax 454 movl PCB_FSBASE+4(%r10),%edx 455 wrmsr 456 movq %r10,%rdx 4574: 458 movq PCB_GSBASE(%rdx),%r9 459 cmpq PCPU(user_gs),%r9 460 je 5f 461 movq %rdx,%r10 462 movq %r9,PCPU(user_gs) 463 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 464 movl PCB_GSBASE(%r10),%eax 465 movl PCB_GSBASE+4(%r10),%edx 466 wrmsr 467 movq %r10,%rdx 4685: 469 470 /* 471 * Restore general registers. %rbx is restored later. 472 */ 473 movq PCB_RSP(%rdx), %rsp 474 movq PCB_RBP(%rdx), %rbp 475 movq PCB_R12(%rdx), %r12 476 movq PCB_R13(%rdx), %r13 477 movq PCB_R14(%rdx), %r14 478 movq PCB_R15(%rdx), %r15 479 movq PCB_RIP(%rdx), %rax 480 movq %rax, (%rsp) 481 482#if JG 483 /* 484 * Restore the user LDT if we have one 485 */ 486 cmpl $0, PCB_USERLDT(%edx) 487 jnz 1f 488 movl _default_ldt,%eax 489 cmpl PCPU(currentldt),%eax 490 je 2f 491 lldt _default_ldt 492 movl %eax,PCPU(currentldt) 493 jmp 2f 4941: pushl %edx 495 call set_user_ldt 496 popl %edx 4972: 498#endif 499#if JG 500 /* 501 * Restore the user TLS if we have one 502 */ 503 pushl %edx 504 call set_user_TLS 505 popl %edx 506#endif 507 508 /* 509 * Restore the DEBUG register state if necessary. 510 */ 511 movq PCB_FLAGS(%rdx),%rax 512 andq $PCB_DBREGS,%rax 513 jz 1f /* no, skip over */ 514 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 515 movq %rax,%dr6 516 movq PCB_DR3(%rdx),%rax 517 movq %rax,%dr3 518 movq PCB_DR2(%rdx),%rax 519 movq %rax,%dr2 520 movq PCB_DR1(%rdx),%rax 521 movq %rax,%dr1 522 movq PCB_DR0(%rdx),%rax 523 movq %rax,%dr0 524 movq %dr7,%rax /* load dr7 so as not to disturb */ 525 /* JG correct value? */ 526 andq $0x0000fc00,%rax /* reserved bits */ 527 /* JG we've got more registers on x86_64 */ 528 movq PCB_DR7(%rdx),%rcx 529 /* JG correct value? */ 530 andq $~0x0000fc00,%rcx 531 orq %rcx,%rax 532 movq %rax,%dr7 533 534 /* 535 * Clear the QUICKRET flag when restoring a user process context 536 * so we don't try to do a quick syscall return. 537 */ 5381: 539 andl $~RQF_QUICKRET,PCPU(reqflags) 540 movq %rbx,%rax 541 movq PCB_RBX(%rdx),%rbx 542 ret 543 544/* 545 * savectx(struct pcb *pcb) 546 * 547 * Update pcb, saving current processor state. 548 */ 549ENTRY(savectx) 550 /* fetch PCB */ 551 /* JG use %rdi instead of %rcx everywhere? */ 552 movq %rdi,%rcx 553 554 /* caller's return address - child won't execute this routine */ 555 movq (%rsp),%rax 556 movq %rax,PCB_RIP(%rcx) 557 558 movq %cr3,%rax 559 movq %rax,PCB_CR3(%rcx) 560 561 movq %rbx,PCB_RBX(%rcx) 562 movq %rsp,PCB_RSP(%rcx) 563 movq %rbp,PCB_RBP(%rcx) 564 movq %r12,PCB_R12(%rcx) 565 movq %r13,PCB_R13(%rcx) 566 movq %r14,PCB_R14(%rcx) 567 movq %r15,PCB_R15(%rcx) 568 569#if 1 570 /* 571 * If npxthread == NULL, then the npx h/w state is irrelevant and the 572 * state had better already be in the pcb. This is true for forks 573 * but not for dumps (the old book-keeping with FP flags in the pcb 574 * always lost for dumps because the dump pcb has 0 flags). 575 * 576 * If npxthread != NULL, then we have to save the npx h/w state to 577 * npxthread's pcb and copy it to the requested pcb, or save to the 578 * requested pcb and reload. Copying is easier because we would 579 * have to handle h/w bugs for reloading. We used to lose the 580 * parent's npx state for forks by forgetting to reload. 581 */ 582 movq PCPU(npxthread),%rax 583 testq %rax,%rax 584 jz 1f 585 586 pushq %rcx /* target pcb */ 587 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 588 pushq %rax 589 590 movq %rax,%rdi 591 call npxsave 592 593 popq %rax 594 popq %rcx 595 596 movq $PCB_SAVEFPU_SIZE,%rdx 597 leaq PCB_SAVEFPU(%rcx),%rcx 598 movq %rcx,%rsi 599 movq %rax,%rdi 600 call bcopy 601#endif 602 6031: 604 ret 605 606/* 607 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 608 * 609 * Don't bother setting up any regs other than %rbp so backtraces 610 * don't die. This restore function is used to bootstrap into the 611 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 612 * switching. 613 * 614 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 615 * This only occurs during system boot so no special handling is 616 * required for migration. 617 * 618 * If we are an AP we have to call ap_init() before jumping to 619 * cpu_idle(). ap_init() will synchronize with the BP and finish 620 * setting up various ncpu-dependant globaldata fields. This may 621 * happen on UP as well as SMP if we happen to be simulating multiple 622 * cpus. 623 */ 624ENTRY(cpu_idle_restore) 625 /* cli */ 626 movq KPML4phys,%rcx 627 /* JG xor? */ 628 movq $0,%rbp 629 /* JG push RBP? */ 630 pushq $0 631 movq %rcx,%cr3 632 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 633 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 634#ifdef SMP 635 cmpl $0,PCPU(cpuid) 636 je 1f 637 call ap_init 6381: 639#endif 640 /* 641 * ap_init can decide to enable interrupts early, but otherwise, or if 642 * we are UP, do it here. 643 */ 644 sti 645 jmp cpu_idle 646 647/* 648 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx) 649 * (one-time execution) 650 * 651 * Don't bother setting up any regs other then %rbp so backtraces 652 * don't die. This restore function is used to bootstrap into an 653 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 654 * after this. 655 * 656 * Because this switch target does not 'return' to lwkt_switch() 657 * we have to call lwkt_switch_return(otd) to clean up otd. 658 * otd is in %ebx. 659 * 660 * Since all of our context is on the stack we are reentrant and 661 * we can release our critical section and enable interrupts early. 662 */ 663ENTRY(cpu_kthread_restore) 664 sti 665 movq KPML4phys,%rcx 666 movq TD_PCB(%rax),%r13 667 xorq %rbp,%rbp 668 movq %rcx,%cr3 669 670 /* 671 * rax and rbx come from the switchout code. Call 672 * lwkt_switch_return(otd). 673 * 674 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 675 */ 676 pushq %rax 677 movq %rbx,%rdi 678 call lwkt_switch_return 679 popq %rax 680 decl TD_CRITCOUNT(%rax) 681 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 682 movq PCB_RBX(%r13),%rax /* thread function */ 683 /* note: top of stack return address inherited by function */ 684 jmp *%rax 685 686/* 687 * cpu_lwkt_switch(struct thread *) 688 * 689 * Standard LWKT switching function. Only non-scratch registers are 690 * saved and we don't bother with the MMU state or anything else. 691 * 692 * This function is always called while in a critical section. 693 * 694 * There is a one-instruction window where curthread is the new 695 * thread but %rsp still points to the old thread's stack, but 696 * we are protected by a critical section so it is ok. 697 */ 698ENTRY(cpu_lwkt_switch) 699 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */ 700 pushq %rbx 701 movq PCPU(curthread),%rbx /* becomes old thread in restore */ 702 pushq %r12 703 pushq %r13 704 pushq %r14 705 pushq %r15 706 pushfq 707 708#if 1 709 /* 710 * Save the FP state if we have used the FP. Note that calling 711 * npxsave will NULL out PCPU(npxthread). 712 * 713 * We have to deal with the FP state for LWKT threads in case they 714 * happen to get preempted or block while doing an optimized 715 * bzero/bcopy/memcpy. 716 */ 717 cmpq %rbx,PCPU(npxthread) 718 jne 1f 719 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 720 movq TD_SAVEFPU(%rbx),%rdi 721 call npxsave /* do it in a big C function */ 722 movq %r12,%rdi /* restore %rdi */ 7231: 724#endif 725 726 movq %rdi,%rax /* switch to this thread */ 727 pushq $cpu_lwkt_restore 728 movq %rsp,TD_SP(%rbx) 729 /* 730 * %rax contains new thread, %rbx contains old thread. 731 */ 732 movq %rax,PCPU(curthread) 733 movq TD_SP(%rax),%rsp 734 ret 735 736/* 737 * cpu_lwkt_restore() (current thread in %rax on entry) 738 * 739 * Standard LWKT restore function. This function is always called 740 * while in a critical section. 741 * 742 * Warning: due to preemption the restore function can be used to 743 * 'return' to the original thread. Interrupt disablement must be 744 * protected through the switch so we cannot run splz here. 745 * 746 * YYY we theoretically do not need to load KPML4phys into cr3, but if 747 * so we need a way to detect when the PTD we are using is being 748 * deleted due to a process exiting. 749 */ 750ENTRY(cpu_lwkt_restore) 751 movq KPML4phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */ 752 movq %cr3,%rdx 753#if 1 754 cmpq %rcx,%rdx 755 je 1f 756#endif 757 movq %rcx,%cr3 7581: 759 /* 760 * Safety, clear RSP0 in the tss so it isn't pointing at the 761 * previous thread's kstack (if a heavy weight user thread). 762 * RSP0 should only be used in ring 3 transitions and kernel 763 * threads run in ring 0 so there should be none. 764 */ 765 xorq %rdx,%rdx 766 movq %rdx, PCPU(common_tss) + TSS_RSP0 767 768 /* 769 * NOTE: %rbx is the previous thread and %rax is the new thread. 770 * %rbx is retained throughout so we can return it. 771 * 772 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 773 */ 774 movq %rbx,%rax 775 popfq 776 popq %r15 777 popq %r14 778 popq %r13 779 popq %r12 780 popq %rbx 781 popq %rbp 782 ret 783