1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 * $DragonFly: src/sys/platform/pc64/amd64/swtch.s,v 1.3 2008/08/29 17:07:10 dillon Exp $ 71 */ 72 73//#include "use_npx.h" 74 75#include <sys/rtprio.h> 76 77#include <machine/asmacros.h> 78#include <machine/segments.h> 79 80#include <machine/pmap.h> 81#include <machine/lock.h> 82 83#define CHECKNZ(expr, scratch_reg) \ 84 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7: 85 86#include "assym.s" 87 88#if defined(SMP) 89#define MPLOCKED lock ; 90#else 91#define MPLOCKED 92#endif 93 94 .data 95 96 .globl panic 97 98#if defined(SWTCH_OPTIM_STATS) 99 .globl swtch_optim_stats, tlb_flush_count 100swtch_optim_stats: .long 0 /* number of _swtch_optims */ 101tlb_flush_count: .long 0 102#endif 103 104 .text 105 106 107/* 108 * cpu_heavy_switch(struct thread *next_thread) 109 * 110 * Switch from the current thread to a new thread. This entry 111 * is normally called via the thread->td_switch function, and will 112 * only be called when the current thread is a heavy weight process. 113 * 114 * Some instructions have been reordered to reduce pipeline stalls. 115 * 116 * YYY disable interrupts once giant is removed. 117 */ 118ENTRY(cpu_heavy_switch) 119 /* 120 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 121 */ 122 movq PCPU(curthread),%rcx 123 /* On top of the stack is the return adress. */ 124 movq (%rsp),%rax /* (reorder optimization) */ 125 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 126 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 127 movq %rbx,PCB_RBX(%rdx) 128 movq %rsp,PCB_RSP(%rdx) 129 movq %rbp,PCB_RBP(%rdx) 130 movq %r12,PCB_R12(%rdx) 131 movq %r13,PCB_R13(%rdx) 132 movq %r14,PCB_R14(%rdx) 133 movq %r15,PCB_R15(%rdx) 134 135 movq %rcx,%rbx /* RBX = curthread */ 136 movq TD_LWP(%rcx),%rcx 137 movl PCPU(cpuid), %eax 138 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 139 MPLOCKED btrl %eax, VM_PMAP+PM_ACTIVE(%rcx) 140 141 /* 142 * Push the LWKT switch restore function, which resumes a heavy 143 * weight process. Note that the LWKT switcher is based on 144 * TD_SP, while the heavy weight process switcher is based on 145 * PCB_RSP. TD_SP is usually two ints pushed relative to 146 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 147 */ 148 pushfq 149 movq $cpu_heavy_restore, %rax 150 pushq %rax 151 movq %rsp,TD_SP(%rbx) 152 153 /* 154 * Save debug regs if necessary 155 */ 156 movq PCB_FLAGS(%rdx),%rax 157 andq $PCB_DBREGS,%rax 158 jz 1f /* no, skip over */ 159 movq %dr7,%rax /* yes, do the save */ 160 movq %rax,PCB_DR7(%rdx) 161 /* JG correct value? */ 162 andq $0x0000fc00, %rax /* disable all watchpoints */ 163 movq %rax,%dr7 164 movq %dr6,%rax 165 movq %rax,PCB_DR6(%rdx) 166 movq %dr3,%rax 167 movq %rax,PCB_DR3(%rdx) 168 movq %dr2,%rax 169 movq %rax,PCB_DR2(%rdx) 170 movq %dr1,%rax 171 movq %rax,PCB_DR1(%rdx) 172 movq %dr0,%rax 173 movq %rax,PCB_DR0(%rdx) 1741: 175 176#if 1 177 /* 178 * Save the FP state if we have used the FP. Note that calling 179 * npxsave will NULL out PCPU(npxthread). 180 */ 181 cmpq %rbx,PCPU(npxthread) 182 jne 1f 183 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 184 movq TD_SAVEFPU(%rbx),%rdi 185 call npxsave /* do it in a big C function */ 186 movq %r12,%rdi /* restore %rdi */ 1871: 188#endif 189 190 /* 191 * Switch to the next thread, which was passed as an argument 192 * to cpu_heavy_switch(). The argument is in %rdi. 193 * Set the current thread, load the stack pointer, 194 * and 'ret' into the switch-restore function. 195 * 196 * The switch restore function expects the new thread to be in %rax 197 * and the old one to be in %rbx. 198 * 199 * There is a one-instruction window where curthread is the new 200 * thread but %rsp still points to the old thread's stack, but 201 * we are protected by a critical section so it is ok. 202 */ 203 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 204 movq %rax,PCPU(curthread) 205 movq TD_SP(%rax),%rsp 206 CHECKNZ((%rsp), %r9) 207 ret 208 209/* 210 * cpu_exit_switch(struct thread *next) 211 * 212 * The switch function is changed to this when a thread is going away 213 * for good. We have to ensure that the MMU state is not cached, and 214 * we don't bother saving the existing thread state before switching. 215 * 216 * At this point we are in a critical section and this cpu owns the 217 * thread's token, which serves as an interlock until the switchout is 218 * complete. 219 */ 220ENTRY(cpu_exit_switch) 221 /* 222 * Get us out of the vmspace 223 */ 224#if 0 225 movq KPML4phys,%rcx 226 movq %cr3,%rax 227 cmpq %rcx,%rax 228 je 1f 229 /* JG no increment of statistics counters? see cpu_heavy_restore */ 230 movq %rcx,%cr3 2311: 232#endif 233 movq PCPU(curthread),%rbx 234 235 /* 236 * If this is a process/lwp, deactivate the pmap after we've 237 * switched it out. 238 */ 239 movq TD_LWP(%rbx),%rcx 240 testq %rcx,%rcx 241 jz 2f 242 movl PCPU(cpuid), %eax 243 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 244 MPLOCKED btrl %eax, VM_PMAP+PM_ACTIVE(%rcx) 2452: 246 /* 247 * Switch to the next thread. RET into the restore function, which 248 * expects the new thread in RAX and the old in RBX. 249 * 250 * There is a one-instruction window where curthread is the new 251 * thread but %rsp still points to the old thread's stack, but 252 * we are protected by a critical section so it is ok. 253 */ 254 movq %rdi,%rax 255 movq %rax,PCPU(curthread) 256 movq TD_SP(%rax),%rsp 257 CHECKNZ((%rsp), %r9) 258 ret 259 260/* 261 * cpu_heavy_restore() (current thread in %rax on entry) 262 * 263 * Restore the thread after an LWKT switch. This entry is normally 264 * called via the LWKT switch restore function, which was pulled 265 * off the thread stack and jumped to. 266 * 267 * This entry is only called if the thread was previously saved 268 * using cpu_heavy_switch() (the heavy weight process thread switcher), 269 * or when a new process is initially scheduled. The first thing we 270 * do is clear the TDF_RUNNING bit in the old thread and set it in the 271 * new thread. 272 * 273 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 274 * a preemption switch may interrupt the process and then return via 275 * cpu_heavy_restore. 276 * 277 * YYY theoretically we do not have to restore everything here, a lot 278 * of this junk can wait until we return to usermode. But for now 279 * we restore everything. 280 * 281 * YYY the PCB crap is really crap, it makes startup a bitch because 282 * we can't switch away. 283 * 284 * YYY note: spl check is done in mi_switch when it splx()'s. 285 */ 286 287ENTRY(cpu_heavy_restore) 288 popfq 289 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 290 movq TD_LWP(%rax),%rcx 291 292#if defined(SWTCH_OPTIM_STATS) 293 incl _swtch_optim_stats 294#endif 295 /* 296 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 297 * safely test/reload %cr3 until after we have set the bit in the 298 * pmap (remember, we do not hold the MP lock in the switch code). 299 */ 300 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 301 movl PCPU(cpuid), %esi 302 MPLOCKED btsl %esi, VM_PMAP+PM_ACTIVE(%rcx) 303 304 /* 305 * Restore the MMU address space. If it is the same as the last 306 * thread we don't have to invalidate the tlb (i.e. reload cr3). 307 * YYY which naturally also means that the PM_ACTIVE bit had better 308 * already have been set before we set it above, check? YYY 309 */ 310#if 0 311 movq %cr3,%rsi 312 movq PCB_CR3(%rdx),%rcx 313 cmpq %rsi,%rcx 314 je 4f 315#if defined(SWTCH_OPTIM_STATS) 316 decl _swtch_optim_stats 317 incl _tlb_flush_count 318#endif 319 movq %rcx,%cr3 3204: 321#endif 322 /* 323 * Clear TDF_RUNNING flag in old thread only after cleaning up 324 * %cr3. The target thread is already protected by being TDF_RUNQ 325 * so setting TDF_RUNNING isn't as big a deal. 326 */ 327 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 328 orl $TDF_RUNNING,TD_FLAGS(%rax) 329 330#if 0 331 /* 332 * Deal with the PCB extension, restore the private tss 333 */ 334 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 335 /* JG cheaper than "movq $1,%rbx", right? */ 336 /* JG what's that magic value $1? */ 337 movl $1,%ebx /* maybe mark use of a private tss */ 338 testq %rdi,%rdi 339#if JG 340 jnz 2f 341#endif 342 343 /* JG 344 * Going back to the common_tss. We may need to update TSS_ESP0 345 * which sets the top of the supervisor stack when entering from 346 * usermode. The PCB is at the top of the stack but we need another 347 * 16 bytes to take vm86 into account. 348 */ 349 leaq -16(%rdx),%rbx 350 movq %rbx, PCPU(common_tss) + TSS_RSP0 351 movq %rbx, PCPU(rsp0) 352 353#if JG 354 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 355 je 3f /* already using the common TSS */ 356 357 /* JG? */ 358 subl %ebx,%ebx /* unmark use of private tss */ 359 360 /* 361 * Get the address of the common TSS descriptor for the ltr. 362 * There is no way to get the address of a segment-accessed variable 363 * so we store a self-referential pointer at the base of the per-cpu 364 * data area and add the appropriate offset. 365 */ 366 /* JG movl? */ 367 movq $gd_common_tssd, %rdi 368 /* JG name for "%gs:0"? */ 369 addq %gs:0, %rdi 370 371 /* 372 * Move the correct TSS descriptor into the GDT slot, then reload 373 * ltr. 374 */ 3752: 376 /* JG */ 377 movl %ebx,PCPU(private_tss) /* mark/unmark private tss */ 378 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 379 movq 0(%rdi), %rax 380 movq %rax, 0(%rbx) 381 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 382 ltr %si 383#endif 384 3853: 386#endif 387#if 0 388 /* 389 * Restore the user %gs and %fs 390 */ 391 movq PCB_FSBASE(%rdx),%r9 392 cmpq PCPU(user_fs),%r9 393 je 4f 394 movq %rdx,%r10 395 movq %r9,PCPU(user_fs) 396 movl $MSR_FSBASE,%ecx 397 movl PCB_FSBASE(%r10),%eax 398 movl PCB_FSBASE+4(%r10),%edx 399 wrmsr 400 movq %r10,%rdx 4014: 402 movq PCB_GSBASE(%rdx),%r9 403 cmpq PCPU(user_gs),%r9 404 je 5f 405 movq %rdx,%r10 406 movq %r9,PCPU(user_gs) 407 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 408 movl PCB_GSBASE(%r10),%eax 409 movl PCB_GSBASE+4(%r10),%edx 410 wrmsr 411 movq %r10,%rdx 4125: 413#endif 414 415 /* 416 * Restore general registers. 417 */ 418 movq PCB_RBX(%rdx), %rbx 419 movq PCB_RSP(%rdx), %rsp 420 movq PCB_RBP(%rdx), %rbp 421 movq PCB_R12(%rdx), %r12 422 movq PCB_R13(%rdx), %r13 423 movq PCB_R14(%rdx), %r14 424 movq PCB_R15(%rdx), %r15 425 movq PCB_RIP(%rdx), %rax 426 movq %rax, (%rsp) 427 428#if 0 429 /* 430 * Restore the user LDT if we have one 431 */ 432 cmpl $0, PCB_USERLDT(%edx) 433 jnz 1f 434 movl _default_ldt,%eax 435 cmpl PCPU(currentldt),%eax 436 je 2f 437 lldt _default_ldt 438 movl %eax,PCPU(currentldt) 439 jmp 2f 4401: pushl %edx 441 call set_user_ldt 442 popl %edx 4432: 444#endif 445#if 0 446 /* 447 * Restore the user TLS if we have one 448 */ 449 pushl %edx 450 call set_user_TLS 451 popl %edx 452#endif 453 454 /* 455 * Restore the DEBUG register state if necessary. 456 */ 457 movq PCB_FLAGS(%rdx),%rax 458 andq $PCB_DBREGS,%rax 459 jz 1f /* no, skip over */ 460 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 461 movq %rax,%dr6 462 movq PCB_DR3(%rdx),%rax 463 movq %rax,%dr3 464 movq PCB_DR2(%rdx),%rax 465 movq %rax,%dr2 466 movq PCB_DR1(%rdx),%rax 467 movq %rax,%dr1 468 movq PCB_DR0(%rdx),%rax 469 movq %rax,%dr0 470 movq %dr7,%rax /* load dr7 so as not to disturb */ 471 /* JG correct value? */ 472 andq $0x0000fc00,%rax /* reserved bits */ 473 /* JG we've got more registers on amd64 */ 474 pushq %rbx 475 movq PCB_DR7(%rdx),%rbx 476 /* JG correct value? */ 477 andq $~0x0000fc00,%rbx 478 orq %rbx,%rax 479 popq %rbx 480 movq %rax,%dr7 4811: 482 483 CHECKNZ((%rsp), %r9) 484 ret 485 486/* 487 * savectx(struct pcb *pcb) 488 * 489 * Update pcb, saving current processor state. 490 */ 491ENTRY(savectx) 492 /* fetch PCB */ 493 /* JG use %rdi instead of %rcx everywhere? */ 494 movq %rdi,%rcx 495 496 /* caller's return address - child won't execute this routine */ 497 movq (%rsp),%rax 498 movq %rax,PCB_RIP(%rcx) 499 movq %rbx,PCB_RBX(%rcx) 500 movq %rsp,PCB_RSP(%rcx) 501 movq %rbp,PCB_RBP(%rcx) 502 movq %r12,PCB_R12(%rcx) 503 movq %r13,PCB_R13(%rcx) 504 movq %r14,PCB_R14(%rcx) 505 movq %r15,PCB_R15(%rcx) 506 507#if 1 508 /* 509 * If npxthread == NULL, then the npx h/w state is irrelevant and the 510 * state had better already be in the pcb. This is true for forks 511 * but not for dumps (the old book-keeping with FP flags in the pcb 512 * always lost for dumps because the dump pcb has 0 flags). 513 * 514 * If npxthread != NULL, then we have to save the npx h/w state to 515 * npxthread's pcb and copy it to the requested pcb, or save to the 516 * requested pcb and reload. Copying is easier because we would 517 * have to handle h/w bugs for reloading. We used to lose the 518 * parent's npx state for forks by forgetting to reload. 519 */ 520 movq PCPU(npxthread),%rax 521 testq %rax,%rax 522 jz 1f 523 524 pushq %rcx /* target pcb */ 525 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 526 pushq %rax 527 528 movq %rax,%rdi 529 call npxsave 530 531 popq %rax 532 popq %rcx 533 534 movq $PCB_SAVEFPU_SIZE,%rdx 535 leaq PCB_SAVEFPU(%rcx),%rcx 536 movq %rcx,%rsi 537 movq %rax,%rdi 538 call bcopy 539#endif 540 5411: 542 CHECKNZ((%rsp), %r9) 543 ret 544 545/* 546 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 547 * 548 * Don't bother setting up any regs other than %rbp so backtraces 549 * don't die. This restore function is used to bootstrap into the 550 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 551 * switching. 552 * 553 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 554 * 555 * If we are an AP we have to call ap_init() before jumping to 556 * cpu_idle(). ap_init() will synchronize with the BP and finish 557 * setting up various ncpu-dependant globaldata fields. This may 558 * happen on UP as well as SMP if we happen to be simulating multiple 559 * cpus. 560 */ 561ENTRY(cpu_idle_restore) 562 /* cli */ 563 /* JG xor? */ 564 movl $0,%ebp 565 /* JG push RBP? */ 566 pushq $0 567 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 568 orl $TDF_RUNNING,TD_FLAGS(%rax) 569#ifdef SMP 570 cmpl $0,PCPU(cpuid) 571 je 1f 572 call ap_init 5731: 574#endif 575 /* sti */ 576 jmp cpu_idle 577 578/* 579 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution) 580 * 581 * Don't bother setting up any regs other then %rbp so backtraces 582 * don't die. This restore function is used to bootstrap into an 583 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 584 * after this. 585 * 586 * Since all of our context is on the stack we are reentrant and 587 * we can release our critical section and enable interrupts early. 588 */ 589ENTRY(cpu_kthread_restore) 590 /*sti*/ 591 movq TD_PCB(%rax),%rdx 592 /* JG "movq $0, %rbp"? "xorq %rbp, %rbp"? */ 593 movl $0,%ebp 594 /* rax and rbx come from the switchout code */ 595 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 596 orl $TDF_RUNNING,TD_FLAGS(%rax) 597 subl $TDPRI_CRIT,TD_PRI(%rax) 598 movq PCB_R12(%rdx),%rdi /* argument to RBX function */ 599 movq PCB_RBX(%rdx),%rax /* thread function */ 600 /* note: top of stack return address inherited by function */ 601 CHECKNZ(%rax, %r9) 602 jmp *%rax 603 604/* 605 * cpu_lwkt_switch(struct thread *) 606 * 607 * Standard LWKT switching function. Only non-scratch registers are 608 * saved and we don't bother with the MMU state or anything else. 609 * 610 * This function is always called while in a critical section. 611 * 612 * There is a one-instruction window where curthread is the new 613 * thread but %rsp still points to the old thread's stack, but 614 * we are protected by a critical section so it is ok. 615 * 616 * YYY BGL, SPL 617 */ 618ENTRY(cpu_lwkt_switch) 619 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */ 620 /* JG we've got more registers on AMD64 */ 621 pushq %rbx 622 movq PCPU(curthread),%rbx 623 pushq %r12 624 pushq %r13 625 pushq %r14 626 pushq %r15 627 pushfq 628 629#if 1 630 /* 631 * Save the FP state if we have used the FP. Note that calling 632 * npxsave will NULL out PCPU(npxthread). 633 * 634 * We have to deal with the FP state for LWKT threads in case they 635 * happen to get preempted or block while doing an optimized 636 * bzero/bcopy/memcpy. 637 */ 638 cmpq %rbx,PCPU(npxthread) 639 jne 1f 640 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 641 movq TD_SAVEFPU(%rbx),%rdi 642 call npxsave /* do it in a big C function */ 643 movq %r12,%rdi /* restore %rdi */ 6441: 645#endif 646 647 movq %rdi,%rax /* switch to this thread */ 648 pushq $cpu_lwkt_restore 649 movq %rsp,TD_SP(%rbx) 650 movq %rax,PCPU(curthread) 651 movq TD_SP(%rax),%rsp 652 653 /* 654 * %rax contains new thread, %rbx contains old thread. 655 */ 656 CHECKNZ((%rsp), %r9) 657 ret 658 659/* 660 * cpu_lwkt_restore() (current thread in %rax on entry) 661 * 662 * Standard LWKT restore function. This function is always called 663 * while in a critical section. 664 * 665 * Warning: due to preemption the restore function can be used to 666 * 'return' to the original thread. Interrupt disablement must be 667 * protected through the switch so we cannot run splz here. 668 */ 669ENTRY(cpu_lwkt_restore) 670 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 671 orl $TDF_RUNNING,TD_FLAGS(%rax) 672 popfq 673 popq %r15 674 popq %r14 675 popq %r13 676 popq %r12 677 popq %rbx 678 popq %rbp 679 ret 680 681/* 682 * bootstrap_idle() 683 * 684 * Make AP become the idle loop. 685 */ 686ENTRY(bootstrap_idle) 687 movq PCPU(curthread),%rax 688 movq %rax,%rbx 689 movq TD_SP(%rax),%rsp 690 ret 691