1//===--- BuiltinsPPC.def - PowerPC Builtin function database ----*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the PowerPC-specific builtin function database. Users of 10// this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to 11// make use of this information. The latter is used for builtins requiring 12// custom code generation and checking. 13// 14//===----------------------------------------------------------------------===// 15 16// FIXME: this needs to be the full list supported by GCC. Right now, I'm just 17// adding stuff on demand. 18 19// The format of this database matches clang/Basic/Builtins.def except for the 20// MMA builtins that are using their own format documented below. 21 22#ifndef BUILTIN 23#define BUILTIN(ID, TYPE, ATTRS) 24#endif 25 26#if defined(BUILTIN) && !defined(TARGET_BUILTIN) 27#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) 28#endif 29 30#ifndef CUSTOM_BUILTIN 31#define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \ 32 TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE) 33#endif 34 35#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \ 36 CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE) 37 38// GCC predefined macros to rename builtins, undef them to keep original names. 39#if defined(__GNUC__) && !defined(__clang__) 40#undef __builtin_vsx_xvnmaddadp 41#undef __builtin_vsx_xvnmaddasp 42#undef __builtin_vsx_xvmsubasp 43#undef __builtin_vsx_xvmsubadp 44#undef __builtin_vsx_xvmaddadp 45#undef __builtin_vsx_xvnmsubasp 46#undef __builtin_vsx_xvnmsubadp 47#undef __builtin_vsx_xvmaddasp 48#endif 49 50// XL Compatibility built-ins 51BUILTIN(__builtin_ppc_popcntb, "ULiULi", "") 52BUILTIN(__builtin_ppc_poppar4, "iUi", "") 53BUILTIN(__builtin_ppc_poppar8, "iULLi", "") 54BUILTIN(__builtin_ppc_eieio, "v", "") 55BUILTIN(__builtin_ppc_iospace_eieio, "v", "") 56BUILTIN(__builtin_ppc_isync, "v", "") 57BUILTIN(__builtin_ppc_lwsync, "v", "") 58BUILTIN(__builtin_ppc_iospace_lwsync, "v", "") 59BUILTIN(__builtin_ppc_sync, "v", "") 60BUILTIN(__builtin_ppc_iospace_sync, "v", "") 61BUILTIN(__builtin_ppc_dcbfl, "vvC*", "") 62BUILTIN(__builtin_ppc_dcbflp, "vvC*", "") 63BUILTIN(__builtin_ppc_dcbst, "vvC*", "") 64BUILTIN(__builtin_ppc_dcbt, "vv*", "") 65BUILTIN(__builtin_ppc_dcbtst, "vv*", "") 66BUILTIN(__builtin_ppc_dcbz, "vv*", "") 67TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions") 68BUILTIN(__builtin_ppc_fric, "dd", "") 69BUILTIN(__builtin_ppc_frim, "dd", "") 70BUILTIN(__builtin_ppc_frims, "ff", "") 71BUILTIN(__builtin_ppc_frin, "dd", "") 72BUILTIN(__builtin_ppc_frins, "ff", "") 73BUILTIN(__builtin_ppc_frip, "dd", "") 74BUILTIN(__builtin_ppc_frips, "ff", "") 75BUILTIN(__builtin_ppc_friz, "dd", "") 76BUILTIN(__builtin_ppc_frizs, "ff", "") 77BUILTIN(__builtin_ppc_fsel, "dddd", "") 78BUILTIN(__builtin_ppc_fsels, "ffff", "") 79BUILTIN(__builtin_ppc_frsqrte, "dd", "") 80BUILTIN(__builtin_ppc_frsqrtes, "ff", "") 81BUILTIN(__builtin_ppc_fsqrt, "dd", "") 82BUILTIN(__builtin_ppc_fsqrts, "ff", "") 83BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "") 84BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "") 85BUILTIN(__builtin_ppc_fetch_and_add, "iiD*i", "") 86BUILTIN(__builtin_ppc_fetch_and_addlp, "LiLiD*Li", "") 87BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui", "") 88BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi", "") 89BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "") 90BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "") 91BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "") 92BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "") 93BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "") 94BUILTIN(__builtin_ppc_lwarx, "iiD*", "") 95TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions") 96TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*", "", "isa-v207-instructions") 97BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "") 98BUILTIN(__builtin_ppc_stwcx, "iiD*i", "") 99TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s", "", "isa-v207-instructions") 100TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i", "", "isa-v207-instructions") 101BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "") 102BUILTIN(__builtin_ppc_tw, "viiIUi", "") 103BUILTIN(__builtin_ppc_trap, "vi", "") 104BUILTIN(__builtin_ppc_trapd, "vLi", "") 105BUILTIN(__builtin_ppc_fcfid, "dd", "") 106BUILTIN(__builtin_ppc_fcfud, "dd", "") 107BUILTIN(__builtin_ppc_fctid, "dd", "") 108BUILTIN(__builtin_ppc_fctidz, "dd", "") 109BUILTIN(__builtin_ppc_fctiw, "dd", "") 110BUILTIN(__builtin_ppc_fctiwz, "dd", "") 111BUILTIN(__builtin_ppc_fctudz, "dd", "") 112BUILTIN(__builtin_ppc_fctuwz, "dd", "") 113BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "") 114BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "") 115BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc") 116BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc") 117TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", "isa-v30-instructions,vsx") 118TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "", "isa-v30-instructions,vsx") 119TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "", "isa-v30-instructions,vsx") 120TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "", "isa-v30-instructions,vsx") 121TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi", "t", "isa-v30-instructions,vsx") 122BUILTIN(__builtin_ppc_swdiv, "ddd", "") 123BUILTIN(__builtin_ppc_swdivs, "fff", "") 124// Compare 125TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "", "isa-v30-instructions") 126TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii", "", "isa-v30-instructions") 127TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "", "isa-v30-instructions") 128BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "") 129// Multiply 130BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "") 131BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "") 132BUILTIN(__builtin_ppc_mulhw, "iii", "") 133BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "") 134TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "", "isa-v30-instructions") 135TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "", 136 "isa-v30-instructions") 137TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "", "isa-v30-instructions") 138// Rotate 139BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "") 140BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "") 141BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "") 142// load 143BUILTIN(__builtin_ppc_load2r, "UsUs*", "") 144BUILTIN(__builtin_ppc_load4r, "UiUi*", "") 145TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "", "isa-v206-instructions") 146// store 147BUILTIN(__builtin_ppc_store2r, "vUiUs*", "") 148BUILTIN(__builtin_ppc_store4r, "vUiUi*", "") 149TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions") 150TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector") 151TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector") 152BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "") 153BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "") 154BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "") 155BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "") 156TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector") 157BUILTIN(__builtin_ppc_fmsub, "dddd", "") 158BUILTIN(__builtin_ppc_fmsubs, "ffff", "") 159BUILTIN(__builtin_ppc_fnmadd, "dddd", "") 160BUILTIN(__builtin_ppc_fnmadds, "ffff", "") 161BUILTIN(__builtin_ppc_fnmsub, "dddd", "") 162BUILTIN(__builtin_ppc_fnmsubs, "ffff", "") 163BUILTIN(__builtin_ppc_fre, "dd", "") 164BUILTIN(__builtin_ppc_fres, "ff", "") 165BUILTIN(__builtin_ppc_dcbtstt, "vv*", "") 166BUILTIN(__builtin_ppc_dcbtt, "vv*", "") 167BUILTIN(__builtin_ppc_mftbu, "Ui", "") 168BUILTIN(__builtin_ppc_mfmsr, "Ui", "") 169BUILTIN(__builtin_ppc_mfspr, "ULiIi", "") 170BUILTIN(__builtin_ppc_mtmsr, "vUi", "") 171BUILTIN(__builtin_ppc_mtspr, "vIiULi", "") 172BUILTIN(__builtin_ppc_stfiw, "viC*d", "") 173TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "", "isa-v30-instructions") 174// select 175BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t") 176BUILTIN(__builtin_ppc_maxfl, "dddd.", "t") 177BUILTIN(__builtin_ppc_maxfs, "ffff.", "t") 178BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t") 179BUILTIN(__builtin_ppc_minfl, "dddd.", "t") 180BUILTIN(__builtin_ppc_minfs, "ffff.", "t") 181// Floating Negative Absolute Value 182BUILTIN(__builtin_ppc_fnabs, "dd", "") 183BUILTIN(__builtin_ppc_fnabss, "ff", "") 184 185BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n") 186 187// This is just a placeholder, the types and attributes are wrong. 188TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "", "altivec") 189 190TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "", "altivec") 191TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "", "altivec") 192TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "", "altivec") 193TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "", "altivec") 194TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "", "altivec") 195TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "", "altivec") 196TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 197 "power8-vector") 198TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi", "", 199 "power8-vector") 200TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 201 "power8-vector") 202TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc", "", 203 "power8-vector") 204TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc", "", 205 "power8-vector") 206TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc", "", 207 "power8-vector") 208TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc", "", 209 "power8-vector") 210 211TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "", "altivec") 212TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "", "altivec") 213TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "", "altivec") 214TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "", "altivec") 215TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "", "altivec") 216TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "", "altivec") 217TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 218 "power8-vector") 219TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi", "", 220 "power8-vector") 221TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 222 "power8-vector") 223TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc", "", 224 "power8-vector") 225TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc", "", 226 "power8-vector") 227TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc", "", 228 "power8-vector") 229TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc", "", 230 "power8-vector") 231 232TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "", "altivec") 233TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "", "altivec") 234TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "", "altivec") 235TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "", "altivec") 236TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "", "altivec") 237TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "", "altivec") 238 239TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "", "altivec") 240 241TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "", "altivec") 242TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "", "altivec") 243TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "", "altivec") 244TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "", "altivec") 245 246TARGET_BUILTIN(__builtin_altivec_dss, "vUIi", "", "altivec") 247TARGET_BUILTIN(__builtin_altivec_dssall, "v", "", "altivec") 248TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "", "altivec") 249TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "", "altivec") 250TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "", "altivec") 251TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "", "altivec") 252 253TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "", "altivec") 254 255TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "", "altivec") 256 257TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "", "altivec") 258TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "", "altivec") 259TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "", "altivec") 260TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "", "altivec") 261TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "", "altivec") 262 263TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "", "altivec") 264 265TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "", "altivec") 266TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "", "altivec") 267 268TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "", "altivec") 269TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "", "altivec") 270TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "", "altivec") 271 272TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "", "altivec") 273TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "", "altivec") 274TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "", "altivec") 275TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "", "altivec") 276TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "", "altivec") 277TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "", "altivec") 278 279TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "", "altivec") 280TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "", "altivec") 281TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "", "altivec") 282TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "", "altivec") 283TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "", "power8-vector") 284TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "", "power8-vector") 285TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "", "altivec") 286TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "", "altivec") 287TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "", "altivec") 288TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "", "altivec") 289TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "", "power8-vector") 290TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "", "power8-vector") 291TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "", 292 "power10-vector") 293TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "", 294 "power10-vector") 295TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "", 296 "power10-vector") 297TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "", 298 "power10-vector") 299TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "", 300 "power10-vector") 301 302TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "", "altivec") 303 304TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "", "altivec") 305TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "", "altivec") 306TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "", "altivec") 307TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "", "altivec") 308TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "", "altivec") 309TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "", "altivec") 310TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "", "altivec") 311TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "", 312 "power8-vector") 313TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "", 314 "power8-vector") 315TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "", 316 "power8-vector") 317TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "", 318 "power8-vector") 319 320TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "", "altivec") 321 322TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "", "altivec") 323TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "", "altivec") 324TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "", "altivec") 325TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "", "altivec") 326TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "", "altivec") 327 328TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "", "altivec") 329 330TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "", "altivec") 331 332TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "", "altivec") 333TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "", "altivec") 334TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "", "altivec") 335TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "", 336 "power8-vector") 337TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "", "altivec") 338 339TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "", "power9-vector") 340TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "", "power9-vector") 341TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "", "power9-vector") 342 343TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "", "power9-vector") 344TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "", "power9-vector") 345TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "", "power9-vector") 346 347TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "", "altivec") 348TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "", "altivec") 349TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "", "altivec") 350TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "", "altivec") 351TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "", "altivec") 352TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "", "altivec") 353TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "", 354 "power8-vector") 355TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "", 356 "power8-vector") 357TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "", "altivec") 358 359// P10 Vector compare builtins. 360TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "", 361 "power10-vector") 362TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "", 363 "power10-vector") 364TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "", 365 "power10-vector") 366TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "", "altivec") 367TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "", 368 "power10-vector") 369TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "", 370 "power10-vector") 371 372TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "", "altivec") 373TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "", "altivec") 374TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "", "altivec") 375TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "", "altivec") 376TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "", "altivec") 377TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "", "altivec") 378TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "", "power8-vector") 379TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "", 380 "power8-vector") 381TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "", "altivec") 382 383TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us", "", "altivec") 384 385TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "", "altivec") 386TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "", "altivec") 387TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "", "altivec") 388TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "", "altivec") 389TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "", "altivec") 390TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "", "altivec") 391TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "", "power8-vector") 392TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "", 393 "power8-vector") 394TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "", "altivec") 395 396TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i", "", "altivec") 397 398TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "", "altivec") 399 400TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "", "altivec") 401TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "", "altivec") 402TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "", "altivec") 403TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "", "power8-vector") 404 405TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "", "altivec") 406 407TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "", "altivec") 408TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "", "altivec") 409 410TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "", "altivec") 411TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "", "altivec") 412TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "", "altivec") 413 414TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "", "altivec") 415TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "", "altivec") 416 417TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "", "altivec") 418 419TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "", "altivec") 420 421TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "", "altivec") 422 423TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "", "altivec") 424TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "", "altivec") 425TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "", "altivec") 426 427TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "", "altivec") 428 429TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "", "altivec") 430 431TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "", "altivec") 432 433TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "", "altivec") 434TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "", "altivec") 435TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "", "altivec") 436TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "", "power8-vector") 437 438TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "", "altivec") 439TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "", "altivec") 440TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "", "altivec") 441TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "", "power8-vector") 442 443TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "", "altivec") 444 445TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "", "altivec") 446 447TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "", "altivec") 448TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "", "altivec") 449TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "", "altivec") 450TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "", "vsx") 451TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "", "altivec") 452 453TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "", "power9-vector") 454TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "", "power9-vector") 455TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector") 456TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "vsx") 457 458TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "", "altivec") 459TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "", "altivec") 460TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "", "altivec") 461TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "", "altivec") 462TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "", "altivec") 463TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "", "altivec") 464TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "", "vsx") 465TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "", "vsx") 466TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "", "altivec") 467 468TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "", "power8-vector") 469TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "", 470 "power8-vector") 471TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "", 472 "power9-vector") 473 474// P8 Crypto built-ins. 475TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "", 476 "power8-vector") 477TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "", 478 "power8-vector") 479TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "", 480 "power8-vector") 481TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "", 482 "power8-vector") 483TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "", 484 "power8-vector") 485TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "", 486 "power8-vector") 487TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "", 488 "power8-vector") 489TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "", 490 "power8-vector") 491TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "", 492 "power8-vector") 493TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "", 494 "power8-vector") 495TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "", 496 "power8-vector") 497TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "", 498 "power8-vector") 499TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "", 500 "power8-vector") 501 502TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "", "power8-vector") 503TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "", "power8-vector") 504TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "", "power8-vector") 505TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "", "power8-vector") 506TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "", "power9-vector") 507TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector") 508TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector") 509TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector") 510 511// P8 BCD builtins. 512TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "", 513 "isa-v207-instructions") 514TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "", 515 "isa-v207-instructions") 516TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "", 517 "isa-v207-instructions") 518TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "", 519 "isa-v207-instructions") 520 521TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector") 522TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector") 523TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector") 524TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "", "power9-vector") 525TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "", "power9-vector") 526 527// Vector population count built-ins 528TARGET_BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc", "", "power8-vector") 529TARGET_BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us", "", "power8-vector") 530TARGET_BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui", "", "power8-vector") 531TARGET_BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi", "", "power8-vector") 532 533// Absolute difference built-ins 534TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "", 535 "power9-vector") 536TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "power9-vector") 537TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "power9-vector") 538 539// P9 Shift built-ins. 540TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "", "power9-vector") 541TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "", "power9-vector") 542 543// P9 Vector rotate built-ins 544TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "", 545 "power9-vector") 546TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "", 547 "power9-vector") 548TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "", "power9-vector") 549TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "", 550 "power9-vector") 551 552// P9 Vector extend sign builtins. 553TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "", "power9-vector") 554TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "", "power9-vector") 555TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "", "power9-vector") 556TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "", "power9-vector") 557TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "", "power9-vector") 558 559// P10 Vector extend sign builtins. 560TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "", 561 "power10-vector") 562 563// P10 Vector Extract with Mask built-ins. 564TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "", "power10-vector") 565TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "", "power10-vector") 566TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "", "power10-vector") 567TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "", "power10-vector") 568TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "", "power10-vector") 569 570// P10 Vector Divide Extended built-ins. 571TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "", "power10-vector") 572TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "", "power10-vector") 573TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "", 574 "power10-vector") 575TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "", 576 "power10-vector") 577TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "", 578 "power10-vector") 579TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "", 580 "power10-vector") 581 582// P10 Vector Multiply High built-ins. 583TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "", "power10-vector") 584TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "", "power10-vector") 585TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "", 586 "power10-vector") 587TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "", 588 "power10-vector") 589 590// P10 Vector Expand with Mask built-ins. 591TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector") 592TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "", "power10-vector") 593TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "", "power10-vector") 594TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "", 595 "power10-vector") 596TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "", 597 "power10-vector") 598 599// P10 Vector Count with Mask built-ins. 600TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "", "power10-vector") 601TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "", "power10-vector") 602TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "", "power10-vector") 603TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "", "power10-vector") 604 605// P10 Move to VSR with Mask built-ins. 606TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "", "power10-vector") 607TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "", "power10-vector") 608TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "", "power10-vector") 609TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "", "power10-vector") 610TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "", "power10-vector") 611 612// P10 Vector Parallel Bits built-ins. 613TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "", 614 "power10-vector") 615TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "", 616 "power10-vector") 617 618// P10 Vector String Isolate Built-ins. 619TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "", "power10-vector") 620TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "", "power10-vector") 621TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "", "power10-vector") 622TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "", "power10-vector") 623TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "", "power10-vector") 624TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "", "power10-vector") 625TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "", "power10-vector") 626TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "", "power10-vector") 627 628// P10 Vector Centrifuge built-in. 629TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "", 630 "power10-vector") 631 632// P10 Vector Gather Every N-th Bit built-in. 633TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "", "power10-vector") 634 635// P10 Vector Clear Bytes built-ins. 636TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "", "power10-vector") 637TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "", "power10-vector") 638 639// P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins. 640TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "", 641 "power10-vector") 642TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "", 643 "power10-vector") 644 645// P10 Vector Shift built-ins. 646TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "", 647 "power10-vector") 648TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "", 649 "power10-vector") 650 651// P10 Vector Insert built-ins. 652TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "", 653 "power10-vector") 654TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "", 655 "power10-vector") 656TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "", "power10-vector") 657TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "", "power10-vector") 658TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "", "power10-vector") 659TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "", "power10-vector") 660TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "", 661 "power10-vector") 662TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "", 663 "power10-vector") 664TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "", 665 "power10-vector") 666TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "", 667 "power10-vector") 668TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "", 669 "power10-vector") 670TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "", 671 "power10-vector") 672TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "", 673 "power10-vector") 674TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "", 675 "power10-vector") 676TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "", "power10-vector") 677TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "", 678 "power10-vector") 679TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "", 680 "power10-vector") 681TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "", 682 "power10-vector") 683 684// P10 Vector Extract built-ins. 685TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "", 686 "power10-vector") 687TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "", 688 "power10-vector") 689TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "", 690 "power10-vector") 691TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "", 692 "power10-vector") 693TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "", 694 "power10-vector") 695TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "", 696 "power10-vector") 697TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "", 698 "power10-vector") 699TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "", 700 "power10-vector") 701 702// P10 Vector rotate built-ins. 703TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 704 "power10-vector") 705TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "", 706 "power10-vector") 707 708// VSX built-ins. 709 710TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "", "vsx") 711TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "", "vsx") 712TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "", "vsx") 713TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "", "vsx") 714 715TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "", "vsx") 716TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "", "vsx") 717TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "", "vsx") 718TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "", "vsx") 719 720TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "", "power9-vector") 721TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "", "power9-vector") 722TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "", "power9-vector") 723TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "", "power9-vector") 724TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "", "isa-v207-instructions") 725TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "", "isa-v207-instructions") 726 727TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "", "vsx") 728TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "", "vsx") 729TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "", "vsx") 730 731TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "", "vsx") 732TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "", "vsx") 733TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd", "", "vsx") 734 735TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "", "vsx") 736TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "", "vsx") 737 738TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "", "vsx") 739TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "", "vsx") 740 741TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "", "vsx") 742TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "", "vsx") 743 744TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "", "vsx") 745TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "", "vsx") 746 747TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "", "vsx") 748TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "", "vsx") 749 750TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "", "vsx") 751TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "", "vsx") 752 753TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "", "vsx") 754TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "", "vsx") 755 756TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "", "vsx") 757TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "", "vsx") 758 759TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "", "vsx") 760TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "", "vsx") 761 762TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "", "vsx") 763TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "", "vsx") 764 765TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "", "vsx") 766TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "", "vsx") 767 768TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "", "vsx") 769TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "", "vsx") 770 771TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "", "vsx") 772TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "", "vsx") 773 774TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "", "vsx") 775TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "", "vsx") 776 777TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "", "vsx") 778TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "", "vsx") 779 780TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "", "vsx") 781TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "", "vsx") 782 783TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "", "vsx") 784TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "", "vsx") 785 786TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "", "vsx") 787TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "", "vsx") 788 789TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "", "vsx") 790TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "", "vsx") 791 792TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "", "vsx") 793TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "", "vsx") 794 795TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "", "power8-vector") 796 797TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "", "vsx") 798TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "", "vsx") 799 800TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "", "vsx") 801TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "", "vsx") 802 803TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "", "power10-vector") 804TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "", "power10-vector") 805TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "", "power10-vector") 806TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "", "power10-vector") 807 808// vector Insert/Extract exponent/significand builtins 809TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "", "power9-vector") 810TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "", "power9-vector") 811TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "", "power9-vector") 812TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "", "power9-vector") 813TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "", "power9-vector") 814TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "", "power9-vector") 815 816// Conversion builtins 817TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "", "vsx") 818TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "", "vsx") 819TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "", "vsx") 820TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "", "vsx") 821TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "", "vsx") 822TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "", "vsx") 823TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "", "vsx") 824TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "", "vsx") 825TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "", "vsx") 826TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "", "vsx") 827 828TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "", "power9-vector") 829TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "", "power9-vector") 830 831TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector") 832TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "power10-vector") 833 834// Vector Test Data Class builtins 835TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "", "power9-vector") 836TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "", "power9-vector") 837 838TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "", "vsx") 839TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "", "vsx") 840 841TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v.", "t", "vsx") 842TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v.", "t", "vsx") 843 844TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "", 845 "power10-vector") 846 847TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "", "power10-vector") 848 849TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "", "vsx") 850TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "", "vsx") 851TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "", "vsx") 852TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "", "vsx") 853 854// P10 Vector Permute Extended built-in. 855TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "", 856 "power10-vector") 857 858// P10 Vector Blend built-ins. 859TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "", 860 "power10-vector") 861TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "", 862 "power10-vector") 863TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "", 864 "power10-vector") 865TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "", 866 "power10-vector") 867 868// Float 128 built-ins 869TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "", "float128") 870TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "", "float128") 871TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "", "float128") 872TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "", "float128") 873TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "", "float128") 874TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "", "float128") 875TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "", "float128") 876TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "", "float128") 877TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "", "float128") 878 879// Fastmath by default builtins 880BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f", "") 881BUILTIN(__builtin_ppc_rsqrtd, "V2dV2d", "") 882BUILTIN(__builtin_ppc_recipdivf, "V4fV4fV4f", "") 883BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d", "") 884 885// HTM builtins 886TARGET_BUILTIN(__builtin_tbegin, "UiUIi", "", "htm") 887TARGET_BUILTIN(__builtin_tend, "UiUIi", "", "htm") 888 889TARGET_BUILTIN(__builtin_tabort, "UiUi", "", "htm") 890TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi", "", "htm") 891TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii", "", "htm") 892TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi", "", "htm") 893TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii", "", "htm") 894 895TARGET_BUILTIN(__builtin_tcheck, "Ui", "", "htm") 896TARGET_BUILTIN(__builtin_treclaim, "UiUi", "", "htm") 897TARGET_BUILTIN(__builtin_trechkpt, "Ui", "", "htm") 898TARGET_BUILTIN(__builtin_tsr, "UiUi", "", "htm") 899 900TARGET_BUILTIN(__builtin_tendall, "Ui", "", "htm") 901TARGET_BUILTIN(__builtin_tresume, "Ui", "", "htm") 902TARGET_BUILTIN(__builtin_tsuspend, "Ui", "", "htm") 903 904TARGET_BUILTIN(__builtin_get_texasr, "LUi", "c", "htm") 905TARGET_BUILTIN(__builtin_get_texasru, "LUi", "c", "htm") 906TARGET_BUILTIN(__builtin_get_tfhar, "LUi", "c", "htm") 907TARGET_BUILTIN(__builtin_get_tfiar, "LUi", "c", "htm") 908 909TARGET_BUILTIN(__builtin_set_texasr, "vLUi", "c", "htm") 910TARGET_BUILTIN(__builtin_set_texasru, "vLUi", "c", "htm") 911TARGET_BUILTIN(__builtin_set_tfhar, "vLUi", "c", "htm") 912TARGET_BUILTIN(__builtin_set_tfiar, "vLUi", "c", "htm") 913 914TARGET_BUILTIN(__builtin_ttest, "LUi", "", "htm") 915 916// Scalar built-ins 917TARGET_BUILTIN(__builtin_divwe, "SiSiSi", "", "extdiv") 918TARGET_BUILTIN(__builtin_divweu, "UiUiUi", "", "extdiv") 919TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "", "extdiv") 920TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "", "extdiv") 921TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "", "bpermd") 922TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "", "isa-v31-instructions") 923TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi", "", "isa-v31-instructions") 924TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "", "isa-v31-instructions") 925TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "", "isa-v31-instructions") 926TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "", "isa-v31-instructions") 927 928// Double-double (un)pack 929BUILTIN(__builtin_unpack_longdouble, "dLdIi", "") 930BUILTIN(__builtin_pack_longdouble, "Lddd", "") 931 932// Generate random number 933TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions") 934TARGET_BUILTIN(__builtin_darn_raw, "LLi", "", "isa-v30-instructions") 935TARGET_BUILTIN(__builtin_darn_32, "i", "", "isa-v30-instructions") 936 937// Vector int128 (un)pack 938TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "", "vsx") 939TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx") 940 941// Set the floating point rounding mode 942BUILTIN(__builtin_setrnd, "di", "") 943 944// Get content from current FPSCR 945BUILTIN(__builtin_readflm, "d", "") 946 947// Set content of FPSCR, and return its content before update 948BUILTIN(__builtin_setflm, "dd", "") 949 950// Cache built-ins 951BUILTIN(__builtin_dcbf, "vvC*", "") 952 953// Built-ins requiring custom code generation. 954// Because these built-ins rely on target-dependent types and to avoid pervasive 955// change, they are type checked manually in Sema using custom type descriptors. 956// The first argument of the CUSTOM_BUILTIN macro is the name of the built-in 957// with its prefix, the second argument is the name of the intrinsic this 958// built-in generates, the third argument specifies the type of the function 959// (result value, then each argument) as follows: 960// i -> Unsigned integer followed by the greatest possible value for that 961// argument or 0 if no constraint on the value. 962// (e.g. i15 for a 4-bits value) 963// V -> Vector type used with MMA built-ins (vector unsigned char) 964// W -> PPC Vector type followed by the size of the vector type. 965// (e.g. W512 for __vector_quad) 966// any other descriptor -> Fall back to generic type descriptor decoding. 967// The 'C' suffix can be used as a suffix to specify the const type. 968// The '*' suffix can be used as a suffix to specify a pointer to a type. 969// The fourth argument is set to true if the built-in accumulates its result into 970// its given accumulator. 971 972// Provided builtins with _mma_ prefix for compatibility. 973CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false, 974 "paired-vector-memops") 975CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false, 976 "paired-vector-memops") 977CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false, 978 "paired-vector-memops") 979CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false, 980 "paired-vector-memops") 981CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false, 982 "paired-vector-memops") 983CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false, "mma") 984 985// UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have 986// the same name as that of the intrinsic they generate, i.e. the 987// ID and INTR are the same. 988// This avoids repeating the ID and INTR in the macro expression. 989 990UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false, 991 "paired-vector-memops") 992UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false, 993 "paired-vector-memops") 994UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false, 995 "paired-vector-memops") 996UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false, 997 "paired-vector-memops") 998 999// TODO: Require only mma after backend supports these without paired memops 1000UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false, 1001 "mma,paired-vector-memops") 1002UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, 1003 "mma,paired-vector-memops") 1004UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true, 1005 "mma,paired-vector-memops") 1006UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true, 1007 "mma,paired-vector-memops") 1008UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false, 1009 "mma,paired-vector-memops") 1010UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false, 1011 "mma,paired-vector-memops") 1012UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false, 1013 "mma,paired-vector-memops") 1014UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false, 1015 "mma,paired-vector-memops") 1016UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false, 1017 "mma,paired-vector-memops") 1018UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV", false, 1019 "mma,paired-vector-memops") 1020UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV", false, 1021 "mma,paired-vector-memops") 1022UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V", false, 1023 "mma,paired-vector-memops") 1024UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false, 1025 "mma,paired-vector-memops") 1026UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false, 1027 "mma,paired-vector-memops") 1028UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false, 1029 "mma,paired-vector-memops") 1030UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false, 1031 "mma,paired-vector-memops") 1032UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3", false, 1033 "mma,paired-vector-memops") 1034UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15", false, 1035 "mma,paired-vector-memops") 1036UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3", false, 1037 "mma,paired-vector-memops") 1038UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true, 1039 "mma,paired-vector-memops") 1040UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true, 1041 "mma,paired-vector-memops") 1042UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true, 1043 "mma,paired-vector-memops") 1044UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true, 1045 "mma,paired-vector-memops") 1046UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true, 1047 "mma,paired-vector-memops") 1048UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true, 1049 "mma,paired-vector-memops") 1050UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true, 1051 "mma,paired-vector-memops") 1052UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true, 1053 "mma,paired-vector-memops") 1054UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true, 1055 "mma,paired-vector-memops") 1056UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true, 1057 "mma,paired-vector-memops") 1058UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV", true, 1059 "mma,paired-vector-memops") 1060UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV", true, 1061 "mma,paired-vector-memops") 1062UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV", true, 1063 "mma,paired-vector-memops") 1064UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV", true, 1065 "mma,paired-vector-memops") 1066UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3", true, 1067 "mma,paired-vector-memops") 1068UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3", true, 1069 "mma,paired-vector-memops") 1070UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3", true, 1071 "mma,paired-vector-memops") 1072UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3", true, 1073 "mma,paired-vector-memops") 1074UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV", true, 1075 "mma,paired-vector-memops") 1076UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV", true, 1077 "mma,paired-vector-memops") 1078UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV", true, 1079 "mma,paired-vector-memops") 1080UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV", true, 1081 "mma,paired-vector-memops") 1082UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15", true, 1083 "mma,paired-vector-memops") 1084UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15", true, 1085 "mma,paired-vector-memops") 1086UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15", true, 1087 "mma,paired-vector-memops") 1088UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15", true, 1089 "mma,paired-vector-memops") 1090UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V", true, 1091 "mma,paired-vector-memops") 1092UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V", true, 1093 "mma,paired-vector-memops") 1094UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V", true, 1095 "mma,paired-vector-memops") 1096UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V", true, 1097 "mma,paired-vector-memops") 1098UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3", true, 1099 "mma,paired-vector-memops") 1100UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3", true, 1101 "mma,paired-vector-memops") 1102UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3", true, 1103 "mma,paired-vector-memops") 1104UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3", true, 1105 "mma,paired-vector-memops") 1106UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV", false, 1107 "mma,paired-vector-memops") 1108UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3", false, 1109 "mma,paired-vector-memops") 1110UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV", true, 1111 "mma,paired-vector-memops") 1112UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV", true, 1113 "mma,paired-vector-memops") 1114UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV", true, 1115 "mma,paired-vector-memops") 1116UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV", true, 1117 "mma,paired-vector-memops") 1118UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3", true, 1119 "mma,paired-vector-memops") 1120UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3", true, 1121 "mma,paired-vector-memops") 1122UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true, 1123 "mma,paired-vector-memops") 1124UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true, 1125 "mma,paired-vector-memops") 1126 1127// FIXME: Obviously incomplete. 1128 1129#undef BUILTIN 1130#undef CUSTOM_BUILTIN 1131#undef UNALIASED_CUSTOM_BUILTIN 1132