1//==--- riscv_sifive_vector.td - RISC-V SiFive VCIX function list ---------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the builtins for RISC-V SiFive VCIX. See: 10// 11// https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf 12// 13//===----------------------------------------------------------------------===// 14 15include "riscv_vector_common.td" 16 17//===----------------------------------------------------------------------===// 18// Instruction definitions 19//===----------------------------------------------------------------------===// 20 21class VCIXSuffix<string range> { 22 list<string> suffix = !cond(!eq(range, "c"): ["8mf8", "8mf4", "8mf2", "8m1", "8m2", "8m4", "8m8"], 23 !eq(range, "s"): ["16mf4", "16mf2", "16m1", "16m2", "16m4", "16m8"], 24 !eq(range, "i"): ["32mf2", "32m1", "32m2", "32m4", "32m8"], 25 !eq(range, "l"): ["64m1", "64m2", "64m4", "64m8"]); 26} 27 28class VCIXBuiltinSet<string name, string IR_name, string suffix, 29 string prototype, string type_range, 30 list<int> intrinsic_types> 31 : RVVBuiltin<suffix, prototype, type_range> { 32 let Name = name; 33 let OverloadedName = name; 34 let IRName = IR_name; 35 let HasMasked = false; 36 let IntrinsicTypes = intrinsic_types; 37} 38 39multiclass VCIXBuiltinSet<string name, string IR_name, string suffix, 40 string prototype, string type_range, 41 list<int> intrinsic_types> { 42 if !find(prototype, "0") then { 43 def : VCIXBuiltinSet<name, IR_name, suffix, prototype, type_range, intrinsic_types>; 44 } 45 def : VCIXBuiltinSet<name # "_se", IR_name # "_se", suffix, prototype, type_range, intrinsic_types>; 46} 47 48multiclass RVVVCIXBuiltinSet<list<string> range, string prototype, 49 list<int> intrinsic_types, bit UseGPR> { 50 foreach r = range in 51 let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")), 52 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in 53 defm : VCIXBuiltinSet<NAME, NAME, "Uv", prototype, r, intrinsic_types>; 54} 55 56multiclass RVVVCIXBuiltinSetWVType<list<string> range, string prototype, 57 list<int> intrinsic_types, bit UseGPR> { 58 foreach r = range in 59 let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")), 60 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in 61 // These intrinsics don't have any vector types in the output and inputs, 62 // but we still need to add vetvli for them. So we encode different 63 // VTYPE into the intrinsic names, and then will know which vsetvli is 64 // correct. 65 foreach s = VCIXSuffix<r>.suffix in 66 // Since we already encode the Vtype into the name, so just set 67 // Log2LMUL to zero. Otherwise the RISCVVEmitter will expand 68 // lots of redundant intrinsic but have same names. 69 let Log2LMUL = [0] in 70 def : VCIXBuiltinSet<NAME # "_u" # s, NAME # "_e" # s, 71 "", prototype, r, intrinsic_types>; 72} 73 74let SupportOverloading = false in { 75 defm sf_vc_x_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], /*UseGPR*/1>; 76 defm sf_vc_i_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], /*UseGPR*/0>; 77 defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], /*UseGPR*/1>; 78 defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], /*UseGPR*/0>; 79 defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], /*UseGPR*/0>; 80 defm sf_vc_fv : RVVVCIXBuiltinSet<["si", "l"], "0KzKzUvFe", [0, 2, 3], /*UseGPR*/0>; 81 defm sf_vc_xvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe", [0, 1, 3], /*UseGPR*/1>; 82 defm sf_vc_ivv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz", [0, 1, 3], /*UseGPR*/0>; 83 defm sf_vc_vvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv", [0, 1, 3], /*UseGPR*/0>; 84 defm sf_vc_fvv : RVVVCIXBuiltinSet<["si", "l"], "0KzUvUvFe", [0, 1, 3], /*UseGPR*/0>; 85 defm sf_vc_v_x : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe", [-1, 1, 2], /*UseGPR*/1>; 86 defm sf_vc_v_i : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz", [-1, 1, 2], /*UseGPR*/0>; 87 defm sf_vc_v_xv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe", [-1, 0, 2], /*UseGPR*/1>; 88 defm sf_vc_v_iv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz", [-1, 0, 2], /*UseGPR*/0>; 89 defm sf_vc_v_vv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUv", [-1, 0, 2], /*UseGPR*/0>; 90 defm sf_vc_v_fv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvFe", [-1, 0, 2], /*UseGPR*/0>; 91 defm sf_vc_v_xvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUe", [-1, 0, 3], /*UseGPR*/1>; 92 defm sf_vc_v_ivv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvKz", [-1, 0, 3], /*UseGPR*/0>; 93 defm sf_vc_v_vvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUv", [-1, 0, 3], /*UseGPR*/0>; 94 defm sf_vc_v_fvv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvUvFe", [-1, 0, 3], /*UseGPR*/0>; 95 let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { 96 defm sf_vc_xvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUe", [0, 1, 2, 3], /*UseGPR*/1>; 97 defm sf_vc_ivw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvKz", [0, 1, 2, 3], /*UseGPR*/0>; 98 defm sf_vc_vvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUv", [0, 1, 2, 3], /*UseGPR*/0>; 99 defm sf_vc_fvw : RVVVCIXBuiltinSet<["si"], "0KzUwUvFe", [0, 1, 2, 3], /*UseGPR*/0>; 100 defm sf_vc_v_xvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUe", [-1, 0, 2, 3], /*UseGPR*/1>; 101 defm sf_vc_v_ivw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvKz", [-1, 0, 2, 3], /*UseGPR*/0>; 102 defm sf_vc_v_vvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUv", [-1, 0, 2, 3], /*UseGPR*/0>; 103 defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], /*UseGPR*/0>; 104 } 105} 106