1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28 
29   /// Flags for architecture specific defines.
30   typedef enum {
31     ArchDefineNone = 0,
32     ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33     ArchDefinePpcgr = 1 << 1,
34     ArchDefinePpcsq = 1 << 2,
35     ArchDefine440 = 1 << 3,
36     ArchDefine603 = 1 << 4,
37     ArchDefine604 = 1 << 5,
38     ArchDefinePwr4 = 1 << 6,
39     ArchDefinePwr5 = 1 << 7,
40     ArchDefinePwr5x = 1 << 8,
41     ArchDefinePwr6 = 1 << 9,
42     ArchDefinePwr6x = 1 << 10,
43     ArchDefinePwr7 = 1 << 11,
44     ArchDefinePwr8 = 1 << 12,
45     ArchDefinePwr9 = 1 << 13,
46     ArchDefineA2 = 1 << 14,
47     ArchDefineA2q = 1 << 15,
48     ArchDefineE500 = 1 << 16
49   } ArchDefineTypes;
50 
51 
52   ArchDefineTypes ArchDefs = ArchDefineNone;
53   static const Builtin::Info BuiltinInfo[];
54   static const char *const GCCRegNames[];
55   static const TargetInfo::GCCRegAlias GCCRegAliases[];
56   std::string CPU;
57   enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58 
59   // Target cpu features.
60   bool HasAltivec = false;
61   bool HasVSX = false;
62   bool HasP8Vector = false;
63   bool HasP8Crypto = false;
64   bool HasDirectMove = false;
65   bool HasQPX = false;
66   bool HasHTM = false;
67   bool HasBPERMD = false;
68   bool HasExtDiv = false;
69   bool HasP9Vector = false;
70   bool HasSPE = false;
71 
72 protected:
73   std::string ABI;
74 
75 public:
76   PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
77       : TargetInfo(Triple) {
78     SuitableAlign = 128;
79     SimdDefaultAlign = 128;
80     LongDoubleWidth = LongDoubleAlign = 128;
81     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
82   }
83 
84   // Set the language option for altivec based on our value.
85   void adjust(LangOptions &Opts) override;
86 
87   // Note: GCC recognizes the following additional cpus:
88   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
89   //  821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
90   bool isValidCPUName(StringRef Name) const override;
91   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
92 
93   bool setCPU(const std::string &Name) override {
94     bool CPUKnown = isValidCPUName(Name);
95     if (CPUKnown) {
96       CPU = Name;
97 
98       // CPU identification.
99       ArchDefs =
100           (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
101               .Case("440", ArchDefineName)
102               .Case("450", ArchDefineName | ArchDefine440)
103               .Case("601", ArchDefineName)
104               .Case("602", ArchDefineName | ArchDefinePpcgr)
105               .Case("603", ArchDefineName | ArchDefinePpcgr)
106               .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
107               .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
108               .Case("604", ArchDefineName | ArchDefinePpcgr)
109               .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
110               .Case("620", ArchDefineName | ArchDefinePpcgr)
111               .Case("630", ArchDefineName | ArchDefinePpcgr)
112               .Case("7400", ArchDefineName | ArchDefinePpcgr)
113               .Case("7450", ArchDefineName | ArchDefinePpcgr)
114               .Case("750", ArchDefineName | ArchDefinePpcgr)
115               .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
116                                ArchDefinePpcsq)
117               .Case("a2", ArchDefineA2)
118               .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
119               .Cases("power3", "pwr3", ArchDefinePpcgr)
120               .Cases("power4", "pwr4",
121                     ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
122               .Cases("power5", "pwr5",
123                     ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
124                         ArchDefinePpcsq)
125               .Cases("power5x", "pwr5x",
126                     ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
127                         ArchDefinePpcgr | ArchDefinePpcsq)
128               .Cases("power6", "pwr6",
129                     ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
130                         ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
131               .Cases("power6x", "pwr6x",
132                     ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
133                         ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
134                         ArchDefinePpcsq)
135               .Cases("power7", "pwr7",
136                      ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
137                          ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
138                          ArchDefinePpcsq)
139               // powerpc64le automatically defaults to at least power8.
140               .Cases("power8", "pwr8", "ppc64le",
141                      ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
142                          ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
143                          ArchDefinePpcgr | ArchDefinePpcsq)
144               .Cases("power9", "pwr9",
145                      ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
146                          ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
147                          ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
148               .Cases("8548", "e500", ArchDefineE500)
149               .Default(ArchDefineNone);
150     }
151     return CPUKnown;
152   }
153 
154   StringRef getABI() const override { return ABI; }
155 
156   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
157 
158   bool isCLZForZeroUndef() const override { return false; }
159 
160   void getTargetDefines(const LangOptions &Opts,
161                         MacroBuilder &Builder) const override;
162 
163   bool
164   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
165                  StringRef CPU,
166                  const std::vector<std::string> &FeaturesVec) const override;
167 
168   bool handleTargetFeatures(std::vector<std::string> &Features,
169                             DiagnosticsEngine &Diags) override;
170 
171   bool hasFeature(StringRef Feature) const override;
172 
173   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
174                          bool Enabled) const override;
175 
176   ArrayRef<const char *> getGCCRegNames() const override;
177 
178   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
179 
180   ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
181 
182   bool validateAsmConstraint(const char *&Name,
183                              TargetInfo::ConstraintInfo &Info) const override {
184     switch (*Name) {
185     default:
186       return false;
187     case 'O': // Zero
188       break;
189     case 'f': // Floating point register
190       // Don't use floating point registers on soft float ABI.
191       if (FloatABI == SoftFloat)
192         return false;
193       LLVM_FALLTHROUGH;
194     case 'b': // Base register
195       Info.setAllowsRegister();
196       break;
197     // FIXME: The following are added to allow parsing.
198     // I just took a guess at what the actions should be.
199     // Also, is more specific checking needed?  I.e. specific registers?
200     case 'd': // Floating point register (containing 64-bit value)
201     case 'v': // Altivec vector register
202       // Don't use floating point and altivec vector registers
203       // on soft float ABI
204       if (FloatABI == SoftFloat)
205         return false;
206       Info.setAllowsRegister();
207       break;
208     case 'w':
209       switch (Name[1]) {
210       case 'd': // VSX vector register to hold vector double data
211       case 'f': // VSX vector register to hold vector float data
212       case 's': // VSX vector register to hold scalar double data
213       case 'w': // VSX vector register to hold scalar double data
214       case 'a': // Any VSX register
215       case 'c': // An individual CR bit
216       case 'i': // FP or VSX register to hold 64-bit integers data
217         break;
218       default:
219         return false;
220       }
221       Info.setAllowsRegister();
222       Name++; // Skip over 'w'.
223       break;
224     case 'h': // `MQ', `CTR', or `LINK' register
225     case 'q': // `MQ' register
226     case 'c': // `CTR' register
227     case 'l': // `LINK' register
228     case 'x': // `CR' register (condition register) number 0
229     case 'y': // `CR' register (condition register)
230     case 'z': // `XER[CA]' carry bit (part of the XER register)
231       Info.setAllowsRegister();
232       break;
233     case 'I': // Signed 16-bit constant
234     case 'J': // Unsigned 16-bit constant shifted left 16 bits
235               //  (use `L' instead for SImode constants)
236     case 'K': // Unsigned 16-bit constant
237     case 'L': // Signed 16-bit constant shifted left 16 bits
238     case 'M': // Constant larger than 31
239     case 'N': // Exact power of 2
240     case 'P': // Constant whose negation is a signed 16-bit constant
241     case 'G': // Floating point constant that can be loaded into a
242               // register with one instruction per word
243     case 'H': // Integer/Floating point constant that can be loaded
244               // into a register using three instructions
245       break;
246     case 'm': // Memory operand. Note that on PowerPC targets, m can
247               // include addresses that update the base register. It
248               // is therefore only safe to use `m' in an asm statement
249               // if that asm statement accesses the operand exactly once.
250               // The asm statement must also use `%U<opno>' as a
251               // placeholder for the "update" flag in the corresponding
252               // load or store instruction. For example:
253               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
254               // is correct but:
255               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
256               // is not. Use es rather than m if you don't want the base
257               // register to be updated.
258     case 'e':
259       if (Name[1] != 's')
260         return false;
261       // es: A "stable" memory operand; that is, one which does not
262       // include any automodification of the base register. Unlike
263       // `m', this constraint can be used in asm statements that
264       // might access the operand several times, or that might not
265       // access it at all.
266       Info.setAllowsMemory();
267       Name++; // Skip over 'e'.
268       break;
269     case 'Q': // Memory operand that is an offset from a register (it is
270               // usually better to use `m' or `es' in asm statements)
271     case 'Z': // Memory operand that is an indexed or indirect from a
272               // register (it is usually better to use `m' or `es' in
273               // asm statements)
274       Info.setAllowsMemory();
275       Info.setAllowsRegister();
276       break;
277     case 'R': // AIX TOC entry
278     case 'a': // Address operand that is an indexed or indirect from a
279               // register (`p' is preferable for asm statements)
280     case 'S': // Constant suitable as a 64-bit mask operand
281     case 'T': // Constant suitable as a 32-bit mask operand
282     case 'U': // System V Release 4 small data area reference
283     case 't': // AND masks that can be performed by two rldic{l, r}
284               // instructions
285     case 'W': // Vector constant that does not require memory
286     case 'j': // Vector constant that is all zeros.
287       break;
288       // End FIXME.
289     }
290     return true;
291   }
292 
293   std::string convertConstraint(const char *&Constraint) const override {
294     std::string R;
295     switch (*Constraint) {
296     case 'e':
297     case 'w':
298       // Two-character constraint; add "^" hint for later parsing.
299       R = std::string("^") + std::string(Constraint, 2);
300       Constraint++;
301       break;
302     default:
303       return TargetInfo::convertConstraint(Constraint);
304     }
305     return R;
306   }
307 
308   const char *getClobbers() const override { return ""; }
309   int getEHDataRegisterNumber(unsigned RegNo) const override {
310     if (RegNo == 0)
311       return 3;
312     if (RegNo == 1)
313       return 4;
314     return -1;
315   }
316 
317   bool hasSjLjLowering() const override { return true; }
318 
319   const char *getLongDoubleMangling() const override {
320     if (LongDoubleWidth == 64)
321       return "e";
322     return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
323                ? "g"
324                : "u9__ieee128";
325   }
326   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
327 };
328 
329 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
330 public:
331   PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
332       : PPCTargetInfo(Triple, Opts) {
333     resetDataLayout("E-m:e-p:32:32-i64:64-n32");
334 
335     switch (getTriple().getOS()) {
336     case llvm::Triple::Linux:
337     case llvm::Triple::FreeBSD:
338     case llvm::Triple::NetBSD:
339       SizeType = UnsignedInt;
340       PtrDiffType = SignedInt;
341       IntPtrType = SignedInt;
342       break;
343     case llvm::Triple::AIX:
344       SizeType = UnsignedLong;
345       PtrDiffType = SignedLong;
346       IntPtrType = SignedLong;
347       SuitableAlign = 64;
348       break;
349     default:
350       break;
351     }
352 
353     if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
354         Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
355       LongDoubleWidth = LongDoubleAlign = 64;
356       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
357     }
358 
359     // PPC32 supports atomics up to 4 bytes.
360     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
361   }
362 
363   BuiltinVaListKind getBuiltinVaListKind() const override {
364     // This is the ELF definition, and is overridden by the Darwin sub-target
365     return TargetInfo::PowerABIBuiltinVaList;
366   }
367 };
368 
369 // Note: ABI differences may eventually require us to have a separate
370 // TargetInfo for little endian.
371 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
372 public:
373   PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
374       : PPCTargetInfo(Triple, Opts) {
375     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
376     IntMaxType = SignedLong;
377     Int64Type = SignedLong;
378 
379     if (Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) {
380       switch (Triple.getEnvironment()){
381         case llvm::Triple::ELFv1:
382           ABI = "elfv1";
383           break;
384 	default:
385           ABI = "elfv2";
386 	break;
387       }
388     } else {
389       if ((Triple.getOS() == llvm::Triple::FreeBSD) &&
390 	      (Triple.getOSMajorVersion() < 13)) {
391         ABI = "elfv1";
392       } else {
393         ABI = "elfv2";
394       }
395     }
396 
397 
398     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
399       resetDataLayout("e-m:e-i64:64-n32:64");
400     } else {
401       resetDataLayout("E-m:e-i64:64-n32:64");
402     }
403 
404     if (Triple.getOS() == llvm::Triple::AIX)
405       SuitableAlign = 64;
406 
407     if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||
408         Triple.isMusl()) {
409       LongDoubleWidth = LongDoubleAlign = 64;
410       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
411     }
412 
413     // PPC64 supports atomics up to 8 bytes.
414     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
415   }
416 
417   BuiltinVaListKind getBuiltinVaListKind() const override {
418     return TargetInfo::CharPtrBuiltinVaList;
419   }
420 
421   // PPC64 Linux-specific ABI options.
422   bool setABI(const std::string &Name) override {
423     if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
424       ABI = Name;
425       return true;
426     }
427     return false;
428   }
429 
430   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
431     switch (CC) {
432     case CC_Swift:
433       return CCCR_OK;
434     default:
435       return CCCR_Warning;
436     }
437   }
438 };
439 
440 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
441     : public DarwinTargetInfo<PPC32TargetInfo> {
442 public:
443   DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
444       : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
445     HasAlignMac68kSupport = true;
446     BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
447     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
448     LongLongAlign = 32;
449     resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
450   }
451 
452   BuiltinVaListKind getBuiltinVaListKind() const override {
453     return TargetInfo::CharPtrBuiltinVaList;
454   }
455 };
456 
457 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
458     : public DarwinTargetInfo<PPC64TargetInfo> {
459 public:
460   DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
461       : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
462     HasAlignMac68kSupport = true;
463     resetDataLayout("E-m:o-i64:64-n32:64");
464   }
465 };
466 
467 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
468   public AIXTargetInfo<PPC32TargetInfo> {
469 public:
470   using AIXTargetInfo::AIXTargetInfo;
471   BuiltinVaListKind getBuiltinVaListKind() const override {
472     return TargetInfo::CharPtrBuiltinVaList;
473   }
474 };
475 
476 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
477   public AIXTargetInfo<PPC64TargetInfo> {
478 public:
479   using AIXTargetInfo::AIXTargetInfo;
480 };
481 
482 } // namespace targets
483 } // namespace clang
484 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
485