1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 } else if (Feature == "+avx512pf") { 243 HasAVX512PF = true; 244 } else if (Feature == "+avx512dq") { 245 HasAVX512DQ = true; 246 } else if (Feature == "+avx512bitalg") { 247 HasAVX512BITALG = true; 248 } else if (Feature == "+avx512bw") { 249 HasAVX512BW = true; 250 } else if (Feature == "+avx512vl") { 251 HasAVX512VL = true; 252 } else if (Feature == "+avx512vbmi") { 253 HasAVX512VBMI = true; 254 } else if (Feature == "+avx512vbmi2") { 255 HasAVX512VBMI2 = true; 256 } else if (Feature == "+avx512ifma") { 257 HasAVX512IFMA = true; 258 } else if (Feature == "+avx512vp2intersect") { 259 HasAVX512VP2INTERSECT = true; 260 } else if (Feature == "+sha") { 261 HasSHA = true; 262 } else if (Feature == "+shstk") { 263 HasSHSTK = true; 264 } else if (Feature == "+movbe") { 265 HasMOVBE = true; 266 } else if (Feature == "+sgx") { 267 HasSGX = true; 268 } else if (Feature == "+cx8") { 269 HasCX8 = true; 270 } else if (Feature == "+cx16") { 271 HasCX16 = true; 272 } else if (Feature == "+fxsr") { 273 HasFXSR = true; 274 } else if (Feature == "+xsave") { 275 HasXSAVE = true; 276 } else if (Feature == "+xsaveopt") { 277 HasXSAVEOPT = true; 278 } else if (Feature == "+xsavec") { 279 HasXSAVEC = true; 280 } else if (Feature == "+xsaves") { 281 HasXSAVES = true; 282 } else if (Feature == "+mwaitx") { 283 HasMWAITX = true; 284 } else if (Feature == "+pku") { 285 HasPKU = true; 286 } else if (Feature == "+clflushopt") { 287 HasCLFLUSHOPT = true; 288 } else if (Feature == "+clwb") { 289 HasCLWB = true; 290 } else if (Feature == "+wbnoinvd") { 291 HasWBNOINVD = true; 292 } else if (Feature == "+prefetchwt1") { 293 HasPREFETCHWT1 = true; 294 } else if (Feature == "+clzero") { 295 HasCLZERO = true; 296 } else if (Feature == "+cldemote") { 297 HasCLDEMOTE = true; 298 } else if (Feature == "+rdpid") { 299 HasRDPID = true; 300 } else if (Feature == "+rdpru") { 301 HasRDPRU = true; 302 } else if (Feature == "+kl") { 303 HasKL = true; 304 } else if (Feature == "+widekl") { 305 HasWIDEKL = true; 306 } else if (Feature == "+retpoline-external-thunk") { 307 HasRetpolineExternalThunk = true; 308 } else if (Feature == "+sahf") { 309 HasLAHFSAHF = true; 310 } else if (Feature == "+waitpkg") { 311 HasWAITPKG = true; 312 } else if (Feature == "+movdiri") { 313 HasMOVDIRI = true; 314 } else if (Feature == "+movdir64b") { 315 HasMOVDIR64B = true; 316 } else if (Feature == "+pconfig") { 317 HasPCONFIG = true; 318 } else if (Feature == "+ptwrite") { 319 HasPTWRITE = true; 320 } else if (Feature == "+invpcid") { 321 HasINVPCID = true; 322 } else if (Feature == "+enqcmd") { 323 HasENQCMD = true; 324 } else if (Feature == "+hreset") { 325 HasHRESET = true; 326 } else if (Feature == "+amx-bf16") { 327 HasAMXBF16 = true; 328 } else if (Feature == "+amx-int8") { 329 HasAMXINT8 = true; 330 } else if (Feature == "+amx-tile") { 331 HasAMXTILE = true; 332 } else if (Feature == "+avxvnni") { 333 HasAVXVNNI = true; 334 } else if (Feature == "+serialize") { 335 HasSERIALIZE = true; 336 } else if (Feature == "+tsxldtrk") { 337 HasTSXLDTRK = true; 338 } else if (Feature == "+uintr") { 339 HasUINTR = true; 340 } else if (Feature == "+crc32") { 341 HasCRC32 = true; 342 } else if (Feature == "+x87") { 343 HasX87 = true; 344 } 345 346 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 347 .Case("+avx512f", AVX512F) 348 .Case("+avx2", AVX2) 349 .Case("+avx", AVX) 350 .Case("+sse4.2", SSE42) 351 .Case("+sse4.1", SSE41) 352 .Case("+ssse3", SSSE3) 353 .Case("+sse3", SSE3) 354 .Case("+sse2", SSE2) 355 .Case("+sse", SSE1) 356 .Default(NoSSE); 357 SSELevel = std::max(SSELevel, Level); 358 359 HasFloat16 = SSELevel >= SSE2; 360 361 HasBFloat16 = SSELevel >= SSE2; 362 363 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 364 .Case("+3dnowa", AMD3DNowAthlon) 365 .Case("+3dnow", AMD3DNow) 366 .Case("+mmx", MMX) 367 .Default(NoMMX3DNow); 368 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 369 370 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 371 .Case("+xop", XOP) 372 .Case("+fma4", FMA4) 373 .Case("+sse4a", SSE4A) 374 .Default(NoXOP); 375 XOPLevel = std::max(XOPLevel, XLevel); 376 } 377 378 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 379 // matches the selected sse level. 380 if ((FPMath == FP_SSE && SSELevel < SSE1) || 381 (FPMath == FP_387 && SSELevel >= SSE1)) { 382 Diags.Report(diag::err_target_unsupported_fpmath) 383 << (FPMath == FP_SSE ? "sse" : "387"); 384 return false; 385 } 386 387 SimdDefaultAlign = 388 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 389 390 // FIXME: We should allow long double type on 32-bits to match with GCC. 391 // This requires backend to be able to lower f80 without x87 first. 392 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 393 HasLongDouble = false; 394 395 return true; 396 } 397 398 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 399 /// definitions for this particular subtarget. 400 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 401 MacroBuilder &Builder) const { 402 // Inline assembly supports X86 flag outputs. 403 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 404 405 std::string CodeModel = getTargetOpts().CodeModel; 406 if (CodeModel == "default") 407 CodeModel = "small"; 408 Builder.defineMacro("__code_model_" + CodeModel + "__"); 409 410 // Target identification. 411 if (getTriple().getArch() == llvm::Triple::x86_64) { 412 Builder.defineMacro("__amd64__"); 413 Builder.defineMacro("__amd64"); 414 Builder.defineMacro("__x86_64"); 415 Builder.defineMacro("__x86_64__"); 416 if (getTriple().getArchName() == "x86_64h") { 417 Builder.defineMacro("__x86_64h"); 418 Builder.defineMacro("__x86_64h__"); 419 } 420 } else { 421 DefineStd(Builder, "i386", Opts); 422 } 423 424 Builder.defineMacro("__SEG_GS"); 425 Builder.defineMacro("__SEG_FS"); 426 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 427 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 428 429 // Subtarget options. 430 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 431 // truly should be based on -mtune options. 432 using namespace llvm::X86; 433 switch (CPU) { 434 case CK_None: 435 break; 436 case CK_i386: 437 // The rest are coming from the i386 define above. 438 Builder.defineMacro("__tune_i386__"); 439 break; 440 case CK_i486: 441 case CK_WinChipC6: 442 case CK_WinChip2: 443 case CK_C3: 444 defineCPUMacros(Builder, "i486"); 445 break; 446 case CK_PentiumMMX: 447 Builder.defineMacro("__pentium_mmx__"); 448 Builder.defineMacro("__tune_pentium_mmx__"); 449 LLVM_FALLTHROUGH; 450 case CK_i586: 451 case CK_Pentium: 452 defineCPUMacros(Builder, "i586"); 453 defineCPUMacros(Builder, "pentium"); 454 break; 455 case CK_Pentium3: 456 case CK_PentiumM: 457 Builder.defineMacro("__tune_pentium3__"); 458 LLVM_FALLTHROUGH; 459 case CK_Pentium2: 460 case CK_C3_2: 461 Builder.defineMacro("__tune_pentium2__"); 462 LLVM_FALLTHROUGH; 463 case CK_PentiumPro: 464 case CK_i686: 465 defineCPUMacros(Builder, "i686"); 466 defineCPUMacros(Builder, "pentiumpro"); 467 break; 468 case CK_Pentium4: 469 defineCPUMacros(Builder, "pentium4"); 470 break; 471 case CK_Yonah: 472 case CK_Prescott: 473 case CK_Nocona: 474 defineCPUMacros(Builder, "nocona"); 475 break; 476 case CK_Core2: 477 case CK_Penryn: 478 defineCPUMacros(Builder, "core2"); 479 break; 480 case CK_Bonnell: 481 defineCPUMacros(Builder, "atom"); 482 break; 483 case CK_Silvermont: 484 defineCPUMacros(Builder, "slm"); 485 break; 486 case CK_Goldmont: 487 defineCPUMacros(Builder, "goldmont"); 488 break; 489 case CK_GoldmontPlus: 490 defineCPUMacros(Builder, "goldmont_plus"); 491 break; 492 case CK_Tremont: 493 defineCPUMacros(Builder, "tremont"); 494 break; 495 case CK_Nehalem: 496 case CK_Westmere: 497 case CK_SandyBridge: 498 case CK_IvyBridge: 499 case CK_Haswell: 500 case CK_Broadwell: 501 case CK_SkylakeClient: 502 case CK_SkylakeServer: 503 case CK_Cascadelake: 504 case CK_Cooperlake: 505 case CK_Cannonlake: 506 case CK_IcelakeClient: 507 case CK_Rocketlake: 508 case CK_IcelakeServer: 509 case CK_Tigerlake: 510 case CK_SapphireRapids: 511 case CK_Alderlake: 512 // FIXME: Historically, we defined this legacy name, it would be nice to 513 // remove it at some point. We've never exposed fine-grained names for 514 // recent primary x86 CPUs, and we should keep it that way. 515 defineCPUMacros(Builder, "corei7"); 516 break; 517 case CK_KNL: 518 defineCPUMacros(Builder, "knl"); 519 break; 520 case CK_KNM: 521 break; 522 case CK_Lakemont: 523 defineCPUMacros(Builder, "i586", /*Tuning*/false); 524 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 525 Builder.defineMacro("__tune_lakemont__"); 526 break; 527 case CK_K6_2: 528 Builder.defineMacro("__k6_2__"); 529 Builder.defineMacro("__tune_k6_2__"); 530 LLVM_FALLTHROUGH; 531 case CK_K6_3: 532 if (CPU != CK_K6_2) { // In case of fallthrough 533 // FIXME: GCC may be enabling these in cases where some other k6 534 // architecture is specified but -m3dnow is explicitly provided. The 535 // exact semantics need to be determined and emulated here. 536 Builder.defineMacro("__k6_3__"); 537 Builder.defineMacro("__tune_k6_3__"); 538 } 539 LLVM_FALLTHROUGH; 540 case CK_K6: 541 defineCPUMacros(Builder, "k6"); 542 break; 543 case CK_Athlon: 544 case CK_AthlonXP: 545 defineCPUMacros(Builder, "athlon"); 546 if (SSELevel != NoSSE) { 547 Builder.defineMacro("__athlon_sse__"); 548 Builder.defineMacro("__tune_athlon_sse__"); 549 } 550 break; 551 case CK_K8: 552 case CK_K8SSE3: 553 case CK_x86_64: 554 defineCPUMacros(Builder, "k8"); 555 break; 556 case CK_x86_64_v2: 557 case CK_x86_64_v3: 558 case CK_x86_64_v4: 559 break; 560 case CK_AMDFAM10: 561 defineCPUMacros(Builder, "amdfam10"); 562 break; 563 case CK_BTVER1: 564 defineCPUMacros(Builder, "btver1"); 565 break; 566 case CK_BTVER2: 567 defineCPUMacros(Builder, "btver2"); 568 break; 569 case CK_BDVER1: 570 defineCPUMacros(Builder, "bdver1"); 571 break; 572 case CK_BDVER2: 573 defineCPUMacros(Builder, "bdver2"); 574 break; 575 case CK_BDVER3: 576 defineCPUMacros(Builder, "bdver3"); 577 break; 578 case CK_BDVER4: 579 defineCPUMacros(Builder, "bdver4"); 580 break; 581 case CK_ZNVER1: 582 defineCPUMacros(Builder, "znver1"); 583 break; 584 case CK_ZNVER2: 585 defineCPUMacros(Builder, "znver2"); 586 break; 587 case CK_ZNVER3: 588 defineCPUMacros(Builder, "znver3"); 589 break; 590 case CK_Geode: 591 defineCPUMacros(Builder, "geode"); 592 break; 593 } 594 595 // Target properties. 596 Builder.defineMacro("__REGISTER_PREFIX__", ""); 597 598 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 599 // functions in glibc header files that use FP Stack inline asm which the 600 // backend can't deal with (PR879). 601 Builder.defineMacro("__NO_MATH_INLINES"); 602 603 if (HasAES) 604 Builder.defineMacro("__AES__"); 605 606 if (HasVAES) 607 Builder.defineMacro("__VAES__"); 608 609 if (HasPCLMUL) 610 Builder.defineMacro("__PCLMUL__"); 611 612 if (HasVPCLMULQDQ) 613 Builder.defineMacro("__VPCLMULQDQ__"); 614 615 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 616 // the feature flag only applies to 64-bit mode. 617 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 618 Builder.defineMacro("__LAHF_SAHF__"); 619 620 if (HasLZCNT) 621 Builder.defineMacro("__LZCNT__"); 622 623 if (HasRDRND) 624 Builder.defineMacro("__RDRND__"); 625 626 if (HasFSGSBASE) 627 Builder.defineMacro("__FSGSBASE__"); 628 629 if (HasBMI) 630 Builder.defineMacro("__BMI__"); 631 632 if (HasBMI2) 633 Builder.defineMacro("__BMI2__"); 634 635 if (HasPOPCNT) 636 Builder.defineMacro("__POPCNT__"); 637 638 if (HasRTM) 639 Builder.defineMacro("__RTM__"); 640 641 if (HasPRFCHW) 642 Builder.defineMacro("__PRFCHW__"); 643 644 if (HasRDSEED) 645 Builder.defineMacro("__RDSEED__"); 646 647 if (HasADX) 648 Builder.defineMacro("__ADX__"); 649 650 if (HasTBM) 651 Builder.defineMacro("__TBM__"); 652 653 if (HasLWP) 654 Builder.defineMacro("__LWP__"); 655 656 if (HasMWAITX) 657 Builder.defineMacro("__MWAITX__"); 658 659 if (HasMOVBE) 660 Builder.defineMacro("__MOVBE__"); 661 662 switch (XOPLevel) { 663 case XOP: 664 Builder.defineMacro("__XOP__"); 665 LLVM_FALLTHROUGH; 666 case FMA4: 667 Builder.defineMacro("__FMA4__"); 668 LLVM_FALLTHROUGH; 669 case SSE4A: 670 Builder.defineMacro("__SSE4A__"); 671 LLVM_FALLTHROUGH; 672 case NoXOP: 673 break; 674 } 675 676 if (HasFMA) 677 Builder.defineMacro("__FMA__"); 678 679 if (HasF16C) 680 Builder.defineMacro("__F16C__"); 681 682 if (HasGFNI) 683 Builder.defineMacro("__GFNI__"); 684 685 if (HasAVX512CD) 686 Builder.defineMacro("__AVX512CD__"); 687 if (HasAVX512VPOPCNTDQ) 688 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 689 if (HasAVX512VNNI) 690 Builder.defineMacro("__AVX512VNNI__"); 691 if (HasAVX512BF16) 692 Builder.defineMacro("__AVX512BF16__"); 693 if (HasAVX512ER) 694 Builder.defineMacro("__AVX512ER__"); 695 if (HasAVX512FP16) 696 Builder.defineMacro("__AVX512FP16__"); 697 if (HasAVX512PF) 698 Builder.defineMacro("__AVX512PF__"); 699 if (HasAVX512DQ) 700 Builder.defineMacro("__AVX512DQ__"); 701 if (HasAVX512BITALG) 702 Builder.defineMacro("__AVX512BITALG__"); 703 if (HasAVX512BW) 704 Builder.defineMacro("__AVX512BW__"); 705 if (HasAVX512VL) 706 Builder.defineMacro("__AVX512VL__"); 707 if (HasAVX512VBMI) 708 Builder.defineMacro("__AVX512VBMI__"); 709 if (HasAVX512VBMI2) 710 Builder.defineMacro("__AVX512VBMI2__"); 711 if (HasAVX512IFMA) 712 Builder.defineMacro("__AVX512IFMA__"); 713 if (HasAVX512VP2INTERSECT) 714 Builder.defineMacro("__AVX512VP2INTERSECT__"); 715 if (HasSHA) 716 Builder.defineMacro("__SHA__"); 717 718 if (HasFXSR) 719 Builder.defineMacro("__FXSR__"); 720 if (HasXSAVE) 721 Builder.defineMacro("__XSAVE__"); 722 if (HasXSAVEOPT) 723 Builder.defineMacro("__XSAVEOPT__"); 724 if (HasXSAVEC) 725 Builder.defineMacro("__XSAVEC__"); 726 if (HasXSAVES) 727 Builder.defineMacro("__XSAVES__"); 728 if (HasPKU) 729 Builder.defineMacro("__PKU__"); 730 if (HasCLFLUSHOPT) 731 Builder.defineMacro("__CLFLUSHOPT__"); 732 if (HasCLWB) 733 Builder.defineMacro("__CLWB__"); 734 if (HasWBNOINVD) 735 Builder.defineMacro("__WBNOINVD__"); 736 if (HasSHSTK) 737 Builder.defineMacro("__SHSTK__"); 738 if (HasSGX) 739 Builder.defineMacro("__SGX__"); 740 if (HasPREFETCHWT1) 741 Builder.defineMacro("__PREFETCHWT1__"); 742 if (HasCLZERO) 743 Builder.defineMacro("__CLZERO__"); 744 if (HasKL) 745 Builder.defineMacro("__KL__"); 746 if (HasWIDEKL) 747 Builder.defineMacro("__WIDEKL__"); 748 if (HasRDPID) 749 Builder.defineMacro("__RDPID__"); 750 if (HasRDPRU) 751 Builder.defineMacro("__RDPRU__"); 752 if (HasCLDEMOTE) 753 Builder.defineMacro("__CLDEMOTE__"); 754 if (HasWAITPKG) 755 Builder.defineMacro("__WAITPKG__"); 756 if (HasMOVDIRI) 757 Builder.defineMacro("__MOVDIRI__"); 758 if (HasMOVDIR64B) 759 Builder.defineMacro("__MOVDIR64B__"); 760 if (HasPCONFIG) 761 Builder.defineMacro("__PCONFIG__"); 762 if (HasPTWRITE) 763 Builder.defineMacro("__PTWRITE__"); 764 if (HasINVPCID) 765 Builder.defineMacro("__INVPCID__"); 766 if (HasENQCMD) 767 Builder.defineMacro("__ENQCMD__"); 768 if (HasHRESET) 769 Builder.defineMacro("__HRESET__"); 770 if (HasAMXTILE) 771 Builder.defineMacro("__AMXTILE__"); 772 if (HasAMXINT8) 773 Builder.defineMacro("__AMXINT8__"); 774 if (HasAMXBF16) 775 Builder.defineMacro("__AMXBF16__"); 776 if (HasAVXVNNI) 777 Builder.defineMacro("__AVXVNNI__"); 778 if (HasSERIALIZE) 779 Builder.defineMacro("__SERIALIZE__"); 780 if (HasTSXLDTRK) 781 Builder.defineMacro("__TSXLDTRK__"); 782 if (HasUINTR) 783 Builder.defineMacro("__UINTR__"); 784 if (HasCRC32) 785 Builder.defineMacro("__CRC32__"); 786 787 // Each case falls through to the previous one here. 788 switch (SSELevel) { 789 case AVX512F: 790 Builder.defineMacro("__AVX512F__"); 791 LLVM_FALLTHROUGH; 792 case AVX2: 793 Builder.defineMacro("__AVX2__"); 794 LLVM_FALLTHROUGH; 795 case AVX: 796 Builder.defineMacro("__AVX__"); 797 LLVM_FALLTHROUGH; 798 case SSE42: 799 Builder.defineMacro("__SSE4_2__"); 800 LLVM_FALLTHROUGH; 801 case SSE41: 802 Builder.defineMacro("__SSE4_1__"); 803 LLVM_FALLTHROUGH; 804 case SSSE3: 805 Builder.defineMacro("__SSSE3__"); 806 LLVM_FALLTHROUGH; 807 case SSE3: 808 Builder.defineMacro("__SSE3__"); 809 LLVM_FALLTHROUGH; 810 case SSE2: 811 Builder.defineMacro("__SSE2__"); 812 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 813 LLVM_FALLTHROUGH; 814 case SSE1: 815 Builder.defineMacro("__SSE__"); 816 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 817 LLVM_FALLTHROUGH; 818 case NoSSE: 819 break; 820 } 821 822 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 823 switch (SSELevel) { 824 case AVX512F: 825 case AVX2: 826 case AVX: 827 case SSE42: 828 case SSE41: 829 case SSSE3: 830 case SSE3: 831 case SSE2: 832 Builder.defineMacro("_M_IX86_FP", Twine(2)); 833 break; 834 case SSE1: 835 Builder.defineMacro("_M_IX86_FP", Twine(1)); 836 break; 837 default: 838 Builder.defineMacro("_M_IX86_FP", Twine(0)); 839 break; 840 } 841 } 842 843 // Each case falls through to the previous one here. 844 switch (MMX3DNowLevel) { 845 case AMD3DNowAthlon: 846 Builder.defineMacro("__3dNOW_A__"); 847 LLVM_FALLTHROUGH; 848 case AMD3DNow: 849 Builder.defineMacro("__3dNOW__"); 850 LLVM_FALLTHROUGH; 851 case MMX: 852 Builder.defineMacro("__MMX__"); 853 LLVM_FALLTHROUGH; 854 case NoMMX3DNow: 855 break; 856 } 857 858 if (CPU >= CK_i486 || CPU == CK_None) { 859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 860 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 861 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 862 } 863 if (HasCX8) 864 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 865 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 866 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 867 868 if (HasFloat128) 869 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 870 } 871 872 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 873 return llvm::StringSwitch<bool>(Name) 874 .Case("3dnow", true) 875 .Case("3dnowa", true) 876 .Case("adx", true) 877 .Case("aes", true) 878 .Case("amx-bf16", true) 879 .Case("amx-int8", true) 880 .Case("amx-tile", true) 881 .Case("avx", true) 882 .Case("avx2", true) 883 .Case("avx512f", true) 884 .Case("avx512cd", true) 885 .Case("avx512vpopcntdq", true) 886 .Case("avx512vnni", true) 887 .Case("avx512bf16", true) 888 .Case("avx512er", true) 889 .Case("avx512fp16", true) 890 .Case("avx512pf", true) 891 .Case("avx512dq", true) 892 .Case("avx512bitalg", true) 893 .Case("avx512bw", true) 894 .Case("avx512vl", true) 895 .Case("avx512vbmi", true) 896 .Case("avx512vbmi2", true) 897 .Case("avx512ifma", true) 898 .Case("avx512vp2intersect", true) 899 .Case("avxvnni", true) 900 .Case("bmi", true) 901 .Case("bmi2", true) 902 .Case("cldemote", true) 903 .Case("clflushopt", true) 904 .Case("clwb", true) 905 .Case("clzero", true) 906 .Case("crc32", true) 907 .Case("cx16", true) 908 .Case("enqcmd", true) 909 .Case("f16c", true) 910 .Case("fma", true) 911 .Case("fma4", true) 912 .Case("fsgsbase", true) 913 .Case("fxsr", true) 914 .Case("general-regs-only", true) 915 .Case("gfni", true) 916 .Case("hreset", true) 917 .Case("invpcid", true) 918 .Case("kl", true) 919 .Case("widekl", true) 920 .Case("lwp", true) 921 .Case("lzcnt", true) 922 .Case("mmx", true) 923 .Case("movbe", true) 924 .Case("movdiri", true) 925 .Case("movdir64b", true) 926 .Case("mwaitx", true) 927 .Case("pclmul", true) 928 .Case("pconfig", true) 929 .Case("pku", true) 930 .Case("popcnt", true) 931 .Case("prefetchwt1", true) 932 .Case("prfchw", true) 933 .Case("ptwrite", true) 934 .Case("rdpid", true) 935 .Case("rdpru", true) 936 .Case("rdrnd", true) 937 .Case("rdseed", true) 938 .Case("rtm", true) 939 .Case("sahf", true) 940 .Case("serialize", true) 941 .Case("sgx", true) 942 .Case("sha", true) 943 .Case("shstk", true) 944 .Case("sse", true) 945 .Case("sse2", true) 946 .Case("sse3", true) 947 .Case("ssse3", true) 948 .Case("sse4", true) 949 .Case("sse4.1", true) 950 .Case("sse4.2", true) 951 .Case("sse4a", true) 952 .Case("tbm", true) 953 .Case("tsxldtrk", true) 954 .Case("uintr", true) 955 .Case("vaes", true) 956 .Case("vpclmulqdq", true) 957 .Case("wbnoinvd", true) 958 .Case("waitpkg", true) 959 .Case("x87", true) 960 .Case("xop", true) 961 .Case("xsave", true) 962 .Case("xsavec", true) 963 .Case("xsaves", true) 964 .Case("xsaveopt", true) 965 .Default(false); 966 } 967 968 bool X86TargetInfo::hasFeature(StringRef Feature) const { 969 return llvm::StringSwitch<bool>(Feature) 970 .Case("adx", HasADX) 971 .Case("aes", HasAES) 972 .Case("amx-bf16", HasAMXBF16) 973 .Case("amx-int8", HasAMXINT8) 974 .Case("amx-tile", HasAMXTILE) 975 .Case("avxvnni", HasAVXVNNI) 976 .Case("avx", SSELevel >= AVX) 977 .Case("avx2", SSELevel >= AVX2) 978 .Case("avx512f", SSELevel >= AVX512F) 979 .Case("avx512cd", HasAVX512CD) 980 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 981 .Case("avx512vnni", HasAVX512VNNI) 982 .Case("avx512bf16", HasAVX512BF16) 983 .Case("avx512er", HasAVX512ER) 984 .Case("avx512fp16", HasAVX512FP16) 985 .Case("avx512pf", HasAVX512PF) 986 .Case("avx512dq", HasAVX512DQ) 987 .Case("avx512bitalg", HasAVX512BITALG) 988 .Case("avx512bw", HasAVX512BW) 989 .Case("avx512vl", HasAVX512VL) 990 .Case("avx512vbmi", HasAVX512VBMI) 991 .Case("avx512vbmi2", HasAVX512VBMI2) 992 .Case("avx512ifma", HasAVX512IFMA) 993 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 994 .Case("bmi", HasBMI) 995 .Case("bmi2", HasBMI2) 996 .Case("cldemote", HasCLDEMOTE) 997 .Case("clflushopt", HasCLFLUSHOPT) 998 .Case("clwb", HasCLWB) 999 .Case("clzero", HasCLZERO) 1000 .Case("crc32", HasCRC32) 1001 .Case("cx8", HasCX8) 1002 .Case("cx16", HasCX16) 1003 .Case("enqcmd", HasENQCMD) 1004 .Case("f16c", HasF16C) 1005 .Case("fma", HasFMA) 1006 .Case("fma4", XOPLevel >= FMA4) 1007 .Case("fsgsbase", HasFSGSBASE) 1008 .Case("fxsr", HasFXSR) 1009 .Case("gfni", HasGFNI) 1010 .Case("hreset", HasHRESET) 1011 .Case("invpcid", HasINVPCID) 1012 .Case("kl", HasKL) 1013 .Case("widekl", HasWIDEKL) 1014 .Case("lwp", HasLWP) 1015 .Case("lzcnt", HasLZCNT) 1016 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1017 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1018 .Case("mmx", MMX3DNowLevel >= MMX) 1019 .Case("movbe", HasMOVBE) 1020 .Case("movdiri", HasMOVDIRI) 1021 .Case("movdir64b", HasMOVDIR64B) 1022 .Case("mwaitx", HasMWAITX) 1023 .Case("pclmul", HasPCLMUL) 1024 .Case("pconfig", HasPCONFIG) 1025 .Case("pku", HasPKU) 1026 .Case("popcnt", HasPOPCNT) 1027 .Case("prefetchwt1", HasPREFETCHWT1) 1028 .Case("prfchw", HasPRFCHW) 1029 .Case("ptwrite", HasPTWRITE) 1030 .Case("rdpid", HasRDPID) 1031 .Case("rdpru", HasRDPRU) 1032 .Case("rdrnd", HasRDRND) 1033 .Case("rdseed", HasRDSEED) 1034 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1035 .Case("rtm", HasRTM) 1036 .Case("sahf", HasLAHFSAHF) 1037 .Case("serialize", HasSERIALIZE) 1038 .Case("sgx", HasSGX) 1039 .Case("sha", HasSHA) 1040 .Case("shstk", HasSHSTK) 1041 .Case("sse", SSELevel >= SSE1) 1042 .Case("sse2", SSELevel >= SSE2) 1043 .Case("sse3", SSELevel >= SSE3) 1044 .Case("ssse3", SSELevel >= SSSE3) 1045 .Case("sse4.1", SSELevel >= SSE41) 1046 .Case("sse4.2", SSELevel >= SSE42) 1047 .Case("sse4a", XOPLevel >= SSE4A) 1048 .Case("tbm", HasTBM) 1049 .Case("tsxldtrk", HasTSXLDTRK) 1050 .Case("uintr", HasUINTR) 1051 .Case("vaes", HasVAES) 1052 .Case("vpclmulqdq", HasVPCLMULQDQ) 1053 .Case("wbnoinvd", HasWBNOINVD) 1054 .Case("waitpkg", HasWAITPKG) 1055 .Case("x86", true) 1056 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1057 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1058 .Case("x87", HasX87) 1059 .Case("xop", XOPLevel >= XOP) 1060 .Case("xsave", HasXSAVE) 1061 .Case("xsavec", HasXSAVEC) 1062 .Case("xsaves", HasXSAVES) 1063 .Case("xsaveopt", HasXSAVEOPT) 1064 .Default(false); 1065 } 1066 1067 // We can't use a generic validation scheme for the features accepted here 1068 // versus subtarget features accepted in the target attribute because the 1069 // bitfield structure that's initialized in the runtime only supports the 1070 // below currently rather than the full range of subtarget features. (See 1071 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1072 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1073 return llvm::StringSwitch<bool>(FeatureStr) 1074 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1075 #include "llvm/Support/X86TargetParser.def" 1076 .Default(false); 1077 } 1078 1079 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1080 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1081 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1082 .Case(STR, llvm::X86::FEATURE_##ENUM) 1083 1084 #include "llvm/Support/X86TargetParser.def" 1085 ; 1086 // Note, this function should only be used after ensuring the value is 1087 // correct, so it asserts if the value is out of range. 1088 } 1089 1090 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1091 // Valid CPUs have a 'key feature' that compares just better than its key 1092 // feature. 1093 using namespace llvm::X86; 1094 CPUKind Kind = parseArchX86(Name); 1095 if (Kind != CK_None) { 1096 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1097 return (getFeaturePriority(KeyFeature) << 1) + 1; 1098 } 1099 1100 // Now we know we have a feature, so get its priority and shift it a few so 1101 // that we have sufficient room for the CPUs (above). 1102 return getFeaturePriority(getFeature(Name)) << 1; 1103 } 1104 1105 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1106 return llvm::StringSwitch<bool>(Name) 1107 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true) 1108 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true) 1109 #include "llvm/Support/X86TargetParser.def" 1110 .Default(false); 1111 } 1112 1113 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1114 return llvm::StringSwitch<StringRef>(Name) 1115 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME) 1116 #include "llvm/Support/X86TargetParser.def" 1117 .Default(Name); 1118 } 1119 1120 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1121 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1122 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1123 #include "llvm/Support/X86TargetParser.def" 1124 .Default(0); 1125 } 1126 1127 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1128 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1129 StringRef WholeList = 1130 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1131 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1132 #include "llvm/Support/X86TargetParser.def" 1133 .Default(""); 1134 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1135 } 1136 1137 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const { 1138 return llvm::StringSwitch<StringRef>(Name) 1139 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME) 1140 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME) 1141 #include "llvm/Support/X86TargetParser.def" 1142 .Default(""); 1143 } 1144 1145 // We can't use a generic validation scheme for the cpus accepted here 1146 // versus subtarget cpus accepted in the target attribute because the 1147 // variables intitialized by the runtime only support the below currently 1148 // rather than the full range of cpus. 1149 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1150 return llvm::StringSwitch<bool>(FeatureStr) 1151 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1152 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1153 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1154 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1155 #include "llvm/Support/X86TargetParser.def" 1156 .Default(false); 1157 } 1158 1159 static unsigned matchAsmCCConstraint(const char *&Name) { 1160 auto RV = llvm::StringSwitch<unsigned>(Name) 1161 .Case("@cca", 4) 1162 .Case("@ccae", 5) 1163 .Case("@ccb", 4) 1164 .Case("@ccbe", 5) 1165 .Case("@ccc", 4) 1166 .Case("@cce", 4) 1167 .Case("@ccz", 4) 1168 .Case("@ccg", 4) 1169 .Case("@ccge", 5) 1170 .Case("@ccl", 4) 1171 .Case("@ccle", 5) 1172 .Case("@ccna", 5) 1173 .Case("@ccnae", 6) 1174 .Case("@ccnb", 5) 1175 .Case("@ccnbe", 6) 1176 .Case("@ccnc", 5) 1177 .Case("@ccne", 5) 1178 .Case("@ccnz", 5) 1179 .Case("@ccng", 5) 1180 .Case("@ccnge", 6) 1181 .Case("@ccnl", 5) 1182 .Case("@ccnle", 6) 1183 .Case("@ccno", 5) 1184 .Case("@ccnp", 5) 1185 .Case("@ccns", 5) 1186 .Case("@cco", 4) 1187 .Case("@ccp", 4) 1188 .Case("@ccs", 4) 1189 .Default(0); 1190 return RV; 1191 } 1192 1193 bool X86TargetInfo::validateAsmConstraint( 1194 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1195 switch (*Name) { 1196 default: 1197 return false; 1198 // Constant constraints. 1199 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1200 // instructions. 1201 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1202 // x86_64 instructions. 1203 case 's': 1204 Info.setRequiresImmediate(); 1205 return true; 1206 case 'I': 1207 Info.setRequiresImmediate(0, 31); 1208 return true; 1209 case 'J': 1210 Info.setRequiresImmediate(0, 63); 1211 return true; 1212 case 'K': 1213 Info.setRequiresImmediate(-128, 127); 1214 return true; 1215 case 'L': 1216 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1217 return true; 1218 case 'M': 1219 Info.setRequiresImmediate(0, 3); 1220 return true; 1221 case 'N': 1222 Info.setRequiresImmediate(0, 255); 1223 return true; 1224 case 'O': 1225 Info.setRequiresImmediate(0, 127); 1226 return true; 1227 // Register constraints. 1228 case 'Y': // 'Y' is the first character for several 2-character constraints. 1229 // Shift the pointer to the second character of the constraint. 1230 Name++; 1231 switch (*Name) { 1232 default: 1233 return false; 1234 case 'z': // First SSE register. 1235 case '2': 1236 case 't': // Any SSE register, when SSE2 is enabled. 1237 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1238 case 'm': // Any MMX register, when inter-unit moves enabled. 1239 case 'k': // AVX512 arch mask registers: k1-k7. 1240 Info.setAllowsRegister(); 1241 return true; 1242 } 1243 case 'f': // Any x87 floating point stack register. 1244 // Constraint 'f' cannot be used for output operands. 1245 if (Info.ConstraintStr[0] == '=') 1246 return false; 1247 Info.setAllowsRegister(); 1248 return true; 1249 case 'a': // eax. 1250 case 'b': // ebx. 1251 case 'c': // ecx. 1252 case 'd': // edx. 1253 case 'S': // esi. 1254 case 'D': // edi. 1255 case 'A': // edx:eax. 1256 case 't': // Top of floating point stack. 1257 case 'u': // Second from top of floating point stack. 1258 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1259 case 'y': // Any MMX register. 1260 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1261 case 'x': // Any SSE register. 1262 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1263 // for intermideate k reg operations). 1264 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1265 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1266 case 'l': // "Index" registers: any general register that can be used as an 1267 // index in a base+index memory access. 1268 Info.setAllowsRegister(); 1269 return true; 1270 // Floating point constant constraints. 1271 case 'C': // SSE floating point constant. 1272 case 'G': // x87 floating point constant. 1273 return true; 1274 case '@': 1275 // CC condition changes. 1276 if (auto Len = matchAsmCCConstraint(Name)) { 1277 Name += Len - 1; 1278 Info.setAllowsRegister(); 1279 return true; 1280 } 1281 return false; 1282 } 1283 } 1284 1285 // Below is based on the following information: 1286 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1287 // | Processor Name | Cache Line Size (Bytes) | Source | 1288 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1289 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1290 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1291 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1292 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1293 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1294 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1295 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1296 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1297 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1298 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1299 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1300 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1301 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1302 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1303 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1304 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1305 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1306 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1307 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1308 using namespace llvm::X86; 1309 switch (CPU) { 1310 // i386 1311 case CK_i386: 1312 // i486 1313 case CK_i486: 1314 case CK_WinChipC6: 1315 case CK_WinChip2: 1316 case CK_C3: 1317 // Lakemont 1318 case CK_Lakemont: 1319 return 16; 1320 1321 // i586 1322 case CK_i586: 1323 case CK_Pentium: 1324 case CK_PentiumMMX: 1325 // i686 1326 case CK_PentiumPro: 1327 case CK_i686: 1328 case CK_Pentium2: 1329 case CK_Pentium3: 1330 case CK_PentiumM: 1331 case CK_C3_2: 1332 // K6 1333 case CK_K6: 1334 case CK_K6_2: 1335 case CK_K6_3: 1336 // Geode 1337 case CK_Geode: 1338 return 32; 1339 1340 // Netburst 1341 case CK_Pentium4: 1342 case CK_Prescott: 1343 case CK_Nocona: 1344 // Atom 1345 case CK_Bonnell: 1346 case CK_Silvermont: 1347 case CK_Goldmont: 1348 case CK_GoldmontPlus: 1349 case CK_Tremont: 1350 1351 case CK_Westmere: 1352 case CK_SandyBridge: 1353 case CK_IvyBridge: 1354 case CK_Haswell: 1355 case CK_Broadwell: 1356 case CK_SkylakeClient: 1357 case CK_SkylakeServer: 1358 case CK_Cascadelake: 1359 case CK_Nehalem: 1360 case CK_Cooperlake: 1361 case CK_Cannonlake: 1362 case CK_Tigerlake: 1363 case CK_SapphireRapids: 1364 case CK_IcelakeClient: 1365 case CK_Rocketlake: 1366 case CK_IcelakeServer: 1367 case CK_Alderlake: 1368 case CK_KNL: 1369 case CK_KNM: 1370 // K7 1371 case CK_Athlon: 1372 case CK_AthlonXP: 1373 // K8 1374 case CK_K8: 1375 case CK_K8SSE3: 1376 case CK_AMDFAM10: 1377 // Bobcat 1378 case CK_BTVER1: 1379 case CK_BTVER2: 1380 // Bulldozer 1381 case CK_BDVER1: 1382 case CK_BDVER2: 1383 case CK_BDVER3: 1384 case CK_BDVER4: 1385 // Zen 1386 case CK_ZNVER1: 1387 case CK_ZNVER2: 1388 case CK_ZNVER3: 1389 // Deprecated 1390 case CK_x86_64: 1391 case CK_x86_64_v2: 1392 case CK_x86_64_v3: 1393 case CK_x86_64_v4: 1394 case CK_Yonah: 1395 case CK_Penryn: 1396 case CK_Core2: 1397 return 64; 1398 1399 // The following currently have unknown cache line sizes (but they are probably all 64): 1400 // Core 1401 case CK_None: 1402 return None; 1403 } 1404 llvm_unreachable("Unknown CPU kind"); 1405 } 1406 1407 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1408 StringRef Constraint, 1409 unsigned Size) const { 1410 // Strip off constraint modifiers. 1411 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1412 Constraint = Constraint.substr(1); 1413 1414 return validateOperandSize(FeatureMap, Constraint, Size); 1415 } 1416 1417 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1418 StringRef Constraint, 1419 unsigned Size) const { 1420 return validateOperandSize(FeatureMap, Constraint, Size); 1421 } 1422 1423 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1424 StringRef Constraint, 1425 unsigned Size) const { 1426 switch (Constraint[0]) { 1427 default: 1428 break; 1429 case 'k': 1430 // Registers k0-k7 (AVX512) size limit is 64 bit. 1431 case 'y': 1432 return Size <= 64; 1433 case 'f': 1434 case 't': 1435 case 'u': 1436 return Size <= 128; 1437 case 'Y': 1438 // 'Y' is the first character for several 2-character constraints. 1439 switch (Constraint[1]) { 1440 default: 1441 return false; 1442 case 'm': 1443 // 'Ym' is synonymous with 'y'. 1444 case 'k': 1445 return Size <= 64; 1446 case 'z': 1447 // XMM0/YMM/ZMM0 1448 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1449 // ZMM0 can be used if target supports AVX512F. 1450 return Size <= 512U; 1451 else if (hasFeatureEnabled(FeatureMap, "avx")) 1452 // YMM0 can be used if target supports AVX. 1453 return Size <= 256U; 1454 else if (hasFeatureEnabled(FeatureMap, "sse")) 1455 return Size <= 128U; 1456 return false; 1457 case 'i': 1458 case 't': 1459 case '2': 1460 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1461 if (SSELevel < SSE2) 1462 return false; 1463 break; 1464 } 1465 break; 1466 case 'v': 1467 case 'x': 1468 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1469 // 512-bit zmm registers can be used if target supports AVX512F. 1470 return Size <= 512U; 1471 else if (hasFeatureEnabled(FeatureMap, "avx")) 1472 // 256-bit ymm registers can be used if target supports AVX. 1473 return Size <= 256U; 1474 return Size <= 128U; 1475 1476 } 1477 1478 return true; 1479 } 1480 1481 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1482 switch (*Constraint) { 1483 case '@': 1484 if (auto Len = matchAsmCCConstraint(Constraint)) { 1485 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1486 Constraint += Len - 1; 1487 return Converted; 1488 } 1489 return std::string(1, *Constraint); 1490 case 'a': 1491 return std::string("{ax}"); 1492 case 'b': 1493 return std::string("{bx}"); 1494 case 'c': 1495 return std::string("{cx}"); 1496 case 'd': 1497 return std::string("{dx}"); 1498 case 'S': 1499 return std::string("{si}"); 1500 case 'D': 1501 return std::string("{di}"); 1502 case 'p': // Keep 'p' constraint (address). 1503 return std::string("p"); 1504 case 't': // top of floating point stack. 1505 return std::string("{st}"); 1506 case 'u': // second from top of floating point stack. 1507 return std::string("{st(1)}"); // second from top of floating point stack. 1508 case 'Y': 1509 switch (Constraint[1]) { 1510 default: 1511 // Break from inner switch and fall through (copy single char), 1512 // continue parsing after copying the current constraint into 1513 // the return string. 1514 break; 1515 case 'k': 1516 case 'm': 1517 case 'i': 1518 case 't': 1519 case 'z': 1520 case '2': 1521 // "^" hints llvm that this is a 2 letter constraint. 1522 // "Constraint++" is used to promote the string iterator 1523 // to the next constraint. 1524 return std::string("^") + std::string(Constraint++, 2); 1525 } 1526 LLVM_FALLTHROUGH; 1527 default: 1528 return std::string(1, *Constraint); 1529 } 1530 } 1531 1532 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1533 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1534 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1535 } 1536 1537 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1538 llvm::X86::fillValidTuneCPUList(Values); 1539 } 1540 1541 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1542 return llvm::makeArrayRef(GCCRegNames); 1543 } 1544 1545 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1546 return llvm::makeArrayRef(AddlRegNames); 1547 } 1548 1549 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1550 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1551 Builtin::FirstTSBuiltin + 1); 1552 } 1553 1554 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1555 return llvm::makeArrayRef(BuiltinInfoX86, 1556 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1557 } 1558