1 //===-- Hexagon.cpp -------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/Support/Endian.h" 16 17 using namespace llvm; 18 using namespace llvm::object; 19 using namespace llvm::support::endian; 20 using namespace llvm::ELF; 21 using namespace lld; 22 using namespace lld::elf; 23 24 namespace { 25 class Hexagon final : public TargetInfo { 26 public: 27 Hexagon(); 28 uint32_t calcEFlags() const override; 29 RelExpr getRelExpr(RelType type, const Symbol &s, 30 const uint8_t *loc) const override; 31 RelType getDynRel(RelType type) const override; 32 void relocate(uint8_t *loc, const Relocation &rel, 33 uint64_t val) const override; 34 void writePltHeader(uint8_t *buf) const override; 35 void writePlt(uint8_t *buf, const Symbol &sym, 36 uint64_t pltEntryAddr) const override; 37 }; 38 } // namespace 39 40 Hexagon::Hexagon() { 41 pltRel = R_HEX_JMP_SLOT; 42 relativeRel = R_HEX_RELATIVE; 43 gotRel = R_HEX_GLOB_DAT; 44 symbolicRel = R_HEX_32; 45 46 gotBaseSymInGotPlt = true; 47 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The 48 // next 3 are reserved for the dynamic loader. 49 gotPltHeaderEntriesNum = 4; 50 51 pltEntrySize = 16; 52 pltHeaderSize = 32; 53 54 // Hexagon Linux uses 64K pages by default. 55 defaultMaxPageSize = 0x10000; 56 tlsGotRel = R_HEX_TPREL_32; 57 tlsModuleIndexRel = R_HEX_DTPMOD_32; 58 tlsOffsetRel = R_HEX_DTPREL_32; 59 } 60 61 uint32_t Hexagon::calcEFlags() const { 62 assert(!ctx->objectFiles.empty()); 63 64 // The architecture revision must always be equal to or greater than 65 // greatest revision in the list of inputs. 66 uint32_t ret = 0; 67 for (InputFile *f : ctx->objectFiles) { 68 uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags; 69 if (eflags > ret) 70 ret = eflags; 71 } 72 return ret; 73 } 74 75 static uint32_t applyMask(uint32_t mask, uint32_t data) { 76 uint32_t result = 0; 77 size_t off = 0; 78 79 for (size_t bit = 0; bit != 32; ++bit) { 80 uint32_t valBit = (data >> off) & 1; 81 uint32_t maskBit = (mask >> bit) & 1; 82 if (maskBit) { 83 result |= (valBit << bit); 84 ++off; 85 } 86 } 87 return result; 88 } 89 90 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s, 91 const uint8_t *loc) const { 92 switch (type) { 93 case R_HEX_NONE: 94 return R_NONE; 95 case R_HEX_6_X: 96 case R_HEX_8_X: 97 case R_HEX_9_X: 98 case R_HEX_10_X: 99 case R_HEX_11_X: 100 case R_HEX_12_X: 101 case R_HEX_16_X: 102 case R_HEX_32: 103 case R_HEX_32_6_X: 104 case R_HEX_HI16: 105 case R_HEX_LO16: 106 case R_HEX_DTPREL_32: 107 return R_ABS; 108 case R_HEX_B9_PCREL: 109 case R_HEX_B13_PCREL: 110 case R_HEX_B15_PCREL: 111 case R_HEX_6_PCREL_X: 112 case R_HEX_32_PCREL: 113 return R_PC; 114 case R_HEX_B9_PCREL_X: 115 case R_HEX_B15_PCREL_X: 116 case R_HEX_B22_PCREL: 117 case R_HEX_PLT_B22_PCREL: 118 case R_HEX_B22_PCREL_X: 119 case R_HEX_B32_PCREL_X: 120 case R_HEX_GD_PLT_B22_PCREL: 121 case R_HEX_GD_PLT_B22_PCREL_X: 122 case R_HEX_GD_PLT_B32_PCREL_X: 123 return R_PLT_PC; 124 case R_HEX_IE_32_6_X: 125 case R_HEX_IE_16_X: 126 case R_HEX_IE_HI16: 127 case R_HEX_IE_LO16: 128 return R_GOT; 129 case R_HEX_GD_GOT_11_X: 130 case R_HEX_GD_GOT_16_X: 131 case R_HEX_GD_GOT_32_6_X: 132 return R_TLSGD_GOTPLT; 133 case R_HEX_GOTREL_11_X: 134 case R_HEX_GOTREL_16_X: 135 case R_HEX_GOTREL_32_6_X: 136 case R_HEX_GOTREL_HI16: 137 case R_HEX_GOTREL_LO16: 138 return R_GOTPLTREL; 139 case R_HEX_GOT_11_X: 140 case R_HEX_GOT_16_X: 141 case R_HEX_GOT_32_6_X: 142 return R_GOTPLT; 143 case R_HEX_IE_GOT_11_X: 144 case R_HEX_IE_GOT_16_X: 145 case R_HEX_IE_GOT_32_6_X: 146 case R_HEX_IE_GOT_HI16: 147 case R_HEX_IE_GOT_LO16: 148 config->hasTlsIe = true; 149 return R_GOTPLT; 150 case R_HEX_TPREL_11_X: 151 case R_HEX_TPREL_16: 152 case R_HEX_TPREL_16_X: 153 case R_HEX_TPREL_32_6_X: 154 case R_HEX_TPREL_HI16: 155 case R_HEX_TPREL_LO16: 156 return R_TPREL; 157 default: 158 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 159 ") against symbol " + toString(s)); 160 return R_NONE; 161 } 162 } 163 164 // There are (arguably too) many relocation masks for the DSP's 165 // R_HEX_6_X type. The table below is used to select the correct mask 166 // for the given instruction. 167 struct InstructionMask { 168 uint32_t cmpMask; 169 uint32_t relocMask; 170 }; 171 static const InstructionMask r6[] = { 172 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 173 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 174 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 175 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, 176 {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0}, 177 {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0}, 178 {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000}, 179 {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60}, 180 {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60}, 181 {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f}, 182 {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078}, 183 {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0}, 184 {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}}; 185 186 static bool isDuplex(uint32_t insn) { 187 // Duplex forms have a fixed mask and parse bits 15:14 are always 188 // zero. Non-duplex insns will always have at least one bit set in the 189 // parse field. 190 return (0xC000 & insn) == 0; 191 } 192 193 static uint32_t findMaskR6(uint32_t insn) { 194 if (isDuplex(insn)) 195 return 0x03f00000; 196 197 for (InstructionMask i : r6) 198 if ((0xff000000 & insn) == i.cmpMask) 199 return i.relocMask; 200 201 error("unrecognized instruction for 6_X relocation: 0x" + 202 utohexstr(insn)); 203 return 0; 204 } 205 206 static uint32_t findMaskR8(uint32_t insn) { 207 if ((0xff000000 & insn) == 0xde000000) 208 return 0x00e020e8; 209 if ((0xff000000 & insn) == 0x3c000000) 210 return 0x0000207f; 211 return 0x00001fe0; 212 } 213 214 static uint32_t findMaskR11(uint32_t insn) { 215 if ((0xff000000 & insn) == 0xa1000000) 216 return 0x060020ff; 217 return 0x06003fe0; 218 } 219 220 static uint32_t findMaskR16(uint32_t insn) { 221 if ((0xff000000 & insn) == 0x48000000) 222 return 0x061f20ff; 223 if ((0xff000000 & insn) == 0x49000000) 224 return 0x061f3fe0; 225 if ((0xff000000 & insn) == 0x78000000) 226 return 0x00df3fe0; 227 if ((0xff000000 & insn) == 0xb0000000) 228 return 0x0fe03fe0; 229 230 if (isDuplex(insn)) 231 return 0x03f00000; 232 233 for (InstructionMask i : r6) 234 if ((0xff000000 & insn) == i.cmpMask) 235 return i.relocMask; 236 237 error("unrecognized instruction for 16_X type: 0x" + 238 utohexstr(insn)); 239 return 0; 240 } 241 242 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 243 244 void Hexagon::relocate(uint8_t *loc, const Relocation &rel, 245 uint64_t val) const { 246 switch (rel.type) { 247 case R_HEX_NONE: 248 break; 249 case R_HEX_6_PCREL_X: 250 case R_HEX_6_X: 251 or32le(loc, applyMask(findMaskR6(read32le(loc)), val)); 252 break; 253 case R_HEX_8_X: 254 or32le(loc, applyMask(findMaskR8(read32le(loc)), val)); 255 break; 256 case R_HEX_9_X: 257 or32le(loc, applyMask(0x00003fe0, val & 0x3f)); 258 break; 259 case R_HEX_10_X: 260 or32le(loc, applyMask(0x00203fe0, val & 0x3f)); 261 break; 262 case R_HEX_11_X: 263 case R_HEX_GD_GOT_11_X: 264 case R_HEX_IE_GOT_11_X: 265 case R_HEX_GOT_11_X: 266 case R_HEX_GOTREL_11_X: 267 case R_HEX_TPREL_11_X: 268 or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f)); 269 break; 270 case R_HEX_12_X: 271 or32le(loc, applyMask(0x000007e0, val)); 272 break; 273 case R_HEX_16_X: // These relocs only have 6 effective bits. 274 case R_HEX_IE_16_X: 275 case R_HEX_IE_GOT_16_X: 276 case R_HEX_GD_GOT_16_X: 277 case R_HEX_GOT_16_X: 278 case R_HEX_GOTREL_16_X: 279 case R_HEX_TPREL_16_X: 280 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f)); 281 break; 282 case R_HEX_TPREL_16: 283 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0xffff)); 284 break; 285 case R_HEX_32: 286 case R_HEX_32_PCREL: 287 case R_HEX_DTPREL_32: 288 or32le(loc, val); 289 break; 290 case R_HEX_32_6_X: 291 case R_HEX_GD_GOT_32_6_X: 292 case R_HEX_GOT_32_6_X: 293 case R_HEX_GOTREL_32_6_X: 294 case R_HEX_IE_GOT_32_6_X: 295 case R_HEX_IE_32_6_X: 296 case R_HEX_TPREL_32_6_X: 297 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 298 break; 299 case R_HEX_B9_PCREL: 300 checkInt(loc, val, 11, rel); 301 or32le(loc, applyMask(0x003000fe, val >> 2)); 302 break; 303 case R_HEX_B9_PCREL_X: 304 or32le(loc, applyMask(0x003000fe, val & 0x3f)); 305 break; 306 case R_HEX_B13_PCREL: 307 checkInt(loc, val, 15, rel); 308 or32le(loc, applyMask(0x00202ffe, val >> 2)); 309 break; 310 case R_HEX_B15_PCREL: 311 checkInt(loc, val, 17, rel); 312 or32le(loc, applyMask(0x00df20fe, val >> 2)); 313 break; 314 case R_HEX_B15_PCREL_X: 315 or32le(loc, applyMask(0x00df20fe, val & 0x3f)); 316 break; 317 case R_HEX_B22_PCREL: 318 case R_HEX_GD_PLT_B22_PCREL: 319 case R_HEX_PLT_B22_PCREL: 320 checkInt(loc, val, 22, rel); 321 or32le(loc, applyMask(0x1ff3ffe, val >> 2)); 322 break; 323 case R_HEX_B22_PCREL_X: 324 case R_HEX_GD_PLT_B22_PCREL_X: 325 or32le(loc, applyMask(0x1ff3ffe, val & 0x3f)); 326 break; 327 case R_HEX_B32_PCREL_X: 328 case R_HEX_GD_PLT_B32_PCREL_X: 329 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 330 break; 331 case R_HEX_GOTREL_HI16: 332 case R_HEX_HI16: 333 case R_HEX_IE_GOT_HI16: 334 case R_HEX_IE_HI16: 335 case R_HEX_TPREL_HI16: 336 or32le(loc, applyMask(0x00c03fff, val >> 16)); 337 break; 338 case R_HEX_GOTREL_LO16: 339 case R_HEX_LO16: 340 case R_HEX_IE_GOT_LO16: 341 case R_HEX_IE_LO16: 342 case R_HEX_TPREL_LO16: 343 or32le(loc, applyMask(0x00c03fff, val)); 344 break; 345 default: 346 llvm_unreachable("unknown relocation"); 347 } 348 } 349 350 void Hexagon::writePltHeader(uint8_t *buf) const { 351 const uint8_t pltData[] = { 352 0x00, 0x40, 0x00, 0x00, // { immext (#0) 353 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0 354 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn 355 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2 356 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1 357 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn 358 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker 359 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment 360 }; 361 memcpy(buf, pltData, sizeof(pltData)); 362 363 // Offset from PLT0 to the GOT. 364 uint64_t off = in.gotPlt->getVA() - in.plt->getVA(); 365 relocateNoSym(buf, R_HEX_B32_PCREL_X, off); 366 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, off); 367 } 368 369 void Hexagon::writePlt(uint8_t *buf, const Symbol &sym, 370 uint64_t pltEntryAddr) const { 371 const uint8_t inst[] = { 372 0x00, 0x40, 0x00, 0x00, // { immext (#0) 373 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) } 374 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14) 375 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 376 }; 377 memcpy(buf, inst, sizeof(inst)); 378 379 uint64_t gotPltEntryAddr = sym.getGotPltVA(); 380 relocateNoSym(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr); 381 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr); 382 } 383 384 RelType Hexagon::getDynRel(RelType type) const { 385 if (type == R_HEX_32) 386 return type; 387 return R_HEX_NONE; 388 } 389 390 TargetInfo *elf::getHexagonTargetInfo() { 391 static Hexagon target; 392 return ⌖ 393 } 394