1 //===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 10 #define LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 11 12 #include "Plugins/Process/Utility/ARMDefines.h" 13 #include "lldb/Core/EmulateInstruction.h" 14 #include "lldb/Utility/ConstString.h" 15 #include "lldb/Utility/Status.h" 16 #include <optional> 17 18 namespace lldb_private { 19 20 // ITSession - Keep track of the IT Block progression. 21 class ITSession { 22 public: 23 ITSession() = default; 24 ~ITSession() = default; 25 26 // InitIT - Initializes ITCounter/ITState. 27 bool InitIT(uint32_t bits7_0); 28 29 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 30 void ITAdvance(); 31 32 // InITBlock - Returns true if we're inside an IT Block. 33 bool InITBlock(); 34 35 // LastInITBlock - Returns true if we're the last instruction inside an IT 36 // Block. 37 bool LastInITBlock(); 38 39 // GetCond - Gets condition bits for the current thumb instruction. 40 uint32_t GetCond(); 41 42 private: 43 uint32_t ITCounter = 0; // Possible values: 0, 1, 2, 3, 4. 44 uint32_t ITState = 0; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 45 }; 46 47 class EmulateInstructionARM : public EmulateInstruction { 48 public: 49 enum ARMEncoding { 50 eEncodingA1, 51 eEncodingA2, 52 eEncodingA3, 53 eEncodingA4, 54 eEncodingA5, 55 eEncodingT1, 56 eEncodingT2, 57 eEncodingT3, 58 eEncodingT4, 59 eEncodingT5 60 }; 61 62 static void Initialize(); 63 64 static void Terminate(); 65 66 static llvm::StringRef GetPluginNameStatic() { return "arm"; } 67 68 static llvm::StringRef GetPluginDescriptionStatic(); 69 70 static lldb_private::EmulateInstruction * 71 CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type); 72 73 static bool 74 SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) { 75 switch (inst_type) { 76 case eInstructionTypeAny: 77 case eInstructionTypePrologueEpilogue: 78 case eInstructionTypePCModifying: 79 return true; 80 81 case eInstructionTypeAll: 82 return false; 83 } 84 return false; 85 } 86 87 llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); } 88 89 bool SetTargetTriple(const ArchSpec &arch) override; 90 91 enum Mode { eModeInvalid = -1, eModeARM, eModeThumb }; 92 93 EmulateInstructionARM(const ArchSpec &arch) 94 : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid), 95 m_opcode_cpsr(0), m_new_inst_cpsr(0), m_it_session(), 96 m_ignore_conditions(false) { 97 SetArchitecture(arch); 98 } 99 100 // EmulateInstructionARM (const ArchSpec &arch, 101 // bool ignore_conditions, 102 // void *baton, 103 // ReadMemory read_mem_callback, 104 // WriteMemory write_mem_callback, 105 // ReadRegister read_reg_callback, 106 // WriteRegister write_reg_callback) : 107 // EmulateInstruction (arch, 108 // ignore_conditions, 109 // baton, 110 // read_mem_callback, 111 // write_mem_callback, 112 // read_reg_callback, 113 // write_reg_callback), 114 // m_arm_isa (0), 115 // m_opcode_mode (eModeInvalid), 116 // m_opcode_cpsr (0), 117 // m_it_session () 118 // { 119 // } 120 121 bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override { 122 return SupportsEmulatingInstructionsOfTypeStatic(inst_type); 123 } 124 125 virtual bool SetArchitecture(const ArchSpec &arch); 126 127 bool ReadInstruction() override; 128 129 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr, 130 Target *target) override; 131 132 bool EvaluateInstruction(uint32_t evaluate_options) override; 133 134 InstructionCondition GetInstructionCondition() override; 135 136 bool TestEmulation(Stream *out_stream, ArchSpec &arch, 137 OptionValueDictionary *test_data) override; 138 139 std::optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind, 140 uint32_t reg_num) override; 141 142 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override; 143 144 uint32_t ArchVersion(); 145 146 bool ConditionPassed(const uint32_t opcode); 147 148 uint32_t CurrentCond(const uint32_t opcode); 149 150 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 151 bool InITBlock(); 152 153 // LastInITBlock - Returns true if we're in Thumb mode and the last 154 // instruction inside an IT Block. 155 bool LastInITBlock(); 156 157 bool BadMode(uint32_t mode); 158 159 bool CurrentModeIsPrivileged(); 160 161 void CPSRWriteByInstr(uint32_t value, uint32_t bytemask, 162 bool affect_execstate); 163 164 bool BranchWritePC(const Context &context, uint32_t addr); 165 166 bool BXWritePC(Context &context, uint32_t addr); 167 168 bool LoadWritePC(Context &context, uint32_t addr); 169 170 bool ALUWritePC(Context &context, uint32_t addr); 171 172 Mode CurrentInstrSet(); 173 174 bool SelectInstrSet(Mode arm_or_thumb); 175 176 bool WriteBits32Unknown(int n); 177 178 bool WriteBits32UnknownToMemory(lldb::addr_t address); 179 180 bool UnalignedSupport(); 181 182 typedef struct { 183 uint32_t result; 184 uint8_t carry_out; 185 uint8_t overflow; 186 } AddWithCarryResult; 187 188 AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 189 190 // Helper method to read the content of an ARM core register. 191 uint32_t ReadCoreReg(uint32_t regnum, bool *success); 192 193 // See A8.6.96 MOV (immediate) Operation. 194 // Default arguments are specified for carry and overflow parameters, which 195 // means 196 // not to update the respective flags even if setflags is true. 197 bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result, 198 const uint32_t Rd, bool setflags, 199 const uint32_t carry = ~0u, 200 const uint32_t overflow = ~0u); 201 202 bool WriteCoreReg(Context &context, const uint32_t result, 203 const uint32_t Rd) { 204 // Don't set the flags. 205 return WriteCoreRegOptionalFlags(context, result, Rd, false); 206 } 207 208 // See A8.6.35 CMP (immediate) Operation. 209 // Default arguments are specified for carry and overflow parameters, which 210 // means 211 // not to update the respective flags. 212 bool WriteFlags(Context &context, const uint32_t result, 213 const uint32_t carry = ~0u, const uint32_t overflow = ~0u); 214 215 inline uint64_t MemARead(EmulateInstruction::Context &context, 216 lldb::addr_t address, uint32_t size, 217 uint64_t fail_value, bool *success_ptr) { 218 // This is a stub function corresponding to "MemA[]" in the ARM manual 219 // pseudocode, for 220 // aligned reads from memory. Since we are not trying to write a full 221 // hardware simulator, and since 222 // we are running in User mode (rather than Kernel mode) and therefore won't 223 // have access to many of the 224 // system registers we would need in order to fully implement this function, 225 // we will just call 226 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 227 // do more faithful emulation of 228 // the hardware, we can update this function appropriately. 229 230 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 231 } 232 233 inline bool MemAWrite(EmulateInstruction::Context &context, 234 lldb::addr_t address, uint64_t data_val, uint32_t size) 235 236 { 237 // This is a stub function corresponding to "MemA[]" in the ARM manual 238 // pseudocode, for 239 // aligned writes to memory. Since we are not trying to write a full 240 // hardware simulator, and since 241 // we are running in User mode (rather than Kernel mode) and therefore won't 242 // have access to many of the 243 // system registers we would need in order to fully implement this function, 244 // we will just call 245 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 246 // do more faithful emulation of 247 // the hardware, we can update this function appropriately. 248 249 return WriteMemoryUnsigned(context, address, data_val, size); 250 } 251 252 inline uint64_t MemURead(EmulateInstruction::Context &context, 253 lldb::addr_t address, uint32_t size, 254 uint64_t fail_value, bool *success_ptr) { 255 // This is a stub function corresponding to "MemU[]" in the ARM manual 256 // pseudocode, for 257 // unaligned reads from memory. Since we are not trying to write a full 258 // hardware simulator, and since 259 // we are running in User mode (rather than Kernel mode) and therefore won't 260 // have access to many of the 261 // system registers we would need in order to fully implement this function, 262 // we will just call 263 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 264 // do more faithful emulation of 265 // the hardware, we can update this function appropriately. 266 267 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 268 } 269 270 inline bool MemUWrite(EmulateInstruction::Context &context, 271 lldb::addr_t address, uint64_t data_val, uint32_t size) 272 273 { 274 // This is a stub function corresponding to "MemU[]" in the ARM manual 275 // pseudocode, for 276 // unaligned writes to memory. Since we are not trying to write a full 277 // hardware simulator, and since 278 // we are running in User mode (rather than Kernel mode) and therefore won't 279 // have access to many of the 280 // system registers we would need in order to fully implement this function, 281 // we will just call 282 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 283 // do more faithful emulation of 284 // the hardware, we can update this function appropriately. 285 286 return WriteMemoryUnsigned(context, address, data_val, size); 287 } 288 289 protected: 290 // Typedef for the callback function used during the emulation. 291 // Pass along (ARMEncoding)encoding as the callback data. 292 enum ARMInstrSize { eSize16, eSize32 }; 293 294 typedef struct { 295 uint32_t mask; 296 uint32_t value; 297 uint32_t variants; 298 EmulateInstructionARM::ARMEncoding encoding; 299 uint32_t vfp_variants; 300 ARMInstrSize size; 301 bool (EmulateInstructionARM::*callback)( 302 const uint32_t opcode, 303 const EmulateInstructionARM::ARMEncoding encoding); 304 const char *name; 305 } ARMOpcode; 306 307 uint32_t GetFramePointerRegisterNumber() const; 308 309 uint32_t GetFramePointerDWARFRegisterNumber() const; 310 311 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode, 312 uint32_t isa_mask); 313 314 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode, 315 uint32_t isa_mask); 316 317 // A8.6.123 PUSH 318 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding); 319 320 // A8.6.122 POP 321 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding); 322 323 // A8.6.8 ADD (SP plus immediate) 324 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding); 325 326 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 327 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding); 328 329 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 330 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding); 331 332 // A8.6.59 LDR (literal) 333 bool EmulateLDRRtPCRelative(const uint32_t opcode, 334 const ARMEncoding encoding); 335 336 // A8.6.8 ADD (SP plus immediate) 337 bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding); 338 339 // A8.6.9 ADD (SP plus register) 340 bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding); 341 342 // A8.6.23 BL, BLX (immediate) 343 bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding); 344 345 // A8.6.24 BLX (register) 346 bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding); 347 348 // A8.6.25 BX 349 bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding); 350 351 // A8.6.26 BXJ 352 bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding); 353 354 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 355 bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding); 356 357 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 358 bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding); 359 360 // A8.6.215 SUB (SP minus immediate) 361 bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding); 362 363 // A8.6.216 SUB (SP minus register) 364 bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding); 365 366 // A8.6.194 STR (immediate, ARM) -- Rn == sp 367 bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding); 368 369 // A8.6.355 VPUSH 370 bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding); 371 372 // A8.6.354 VPOP 373 bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding); 374 375 // A8.6.218 SVC (previously SWI) 376 bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding); 377 378 // A8.6.50 IT 379 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding); 380 381 // NOP 382 bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding); 383 384 // A8.6.16 B 385 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding); 386 387 // A8.6.27 CBNZ, CBZ 388 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding); 389 390 // A8.6.226 TBB, TBH 391 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding); 392 393 // A8.6.4 ADD (immediate, Thumb) 394 bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding); 395 396 // A8.6.5 ADD (immediate, ARM) 397 bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding); 398 399 // A8.6.6 ADD (register) 400 bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding); 401 402 // A8.6.7 ADD (register-shifted register) 403 bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding); 404 405 // A8.6.97 MOV (register) 406 bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding); 407 408 // A8.6.96 MOV (immediate) 409 bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding); 410 411 // A8.6.35 CMP (immediate) 412 bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding); 413 414 // A8.6.36 CMP (register) 415 bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding); 416 417 // A8.6.14 ASR (immediate) 418 bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding); 419 420 // A8.6.15 ASR (register) 421 bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding); 422 423 // A8.6.88 LSL (immediate) 424 bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding); 425 426 // A8.6.89 LSL (register) 427 bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding); 428 429 // A8.6.90 LSR (immediate) 430 bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding); 431 432 // A8.6.91 LSR (register) 433 bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding); 434 435 // A8.6.139 ROR (immediate) 436 bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding); 437 438 // A8.6.140 ROR (register) 439 bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding); 440 441 // A8.6.141 RRX 442 bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding); 443 444 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 445 bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding, 446 ARM_ShifterType shift_type); 447 448 // Helper method for ASR, LSL, LSR, and ROR (register) 449 bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, 450 ARM_ShifterType shift_type); 451 452 // LOAD FUNCTIONS 453 454 // A8.6.53 LDM/LDMIA/LDMFD 455 bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding); 456 457 // A8.6.54 LDMDA/LDMFA 458 bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding); 459 460 // A8.6.55 LDMDB/LDMEA 461 bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding); 462 463 // A8.6.56 LDMIB/LDMED 464 bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding); 465 466 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 467 bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding); 468 469 // A8.6.58 LDR (immediate, ARM) - Encoding A1 470 bool EmulateLDRImmediateARM(const uint32_t opcode, 471 const ARMEncoding encoding); 472 473 // A8.6.59 LDR (literal) 474 bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding); 475 476 // A8.6.60 LDR (register) - Encoding T1, T2, A1 477 bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding); 478 479 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 480 bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding); 481 482 // A8.6.62 LDRB (immediate, ARM) 483 bool EmulateLDRBImmediateARM(const uint32_t opcode, 484 const ARMEncoding encoding); 485 486 // A8.6.63 LDRB (literal) - Encoding T1, A1 487 bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding); 488 489 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 490 bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding); 491 492 // A8.6.65 LDRBT 493 bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding); 494 495 // A8.6.66 LDRD (immediate) 496 bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding); 497 498 // A8.6.67 499 bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding); 500 501 // A8.6.68 LDRD (register) 502 bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding); 503 504 // A8.6.69 LDREX 505 bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding); 506 507 // A8.6.70 LDREXB 508 bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding); 509 510 // A8.6.71 LDREXD 511 bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding); 512 513 // A8.6.72 LDREXH 514 bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding); 515 516 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 517 bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding); 518 519 // A8.6.74 LDRS (immediate, ARM) 520 bool EmulateLDRHImmediateARM(const uint32_t opcode, 521 const ARMEncoding encoding); 522 523 // A8.6.75 LDRH (literal) - Encoding T1, A1 524 bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding); 525 526 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 527 bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding); 528 529 // A8.6.77 LDRHT 530 bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding); 531 532 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 533 bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding); 534 535 // A8.6.79 LDRSB (literal) - Encoding T1, A1 536 bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding); 537 538 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 539 bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding); 540 541 // A8.6.81 LDRSBT 542 bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding); 543 544 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 545 bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding); 546 547 // A8.6.83 LDRSH (literal) - Encoding T1, A1 548 bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding); 549 550 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 551 bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding); 552 553 // A8.6.85 LDRSHT 554 bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding); 555 556 // A8.6.86 557 bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding); 558 559 // STORE FUNCTIONS 560 561 // A8.6.189 STM/STMIA/STMEA 562 bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding); 563 564 // A8.6.190 STMDA/STMED 565 bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding); 566 567 // A8.6.191 STMDB/STMFD 568 bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding); 569 570 // A8.6.192 STMIB/STMFA 571 bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding); 572 573 // A8.6.193 STR (immediate, Thumb) 574 bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 575 576 // A8.6.194 STR (immediate, ARM) 577 bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding); 578 579 // A8.6.195 STR (register) 580 bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding); 581 582 // A8.6.196 STRB (immediate, Thumb) 583 bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding); 584 585 // A8.6.197 STRB (immediate, ARM) 586 bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding); 587 588 // A8.6.198 STRB (register) 589 bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding); 590 591 // A8.6.199 STRBT 592 bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding); 593 594 // A8.6.200 STRD (immediate) 595 bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding); 596 597 // A8.6.201 STRD (register) 598 bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding); 599 600 // A8.6.202 STREX 601 bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding); 602 603 // A8.6.203 STREXB 604 bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding); 605 606 // A8.6.204 STREXD 607 bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding); 608 609 // A8.6.205 STREXH 610 bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding); 611 612 // A8.6.206 STRH (immediate, Thumb) 613 bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding); 614 615 // A8.6.207 STRH (immediate, ARM) 616 bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding); 617 618 // A8.6.208 STRH (register) 619 bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding); 620 621 // A8.6.209 STRHT 622 bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding); 623 624 // A8.6.210 STRT 625 bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding); 626 627 // A8.6.1 ADC (immediate) 628 bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding); 629 630 // A8.6.2 ADC (Register) 631 bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding); 632 633 // A8.6.10 ADR 634 bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding); 635 636 // A8.6.11 AND (immediate) 637 bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding); 638 639 // A8.6.12 AND (register) 640 bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding); 641 642 // A8.6.19 BIC (immediate) 643 bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding); 644 645 // A8.6.20 BIC (register) 646 bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding); 647 648 // A8.6.26 BXJ 649 bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding); 650 651 // A8.6.32 CMN (immediate) 652 bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding); 653 654 // A8.6.33 CMN (register) 655 bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding); 656 657 // A8.6.44 EOR (immediate) 658 bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding); 659 660 // A8.6.45 EOR (register) 661 bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding); 662 663 // A8.6.105 MUL 664 bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding); 665 666 // A8.6.106 MVN (immediate) 667 bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding); 668 669 // A8.6.107 MVN (register) 670 bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding); 671 672 // A8.6.113 ORR (immediate) 673 bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding); 674 675 // A8.6.114 ORR (register) 676 bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding); 677 678 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 679 bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding); 680 681 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 682 bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding); 683 684 // A8.6.120 PLI (register) - Encoding T1, A1 685 bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding); 686 687 // A8.6.141 RSB (immediate) 688 bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding); 689 690 // A8.6.142 RSB (register) 691 bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding); 692 693 // A8.6.144 RSC (immediate) 694 bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding); 695 696 // A8.6.145 RSC (register) 697 bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding); 698 699 // A8.6.150 SBC (immediate) 700 bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding); 701 702 // A8.6.151 SBC (register) 703 bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding); 704 705 // A8.6.211 SUB (immediate, Thumb) 706 bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding); 707 708 // A8.6.212 SUB (immediate, ARM) 709 bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding); 710 711 // A8.6.213 SUB (register) 712 bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding); 713 714 // A8.6.214 SUB (register-shifted register) 715 bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding); 716 717 // A8.6.222 SXTB - Encoding T1 718 bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding); 719 720 // A8.6.224 SXTH - EncodingT1 721 bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding); 722 723 // A8.6.227 TEQ (immediate) - Encoding A1 724 bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding); 725 726 // A8.6.228 TEQ (register) - Encoding A1 727 bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding); 728 729 // A8.6.230 TST (immediate) - Encoding A1 730 bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding); 731 732 // A8.6.231 TST (register) - Encoding T1, A1 733 bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding); 734 735 // A8.6.262 UXTB - Encoding T1 736 bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding); 737 738 // A8.6.264 UXTH - Encoding T1 739 bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding); 740 741 // B6.1.8 RFE 742 bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding); 743 744 // A8.6.319 VLDM 745 bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding); 746 747 // A8.6.399 VSTM 748 bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding); 749 750 // A8.6.307 VLD1 (multiple single elements) 751 bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding); 752 753 // A8.6.308 VLD1 (single element to one lane) 754 bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding); 755 756 // A8.6.309 VLD1 (single element to all lanes) 757 bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding); 758 759 // A8.6.391 VST1 (multiple single elements) 760 bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding); 761 762 // A8.6.392 VST1 (single element from one lane) 763 bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding); 764 765 // A8.6.317 VLDR 766 bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding); 767 768 // A8.6.400 VSTR 769 bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding); 770 771 // B6.2.13 SUBS PC, LR and related instructions 772 bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding); 773 774 uint32_t m_arm_isa; 775 Mode m_opcode_mode; 776 uint32_t m_opcode_cpsr; 777 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 778 ITSession m_it_session; 779 bool m_ignore_conditions; 780 }; 781 782 } // namespace lldb_private 783 784 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 785