1 //===-- RegisterContextDarwin_arm.h -----------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
11 
12 #include "lldb/Target/RegisterContext.h"
13 #include "lldb/lldb-private.h"
14 
15 // BCR address match type
16 #define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21))
17 #define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21))
18 #define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21))
19 #define BCR_M_RESERVED ((uint32_t)(3u << 21))
20 
21 // Link a BVR/BCR or WVR/WCR pair to another
22 #define E_ENABLE_LINKING ((uint32_t)(1u << 20))
23 
24 // Byte Address Select
25 #define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5))
26 #define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6))
27 #define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7))
28 #define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8))
29 #define BAS_IMVA_0_1 ((uint32_t)(3u << 5))
30 #define BAS_IMVA_2_3 ((uint32_t)(3u << 7))
31 #define BAS_IMVA_ALL ((uint32_t)(0xfu << 5))
32 
33 // Break only in privileged or user mode
34 #define S_RSVD ((uint32_t)(0u << 1))
35 #define S_PRIV ((uint32_t)(1u << 1))
36 #define S_USER ((uint32_t)(2u << 1))
37 #define S_PRIV_USER ((S_PRIV) | (S_USER))
38 
39 #define BCR_ENABLE ((uint32_t)(1u))
40 #define WCR_ENABLE ((uint32_t)(1u))
41 
42 // Watchpoint load/store
43 #define WCR_LOAD ((uint32_t)(1u << 3))
44 #define WCR_STORE ((uint32_t)(1u << 4))
45 
46 class RegisterContextDarwin_arm : public lldb_private::RegisterContext {
47 public:
48   RegisterContextDarwin_arm(lldb_private::Thread &thread,
49                             uint32_t concrete_frame_idx);
50 
51   ~RegisterContextDarwin_arm() override;
52 
53   void InvalidateAllRegisters() override;
54 
55   size_t GetRegisterCount() override;
56 
57   const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
58 
59   size_t GetRegisterSetCount() override;
60 
61   const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
62 
63   bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
64                     lldb_private::RegisterValue &reg_value) override;
65 
66   bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
67                      const lldb_private::RegisterValue &reg_value) override;
68 
69   bool ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
70 
71   bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
72 
73   uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
74                                                uint32_t num) override;
75 
76   uint32_t NumSupportedHardwareBreakpoints() override;
77 
78   uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override;
79 
80   bool ClearHardwareBreakpoint(uint32_t hw_idx) override;
81 
82   uint32_t NumSupportedHardwareWatchpoints() override;
83 
84   uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size, bool read,
85                                  bool write) override;
86 
87   bool ClearHardwareWatchpoint(uint32_t hw_index) override;
88 
89   struct GPR {
90     uint32_t r[16]; // R0-R15
91     uint32_t cpsr;  // CPSR
92   };
93 
94   struct QReg {
95     uint8_t bytes[16];
96   };
97 
98   struct FPU {
99     union {
100       uint32_t s[32];
101       uint64_t d[32];
102       QReg q[16]; // the 128-bit NEON registers
103     } floats;
104     uint32_t fpscr;
105   };
106 
107   //  struct NeonReg
108   //  {
109   //      uint8_t bytes[16];
110   //  };
111   //
112   //  struct VFPv3
113   //  {
114   //      union {
115   //          uint32_t s[32];
116   //          uint64_t d[32];
117   //          NeonReg  q[16];
118   //      } v3;
119   //      uint32_t fpscr;
120   //  };
121 
122   struct EXC {
123     uint32_t exception;
124     uint32_t fsr; /* Fault status */
125     uint32_t far; /* Virtual Fault Address */
126   };
127 
128   struct DBG {
129     uint32_t bvr[16];
130     uint32_t bcr[16];
131     uint32_t wvr[16];
132     uint32_t wcr[16];
133   };
134 
135   static void LogDBGRegisters(lldb_private::Log *log, const DBG &dbg);
136 
137 protected:
138   enum {
139     GPRRegSet = 1,    // ARM_THREAD_STATE
140     GPRAltRegSet = 9, // ARM_THREAD_STATE32
141     FPURegSet = 2,    // ARM_VFP_STATE
142     EXCRegSet = 3,    // ARM_EXCEPTION_STATE
143     DBGRegSet = 4     // ARM_DEBUG_STATE
144   };
145 
146   enum {
147     GPRWordCount = sizeof(GPR) / sizeof(uint32_t),
148     FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
149     EXCWordCount = sizeof(EXC) / sizeof(uint32_t),
150     DBGWordCount = sizeof(DBG) / sizeof(uint32_t)
151   };
152 
153   enum { Read = 0, Write = 1, kNumErrors = 2 };
154 
155   GPR gpr;
156   FPU fpu;
157   EXC exc;
158   DBG dbg;
159   int gpr_errs[2]; // Read/Write errors
160   int fpu_errs[2]; // Read/Write errors
161   int exc_errs[2]; // Read/Write errors
162   int dbg_errs[2]; // Read/Write errors
163 
164   void InvalidateAllRegisterStates() {
165     SetError(GPRRegSet, Read, -1);
166     SetError(FPURegSet, Read, -1);
167     SetError(EXCRegSet, Read, -1);
168   }
169 
170   int GetError(int flavor, uint32_t err_idx) const {
171     if (err_idx < kNumErrors) {
172       switch (flavor) {
173       // When getting all errors, just OR all values together to see if
174       // we got any kind of error.
175       case GPRRegSet:
176         return gpr_errs[err_idx];
177       case FPURegSet:
178         return fpu_errs[err_idx];
179       case EXCRegSet:
180         return exc_errs[err_idx];
181       case DBGRegSet:
182         return dbg_errs[err_idx];
183       default:
184         break;
185       }
186     }
187     return -1;
188   }
189 
190   bool SetError(int flavor, uint32_t err_idx, int err) {
191     if (err_idx < kNumErrors) {
192       switch (flavor) {
193       case GPRRegSet:
194         gpr_errs[err_idx] = err;
195         return true;
196 
197       case FPURegSet:
198         fpu_errs[err_idx] = err;
199         return true;
200 
201       case EXCRegSet:
202         exc_errs[err_idx] = err;
203         return true;
204 
205       case DBGRegSet:
206         exc_errs[err_idx] = err;
207         return true;
208 
209       default:
210         break;
211       }
212     }
213     return false;
214   }
215 
216   bool RegisterSetIsCached(int set) const { return GetError(set, Read) == 0; }
217 
218   int ReadGPR(bool force);
219 
220   int ReadFPU(bool force);
221 
222   int ReadEXC(bool force);
223 
224   int ReadDBG(bool force);
225 
226   int WriteGPR();
227 
228   int WriteFPU();
229 
230   int WriteEXC();
231 
232   int WriteDBG();
233 
234   // Subclasses override these to do the actual reading.
235   virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) { return -1; }
236 
237   virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
238 
239   virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) = 0;
240 
241   virtual int DoReadDBG(lldb::tid_t tid, int flavor, DBG &dbg) = 0;
242 
243   virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
244 
245   virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
246 
247   virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) = 0;
248 
249   virtual int DoWriteDBG(lldb::tid_t tid, int flavor, const DBG &dbg) = 0;
250 
251   int ReadRegisterSet(uint32_t set, bool force);
252 
253   int WriteRegisterSet(uint32_t set);
254 
255   static uint32_t GetRegisterNumber(uint32_t reg_kind, uint32_t reg_num);
256 
257   static int GetSetForNativeRegNum(int reg_num);
258 
259   static size_t GetRegisterInfosCount();
260 
261   static const lldb_private::RegisterInfo *GetRegisterInfos();
262 };
263 
264 #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
265