1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 #include "lldb/Utility/LLDBLog.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/StringList.h" 14 #include "lldb/lldb-defines.h" 15 #include "llvm/ADT/STLExtras.h" 16 #include "llvm/BinaryFormat/COFF.h" 17 #include "llvm/BinaryFormat/ELF.h" 18 #include "llvm/BinaryFormat/MachO.h" 19 #include "llvm/Support/Compiler.h" 20 #include "llvm/TargetParser/ARMTargetParser.h" 21 22 using namespace lldb; 23 using namespace lldb_private; 24 25 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 26 bool try_inverse, bool enforce_exact_match); 27 28 namespace lldb_private { 29 30 struct CoreDefinition { 31 ByteOrder default_byte_order; 32 uint32_t addr_byte_size; 33 uint32_t min_opcode_byte_size; 34 uint32_t max_opcode_byte_size; 35 llvm::Triple::ArchType machine; 36 ArchSpec::Core core; 37 const char *const name; 38 }; 39 40 } // namespace lldb_private 41 42 // This core information can be looked using the ArchSpec::Core as the index 43 static const CoreDefinition g_core_definitions[] = { 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 45 "arm"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 47 "armv4"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 49 "armv4t"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 51 "armv5"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 53 "armv5e"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 55 "armv5t"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 57 "armv6"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 59 "armv6m"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 61 "armv7"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 63 "armv7l"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 65 "armv7f"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 67 "armv7s"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 69 "armv7k"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 71 "armv7m"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 73 "armv7em"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 75 "xscale"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 77 "thumb"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 79 "thumbv4t"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 81 "thumbv5"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 83 "thumbv5e"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 85 "thumbv6"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 87 "thumbv6m"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 89 "thumbv7"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 91 "thumbv7f"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 93 "thumbv7s"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 95 "thumbv7k"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 97 "thumbv7m"}, 98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 99 "thumbv7em"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_arm64, "arm64"}, 102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 103 ArchSpec::eCore_arm_armv8, "armv8"}, 104 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l, 105 "armv8l"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_arm64e, "arm64e"}, 108 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 109 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 110 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 111 ArchSpec::eCore_arm_aarch64, "aarch64"}, 112 113 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 115 "mips"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 117 "mipsr2"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 119 "mipsr3"}, 120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 121 "mipsr5"}, 122 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 123 "mipsr6"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 125 "mipsel"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 130 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 131 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 132 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 133 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 134 135 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 137 "mips64"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 139 "mips64r2"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 141 "mips64r3"}, 142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 143 "mips64r5"}, 144 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 145 "mips64r6"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64el, "mips64el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 152 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 153 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 154 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 155 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 156 157 // MSP430 158 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430, 159 "msp430"}, 160 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 162 "powerpc"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 164 "ppc601"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 166 "ppc602"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 168 "ppc603"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 170 "ppc603e"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 172 "ppc603ev"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 174 "ppc604"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 176 "ppc604e"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 178 "ppc620"}, 179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 180 "ppc750"}, 181 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 182 "ppc7400"}, 183 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 184 "ppc7450"}, 185 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 186 "ppc970"}, 187 188 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 189 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 190 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 191 "powerpc64"}, 192 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 193 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 194 195 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 196 ArchSpec::eCore_s390x_generic, "s390x"}, 197 198 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 199 ArchSpec::eCore_sparc_generic, "sparc"}, 200 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 201 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 202 203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 204 "i386"}, 205 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 206 "i486"}, 207 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 208 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 209 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 210 "i686"}, 211 212 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 213 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 214 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 215 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 216 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 217 ArchSpec::eCore_hexagon_generic, "hexagon"}, 218 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 219 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 220 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 221 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 222 223 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32, 224 "riscv32"}, 225 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64, 226 "riscv64"}, 227 228 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32, 229 ArchSpec::eCore_loongarch32, "loongarch32"}, 230 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64, 231 ArchSpec::eCore_loongarch64, "loongarch64"}, 232 233 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 234 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 235 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 236 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 237 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 238 239 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 240 241 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 242 "wasm32"}, 243 }; 244 245 // Ensure that we have an entry in the g_core_definitions for each core. If you 246 // comment out an entry above, you will need to comment out the corresponding 247 // ArchSpec::Core enumeration. 248 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 249 ArchSpec::kNumCores, 250 "make sure we have one core definition for each core"); 251 252 struct ArchDefinitionEntry { 253 ArchSpec::Core core; 254 uint32_t cpu; 255 uint32_t sub; 256 uint32_t cpu_mask; 257 uint32_t sub_mask; 258 }; 259 260 struct ArchDefinition { 261 ArchitectureType type; 262 size_t num_entries; 263 const ArchDefinitionEntry *entries; 264 const char *name; 265 }; 266 267 void ArchSpec::ListSupportedArchNames(StringList &list) { 268 for (const auto &def : g_core_definitions) 269 list.AppendString(def.name); 270 } 271 272 void ArchSpec::AutoComplete(CompletionRequest &request) { 273 for (const auto &def : g_core_definitions) 274 request.TryCompleteCurrentArg(def.name); 275 } 276 277 #define CPU_ANY (UINT32_MAX) 278 279 //===----------------------------------------------------------------------===// 280 // A table that gets searched linearly for matches. This table is used to 281 // convert cpu type and subtypes to architecture names, and to convert 282 // architecture names to cpu types and subtypes. The ordering is important and 283 // allows the precedence to be set when the table is built. 284 #define SUBTYPE_MASK 0x00FFFFFFu 285 286 // clang-format off 287 static const ArchDefinitionEntry g_macho_arch_entries[] = { 288 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX}, 289 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 323 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX}, 324 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 325 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK}, 326 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK}, 327 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK}, 328 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK}, 329 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK}, 330 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK}, 331 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK}, 332 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK}, 333 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK}, 334 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK}, 335 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK}, 336 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK}, 337 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK}, 340 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK}, 341 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK}, 342 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK}, 343 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX}, 344 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK}, 345 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK}, 346 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK}, 347 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX}, 348 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 349 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 350 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}}; 351 // clang-format on 352 353 static const ArchDefinition g_macho_arch_def = {eArchTypeMachO, 354 std::size(g_macho_arch_entries), 355 g_macho_arch_entries, "mach-o"}; 356 357 //===----------------------------------------------------------------------===// 358 // A table that gets searched linearly for matches. This table is used to 359 // convert cpu type and subtypes to architecture names, and to convert 360 // architecture names to cpu types and subtypes. The ordering is important and 361 // allows the precedence to be set when the table is built. 362 static const ArchDefinitionEntry g_elf_arch_entries[] = { 363 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 364 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 365 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 366 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 367 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 368 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 369 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 370 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 371 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, 372 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 373 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, 374 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 375 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 376 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 377 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 378 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 379 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 380 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 381 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 382 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 383 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 384 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 385 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 386 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 387 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 388 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 389 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 390 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 391 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 392 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 393 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 394 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 395 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 396 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 397 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 398 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 399 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 400 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 401 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 402 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 403 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 404 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 405 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 406 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 407 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 408 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 409 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430 411 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 412 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 413 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 415 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 416 0xFFFFFFFFu}, // AVR 417 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, 418 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 419 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, 420 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 421 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, 422 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu, 423 0xFFFFFFFFu}, // loongarch32 424 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, 425 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu, 426 0xFFFFFFFFu}, // loongarch64 427 }; 428 429 static const ArchDefinition g_elf_arch_def = { 430 eArchTypeELF, 431 std::size(g_elf_arch_entries), 432 g_elf_arch_entries, 433 "elf", 434 }; 435 436 static const ArchDefinitionEntry g_coff_arch_entries[] = { 437 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 438 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 439 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 440 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 441 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 442 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 443 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 444 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 445 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 446 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 447 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 449 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 450 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 451 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 452 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 453 }; 454 455 static const ArchDefinition g_coff_arch_def = { 456 eArchTypeCOFF, 457 std::size(g_coff_arch_entries), 458 g_coff_arch_entries, 459 "pe-coff", 460 }; 461 462 //===----------------------------------------------------------------------===// 463 // Table of all ArchDefinitions 464 static const ArchDefinition *g_arch_definitions[] = { 465 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 466 467 //===----------------------------------------------------------------------===// 468 // Static helper functions. 469 470 // Get the architecture definition for a given object type. 471 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 472 for (const ArchDefinition *def : g_arch_definitions) { 473 if (def->type == arch_type) 474 return def; 475 } 476 return nullptr; 477 } 478 479 // Get an architecture definition by name. 480 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 481 for (const auto &def : g_core_definitions) { 482 if (name.equals_insensitive(def.name)) 483 return &def; 484 } 485 return nullptr; 486 } 487 488 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 489 if (core < std::size(g_core_definitions)) 490 return &g_core_definitions[core]; 491 return nullptr; 492 } 493 494 // Get a definition entry by cpu type and subtype. 495 static const ArchDefinitionEntry * 496 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 497 if (def == nullptr) 498 return nullptr; 499 500 const ArchDefinitionEntry *entries = def->entries; 501 for (size_t i = 0; i < def->num_entries; ++i) { 502 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 503 if (entries[i].sub == (sub & entries[i].sub_mask)) 504 return &entries[i]; 505 } 506 return nullptr; 507 } 508 509 static const ArchDefinitionEntry * 510 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 511 if (def == nullptr) 512 return nullptr; 513 514 const ArchDefinitionEntry *entries = def->entries; 515 for (size_t i = 0; i < def->num_entries; ++i) { 516 if (entries[i].core == core) 517 return &entries[i]; 518 } 519 return nullptr; 520 } 521 522 //===----------------------------------------------------------------------===// 523 // Constructors and destructors. 524 525 ArchSpec::ArchSpec() = default; 526 527 ArchSpec::ArchSpec(const char *triple_cstr) { 528 if (triple_cstr) 529 SetTriple(triple_cstr); 530 } 531 532 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 533 534 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 535 536 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 537 SetArchitecture(arch_type, cpu, subtype); 538 } 539 540 ArchSpec::~ArchSpec() = default; 541 542 void ArchSpec::Clear() { 543 m_triple = llvm::Triple(); 544 m_core = kCore_invalid; 545 m_byte_order = eByteOrderInvalid; 546 m_flags = 0; 547 } 548 549 //===----------------------------------------------------------------------===// 550 // Predicates. 551 552 const char *ArchSpec::GetArchitectureName() const { 553 const CoreDefinition *core_def = FindCoreDefinition(m_core); 554 if (core_def) 555 return core_def->name; 556 return "unknown"; 557 } 558 559 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 560 561 std::string ArchSpec::GetTargetABI() const { 562 563 std::string abi; 564 565 if (IsMIPS()) { 566 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 567 case ArchSpec::eMIPSABI_N64: 568 abi = "n64"; 569 return abi; 570 case ArchSpec::eMIPSABI_N32: 571 abi = "n32"; 572 return abi; 573 case ArchSpec::eMIPSABI_O32: 574 abi = "o32"; 575 return abi; 576 default: 577 return abi; 578 } 579 } 580 return abi; 581 } 582 583 void ArchSpec::SetFlags(const std::string &elf_abi) { 584 585 uint32_t flag = GetFlags(); 586 if (IsMIPS()) { 587 if (elf_abi == "n64") 588 flag |= ArchSpec::eMIPSABI_N64; 589 else if (elf_abi == "n32") 590 flag |= ArchSpec::eMIPSABI_N32; 591 else if (elf_abi == "o32") 592 flag |= ArchSpec::eMIPSABI_O32; 593 } 594 SetFlags(flag); 595 } 596 597 std::string ArchSpec::GetClangTargetCPU() const { 598 std::string cpu; 599 if (IsMIPS()) { 600 switch (m_core) { 601 case ArchSpec::eCore_mips32: 602 case ArchSpec::eCore_mips32el: 603 cpu = "mips32"; 604 break; 605 case ArchSpec::eCore_mips32r2: 606 case ArchSpec::eCore_mips32r2el: 607 cpu = "mips32r2"; 608 break; 609 case ArchSpec::eCore_mips32r3: 610 case ArchSpec::eCore_mips32r3el: 611 cpu = "mips32r3"; 612 break; 613 case ArchSpec::eCore_mips32r5: 614 case ArchSpec::eCore_mips32r5el: 615 cpu = "mips32r5"; 616 break; 617 case ArchSpec::eCore_mips32r6: 618 case ArchSpec::eCore_mips32r6el: 619 cpu = "mips32r6"; 620 break; 621 case ArchSpec::eCore_mips64: 622 case ArchSpec::eCore_mips64el: 623 cpu = "mips64"; 624 break; 625 case ArchSpec::eCore_mips64r2: 626 case ArchSpec::eCore_mips64r2el: 627 cpu = "mips64r2"; 628 break; 629 case ArchSpec::eCore_mips64r3: 630 case ArchSpec::eCore_mips64r3el: 631 cpu = "mips64r3"; 632 break; 633 case ArchSpec::eCore_mips64r5: 634 case ArchSpec::eCore_mips64r5el: 635 cpu = "mips64r5"; 636 break; 637 case ArchSpec::eCore_mips64r6: 638 case ArchSpec::eCore_mips64r6el: 639 cpu = "mips64r6"; 640 break; 641 default: 642 break; 643 } 644 } 645 646 if (GetTriple().isARM()) 647 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str(); 648 return cpu; 649 } 650 651 uint32_t ArchSpec::GetMachOCPUType() const { 652 const CoreDefinition *core_def = FindCoreDefinition(m_core); 653 if (core_def) { 654 const ArchDefinitionEntry *arch_def = 655 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 656 if (arch_def) { 657 return arch_def->cpu; 658 } 659 } 660 return LLDB_INVALID_CPUTYPE; 661 } 662 663 uint32_t ArchSpec::GetMachOCPUSubType() const { 664 const CoreDefinition *core_def = FindCoreDefinition(m_core); 665 if (core_def) { 666 const ArchDefinitionEntry *arch_def = 667 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 668 if (arch_def) { 669 return arch_def->sub; 670 } 671 } 672 return LLDB_INVALID_CPUTYPE; 673 } 674 675 uint32_t ArchSpec::GetDataByteSize() const { 676 return 1; 677 } 678 679 uint32_t ArchSpec::GetCodeByteSize() const { 680 return 1; 681 } 682 683 llvm::Triple::ArchType ArchSpec::GetMachine() const { 684 const CoreDefinition *core_def = FindCoreDefinition(m_core); 685 if (core_def) 686 return core_def->machine; 687 688 return llvm::Triple::UnknownArch; 689 } 690 691 uint32_t ArchSpec::GetAddressByteSize() const { 692 const CoreDefinition *core_def = FindCoreDefinition(m_core); 693 if (core_def) { 694 if (core_def->machine == llvm::Triple::mips64 || 695 core_def->machine == llvm::Triple::mips64el) { 696 // For N32/O32 applications Address size is 4 bytes. 697 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 698 return 4; 699 } 700 return core_def->addr_byte_size; 701 } 702 return 0; 703 } 704 705 ByteOrder ArchSpec::GetDefaultEndian() const { 706 const CoreDefinition *core_def = FindCoreDefinition(m_core); 707 if (core_def) 708 return core_def->default_byte_order; 709 return eByteOrderInvalid; 710 } 711 712 bool ArchSpec::CharIsSignedByDefault() const { 713 switch (m_triple.getArch()) { 714 default: 715 return true; 716 717 case llvm::Triple::aarch64: 718 case llvm::Triple::aarch64_32: 719 case llvm::Triple::aarch64_be: 720 case llvm::Triple::arm: 721 case llvm::Triple::armeb: 722 case llvm::Triple::thumb: 723 case llvm::Triple::thumbeb: 724 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 725 726 case llvm::Triple::ppc: 727 case llvm::Triple::ppc64: 728 return m_triple.isOSDarwin(); 729 730 case llvm::Triple::ppc64le: 731 case llvm::Triple::systemz: 732 case llvm::Triple::xcore: 733 case llvm::Triple::arc: 734 return false; 735 } 736 } 737 738 lldb::ByteOrder ArchSpec::GetByteOrder() const { 739 if (m_byte_order == eByteOrderInvalid) 740 return GetDefaultEndian(); 741 return m_byte_order; 742 } 743 744 //===----------------------------------------------------------------------===// 745 // Mutators. 746 747 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 748 m_triple = triple; 749 UpdateCore(); 750 return IsValid(); 751 } 752 753 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 754 ArchSpec &arch) { 755 // Accept "12-10" or "12.10" as cpu type/subtype 756 if (triple_str.empty()) 757 return false; 758 759 size_t pos = triple_str.find_first_of("-."); 760 if (pos == llvm::StringRef::npos) 761 return false; 762 763 llvm::StringRef cpu_str = triple_str.substr(0, pos); 764 llvm::StringRef remainder = triple_str.substr(pos + 1); 765 if (cpu_str.empty() || remainder.empty()) 766 return false; 767 768 llvm::StringRef sub_str; 769 llvm::StringRef vendor; 770 llvm::StringRef os; 771 std::tie(sub_str, remainder) = remainder.split('-'); 772 std::tie(vendor, os) = remainder.split('-'); 773 774 uint32_t cpu = 0; 775 uint32_t sub = 0; 776 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 777 return false; 778 779 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 780 return false; 781 if (!vendor.empty() && !os.empty()) { 782 arch.GetTriple().setVendorName(vendor); 783 arch.GetTriple().setOSName(os); 784 } 785 786 return true; 787 } 788 789 bool ArchSpec::SetTriple(llvm::StringRef triple) { 790 if (triple.empty()) { 791 Clear(); 792 return false; 793 } 794 795 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 796 return true; 797 798 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 799 return IsValid(); 800 } 801 802 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 803 return !normalized_triple.getArchName().empty() && 804 normalized_triple.getOSName().empty() && 805 normalized_triple.getVendorName().empty() && 806 normalized_triple.getEnvironmentName().empty(); 807 } 808 809 void ArchSpec::MergeFrom(const ArchSpec &other) { 810 // ios-macabi always wins over macosx. 811 if ((GetTriple().getOS() == llvm::Triple::MacOSX || 812 GetTriple().getOS() == llvm::Triple::UnknownOS) && 813 other.GetTriple().getOS() == llvm::Triple::IOS && 814 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) { 815 (*this) = other; 816 return; 817 } 818 819 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 820 GetTriple().setVendor(other.GetTriple().getVendor()); 821 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 822 GetTriple().setOS(other.GetTriple().getOS()); 823 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 824 GetTriple().setArch(other.GetTriple().getArch()); 825 826 // MachO unknown64 isn't really invalid as the debugger can still obtain 827 // information from the binary, e.g. line tables. As such, we don't update 828 // the core here. 829 if (other.GetCore() != eCore_uknownMach64) 830 UpdateCore(); 831 } 832 if (!TripleEnvironmentWasSpecified() && 833 other.TripleEnvironmentWasSpecified()) { 834 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 835 } 836 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 837 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 838 // adopt the specific arm core. 839 if (GetTriple().getArch() == llvm::Triple::arm && 840 other.GetTriple().getArch() == llvm::Triple::arm && 841 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 842 other.GetCore() != ArchSpec::eCore_arm_generic) { 843 m_core = other.GetCore(); 844 CoreUpdated(false); 845 } 846 if (GetFlags() == 0) { 847 SetFlags(other.GetFlags()); 848 } 849 } 850 851 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 852 uint32_t sub, uint32_t os) { 853 m_core = kCore_invalid; 854 bool update_triple = true; 855 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 856 if (arch_def) { 857 const ArchDefinitionEntry *arch_def_entry = 858 FindArchDefinitionEntry(arch_def, cpu, sub); 859 if (arch_def_entry) { 860 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 861 if (core_def) { 862 m_core = core_def->core; 863 update_triple = false; 864 // Always use the architecture name because it might be more 865 // descriptive than the architecture enum ("armv7" -> 866 // llvm::Triple::arm). 867 m_triple.setArchName(llvm::StringRef(core_def->name)); 868 if (arch_type == eArchTypeMachO) { 869 m_triple.setVendor(llvm::Triple::Apple); 870 871 // Don't set the OS. It could be simulator, macosx, ios, watchos, 872 // tvos, bridgeos. We could get close with the cpu type - but we 873 // can't get it right all of the time. Better to leave this unset 874 // so other sections of code will set it when they have more 875 // information. NB: don't call m_triple.setOS 876 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 877 // the ArchSpec::TripleVendorWasSpecified() method says that any 878 // OSName setting means it was specified. 879 } else if (arch_type == eArchTypeELF) { 880 switch (os) { 881 case llvm::ELF::ELFOSABI_AIX: 882 m_triple.setOS(llvm::Triple::OSType::AIX); 883 break; 884 case llvm::ELF::ELFOSABI_FREEBSD: 885 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 886 break; 887 case llvm::ELF::ELFOSABI_GNU: 888 m_triple.setOS(llvm::Triple::OSType::Linux); 889 break; 890 case llvm::ELF::ELFOSABI_NETBSD: 891 m_triple.setOS(llvm::Triple::OSType::NetBSD); 892 break; 893 case llvm::ELF::ELFOSABI_OPENBSD: 894 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 895 break; 896 case llvm::ELF::ELFOSABI_SOLARIS: 897 m_triple.setOS(llvm::Triple::OSType::Solaris); 898 break; 899 case llvm::ELF::ELFOSABI_STANDALONE: 900 m_triple.setOS(llvm::Triple::OSType::UnknownOS); 901 break; 902 } 903 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 904 m_triple.setVendor(llvm::Triple::PC); 905 m_triple.setOS(llvm::Triple::Win32); 906 } else { 907 m_triple.setVendor(llvm::Triple::UnknownVendor); 908 m_triple.setOS(llvm::Triple::UnknownOS); 909 } 910 // Fall back onto setting the machine type if the arch by name 911 // failed... 912 if (m_triple.getArch() == llvm::Triple::UnknownArch) 913 m_triple.setArch(core_def->machine); 914 } 915 } else { 916 Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform)); 917 LLDB_LOGF(log, 918 "Unable to find a core definition for cpu 0x%" PRIx32 919 " sub %" PRId32, 920 cpu, sub); 921 } 922 } 923 CoreUpdated(update_triple); 924 return IsValid(); 925 } 926 927 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 928 const CoreDefinition *core_def = FindCoreDefinition(m_core); 929 if (core_def) 930 return core_def->min_opcode_byte_size; 931 return 0; 932 } 933 934 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 935 const CoreDefinition *core_def = FindCoreDefinition(m_core); 936 if (core_def) 937 return core_def->max_opcode_byte_size; 938 return 0; 939 } 940 941 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 942 llvm::Triple::EnvironmentType rhs) { 943 if (lhs == rhs) 944 return true; 945 946 // Apple simulators are a different platform than what they simulate. 947 // As the environments are different at this point, if one of them is a 948 // simulator, then they are different. 949 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator) 950 return false; 951 952 // If any of the environment is unknown then they are compatible 953 if (lhs == llvm::Triple::UnknownEnvironment || 954 rhs == llvm::Triple::UnknownEnvironment) 955 return true; 956 957 // If one of the environment is Android and the other one is EABI then they 958 // are considered to be compatible. This is required as a workaround for 959 // shared libraries compiled for Android without the NOTE section indicating 960 // that they are using the Android ABI. 961 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 962 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 963 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 964 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 965 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 966 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 967 return true; 968 969 return false; 970 } 971 972 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const { 973 if (GetByteOrder() != rhs.GetByteOrder() || 974 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch)) 975 return false; 976 977 const llvm::Triple &lhs_triple = GetTriple(); 978 const llvm::Triple &rhs_triple = rhs.GetTriple(); 979 980 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 981 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 982 983 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 984 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 985 986 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows(); 987 988 // On Windows, the vendor field doesn't have any practical effect, but 989 // it is often set to either "pc" or "w64". 990 if ((lhs_triple_vendor != rhs_triple_vendor) && 991 (match == ExactMatch || !both_windows)) { 992 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 993 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 994 // Both architectures had the vendor specified, so if they aren't equal 995 // then we return false 996 if (rhs_vendor_specified && lhs_vendor_specified) 997 return false; 998 999 // Only fail if both vendor types are not unknown 1000 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1001 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1002 return false; 1003 } 1004 1005 const llvm::Triple::EnvironmentType lhs_triple_env = 1006 lhs_triple.getEnvironment(); 1007 const llvm::Triple::EnvironmentType rhs_triple_env = 1008 rhs_triple.getEnvironment(); 1009 1010 if (match == CompatibleMatch) { 1011 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match. 1012 if ((lhs_triple_os == llvm::Triple::IOS && 1013 lhs_triple_env == llvm::Triple::MacABI && 1014 rhs_triple_os == llvm::Triple::MacOSX) || 1015 (lhs_triple_os == llvm::Triple::MacOSX && 1016 rhs_triple_os == llvm::Triple::IOS && 1017 rhs_triple_env == llvm::Triple::MacABI)) 1018 return true; 1019 } 1020 1021 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible. 1022 if (lhs_triple_os == llvm::Triple::IOS && 1023 rhs_triple_os == llvm::Triple::IOS && 1024 (lhs_triple_env == llvm::Triple::MacABI || 1025 rhs_triple_env == llvm::Triple::MacABI) && 1026 lhs_triple_env != rhs_triple_env) 1027 return false; 1028 1029 if (lhs_triple_os != rhs_triple_os) { 1030 const bool lhs_os_specified = TripleOSWasSpecified(); 1031 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1032 // If both OS types are specified and different, fail. 1033 if (lhs_os_specified && rhs_os_specified) 1034 return false; 1035 1036 // If the pair of os+env is both unspecified, match any other os+env combo. 1037 if (match == CompatibleMatch && 1038 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) || 1039 (!rhs_os_specified && !rhs_triple.hasEnvironment()))) 1040 return true; 1041 } 1042 1043 if (match == CompatibleMatch && both_windows) 1044 return true; // The Windows environments (MSVC vs GNU) are compatible 1045 1046 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1047 } 1048 1049 void ArchSpec::UpdateCore() { 1050 llvm::StringRef arch_name(m_triple.getArchName()); 1051 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1052 if (core_def) { 1053 m_core = core_def->core; 1054 // Set the byte order to the default byte order for an architecture. This 1055 // can be modified if needed for cases when cores handle both big and 1056 // little endian 1057 m_byte_order = core_def->default_byte_order; 1058 } else { 1059 Clear(); 1060 } 1061 } 1062 1063 //===----------------------------------------------------------------------===// 1064 // Helper methods. 1065 1066 void ArchSpec::CoreUpdated(bool update_triple) { 1067 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1068 if (core_def) { 1069 if (update_triple) 1070 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1071 m_byte_order = core_def->default_byte_order; 1072 } else { 1073 if (update_triple) 1074 m_triple = llvm::Triple(); 1075 m_byte_order = eByteOrderInvalid; 1076 } 1077 } 1078 1079 //===----------------------------------------------------------------------===// 1080 // Operators. 1081 1082 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1083 bool try_inverse, bool enforce_exact_match) { 1084 if (core1 == core2) 1085 return true; 1086 1087 switch (core1) { 1088 case ArchSpec::kCore_any: 1089 return true; 1090 1091 case ArchSpec::eCore_arm_generic: 1092 if (enforce_exact_match) 1093 break; 1094 [[fallthrough]]; 1095 case ArchSpec::kCore_arm_any: 1096 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1097 return true; 1098 if (core2 >= ArchSpec::kCore_thumb_first && 1099 core2 <= ArchSpec::kCore_thumb_last) 1100 return true; 1101 if (core2 == ArchSpec::kCore_arm_any) 1102 return true; 1103 break; 1104 1105 case ArchSpec::kCore_x86_32_any: 1106 if ((core2 >= ArchSpec::kCore_x86_32_first && 1107 core2 <= ArchSpec::kCore_x86_32_last) || 1108 (core2 == ArchSpec::kCore_x86_32_any)) 1109 return true; 1110 break; 1111 1112 case ArchSpec::kCore_x86_64_any: 1113 if ((core2 >= ArchSpec::kCore_x86_64_first && 1114 core2 <= ArchSpec::kCore_x86_64_last) || 1115 (core2 == ArchSpec::kCore_x86_64_any)) 1116 return true; 1117 break; 1118 1119 case ArchSpec::kCore_ppc_any: 1120 if ((core2 >= ArchSpec::kCore_ppc_first && 1121 core2 <= ArchSpec::kCore_ppc_last) || 1122 (core2 == ArchSpec::kCore_ppc_any)) 1123 return true; 1124 break; 1125 1126 case ArchSpec::kCore_ppc64_any: 1127 if ((core2 >= ArchSpec::kCore_ppc64_first && 1128 core2 <= ArchSpec::kCore_ppc64_last) || 1129 (core2 == ArchSpec::kCore_ppc64_any)) 1130 return true; 1131 break; 1132 1133 case ArchSpec::kCore_hexagon_any: 1134 if ((core2 >= ArchSpec::kCore_hexagon_first && 1135 core2 <= ArchSpec::kCore_hexagon_last) || 1136 (core2 == ArchSpec::kCore_hexagon_any)) 1137 return true; 1138 break; 1139 1140 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1141 // Cortex-M0 - ARMv6-M - armv6m 1142 // Cortex-M3 - ARMv7-M - armv7m 1143 // Cortex-M4 - ARMv7E-M - armv7em 1144 case ArchSpec::eCore_arm_armv7em: 1145 if (!enforce_exact_match) { 1146 if (core2 == ArchSpec::eCore_arm_generic) 1147 return true; 1148 if (core2 == ArchSpec::eCore_arm_armv7m) 1149 return true; 1150 if (core2 == ArchSpec::eCore_arm_armv6m) 1151 return true; 1152 if (core2 == ArchSpec::eCore_arm_armv7) 1153 return true; 1154 try_inverse = true; 1155 } 1156 break; 1157 1158 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1159 // Cortex-M0 - ARMv6-M - armv6m 1160 // Cortex-M3 - ARMv7-M - armv7m 1161 // Cortex-M4 - ARMv7E-M - armv7em 1162 case ArchSpec::eCore_arm_armv7m: 1163 if (!enforce_exact_match) { 1164 if (core2 == ArchSpec::eCore_arm_generic) 1165 return true; 1166 if (core2 == ArchSpec::eCore_arm_armv6m) 1167 return true; 1168 if (core2 == ArchSpec::eCore_arm_armv7) 1169 return true; 1170 if (core2 == ArchSpec::eCore_arm_armv7em) 1171 return true; 1172 try_inverse = true; 1173 } 1174 break; 1175 1176 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1177 // Cortex-M0 - ARMv6-M - armv6m 1178 // Cortex-M3 - ARMv7-M - armv7m 1179 // Cortex-M4 - ARMv7E-M - armv7em 1180 case ArchSpec::eCore_arm_armv6m: 1181 if (!enforce_exact_match) { 1182 if (core2 == ArchSpec::eCore_arm_generic) 1183 return true; 1184 if (core2 == ArchSpec::eCore_arm_armv7em) 1185 return true; 1186 if (core2 == ArchSpec::eCore_arm_armv7) 1187 return true; 1188 if (core2 == ArchSpec::eCore_arm_armv6m) 1189 return true; 1190 try_inverse = false; 1191 } 1192 break; 1193 1194 case ArchSpec::eCore_arm_armv7f: 1195 case ArchSpec::eCore_arm_armv7k: 1196 case ArchSpec::eCore_arm_armv7s: 1197 case ArchSpec::eCore_arm_armv7l: 1198 case ArchSpec::eCore_arm_armv8l: 1199 if (!enforce_exact_match) { 1200 if (core2 == ArchSpec::eCore_arm_generic) 1201 return true; 1202 if (core2 == ArchSpec::eCore_arm_armv7) 1203 return true; 1204 try_inverse = false; 1205 } 1206 break; 1207 1208 case ArchSpec::eCore_x86_64_x86_64h: 1209 if (!enforce_exact_match) { 1210 try_inverse = false; 1211 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1212 return true; 1213 } 1214 break; 1215 1216 case ArchSpec::eCore_arm_armv8: 1217 if (!enforce_exact_match) { 1218 if (core2 == ArchSpec::eCore_arm_arm64) 1219 return true; 1220 if (core2 == ArchSpec::eCore_arm_aarch64) 1221 return true; 1222 if (core2 == ArchSpec::eCore_arm_arm64e) 1223 return true; 1224 try_inverse = false; 1225 } 1226 break; 1227 1228 case ArchSpec::eCore_arm_arm64e: 1229 if (!enforce_exact_match) { 1230 if (core2 == ArchSpec::eCore_arm_arm64) 1231 return true; 1232 if (core2 == ArchSpec::eCore_arm_aarch64) 1233 return true; 1234 if (core2 == ArchSpec::eCore_arm_armv8) 1235 return true; 1236 try_inverse = false; 1237 } 1238 break; 1239 case ArchSpec::eCore_arm_aarch64: 1240 if (!enforce_exact_match) { 1241 if (core2 == ArchSpec::eCore_arm_arm64) 1242 return true; 1243 if (core2 == ArchSpec::eCore_arm_armv8) 1244 return true; 1245 if (core2 == ArchSpec::eCore_arm_arm64e) 1246 return true; 1247 try_inverse = false; 1248 } 1249 break; 1250 1251 case ArchSpec::eCore_arm_arm64: 1252 if (!enforce_exact_match) { 1253 if (core2 == ArchSpec::eCore_arm_aarch64) 1254 return true; 1255 if (core2 == ArchSpec::eCore_arm_armv8) 1256 return true; 1257 if (core2 == ArchSpec::eCore_arm_arm64e) 1258 return true; 1259 try_inverse = false; 1260 } 1261 break; 1262 1263 case ArchSpec::eCore_arm_arm64_32: 1264 if (!enforce_exact_match) { 1265 if (core2 == ArchSpec::eCore_arm_generic) 1266 return true; 1267 try_inverse = false; 1268 } 1269 break; 1270 1271 case ArchSpec::eCore_mips32: 1272 if (!enforce_exact_match) { 1273 if (core2 >= ArchSpec::kCore_mips32_first && 1274 core2 <= ArchSpec::kCore_mips32_last) 1275 return true; 1276 try_inverse = false; 1277 } 1278 break; 1279 1280 case ArchSpec::eCore_mips32el: 1281 if (!enforce_exact_match) { 1282 if (core2 >= ArchSpec::kCore_mips32el_first && 1283 core2 <= ArchSpec::kCore_mips32el_last) 1284 return true; 1285 try_inverse = true; 1286 } 1287 break; 1288 1289 case ArchSpec::eCore_mips64: 1290 if (!enforce_exact_match) { 1291 if (core2 >= ArchSpec::kCore_mips32_first && 1292 core2 <= ArchSpec::kCore_mips32_last) 1293 return true; 1294 if (core2 >= ArchSpec::kCore_mips64_first && 1295 core2 <= ArchSpec::kCore_mips64_last) 1296 return true; 1297 try_inverse = false; 1298 } 1299 break; 1300 1301 case ArchSpec::eCore_mips64el: 1302 if (!enforce_exact_match) { 1303 if (core2 >= ArchSpec::kCore_mips32el_first && 1304 core2 <= ArchSpec::kCore_mips32el_last) 1305 return true; 1306 if (core2 >= ArchSpec::kCore_mips64el_first && 1307 core2 <= ArchSpec::kCore_mips64el_last) 1308 return true; 1309 try_inverse = false; 1310 } 1311 break; 1312 1313 case ArchSpec::eCore_mips64r2: 1314 case ArchSpec::eCore_mips64r3: 1315 case ArchSpec::eCore_mips64r5: 1316 if (!enforce_exact_match) { 1317 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1318 return true; 1319 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1320 return true; 1321 try_inverse = false; 1322 } 1323 break; 1324 1325 case ArchSpec::eCore_mips64r2el: 1326 case ArchSpec::eCore_mips64r3el: 1327 case ArchSpec::eCore_mips64r5el: 1328 if (!enforce_exact_match) { 1329 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1330 return true; 1331 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1332 return true; 1333 try_inverse = false; 1334 } 1335 break; 1336 1337 case ArchSpec::eCore_mips32r2: 1338 case ArchSpec::eCore_mips32r3: 1339 case ArchSpec::eCore_mips32r5: 1340 if (!enforce_exact_match) { 1341 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1342 return true; 1343 } 1344 break; 1345 1346 case ArchSpec::eCore_mips32r2el: 1347 case ArchSpec::eCore_mips32r3el: 1348 case ArchSpec::eCore_mips32r5el: 1349 if (!enforce_exact_match) { 1350 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1351 return true; 1352 } 1353 break; 1354 1355 case ArchSpec::eCore_mips32r6: 1356 if (!enforce_exact_match) { 1357 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1358 return true; 1359 } 1360 break; 1361 1362 case ArchSpec::eCore_mips32r6el: 1363 if (!enforce_exact_match) { 1364 if (core2 == ArchSpec::eCore_mips32el || 1365 core2 == ArchSpec::eCore_mips32r6el) 1366 return true; 1367 } 1368 break; 1369 1370 case ArchSpec::eCore_mips64r6: 1371 if (!enforce_exact_match) { 1372 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1373 return true; 1374 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1375 return true; 1376 } 1377 break; 1378 1379 case ArchSpec::eCore_mips64r6el: 1380 if (!enforce_exact_match) { 1381 if (core2 == ArchSpec::eCore_mips32el || 1382 core2 == ArchSpec::eCore_mips32r6el) 1383 return true; 1384 if (core2 == ArchSpec::eCore_mips64el || 1385 core2 == ArchSpec::eCore_mips64r6el) 1386 return true; 1387 } 1388 break; 1389 1390 default: 1391 break; 1392 } 1393 if (try_inverse) 1394 return cores_match(core2, core1, false, enforce_exact_match); 1395 return false; 1396 } 1397 1398 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1399 const ArchSpec::Core lhs_core = lhs.GetCore(); 1400 const ArchSpec::Core rhs_core = rhs.GetCore(); 1401 return lhs_core < rhs_core; 1402 } 1403 1404 1405 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1406 return lhs.GetCore() == rhs.GetCore(); 1407 } 1408 1409 bool ArchSpec::IsFullySpecifiedTriple() const { 1410 if (!TripleOSWasSpecified()) 1411 return false; 1412 1413 if (!TripleVendorWasSpecified()) 1414 return false; 1415 1416 const unsigned unspecified = 0; 1417 const llvm::Triple &triple = GetTriple(); 1418 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified) 1419 return false; 1420 1421 return true; 1422 } 1423 1424 void ArchSpec::PiecewiseTripleCompare( 1425 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1426 bool &os_different, bool &os_version_different, bool &env_different) const { 1427 const llvm::Triple &me(GetTriple()); 1428 const llvm::Triple &them(other.GetTriple()); 1429 1430 arch_different = (me.getArch() != them.getArch()); 1431 1432 vendor_different = (me.getVendor() != them.getVendor()); 1433 1434 os_different = (me.getOS() != them.getOS()); 1435 1436 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1437 1438 env_different = (me.getEnvironment() != them.getEnvironment()); 1439 } 1440 1441 bool ArchSpec::IsAlwaysThumbInstructions() const { 1442 std::string Status; 1443 if (GetTriple().getArch() == llvm::Triple::arm || 1444 GetTriple().getArch() == llvm::Triple::thumb) { 1445 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1446 // 1447 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1448 // execute thumb instructions. We map the cores to arch names like this: 1449 // 1450 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1451 // Cortex-M7: armv7em 1452 1453 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1454 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1455 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1456 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1457 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1458 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1459 return true; 1460 } 1461 // Windows on ARM is always thumb. 1462 if (GetTriple().isOSWindows()) 1463 return true; 1464 } 1465 return false; 1466 } 1467 1468 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1469 const llvm::Triple &triple = GetTriple(); 1470 llvm::StringRef arch_str = triple.getArchName(); 1471 llvm::StringRef vendor_str = triple.getVendorName(); 1472 llvm::StringRef os_str = triple.getOSName(); 1473 llvm::StringRef environ_str = triple.getEnvironmentName(); 1474 1475 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1476 vendor_str.empty() ? "*" : vendor_str, 1477 os_str.empty() ? "*" : os_str); 1478 1479 if (!environ_str.empty()) 1480 s << "-" << environ_str; 1481 } 1482