1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 209 ArchSpec::eCore_hexagon_generic, "hexagon"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 214 215 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 216 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 217 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 220 221 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 222 223 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 224 "wasm32"}, 225 }; 226 227 // Ensure that we have an entry in the g_core_definitions for each core. If you 228 // comment out an entry above, you will need to comment out the corresponding 229 // ArchSpec::Core enumeration. 230 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 231 ArchSpec::kNumCores, 232 "make sure we have one core definition for each core"); 233 234 struct ArchDefinitionEntry { 235 ArchSpec::Core core; 236 uint32_t cpu; 237 uint32_t sub; 238 uint32_t cpu_mask; 239 uint32_t sub_mask; 240 }; 241 242 struct ArchDefinition { 243 ArchitectureType type; 244 size_t num_entries; 245 const ArchDefinitionEntry *entries; 246 const char *name; 247 }; 248 249 void ArchSpec::ListSupportedArchNames(StringList &list) { 250 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 251 list.AppendString(g_core_definitions[i].name); 252 } 253 254 void ArchSpec::AutoComplete(CompletionRequest &request) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 256 request.TryCompleteCurrentArg(g_core_definitions[i].name); 257 } 258 259 #define CPU_ANY (UINT32_MAX) 260 261 //===----------------------------------------------------------------------===// 262 // A table that gets searched linearly for matches. This table is used to 263 // convert cpu type and subtypes to architecture names, and to convert 264 // architecture names to cpu types and subtypes. The ordering is important and 265 // allows the precedence to be set when the table is built. 266 #define SUBTYPE_MASK 0x00FFFFFFu 267 268 static const ArchDefinitionEntry g_macho_arch_entries[] = { 269 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 270 UINT32_MAX, UINT32_MAX}, 271 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 272 SUBTYPE_MASK}, 273 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 308 UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 312 UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 314 SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 338 UINT32_MAX, UINT32_MAX}, 339 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 340 SUBTYPE_MASK}, 341 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 364 SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 366 UINT32_MAX, SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 370 UINT32_MAX, SUBTYPE_MASK}, 371 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 372 SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 374 SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 376 UINT32_MAX, SUBTYPE_MASK}, 377 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 378 UINT32_MAX, UINT32_MAX}, 379 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 380 SUBTYPE_MASK}, 381 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 382 SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 384 UINT32_MAX, SUBTYPE_MASK}, 385 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 386 UINT32_MAX, UINT32_MAX}, 387 // Catch any unknown mach architectures so we can always use the object and 388 // symbol mach-o files 389 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 390 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 391 0x00000000u}}; 392 393 static const ArchDefinition g_macho_arch_def = { 394 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 395 g_macho_arch_entries, "mach-o"}; 396 397 //===----------------------------------------------------------------------===// 398 // A table that gets searched linearly for matches. This table is used to 399 // convert cpu type and subtypes to architecture names, and to convert 400 // architecture names to cpu types and subtypes. The ordering is important and 401 // allows the precedence to be set when the table is built. 402 static const ArchDefinitionEntry g_elf_arch_entries[] = { 403 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 404 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 405 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 407 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 409 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 411 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 413 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 415 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 417 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 419 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 420 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 421 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 422 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 423 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 424 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 425 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 426 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 427 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 428 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 429 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 431 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 433 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 435 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 437 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 438 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 439 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 440 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 441 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 443 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 445 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 447 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 448 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 449 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 450 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 451 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 452 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 453 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 454 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR 455 }; 456 457 static const ArchDefinition g_elf_arch_def = { 458 eArchTypeELF, 459 llvm::array_lengthof(g_elf_arch_entries), 460 g_elf_arch_entries, 461 "elf", 462 }; 463 464 static const ArchDefinitionEntry g_coff_arch_entries[] = { 465 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 466 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 467 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 469 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 471 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 473 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 475 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 477 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 478 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 479 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 480 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 481 }; 482 483 static const ArchDefinition g_coff_arch_def = { 484 eArchTypeCOFF, 485 llvm::array_lengthof(g_coff_arch_entries), 486 g_coff_arch_entries, 487 "pe-coff", 488 }; 489 490 //===----------------------------------------------------------------------===// 491 // Table of all ArchDefinitions 492 static const ArchDefinition *g_arch_definitions[] = { 493 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 494 495 static const size_t k_num_arch_definitions = 496 llvm::array_lengthof(g_arch_definitions); 497 498 //===----------------------------------------------------------------------===// 499 // Static helper functions. 500 501 // Get the architecture definition for a given object type. 502 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 503 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 504 const ArchDefinition *def = g_arch_definitions[i]; 505 if (def->type == arch_type) 506 return def; 507 } 508 return nullptr; 509 } 510 511 // Get an architecture definition by name. 512 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 513 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 514 if (name.equals_lower(g_core_definitions[i].name)) 515 return &g_core_definitions[i]; 516 } 517 return nullptr; 518 } 519 520 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 521 if (core < llvm::array_lengthof(g_core_definitions)) 522 return &g_core_definitions[core]; 523 return nullptr; 524 } 525 526 // Get a definition entry by cpu type and subtype. 527 static const ArchDefinitionEntry * 528 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 529 if (def == nullptr) 530 return nullptr; 531 532 const ArchDefinitionEntry *entries = def->entries; 533 for (size_t i = 0; i < def->num_entries; ++i) { 534 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 535 if (entries[i].sub == (sub & entries[i].sub_mask)) 536 return &entries[i]; 537 } 538 return nullptr; 539 } 540 541 static const ArchDefinitionEntry * 542 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 543 if (def == nullptr) 544 return nullptr; 545 546 const ArchDefinitionEntry *entries = def->entries; 547 for (size_t i = 0; i < def->num_entries; ++i) { 548 if (entries[i].core == core) 549 return &entries[i]; 550 } 551 return nullptr; 552 } 553 554 //===----------------------------------------------------------------------===// 555 // Constructors and destructors. 556 557 ArchSpec::ArchSpec() {} 558 559 ArchSpec::ArchSpec(const char *triple_cstr) { 560 if (triple_cstr) 561 SetTriple(triple_cstr); 562 } 563 564 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 565 566 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 567 568 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 569 SetArchitecture(arch_type, cpu, subtype); 570 } 571 572 ArchSpec::~ArchSpec() = default; 573 574 void ArchSpec::Clear() { 575 m_triple = llvm::Triple(); 576 m_core = kCore_invalid; 577 m_byte_order = eByteOrderInvalid; 578 m_distribution_id.Clear(); 579 m_flags = 0; 580 } 581 582 //===----------------------------------------------------------------------===// 583 // Predicates. 584 585 const char *ArchSpec::GetArchitectureName() const { 586 const CoreDefinition *core_def = FindCoreDefinition(m_core); 587 if (core_def) 588 return core_def->name; 589 return "unknown"; 590 } 591 592 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 593 594 std::string ArchSpec::GetTargetABI() const { 595 596 std::string abi; 597 598 if (IsMIPS()) { 599 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 600 case ArchSpec::eMIPSABI_N64: 601 abi = "n64"; 602 return abi; 603 case ArchSpec::eMIPSABI_N32: 604 abi = "n32"; 605 return abi; 606 case ArchSpec::eMIPSABI_O32: 607 abi = "o32"; 608 return abi; 609 default: 610 return abi; 611 } 612 } 613 return abi; 614 } 615 616 void ArchSpec::SetFlags(std::string elf_abi) { 617 618 uint32_t flag = GetFlags(); 619 if (IsMIPS()) { 620 if (elf_abi == "n64") 621 flag |= ArchSpec::eMIPSABI_N64; 622 else if (elf_abi == "n32") 623 flag |= ArchSpec::eMIPSABI_N32; 624 else if (elf_abi == "o32") 625 flag |= ArchSpec::eMIPSABI_O32; 626 } 627 SetFlags(flag); 628 } 629 630 std::string ArchSpec::GetClangTargetCPU() const { 631 std::string cpu; 632 633 if (IsMIPS()) { 634 switch (m_core) { 635 case ArchSpec::eCore_mips32: 636 case ArchSpec::eCore_mips32el: 637 cpu = "mips32"; 638 break; 639 case ArchSpec::eCore_mips32r2: 640 case ArchSpec::eCore_mips32r2el: 641 cpu = "mips32r2"; 642 break; 643 case ArchSpec::eCore_mips32r3: 644 case ArchSpec::eCore_mips32r3el: 645 cpu = "mips32r3"; 646 break; 647 case ArchSpec::eCore_mips32r5: 648 case ArchSpec::eCore_mips32r5el: 649 cpu = "mips32r5"; 650 break; 651 case ArchSpec::eCore_mips32r6: 652 case ArchSpec::eCore_mips32r6el: 653 cpu = "mips32r6"; 654 break; 655 case ArchSpec::eCore_mips64: 656 case ArchSpec::eCore_mips64el: 657 cpu = "mips64"; 658 break; 659 case ArchSpec::eCore_mips64r2: 660 case ArchSpec::eCore_mips64r2el: 661 cpu = "mips64r2"; 662 break; 663 case ArchSpec::eCore_mips64r3: 664 case ArchSpec::eCore_mips64r3el: 665 cpu = "mips64r3"; 666 break; 667 case ArchSpec::eCore_mips64r5: 668 case ArchSpec::eCore_mips64r5el: 669 cpu = "mips64r5"; 670 break; 671 case ArchSpec::eCore_mips64r6: 672 case ArchSpec::eCore_mips64r6el: 673 cpu = "mips64r6"; 674 break; 675 default: 676 break; 677 } 678 } 679 return cpu; 680 } 681 682 uint32_t ArchSpec::GetMachOCPUType() const { 683 const CoreDefinition *core_def = FindCoreDefinition(m_core); 684 if (core_def) { 685 const ArchDefinitionEntry *arch_def = 686 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 687 if (arch_def) { 688 return arch_def->cpu; 689 } 690 } 691 return LLDB_INVALID_CPUTYPE; 692 } 693 694 uint32_t ArchSpec::GetMachOCPUSubType() const { 695 const CoreDefinition *core_def = FindCoreDefinition(m_core); 696 if (core_def) { 697 const ArchDefinitionEntry *arch_def = 698 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 699 if (arch_def) { 700 return arch_def->sub; 701 } 702 } 703 return LLDB_INVALID_CPUTYPE; 704 } 705 706 uint32_t ArchSpec::GetDataByteSize() const { 707 return 1; 708 } 709 710 uint32_t ArchSpec::GetCodeByteSize() const { 711 return 1; 712 } 713 714 llvm::Triple::ArchType ArchSpec::GetMachine() const { 715 const CoreDefinition *core_def = FindCoreDefinition(m_core); 716 if (core_def) 717 return core_def->machine; 718 719 return llvm::Triple::UnknownArch; 720 } 721 722 ConstString ArchSpec::GetDistributionId() const { 723 return m_distribution_id; 724 } 725 726 void ArchSpec::SetDistributionId(const char *distribution_id) { 727 m_distribution_id.SetCString(distribution_id); 728 } 729 730 uint32_t ArchSpec::GetAddressByteSize() const { 731 const CoreDefinition *core_def = FindCoreDefinition(m_core); 732 if (core_def) { 733 if (core_def->machine == llvm::Triple::mips64 || 734 core_def->machine == llvm::Triple::mips64el) { 735 // For N32/O32 applications Address size is 4 bytes. 736 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 737 return 4; 738 } 739 return core_def->addr_byte_size; 740 } 741 return 0; 742 } 743 744 ByteOrder ArchSpec::GetDefaultEndian() const { 745 const CoreDefinition *core_def = FindCoreDefinition(m_core); 746 if (core_def) 747 return core_def->default_byte_order; 748 return eByteOrderInvalid; 749 } 750 751 bool ArchSpec::CharIsSignedByDefault() const { 752 switch (m_triple.getArch()) { 753 default: 754 return true; 755 756 case llvm::Triple::aarch64: 757 case llvm::Triple::aarch64_32: 758 case llvm::Triple::aarch64_be: 759 case llvm::Triple::arm: 760 case llvm::Triple::armeb: 761 case llvm::Triple::thumb: 762 case llvm::Triple::thumbeb: 763 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 764 765 case llvm::Triple::ppc: 766 case llvm::Triple::ppc64: 767 return m_triple.isOSDarwin(); 768 769 case llvm::Triple::ppc64le: 770 case llvm::Triple::systemz: 771 case llvm::Triple::xcore: 772 case llvm::Triple::arc: 773 return false; 774 } 775 } 776 777 lldb::ByteOrder ArchSpec::GetByteOrder() const { 778 if (m_byte_order == eByteOrderInvalid) 779 return GetDefaultEndian(); 780 return m_byte_order; 781 } 782 783 //===----------------------------------------------------------------------===// 784 // Mutators. 785 786 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 787 m_triple = triple; 788 UpdateCore(); 789 return IsValid(); 790 } 791 792 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 793 ArchSpec &arch) { 794 // Accept "12-10" or "12.10" as cpu type/subtype 795 if (triple_str.empty()) 796 return false; 797 798 size_t pos = triple_str.find_first_of("-."); 799 if (pos == llvm::StringRef::npos) 800 return false; 801 802 llvm::StringRef cpu_str = triple_str.substr(0, pos); 803 llvm::StringRef remainder = triple_str.substr(pos + 1); 804 if (cpu_str.empty() || remainder.empty()) 805 return false; 806 807 llvm::StringRef sub_str; 808 llvm::StringRef vendor; 809 llvm::StringRef os; 810 std::tie(sub_str, remainder) = remainder.split('-'); 811 std::tie(vendor, os) = remainder.split('-'); 812 813 uint32_t cpu = 0; 814 uint32_t sub = 0; 815 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 816 return false; 817 818 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 819 return false; 820 if (!vendor.empty() && !os.empty()) { 821 arch.GetTriple().setVendorName(vendor); 822 arch.GetTriple().setOSName(os); 823 } 824 825 return true; 826 } 827 828 bool ArchSpec::SetTriple(llvm::StringRef triple) { 829 if (triple.empty()) { 830 Clear(); 831 return false; 832 } 833 834 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 835 return true; 836 837 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 838 return IsValid(); 839 } 840 841 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 842 return !normalized_triple.getArchName().empty() && 843 normalized_triple.getOSName().empty() && 844 normalized_triple.getVendorName().empty() && 845 normalized_triple.getEnvironmentName().empty(); 846 } 847 848 void ArchSpec::MergeFrom(const ArchSpec &other) { 849 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 850 GetTriple().setVendor(other.GetTriple().getVendor()); 851 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 852 GetTriple().setOS(other.GetTriple().getOS()); 853 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 854 GetTriple().setArch(other.GetTriple().getArch()); 855 856 // MachO unknown64 isn't really invalid as the debugger can still obtain 857 // information from the binary, e.g. line tables. As such, we don't update 858 // the core here. 859 if (other.GetCore() != eCore_uknownMach64) 860 UpdateCore(); 861 } 862 if (!TripleEnvironmentWasSpecified() && 863 other.TripleEnvironmentWasSpecified()) { 864 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 865 } 866 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 867 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 868 // adopt the specific arm core. 869 if (GetTriple().getArch() == llvm::Triple::arm && 870 other.GetTriple().getArch() == llvm::Triple::arm && 871 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 872 other.GetCore() != ArchSpec::eCore_arm_generic) { 873 m_core = other.GetCore(); 874 CoreUpdated(false); 875 } 876 if (GetFlags() == 0) { 877 SetFlags(other.GetFlags()); 878 } 879 } 880 881 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 882 uint32_t sub, uint32_t os) { 883 m_core = kCore_invalid; 884 bool update_triple = true; 885 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 886 if (arch_def) { 887 const ArchDefinitionEntry *arch_def_entry = 888 FindArchDefinitionEntry(arch_def, cpu, sub); 889 if (arch_def_entry) { 890 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 891 if (core_def) { 892 m_core = core_def->core; 893 update_triple = false; 894 // Always use the architecture name because it might be more 895 // descriptive than the architecture enum ("armv7" -> 896 // llvm::Triple::arm). 897 m_triple.setArchName(llvm::StringRef(core_def->name)); 898 if (arch_type == eArchTypeMachO) { 899 m_triple.setVendor(llvm::Triple::Apple); 900 901 // Don't set the OS. It could be simulator, macosx, ios, watchos, 902 // tvos, bridgeos. We could get close with the cpu type - but we 903 // can't get it right all of the time. Better to leave this unset 904 // so other sections of code will set it when they have more 905 // information. NB: don't call m_triple.setOS 906 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 907 // the ArchSpec::TripleVendorWasSpecified() method says that any 908 // OSName setting means it was specified. 909 } else if (arch_type == eArchTypeELF) { 910 switch (os) { 911 case llvm::ELF::ELFOSABI_AIX: 912 m_triple.setOS(llvm::Triple::OSType::AIX); 913 break; 914 case llvm::ELF::ELFOSABI_FREEBSD: 915 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 916 break; 917 case llvm::ELF::ELFOSABI_GNU: 918 m_triple.setOS(llvm::Triple::OSType::Linux); 919 break; 920 case llvm::ELF::ELFOSABI_NETBSD: 921 m_triple.setOS(llvm::Triple::OSType::NetBSD); 922 break; 923 case llvm::ELF::ELFOSABI_OPENBSD: 924 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 925 break; 926 case llvm::ELF::ELFOSABI_SOLARIS: 927 m_triple.setOS(llvm::Triple::OSType::Solaris); 928 break; 929 } 930 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 931 m_triple.setVendor(llvm::Triple::PC); 932 m_triple.setOS(llvm::Triple::Win32); 933 } else { 934 m_triple.setVendor(llvm::Triple::UnknownVendor); 935 m_triple.setOS(llvm::Triple::UnknownOS); 936 } 937 // Fall back onto setting the machine type if the arch by name 938 // failed... 939 if (m_triple.getArch() == llvm::Triple::UnknownArch) 940 m_triple.setArch(core_def->machine); 941 } 942 } else { 943 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 944 LLDB_LOGF(log, 945 "Unable to find a core definition for cpu 0x%" PRIx32 946 " sub %" PRId32, 947 cpu, sub); 948 } 949 } 950 CoreUpdated(update_triple); 951 return IsValid(); 952 } 953 954 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 955 const CoreDefinition *core_def = FindCoreDefinition(m_core); 956 if (core_def) 957 return core_def->min_opcode_byte_size; 958 return 0; 959 } 960 961 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 962 const CoreDefinition *core_def = FindCoreDefinition(m_core); 963 if (core_def) 964 return core_def->max_opcode_byte_size; 965 return 0; 966 } 967 968 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 969 return IsEqualTo(rhs, true); 970 } 971 972 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 973 return IsEqualTo(rhs, false); 974 } 975 976 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 977 llvm::Triple::EnvironmentType rhs) { 978 if (lhs == rhs) 979 return true; 980 981 // If any of the environment is unknown then they are compatible 982 if (lhs == llvm::Triple::UnknownEnvironment || 983 rhs == llvm::Triple::UnknownEnvironment) 984 return true; 985 986 // If one of the environment is Android and the other one is EABI then they 987 // are considered to be compatible. This is required as a workaround for 988 // shared libraries compiled for Android without the NOTE section indicating 989 // that they are using the Android ABI. 990 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 991 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 992 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 993 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 994 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 995 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 996 return true; 997 998 return false; 999 } 1000 1001 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1002 // explicitly ignoring m_distribution_id in this method. 1003 1004 if (GetByteOrder() != rhs.GetByteOrder()) 1005 return false; 1006 1007 const ArchSpec::Core lhs_core = GetCore(); 1008 const ArchSpec::Core rhs_core = rhs.GetCore(); 1009 1010 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1011 1012 if (core_match) { 1013 const llvm::Triple &lhs_triple = GetTriple(); 1014 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1015 1016 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1017 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1018 if (lhs_triple_vendor != rhs_triple_vendor) { 1019 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1020 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1021 // Both architectures had the vendor specified, so if they aren't equal 1022 // then we return false 1023 if (rhs_vendor_specified && lhs_vendor_specified) 1024 return false; 1025 1026 // Only fail if both vendor types are not unknown 1027 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1028 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1029 return false; 1030 } 1031 1032 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1033 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1034 if (lhs_triple_os != rhs_triple_os) { 1035 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1036 const bool lhs_os_specified = TripleOSWasSpecified(); 1037 // Both architectures had the OS specified, so if they aren't equal then 1038 // we return false 1039 if (rhs_os_specified && lhs_os_specified) 1040 return false; 1041 1042 // Only fail if both os types are not unknown 1043 if (lhs_triple_os != llvm::Triple::UnknownOS && 1044 rhs_triple_os != llvm::Triple::UnknownOS) 1045 return false; 1046 } 1047 1048 const llvm::Triple::EnvironmentType lhs_triple_env = 1049 lhs_triple.getEnvironment(); 1050 const llvm::Triple::EnvironmentType rhs_triple_env = 1051 rhs_triple.getEnvironment(); 1052 1053 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1054 } 1055 return false; 1056 } 1057 1058 void ArchSpec::UpdateCore() { 1059 llvm::StringRef arch_name(m_triple.getArchName()); 1060 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1061 if (core_def) { 1062 m_core = core_def->core; 1063 // Set the byte order to the default byte order for an architecture. This 1064 // can be modified if needed for cases when cores handle both big and 1065 // little endian 1066 m_byte_order = core_def->default_byte_order; 1067 } else { 1068 Clear(); 1069 } 1070 } 1071 1072 //===----------------------------------------------------------------------===// 1073 // Helper methods. 1074 1075 void ArchSpec::CoreUpdated(bool update_triple) { 1076 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1077 if (core_def) { 1078 if (update_triple) 1079 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1080 m_byte_order = core_def->default_byte_order; 1081 } else { 1082 if (update_triple) 1083 m_triple = llvm::Triple(); 1084 m_byte_order = eByteOrderInvalid; 1085 } 1086 } 1087 1088 //===----------------------------------------------------------------------===// 1089 // Operators. 1090 1091 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1092 bool try_inverse, bool enforce_exact_match) { 1093 if (core1 == core2) 1094 return true; 1095 1096 switch (core1) { 1097 case ArchSpec::kCore_any: 1098 return true; 1099 1100 case ArchSpec::eCore_arm_generic: 1101 if (enforce_exact_match) 1102 break; 1103 LLVM_FALLTHROUGH; 1104 case ArchSpec::kCore_arm_any: 1105 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1106 return true; 1107 if (core2 >= ArchSpec::kCore_thumb_first && 1108 core2 <= ArchSpec::kCore_thumb_last) 1109 return true; 1110 if (core2 == ArchSpec::kCore_arm_any) 1111 return true; 1112 break; 1113 1114 case ArchSpec::kCore_x86_32_any: 1115 if ((core2 >= ArchSpec::kCore_x86_32_first && 1116 core2 <= ArchSpec::kCore_x86_32_last) || 1117 (core2 == ArchSpec::kCore_x86_32_any)) 1118 return true; 1119 break; 1120 1121 case ArchSpec::kCore_x86_64_any: 1122 if ((core2 >= ArchSpec::kCore_x86_64_first && 1123 core2 <= ArchSpec::kCore_x86_64_last) || 1124 (core2 == ArchSpec::kCore_x86_64_any)) 1125 return true; 1126 break; 1127 1128 case ArchSpec::kCore_ppc_any: 1129 if ((core2 >= ArchSpec::kCore_ppc_first && 1130 core2 <= ArchSpec::kCore_ppc_last) || 1131 (core2 == ArchSpec::kCore_ppc_any)) 1132 return true; 1133 break; 1134 1135 case ArchSpec::kCore_ppc64_any: 1136 if ((core2 >= ArchSpec::kCore_ppc64_first && 1137 core2 <= ArchSpec::kCore_ppc64_last) || 1138 (core2 == ArchSpec::kCore_ppc64_any)) 1139 return true; 1140 break; 1141 1142 case ArchSpec::eCore_arm_armv6m: 1143 if (!enforce_exact_match) { 1144 if (core2 == ArchSpec::eCore_arm_generic) 1145 return true; 1146 try_inverse = false; 1147 if (core2 == ArchSpec::eCore_arm_armv7) 1148 return true; 1149 if (core2 == ArchSpec::eCore_arm_armv6m) 1150 return true; 1151 } 1152 break; 1153 1154 case ArchSpec::kCore_hexagon_any: 1155 if ((core2 >= ArchSpec::kCore_hexagon_first && 1156 core2 <= ArchSpec::kCore_hexagon_last) || 1157 (core2 == ArchSpec::kCore_hexagon_any)) 1158 return true; 1159 break; 1160 1161 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1162 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1163 // ARMv7E-M - armv7em 1164 case ArchSpec::eCore_arm_armv7em: 1165 if (!enforce_exact_match) { 1166 if (core2 == ArchSpec::eCore_arm_generic) 1167 return true; 1168 if (core2 == ArchSpec::eCore_arm_armv7m) 1169 return true; 1170 if (core2 == ArchSpec::eCore_arm_armv6m) 1171 return true; 1172 if (core2 == ArchSpec::eCore_arm_armv7) 1173 return true; 1174 try_inverse = true; 1175 } 1176 break; 1177 1178 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1179 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1180 // ARMv7E-M - armv7em 1181 case ArchSpec::eCore_arm_armv7m: 1182 if (!enforce_exact_match) { 1183 if (core2 == ArchSpec::eCore_arm_generic) 1184 return true; 1185 if (core2 == ArchSpec::eCore_arm_armv6m) 1186 return true; 1187 if (core2 == ArchSpec::eCore_arm_armv7) 1188 return true; 1189 if (core2 == ArchSpec::eCore_arm_armv7em) 1190 return true; 1191 try_inverse = true; 1192 } 1193 break; 1194 1195 case ArchSpec::eCore_arm_armv7f: 1196 case ArchSpec::eCore_arm_armv7k: 1197 case ArchSpec::eCore_arm_armv7s: 1198 case ArchSpec::eCore_arm_armv7l: 1199 case ArchSpec::eCore_arm_armv8l: 1200 if (!enforce_exact_match) { 1201 if (core2 == ArchSpec::eCore_arm_generic) 1202 return true; 1203 if (core2 == ArchSpec::eCore_arm_armv7) 1204 return true; 1205 try_inverse = false; 1206 } 1207 break; 1208 1209 case ArchSpec::eCore_x86_64_x86_64h: 1210 if (!enforce_exact_match) { 1211 try_inverse = false; 1212 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1213 return true; 1214 } 1215 break; 1216 1217 case ArchSpec::eCore_arm_armv8: 1218 if (!enforce_exact_match) { 1219 if (core2 == ArchSpec::eCore_arm_arm64) 1220 return true; 1221 if (core2 == ArchSpec::eCore_arm_aarch64) 1222 return true; 1223 try_inverse = false; 1224 } 1225 break; 1226 1227 case ArchSpec::eCore_arm_aarch64: 1228 if (!enforce_exact_match) { 1229 if (core2 == ArchSpec::eCore_arm_arm64) 1230 return true; 1231 if (core2 == ArchSpec::eCore_arm_armv8) 1232 return true; 1233 try_inverse = false; 1234 } 1235 break; 1236 1237 case ArchSpec::eCore_arm_arm64: 1238 if (!enforce_exact_match) { 1239 if (core2 == ArchSpec::eCore_arm_aarch64) 1240 return true; 1241 if (core2 == ArchSpec::eCore_arm_armv8) 1242 return true; 1243 try_inverse = false; 1244 } 1245 break; 1246 1247 case ArchSpec::eCore_arm_arm64_32: 1248 if (!enforce_exact_match) { 1249 if (core2 == ArchSpec::eCore_arm_generic) 1250 return true; 1251 try_inverse = false; 1252 } 1253 break; 1254 1255 case ArchSpec::eCore_mips32: 1256 if (!enforce_exact_match) { 1257 if (core2 >= ArchSpec::kCore_mips32_first && 1258 core2 <= ArchSpec::kCore_mips32_last) 1259 return true; 1260 try_inverse = false; 1261 } 1262 break; 1263 1264 case ArchSpec::eCore_mips32el: 1265 if (!enforce_exact_match) { 1266 if (core2 >= ArchSpec::kCore_mips32el_first && 1267 core2 <= ArchSpec::kCore_mips32el_last) 1268 return true; 1269 try_inverse = true; 1270 } 1271 break; 1272 1273 case ArchSpec::eCore_mips64: 1274 if (!enforce_exact_match) { 1275 if (core2 >= ArchSpec::kCore_mips32_first && 1276 core2 <= ArchSpec::kCore_mips32_last) 1277 return true; 1278 if (core2 >= ArchSpec::kCore_mips64_first && 1279 core2 <= ArchSpec::kCore_mips64_last) 1280 return true; 1281 try_inverse = false; 1282 } 1283 break; 1284 1285 case ArchSpec::eCore_mips64el: 1286 if (!enforce_exact_match) { 1287 if (core2 >= ArchSpec::kCore_mips32el_first && 1288 core2 <= ArchSpec::kCore_mips32el_last) 1289 return true; 1290 if (core2 >= ArchSpec::kCore_mips64el_first && 1291 core2 <= ArchSpec::kCore_mips64el_last) 1292 return true; 1293 try_inverse = false; 1294 } 1295 break; 1296 1297 case ArchSpec::eCore_mips64r2: 1298 case ArchSpec::eCore_mips64r3: 1299 case ArchSpec::eCore_mips64r5: 1300 if (!enforce_exact_match) { 1301 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1302 return true; 1303 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1304 return true; 1305 try_inverse = false; 1306 } 1307 break; 1308 1309 case ArchSpec::eCore_mips64r2el: 1310 case ArchSpec::eCore_mips64r3el: 1311 case ArchSpec::eCore_mips64r5el: 1312 if (!enforce_exact_match) { 1313 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1314 return true; 1315 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1316 return true; 1317 try_inverse = false; 1318 } 1319 break; 1320 1321 case ArchSpec::eCore_mips32r2: 1322 case ArchSpec::eCore_mips32r3: 1323 case ArchSpec::eCore_mips32r5: 1324 if (!enforce_exact_match) { 1325 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1326 return true; 1327 } 1328 break; 1329 1330 case ArchSpec::eCore_mips32r2el: 1331 case ArchSpec::eCore_mips32r3el: 1332 case ArchSpec::eCore_mips32r5el: 1333 if (!enforce_exact_match) { 1334 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1335 return true; 1336 } 1337 break; 1338 1339 case ArchSpec::eCore_mips32r6: 1340 if (!enforce_exact_match) { 1341 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1342 return true; 1343 } 1344 break; 1345 1346 case ArchSpec::eCore_mips32r6el: 1347 if (!enforce_exact_match) { 1348 if (core2 == ArchSpec::eCore_mips32el || 1349 core2 == ArchSpec::eCore_mips32r6el) 1350 return true; 1351 } 1352 break; 1353 1354 case ArchSpec::eCore_mips64r6: 1355 if (!enforce_exact_match) { 1356 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1357 return true; 1358 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1359 return true; 1360 } 1361 break; 1362 1363 case ArchSpec::eCore_mips64r6el: 1364 if (!enforce_exact_match) { 1365 if (core2 == ArchSpec::eCore_mips32el || 1366 core2 == ArchSpec::eCore_mips32r6el) 1367 return true; 1368 if (core2 == ArchSpec::eCore_mips64el || 1369 core2 == ArchSpec::eCore_mips64r6el) 1370 return true; 1371 } 1372 break; 1373 1374 default: 1375 break; 1376 } 1377 if (try_inverse) 1378 return cores_match(core2, core1, false, enforce_exact_match); 1379 return false; 1380 } 1381 1382 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1383 const ArchSpec::Core lhs_core = lhs.GetCore(); 1384 const ArchSpec::Core rhs_core = rhs.GetCore(); 1385 return lhs_core < rhs_core; 1386 } 1387 1388 1389 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1390 return lhs.GetCore() == rhs.GetCore(); 1391 } 1392 1393 bool ArchSpec::IsFullySpecifiedTriple() const { 1394 const auto &user_specified_triple = GetTriple(); 1395 1396 bool user_triple_fully_specified = false; 1397 1398 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1399 TripleOSWasSpecified()) { 1400 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1401 TripleVendorWasSpecified()) { 1402 const unsigned unspecified = 0; 1403 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1404 user_triple_fully_specified = true; 1405 } 1406 } 1407 } 1408 1409 return user_triple_fully_specified; 1410 } 1411 1412 void ArchSpec::PiecewiseTripleCompare( 1413 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1414 bool &os_different, bool &os_version_different, bool &env_different) const { 1415 const llvm::Triple &me(GetTriple()); 1416 const llvm::Triple &them(other.GetTriple()); 1417 1418 arch_different = (me.getArch() != them.getArch()); 1419 1420 vendor_different = (me.getVendor() != them.getVendor()); 1421 1422 os_different = (me.getOS() != them.getOS()); 1423 1424 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1425 1426 env_different = (me.getEnvironment() != them.getEnvironment()); 1427 } 1428 1429 bool ArchSpec::IsAlwaysThumbInstructions() const { 1430 std::string Status; 1431 if (GetTriple().getArch() == llvm::Triple::arm || 1432 GetTriple().getArch() == llvm::Triple::thumb) { 1433 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1434 // 1435 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1436 // execute thumb instructions. We map the cores to arch names like this: 1437 // 1438 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1439 // Cortex-M7: armv7em 1440 1441 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1442 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1443 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1444 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1445 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1446 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1447 return true; 1448 } 1449 // Windows on ARM is always thumb. 1450 if (GetTriple().isOSWindows()) 1451 return true; 1452 } 1453 return false; 1454 } 1455 1456 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1457 const llvm::Triple &triple = GetTriple(); 1458 llvm::StringRef arch_str = triple.getArchName(); 1459 llvm::StringRef vendor_str = triple.getVendorName(); 1460 llvm::StringRef os_str = triple.getOSName(); 1461 llvm::StringRef environ_str = triple.getEnvironmentName(); 1462 1463 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1464 vendor_str.empty() ? "*" : vendor_str, 1465 os_str.empty() ? "*" : os_str); 1466 1467 if (!environ_str.empty()) 1468 s << "-" << environ_str; 1469 } 1470 1471 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *, 1472 raw_ostream &Out) { 1473 Val.DumpTriple(Out); 1474 } 1475 1476 llvm::StringRef 1477 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *, 1478 ArchSpec &Val) { 1479 Val = ArchSpec(Scalar); 1480 return {}; 1481 } 1482