1 //===- LiveRangeEdit.h - Basic tools for split and spill --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // The LiveRangeEdit class represents changes done to a virtual register when it 10 // is spilled or split. 11 // 12 // The parent register is never changed. Instead, a number of new virtual 13 // registers are created and added to the newRegs vector. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 18 #define LLVM_CODEGEN_LIVERANGEEDIT_H 19 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/None.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallPtrSet.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/CodeGen/LiveInterval.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/SlotIndexes.h" 30 #include "llvm/CodeGen/TargetSubtargetInfo.h" 31 #include <cassert> 32 33 namespace llvm { 34 35 class LiveIntervals; 36 class MachineInstr; 37 class MachineOperand; 38 class TargetInstrInfo; 39 class TargetRegisterInfo; 40 class VirtRegMap; 41 class VirtRegAuxInfo; 42 43 class LiveRangeEdit : private MachineRegisterInfo::Delegate { 44 public: 45 /// Callback methods for LiveRangeEdit owners. 46 class Delegate { 47 virtual void anchor(); 48 49 public: 50 virtual ~Delegate() = default; 51 52 /// Called immediately before erasing a dead machine instruction. 53 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 54 55 /// Called when a virtual register is no longer used. Return false to defer 56 /// its deletion from LiveIntervals. 57 virtual bool LRE_CanEraseVirtReg(Register) { return true; } 58 59 /// Called before shrinking the live range of a virtual register. 60 virtual void LRE_WillShrinkVirtReg(Register) {} 61 62 /// Called after cloning a virtual register. 63 /// This is used for new registers representing connected components of Old. 64 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} 65 }; 66 67 private: 68 const LiveInterval *const Parent; 69 SmallVectorImpl<Register> &NewRegs; 70 MachineRegisterInfo &MRI; 71 LiveIntervals &LIS; 72 VirtRegMap *VRM; 73 const TargetInstrInfo &TII; 74 Delegate *const TheDelegate; 75 76 /// FirstNew - Index of the first register added to NewRegs. 77 const unsigned FirstNew; 78 79 /// ScannedRemattable - true when remattable values have been identified. 80 bool ScannedRemattable = false; 81 82 /// DeadRemats - The saved instructions which have already been dead after 83 /// rematerialization but not deleted yet -- to be done in postOptimization. 84 SmallPtrSet<MachineInstr *, 32> *DeadRemats; 85 86 /// Remattable - Values defined by remattable instructions as identified by 87 /// tii.isTriviallyReMaterializable(). 88 SmallPtrSet<const VNInfo *, 4> Remattable; 89 90 /// Rematted - Values that were actually rematted, and so need to have their 91 /// live range trimmed or entirely removed. 92 SmallPtrSet<const VNInfo *, 4> Rematted; 93 94 /// scanRemattable - Identify the Parent values that may rematerialize. 95 void scanRemattable(); 96 97 /// foldAsLoad - If LI has a single use and a single def that can be folded as 98 /// a load, eliminate the register by folding the def into the use. 99 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr *> &Dead); 100 101 using ToShrinkSet = SetVector<LiveInterval *, SmallVector<LiveInterval *, 8>, 102 SmallPtrSet<LiveInterval *, 8>>; 103 104 /// Helper for eliminateDeadDefs. 105 void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink); 106 107 /// MachineRegisterInfo callback to notify when new virtual 108 /// registers are created. 109 void MRI_NoteNewVirtualRegister(Register VReg) override; 110 111 /// Check if MachineOperand \p MO is a last use/kill either in the 112 /// main live range of \p LI or in one of the matching subregister ranges. 113 bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const; 114 115 /// Create a new empty interval based on OldReg. 116 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges); 117 118 public: 119 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 120 /// @param parent The register being spilled or split. 121 /// @param newRegs List to receive any new registers created. This needn't be 122 /// empty initially, any existing registers are ignored. 123 /// @param MF The MachineFunction the live range edit is taking place in. 124 /// @param lis The collection of all live intervals in this function. 125 /// @param vrm Map of virtual registers to physical registers for this 126 /// function. If NULL, no virtual register map updates will 127 /// be done. This could be the case if called before Regalloc. 128 /// @param deadRemats The collection of all the instructions defining an 129 /// original reg and are dead after remat. 130 LiveRangeEdit(const LiveInterval *parent, SmallVectorImpl<Register> &newRegs, 131 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm, 132 Delegate *delegate = nullptr, 133 SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr) 134 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis), 135 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate), 136 FirstNew(newRegs.size()), DeadRemats(deadRemats) { 137 MRI.setDelegate(this); 138 } 139 140 ~LiveRangeEdit() override { MRI.resetDelegate(this); } 141 142 const LiveInterval &getParent() const { 143 assert(Parent && "No parent LiveInterval"); 144 return *Parent; 145 } 146 147 Register getReg() const { return getParent().reg(); } 148 149 /// Iterator for accessing the new registers added by this edit. 150 using iterator = SmallVectorImpl<Register>::const_iterator; 151 iterator begin() const { return NewRegs.begin() + FirstNew; } 152 iterator end() const { return NewRegs.end(); } 153 unsigned size() const { return NewRegs.size() - FirstNew; } 154 bool empty() const { return size() == 0; } 155 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } 156 157 /// pop_back - It allows LiveRangeEdit users to drop new registers. 158 /// The context is when an original def instruction of a register is 159 /// dead after rematerialization, we still want to keep it for following 160 /// rematerializations. We save the def instruction in DeadRemats, 161 /// and replace the original dst register with a new dummy register so 162 /// the live range of original dst register can be shrinked normally. 163 /// We don't want to allocate phys register for the dummy register, so 164 /// we want to drop it from the NewRegs set. 165 void pop_back() { NewRegs.pop_back(); } 166 167 ArrayRef<Register> regs() const { 168 return makeArrayRef(NewRegs).slice(FirstNew); 169 } 170 171 /// createFrom - Create a new virtual register based on OldReg. 172 Register createFrom(Register OldReg); 173 174 /// create - Create a new register with the same class and original slot as 175 /// parent. 176 LiveInterval &createEmptyInterval() { 177 return createEmptyIntervalFrom(getReg(), true); 178 } 179 180 Register create() { return createFrom(getReg()); } 181 182 /// anyRematerializable - Return true if any parent values may be 183 /// rematerializable. 184 /// This function must be called before any rematerialization is attempted. 185 bool anyRematerializable(); 186 187 /// checkRematerializable - Manually add VNI to the list of rematerializable 188 /// values if DefMI may be rematerializable. 189 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI); 190 191 /// Remat - Information needed to rematerialize at a specific location. 192 struct Remat { 193 const VNInfo *const ParentVNI; // parent_'s value at the remat location. 194 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains 195 // the real expr for remat. 196 197 explicit Remat(const VNInfo *ParentVNI) : ParentVNI(ParentVNI) {} 198 }; 199 200 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 201 /// OrigIdx are also available with the same value at UseIdx. 202 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 203 SlotIndex UseIdx) const; 204 205 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 206 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 207 /// When cheapAsAMove is set, only cheap remats are allowed. 208 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, 209 bool cheapAsAMove); 210 211 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 212 /// instruction into MBB before MI. The new instruction is mapped, but 213 /// liveness is not updated. 214 /// Return the SlotIndex of the new instruction. 215 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 216 MachineBasicBlock::iterator MI, unsigned DestReg, 217 const Remat &RM, const TargetRegisterInfo &, 218 bool Late = false); 219 220 /// markRematerialized - explicitly mark a value as rematerialized after doing 221 /// it manually. 222 void markRematerialized(const VNInfo *ParentVNI) { 223 Rematted.insert(ParentVNI); 224 } 225 226 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. 227 bool didRematerialize(const VNInfo *ParentVNI) const { 228 return Rematted.count(ParentVNI); 229 } 230 231 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 232 /// to erase it from LIS. 233 void eraseVirtReg(Register Reg); 234 235 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 236 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 237 /// and further dead efs to be eliminated. 238 /// RegsBeingSpilled lists registers currently being spilled by the register 239 /// allocator. These registers should not be split into new intervals 240 /// as currently those new intervals are not guaranteed to spill. 241 void eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead, 242 ArrayRef<Register> RegsBeingSpilled = None); 243 244 /// calculateRegClassAndHint - Recompute register class and hint for each new 245 /// register. 246 void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &); 247 }; 248 249 } // end namespace llvm 250 251 #endif // LLVM_CODEGEN_LIVERANGEEDIT_H 252