1 //===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file exposes a function named BuildMI, which is useful for dramatically 10 // simplifying how MachineInstr's are created. It allows use of code like this: 11 // 12 // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst) 13 // .addReg(argVal1) 14 // .addReg(argVal2); 15 // 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H 19 #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H 20 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/CodeGen/GlobalISel/Utils.h" 23 #include "llvm/CodeGen/MachineBasicBlock.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstr.h" 26 #include "llvm/CodeGen/MachineInstrBundle.h" 27 #include "llvm/CodeGen/MachineOperand.h" 28 #include "llvm/CodeGen/TargetRegisterInfo.h" 29 #include "llvm/IR/InstrTypes.h" 30 #include "llvm/IR/Intrinsics.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include <cassert> 33 #include <cstdint> 34 35 namespace llvm { 36 37 class MCInstrDesc; 38 class MDNode; 39 40 namespace RegState { 41 42 enum { 43 /// Register definition. 44 Define = 0x2, 45 /// Not emitted register (e.g. carry, or temporary result). 46 Implicit = 0x4, 47 /// The last use of a register. 48 Kill = 0x8, 49 /// Unused definition. 50 Dead = 0x10, 51 /// Value of the register doesn't matter. 52 Undef = 0x20, 53 /// Register definition happens before uses. 54 EarlyClobber = 0x40, 55 /// Register 'use' is for debugging purpose. 56 Debug = 0x80, 57 /// Register reads a value that is defined inside the same instruction or 58 /// bundle. 59 InternalRead = 0x100, 60 /// Register that may be renamed. 61 Renamable = 0x200, 62 DefineNoRead = Define | Undef, 63 ImplicitDefine = Implicit | Define, 64 ImplicitKill = Implicit | Kill 65 }; 66 67 } // end namespace RegState 68 69 class MachineInstrBuilder { 70 MachineFunction *MF = nullptr; 71 MachineInstr *MI = nullptr; 72 73 public: 74 MachineInstrBuilder() = default; 75 76 /// Create a MachineInstrBuilder for manipulating an existing instruction. 77 /// F must be the machine function that was used to allocate I. 78 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} 79 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I) 80 : MF(&F), MI(&*I) {} 81 82 /// Allow automatic conversion to the machine instruction we are working on. 83 operator MachineInstr*() const { return MI; } 84 MachineInstr *operator->() const { return MI; } 85 operator MachineBasicBlock::iterator() const { return MI; } 86 87 /// If conversion operators fail, use this method to get the MachineInstr 88 /// explicitly. 89 MachineInstr *getInstr() const { return MI; } 90 91 /// Get the register for the operand index. 92 /// The operand at the index should be a register (asserted by 93 /// MachineOperand). 94 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); } 95 96 /// Add a new virtual register operand. 97 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0, 98 unsigned SubReg = 0) const { 99 assert((flags & 0x1) == 0 && 100 "Passing in 'true' to addReg is forbidden! Use enums instead."); 101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 102 flags & RegState::Define, 103 flags & RegState::Implicit, 104 flags & RegState::Kill, 105 flags & RegState::Dead, 106 flags & RegState::Undef, 107 flags & RegState::EarlyClobber, 108 SubReg, 109 flags & RegState::Debug, 110 flags & RegState::InternalRead, 111 flags & RegState::Renamable)); 112 return *this; 113 } 114 115 /// Add a virtual register definition operand. 116 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0, 117 unsigned SubReg = 0) const { 118 return addReg(RegNo, Flags | RegState::Define, SubReg); 119 } 120 121 /// Add a virtual register use operand. It is an error for Flags to contain 122 /// `RegState::Define` when calling this function. 123 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0, 124 unsigned SubReg = 0) const { 125 assert(!(Flags & RegState::Define) && 126 "Misleading addUse defines register, use addReg instead."); 127 return addReg(RegNo, Flags, SubReg); 128 } 129 130 /// Add a new immediate operand. 131 const MachineInstrBuilder &addImm(int64_t Val) const { 132 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); 133 return *this; 134 } 135 136 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const { 137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); 138 return *this; 139 } 140 141 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const { 142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); 143 return *this; 144 } 145 146 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, 147 unsigned TargetFlags = 0) const { 148 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags)); 149 return *this; 150 } 151 152 const MachineInstrBuilder &addFrameIndex(int Idx) const { 153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); 154 return *this; 155 } 156 157 const MachineInstrBuilder & 158 addConstantPoolIndex(unsigned Idx, int Offset = 0, 159 unsigned TargetFlags = 0) const { 160 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); 161 return *this; 162 } 163 164 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0, 165 unsigned TargetFlags = 0) const { 166 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset, 167 TargetFlags)); 168 return *this; 169 } 170 171 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx, 172 unsigned TargetFlags = 0) const { 173 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags)); 174 return *this; 175 } 176 177 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV, 178 int64_t Offset = 0, 179 unsigned TargetFlags = 0) const { 180 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags)); 181 return *this; 182 } 183 184 const MachineInstrBuilder &addExternalSymbol(const char *FnName, 185 unsigned TargetFlags = 0) const { 186 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags)); 187 return *this; 188 } 189 190 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA, 191 int64_t Offset = 0, 192 unsigned TargetFlags = 0) const { 193 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags)); 194 return *this; 195 } 196 197 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { 198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); 199 return *this; 200 } 201 202 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const { 203 MI->addMemOperand(*MF, MMO); 204 return *this; 205 } 206 207 const MachineInstrBuilder & 208 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const { 209 MI->setMemRefs(*MF, MMOs); 210 return *this; 211 } 212 213 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const { 214 MI->cloneMemRefs(*MF, OtherMI); 215 return *this; 216 } 217 218 const MachineInstrBuilder & 219 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const { 220 MI->cloneMergedMemRefs(*MF, OtherMIs); 221 return *this; 222 } 223 224 const MachineInstrBuilder &add(const MachineOperand &MO) const { 225 MI->addOperand(*MF, MO); 226 return *this; 227 } 228 229 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const { 230 for (const MachineOperand &MO : MOs) { 231 MI->addOperand(*MF, MO); 232 } 233 return *this; 234 } 235 236 const MachineInstrBuilder &addMetadata(const MDNode *MD) const { 237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); 238 assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable()) 239 : true) && 240 "first MDNode argument of a DBG_VALUE not a variable"); 241 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) 242 : true) && 243 "first MDNode argument of a DBG_LABEL not a label"); 244 return *this; 245 } 246 247 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const { 248 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex)); 249 return *this; 250 } 251 252 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const { 253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); 254 return *this; 255 } 256 257 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const { 258 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred)); 259 return *this; 260 } 261 262 const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const { 263 MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val)); 264 return *this; 265 } 266 267 const MachineInstrBuilder &addSym(MCSymbol *Sym, 268 unsigned char TargetFlags = 0) const { 269 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags)); 270 return *this; 271 } 272 273 const MachineInstrBuilder &setMIFlags(unsigned Flags) const { 274 MI->setFlags(Flags); 275 return *this; 276 } 277 278 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const { 279 MI->setFlag(Flag); 280 return *this; 281 } 282 283 // Add a displacement from an existing MachineOperand with an added offset. 284 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, 285 unsigned char TargetFlags = 0) const { 286 // If caller specifies new TargetFlags then use it, otherwise the 287 // default behavior is to copy the target flags from the existing 288 // MachineOperand. This means if the caller wants to clear the 289 // target flags it needs to do so explicitly. 290 if (0 == TargetFlags) 291 TargetFlags = Disp.getTargetFlags(); 292 293 switch (Disp.getType()) { 294 default: 295 llvm_unreachable("Unhandled operand type in addDisp()"); 296 case MachineOperand::MO_Immediate: 297 return addImm(Disp.getImm() + off); 298 case MachineOperand::MO_ConstantPoolIndex: 299 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off, 300 TargetFlags); 301 case MachineOperand::MO_GlobalAddress: 302 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off, 303 TargetFlags); 304 case MachineOperand::MO_BlockAddress: 305 return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off, 306 TargetFlags); 307 case MachineOperand::MO_JumpTableIndex: 308 assert(off == 0 && "cannot create offset into jump tables"); 309 return addJumpTableIndex(Disp.getIndex(), TargetFlags); 310 } 311 } 312 313 const MachineInstrBuilder &setPCSections(MDNode *MD) const { 314 if (MD) 315 MI->setPCSections(*MF, MD); 316 return *this; 317 } 318 319 /// Copy all the implicit operands from OtherMI onto this one. 320 const MachineInstrBuilder & 321 copyImplicitOps(const MachineInstr &OtherMI) const { 322 MI->copyImplicitOps(*MF, OtherMI); 323 return *this; 324 } 325 326 bool constrainAllUses(const TargetInstrInfo &TII, 327 const TargetRegisterInfo &TRI, 328 const RegisterBankInfo &RBI) const { 329 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); 330 } 331 }; 332 333 /// Set of metadata that should be preserved when using BuildMI(). This provides 334 /// a more convenient way of preserving DebugLoc and PCSections. 335 class MIMetadata { 336 public: 337 MIMetadata() = default; 338 MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr) 339 : DL(std::move(DL)), PCSections(PCSections) {} 340 MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr) 341 : DL(DI), PCSections(PCSections) {} 342 explicit MIMetadata(const Instruction &From) 343 : DL(From.getDebugLoc()), 344 PCSections(From.getMetadata(LLVMContext::MD_pcsections)) {} 345 explicit MIMetadata(const MachineInstr &From) 346 : DL(From.getDebugLoc()), PCSections(From.getPCSections()) {} 347 348 const DebugLoc &getDL() const { return DL; } 349 MDNode *getPCSections() const { return PCSections; } 350 351 private: 352 DebugLoc DL; 353 MDNode *PCSections = nullptr; 354 }; 355 356 /// Builder interface. Specify how to create the initial instruction itself. 357 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, 358 const MCInstrDesc &MCID) { 359 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) 360 .setPCSections(MIMD.getPCSections()); 361 } 362 363 /// This version of the builder sets up the first operand as a 364 /// destination virtual register. 365 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, 366 const MCInstrDesc &MCID, Register DestReg) { 367 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) 368 .setPCSections(MIMD.getPCSections()) 369 .addReg(DestReg, RegState::Define); 370 } 371 372 /// This version of the builder inserts the newly-built instruction before 373 /// the given position in the given MachineBasicBlock, and sets up the first 374 /// operand as a destination virtual register. 375 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 376 MachineBasicBlock::iterator I, 377 const MIMetadata &MIMD, 378 const MCInstrDesc &MCID, Register DestReg) { 379 MachineFunction &MF = *BB.getParent(); 380 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); 381 BB.insert(I, MI); 382 return MachineInstrBuilder(MF, MI) 383 .setPCSections(MIMD.getPCSections()) 384 .addReg(DestReg, RegState::Define); 385 } 386 387 /// This version of the builder inserts the newly-built instruction before 388 /// the given position in the given MachineBasicBlock, and sets up the first 389 /// operand as a destination virtual register. 390 /// 391 /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is 392 /// added to the same bundle. 393 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 394 MachineBasicBlock::instr_iterator I, 395 const MIMetadata &MIMD, 396 const MCInstrDesc &MCID, Register DestReg) { 397 MachineFunction &MF = *BB.getParent(); 398 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); 399 BB.insert(I, MI); 400 return MachineInstrBuilder(MF, MI) 401 .setPCSections(MIMD.getPCSections()) 402 .addReg(DestReg, RegState::Define); 403 } 404 405 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, 406 const MIMetadata &MIMD, 407 const MCInstrDesc &MCID, Register DestReg) { 408 // Calling the overload for instr_iterator is always correct. However, the 409 // definition is not available in headers, so inline the check. 410 if (I.isInsideBundle()) 411 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID, 412 DestReg); 413 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); 414 } 415 416 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, 417 const MIMetadata &MIMD, 418 const MCInstrDesc &MCID, Register DestReg) { 419 return BuildMI(BB, *I, MIMD, MCID, DestReg); 420 } 421 422 /// This version of the builder inserts the newly-built instruction before the 423 /// given position in the given MachineBasicBlock, and does NOT take a 424 /// destination register. 425 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 426 MachineBasicBlock::iterator I, 427 const MIMetadata &MIMD, 428 const MCInstrDesc &MCID) { 429 MachineFunction &MF = *BB.getParent(); 430 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); 431 BB.insert(I, MI); 432 return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections()); 433 } 434 435 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 436 MachineBasicBlock::instr_iterator I, 437 const MIMetadata &MIMD, 438 const MCInstrDesc &MCID) { 439 MachineFunction &MF = *BB.getParent(); 440 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); 441 BB.insert(I, MI); 442 return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections()); 443 } 444 445 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, 446 const MIMetadata &MIMD, 447 const MCInstrDesc &MCID) { 448 // Calling the overload for instr_iterator is always correct. However, the 449 // definition is not available in headers, so inline the check. 450 if (I.isInsideBundle()) 451 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID); 452 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID); 453 } 454 455 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, 456 const MIMetadata &MIMD, 457 const MCInstrDesc &MCID) { 458 return BuildMI(BB, *I, MIMD, MCID); 459 } 460 461 /// This version of the builder inserts the newly-built instruction at the end 462 /// of the given MachineBasicBlock, and does NOT take a destination register. 463 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, 464 const MIMetadata &MIMD, 465 const MCInstrDesc &MCID) { 466 return BuildMI(*BB, BB->end(), MIMD, MCID); 467 } 468 469 /// This version of the builder inserts the newly-built instruction at the 470 /// end of the given MachineBasicBlock, and sets up the first operand as a 471 /// destination virtual register. 472 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, 473 const MIMetadata &MIMD, 474 const MCInstrDesc &MCID, Register DestReg) { 475 return BuildMI(*BB, BB->end(), MIMD, MCID, DestReg); 476 } 477 478 /// This version of the builder builds a DBG_VALUE intrinsic 479 /// for either a value in a register or a register-indirect 480 /// address. The convention is that a DBG_VALUE is indirect iff the 481 /// second operand is an immediate. 482 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, 483 const MCInstrDesc &MCID, bool IsIndirect, 484 Register Reg, const MDNode *Variable, 485 const MDNode *Expr); 486 487 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic 488 /// for a MachineOperand. 489 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, 490 const MCInstrDesc &MCID, bool IsIndirect, 491 ArrayRef<MachineOperand> MOs, 492 const MDNode *Variable, const MDNode *Expr); 493 494 /// This version of the builder builds a DBG_VALUE intrinsic 495 /// for either a value in a register or a register-indirect 496 /// address and inserts it at position I. 497 MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 498 MachineBasicBlock::iterator I, const DebugLoc &DL, 499 const MCInstrDesc &MCID, bool IsIndirect, 500 Register Reg, const MDNode *Variable, 501 const MDNode *Expr); 502 503 /// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or 504 /// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I. 505 MachineInstrBuilder BuildMI(MachineBasicBlock &BB, 506 MachineBasicBlock::iterator I, const DebugLoc &DL, 507 const MCInstrDesc &MCID, bool IsIndirect, 508 ArrayRef<MachineOperand> MOs, 509 const MDNode *Variable, const MDNode *Expr); 510 511 /// Clone a DBG_VALUE whose value has been spilled to FrameIndex. 512 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB, 513 MachineBasicBlock::iterator I, 514 const MachineInstr &Orig, int FrameIndex, 515 Register SpillReg); 516 MachineInstr * 517 buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, 518 const MachineInstr &Orig, int FrameIndex, 519 SmallVectorImpl<const MachineOperand *> &SpilledOperands); 520 521 /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when 522 /// modifying an instruction in place while iterating over a basic block. 523 void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg); 524 525 inline unsigned getDefRegState(bool B) { 526 return B ? RegState::Define : 0; 527 } 528 inline unsigned getImplRegState(bool B) { 529 return B ? RegState::Implicit : 0; 530 } 531 inline unsigned getKillRegState(bool B) { 532 return B ? RegState::Kill : 0; 533 } 534 inline unsigned getDeadRegState(bool B) { 535 return B ? RegState::Dead : 0; 536 } 537 inline unsigned getUndefRegState(bool B) { 538 return B ? RegState::Undef : 0; 539 } 540 inline unsigned getInternalReadRegState(bool B) { 541 return B ? RegState::InternalRead : 0; 542 } 543 inline unsigned getDebugRegState(bool B) { 544 return B ? RegState::Debug : 0; 545 } 546 inline unsigned getRenamableRegState(bool B) { 547 return B ? RegState::Renamable : 0; 548 } 549 550 /// Get all register state flags from machine operand \p RegOp. 551 inline unsigned getRegState(const MachineOperand &RegOp) { 552 assert(RegOp.isReg() && "Not a register operand"); 553 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | 554 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | 555 getUndefRegState(RegOp.isUndef()) | 556 getInternalReadRegState(RegOp.isInternalRead()) | 557 getDebugRegState(RegOp.isDebug()) | 558 getRenamableRegState(RegOp.getReg().isPhysical() && 559 RegOp.isRenamable()); 560 } 561 562 /// Helper class for constructing bundles of MachineInstrs. 563 /// 564 /// MIBundleBuilder can create a bundle from scratch by inserting new 565 /// MachineInstrs one at a time, or it can create a bundle from a sequence of 566 /// existing MachineInstrs in a basic block. 567 class MIBundleBuilder { 568 MachineBasicBlock &MBB; 569 MachineBasicBlock::instr_iterator Begin; 570 MachineBasicBlock::instr_iterator End; 571 572 public: 573 /// Create an MIBundleBuilder that inserts instructions into a new bundle in 574 /// BB above the bundle or instruction at Pos. 575 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos) 576 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {} 577 578 /// Create a bundle from the sequence of instructions between B and E. 579 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, 580 MachineBasicBlock::iterator E) 581 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) { 582 assert(B != E && "No instructions to bundle"); 583 ++B; 584 while (B != E) { 585 MachineInstr &MI = *B; 586 ++B; 587 MI.bundleWithPred(); 588 } 589 } 590 591 /// Create an MIBundleBuilder representing an existing instruction or bundle 592 /// that has MI as its head. 593 explicit MIBundleBuilder(MachineInstr *MI) 594 : MBB(*MI->getParent()), Begin(MI), 595 End(getBundleEnd(MI->getIterator())) {} 596 597 /// Return a reference to the basic block containing this bundle. 598 MachineBasicBlock &getMBB() const { return MBB; } 599 600 /// Return true if no instructions have been inserted in this bundle yet. 601 /// Empty bundles aren't representable in a MachineBasicBlock. 602 bool empty() const { return Begin == End; } 603 604 /// Return an iterator to the first bundled instruction. 605 MachineBasicBlock::instr_iterator begin() const { return Begin; } 606 607 /// Return an iterator beyond the last bundled instruction. 608 MachineBasicBlock::instr_iterator end() const { return End; } 609 610 /// Insert MI into this bundle before I which must point to an instruction in 611 /// the bundle, or end(). 612 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I, 613 MachineInstr *MI) { 614 MBB.insert(I, MI); 615 if (I == Begin) { 616 if (!empty()) 617 MI->bundleWithSucc(); 618 Begin = MI->getIterator(); 619 return *this; 620 } 621 if (I == End) { 622 MI->bundleWithPred(); 623 return *this; 624 } 625 // MI was inserted in the middle of the bundle, so its neighbors' flags are 626 // already fine. Update MI's bundle flags manually. 627 MI->setFlag(MachineInstr::BundledPred); 628 MI->setFlag(MachineInstr::BundledSucc); 629 return *this; 630 } 631 632 /// Insert MI into MBB by prepending it to the instructions in the bundle. 633 /// MI will become the first instruction in the bundle. 634 MIBundleBuilder &prepend(MachineInstr *MI) { 635 return insert(begin(), MI); 636 } 637 638 /// Insert MI into MBB by appending it to the instructions in the bundle. 639 /// MI will become the last instruction in the bundle. 640 MIBundleBuilder &append(MachineInstr *MI) { 641 return insert(end(), MI); 642 } 643 }; 644 645 } // end namespace llvm 646 647 #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H 648