1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes the target machine instruction set to the code generator. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H 14 #define LLVM_CODEGEN_TARGETINSTRINFO_H 15 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/DenseMapInfo.h" 19 #include "llvm/ADT/None.h" 20 #include "llvm/CodeGen/MIRFormatter.h" 21 #include "llvm/CodeGen/MachineBasicBlock.h" 22 #include "llvm/CodeGen/MachineCombinerPattern.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstr.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineOutliner.h" 28 #include "llvm/CodeGen/RegisterClassInfo.h" 29 #include "llvm/CodeGen/VirtRegMap.h" 30 #include "llvm/MC/MCInstrInfo.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include <cassert> 34 #include <cstddef> 35 #include <cstdint> 36 #include <utility> 37 #include <vector> 38 39 namespace llvm { 40 41 class AAResults; 42 class DFAPacketizer; 43 class InstrItineraryData; 44 class LiveIntervals; 45 class LiveVariables; 46 class MachineLoop; 47 class MachineMemOperand; 48 class MachineRegisterInfo; 49 class MCAsmInfo; 50 class MCInst; 51 struct MCSchedModel; 52 class Module; 53 class ScheduleDAG; 54 class ScheduleDAGMI; 55 class ScheduleHazardRecognizer; 56 class SDNode; 57 class SelectionDAG; 58 class RegScavenger; 59 class TargetRegisterClass; 60 class TargetRegisterInfo; 61 class TargetSchedModel; 62 class TargetSubtargetInfo; 63 64 template <class T> class SmallVectorImpl; 65 66 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>; 67 68 struct DestSourcePair { 69 const MachineOperand *Destination; 70 const MachineOperand *Source; 71 72 DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src) 73 : Destination(&Dest), Source(&Src) {} 74 }; 75 76 /// Used to describe a register and immediate addition. 77 struct RegImmPair { 78 Register Reg; 79 int64_t Imm; 80 81 RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {} 82 }; 83 84 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare. 85 /// It holds the register values, the scale value and the displacement. 86 struct ExtAddrMode { 87 Register BaseReg; 88 Register ScaledReg; 89 int64_t Scale; 90 int64_t Displacement; 91 }; 92 93 //--------------------------------------------------------------------------- 94 /// 95 /// TargetInstrInfo - Interface to description of machine instruction set 96 /// 97 class TargetInstrInfo : public MCInstrInfo { 98 public: 99 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, 100 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u) 101 : CallFrameSetupOpcode(CFSetupOpcode), 102 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode), 103 ReturnOpcode(ReturnOpcode) {} 104 TargetInstrInfo(const TargetInstrInfo &) = delete; 105 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete; 106 virtual ~TargetInstrInfo(); 107 108 static bool isGenericOpcode(unsigned Opc) { 109 return Opc <= TargetOpcode::GENERIC_OP_END; 110 } 111 112 /// Given a machine instruction descriptor, returns the register 113 /// class constraint for OpNum, or NULL. 114 virtual 115 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 116 const TargetRegisterInfo *TRI, 117 const MachineFunction &MF) const; 118 119 /// Return true if the instruction is trivially rematerializable, meaning it 120 /// has no side effects and requires no operands that aren't always available. 121 /// This means the only allowed uses are constants and unallocatable physical 122 /// registers so that the instructions result is independent of the place 123 /// in the function. 124 bool isTriviallyReMaterializable(const MachineInstr &MI, 125 AAResults *AA = nullptr) const { 126 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF || 127 (MI.getDesc().isRematerializable() && 128 (isReallyTriviallyReMaterializable(MI, AA) || 129 isReallyTriviallyReMaterializableGeneric(MI, AA))); 130 } 131 132 /// Given \p MO is a PhysReg use return if it can be ignored for the purpose 133 /// of instruction rematerialization. 134 virtual bool isIgnorableUse(const MachineOperand &MO) const { 135 return false; 136 } 137 138 protected: 139 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 140 /// set, this hook lets the target specify whether the instruction is actually 141 /// trivially rematerializable, taking into consideration its operands. This 142 /// predicate must return false if the instruction has any side effects other 143 /// than producing a value, or if it requres any address registers that are 144 /// not always available. 145 /// Requirements must be check as stated in isTriviallyReMaterializable() . 146 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 147 AAResults *AA) const { 148 return false; 149 } 150 151 /// This method commutes the operands of the given machine instruction MI. 152 /// The operands to be commuted are specified by their indices OpIdx1 and 153 /// OpIdx2. 154 /// 155 /// If a target has any instructions that are commutable but require 156 /// converting to different instructions or making non-trivial changes 157 /// to commute them, this method can be overloaded to do that. 158 /// The default implementation simply swaps the commutable operands. 159 /// 160 /// If NewMI is false, MI is modified in place and returned; otherwise, a 161 /// new machine instruction is created and returned. 162 /// 163 /// Do not call this method for a non-commutable instruction. 164 /// Even though the instruction is commutable, the method may still 165 /// fail to commute the operands, null pointer is returned in such cases. 166 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 167 unsigned OpIdx1, 168 unsigned OpIdx2) const; 169 170 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable 171 /// operand indices to (ResultIdx1, ResultIdx2). 172 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be 173 /// predefined to some indices or be undefined (designated by the special 174 /// value 'CommuteAnyOperandIndex'). 175 /// The predefined result indices cannot be re-defined. 176 /// The function returns true iff after the result pair redefinition 177 /// the fixed result pair is equal to or equivalent to the source pair of 178 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that 179 /// the pairs (x,y) and (y,x) are equivalent. 180 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, 181 unsigned CommutableOpIdx1, 182 unsigned CommutableOpIdx2); 183 184 private: 185 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 186 /// set and the target hook isReallyTriviallyReMaterializable returns false, 187 /// this function does target-independent tests to determine if the 188 /// instruction is really trivially rematerializable. 189 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI, 190 AAResults *AA) const; 191 192 public: 193 /// These methods return the opcode of the frame setup/destroy instructions 194 /// if they exist (-1 otherwise). Some targets use pseudo instructions in 195 /// order to abstract away the difference between operating with a frame 196 /// pointer and operating without, through the use of these two instructions. 197 /// 198 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 199 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 200 201 /// Returns true if the argument is a frame pseudo instruction. 202 bool isFrameInstr(const MachineInstr &I) const { 203 return I.getOpcode() == getCallFrameSetupOpcode() || 204 I.getOpcode() == getCallFrameDestroyOpcode(); 205 } 206 207 /// Returns true if the argument is a frame setup pseudo instruction. 208 bool isFrameSetup(const MachineInstr &I) const { 209 return I.getOpcode() == getCallFrameSetupOpcode(); 210 } 211 212 /// Returns size of the frame associated with the given frame instruction. 213 /// For frame setup instruction this is frame that is set up space set up 214 /// after the instruction. For frame destroy instruction this is the frame 215 /// freed by the caller. 216 /// Note, in some cases a call frame (or a part of it) may be prepared prior 217 /// to the frame setup instruction. It occurs in the calls that involve 218 /// inalloca arguments. This function reports only the size of the frame part 219 /// that is set up between the frame setup and destroy pseudo instructions. 220 int64_t getFrameSize(const MachineInstr &I) const { 221 assert(isFrameInstr(I) && "Not a frame instruction"); 222 assert(I.getOperand(0).getImm() >= 0); 223 return I.getOperand(0).getImm(); 224 } 225 226 /// Returns the total frame size, which is made up of the space set up inside 227 /// the pair of frame start-stop instructions and the space that is set up 228 /// prior to the pair. 229 int64_t getFrameTotalSize(const MachineInstr &I) const { 230 if (isFrameSetup(I)) { 231 assert(I.getOperand(1).getImm() >= 0 && 232 "Frame size must not be negative"); 233 return getFrameSize(I) + I.getOperand(1).getImm(); 234 } 235 return getFrameSize(I); 236 } 237 238 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; } 239 unsigned getReturnOpcode() const { return ReturnOpcode; } 240 241 /// Returns the actual stack pointer adjustment made by an instruction 242 /// as part of a call sequence. By default, only call frame setup/destroy 243 /// instructions adjust the stack, but targets may want to override this 244 /// to enable more fine-grained adjustment, or adjust by a different value. 245 virtual int getSPAdjust(const MachineInstr &MI) const; 246 247 /// Return true if the instruction is a "coalescable" extension instruction. 248 /// That is, it's like a copy where it's legal for the source to overlap the 249 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's 250 /// expected the pre-extension value is available as a subreg of the result 251 /// register. This also returns the sub-register index in SubIdx. 252 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 253 Register &DstReg, unsigned &SubIdx) const { 254 return false; 255 } 256 257 /// If the specified machine instruction is a direct 258 /// load from a stack slot, return the virtual or physical register number of 259 /// the destination along with the FrameIndex of the loaded stack slot. If 260 /// not, return 0. This predicate must return 0 if the instruction has 261 /// any side effects other than loading from the stack slot. 262 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 263 int &FrameIndex) const { 264 return 0; 265 } 266 267 /// Optional extension of isLoadFromStackSlot that returns the number of 268 /// bytes loaded from the stack. This must be implemented if a backend 269 /// supports partial stack slot spills/loads to further disambiguate 270 /// what the load does. 271 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 272 int &FrameIndex, 273 unsigned &MemBytes) const { 274 MemBytes = 0; 275 return isLoadFromStackSlot(MI, FrameIndex); 276 } 277 278 /// Check for post-frame ptr elimination stack locations as well. 279 /// This uses a heuristic so it isn't reliable for correctness. 280 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 281 int &FrameIndex) const { 282 return 0; 283 } 284 285 /// If the specified machine instruction has a load from a stack slot, 286 /// return true along with the FrameIndices of the loaded stack slot and the 287 /// machine mem operands containing the reference. 288 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for 289 /// any instructions that loads from the stack. This is just a hint, as some 290 /// cases may be missed. 291 virtual bool hasLoadFromStackSlot( 292 const MachineInstr &MI, 293 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 294 295 /// If the specified machine instruction is a direct 296 /// store to a stack slot, return the virtual or physical register number of 297 /// the source reg along with the FrameIndex of the loaded stack slot. If 298 /// not, return 0. This predicate must return 0 if the instruction has 299 /// any side effects other than storing to the stack slot. 300 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 301 int &FrameIndex) const { 302 return 0; 303 } 304 305 /// Optional extension of isStoreToStackSlot that returns the number of 306 /// bytes stored to the stack. This must be implemented if a backend 307 /// supports partial stack slot spills/loads to further disambiguate 308 /// what the store does. 309 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 310 int &FrameIndex, 311 unsigned &MemBytes) const { 312 MemBytes = 0; 313 return isStoreToStackSlot(MI, FrameIndex); 314 } 315 316 /// Check for post-frame ptr elimination stack locations as well. 317 /// This uses a heuristic, so it isn't reliable for correctness. 318 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 319 int &FrameIndex) const { 320 return 0; 321 } 322 323 /// If the specified machine instruction has a store to a stack slot, 324 /// return true along with the FrameIndices of the loaded stack slot and the 325 /// machine mem operands containing the reference. 326 /// If not, return false. Unlike isStoreToStackSlot, 327 /// this returns true for any instructions that stores to the 328 /// stack. This is just a hint, as some cases may be missed. 329 virtual bool hasStoreToStackSlot( 330 const MachineInstr &MI, 331 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 332 333 /// Return true if the specified machine instruction 334 /// is a copy of one stack slot to another and has no other effect. 335 /// Provide the identity of the two frame indices. 336 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, 337 int &SrcFrameIndex) const { 338 return false; 339 } 340 341 /// Compute the size in bytes and offset within a stack slot of a spilled 342 /// register or subregister. 343 /// 344 /// \param [out] Size in bytes of the spilled value. 345 /// \param [out] Offset in bytes within the stack slot. 346 /// \returns true if both Size and Offset are successfully computed. 347 /// 348 /// Not all subregisters have computable spill slots. For example, 349 /// subregisters registers may not be byte-sized, and a pair of discontiguous 350 /// subregisters has no single offset. 351 /// 352 /// Targets with nontrivial bigendian implementations may need to override 353 /// this, particularly to support spilled vector registers. 354 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 355 unsigned &Size, unsigned &Offset, 356 const MachineFunction &MF) const; 357 358 /// Return true if the given instruction is terminator that is unspillable, 359 /// according to isUnspillableTerminatorImpl. 360 bool isUnspillableTerminator(const MachineInstr *MI) const { 361 return MI->isTerminator() && isUnspillableTerminatorImpl(MI); 362 } 363 364 /// Returns the size in bytes of the specified MachineInstr, or ~0U 365 /// when this function is not implemented by a target. 366 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const { 367 return ~0U; 368 } 369 370 /// Return true if the instruction is as cheap as a move instruction. 371 /// 372 /// Targets for different archs need to override this, and different 373 /// micro-architectures can also be finely tuned inside. 374 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const { 375 return MI.isAsCheapAsAMove(); 376 } 377 378 /// Return true if the instruction should be sunk by MachineSink. 379 /// 380 /// MachineSink determines on its own whether the instruction is safe to sink; 381 /// this gives the target a hook to override the default behavior with regards 382 /// to which instructions should be sunk. 383 virtual bool shouldSink(const MachineInstr &MI) const { return true; } 384 385 /// Re-issue the specified 'original' instruction at the 386 /// specific location targeting a new destination register. 387 /// The register in Orig->getOperand(0).getReg() will be substituted by 388 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 389 /// SubIdx. 390 virtual void reMaterialize(MachineBasicBlock &MBB, 391 MachineBasicBlock::iterator MI, Register DestReg, 392 unsigned SubIdx, const MachineInstr &Orig, 393 const TargetRegisterInfo &TRI) const; 394 395 /// Clones instruction or the whole instruction bundle \p Orig and 396 /// insert into \p MBB before \p InsertBefore. The target may update operands 397 /// that are required to be unique. 398 /// 399 /// \p Orig must not return true for MachineInstr::isNotDuplicable(). 400 virtual MachineInstr &duplicate(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator InsertBefore, 402 const MachineInstr &Orig) const; 403 404 /// This method must be implemented by targets that 405 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 406 /// may be able to convert a two-address instruction into one or more true 407 /// three-address instructions on demand. This allows the X86 target (for 408 /// example) to convert ADD and SHL instructions into LEA instructions if they 409 /// would require register copies due to two-addressness. 410 /// 411 /// This method returns a null pointer if the transformation cannot be 412 /// performed, otherwise it returns the last new instruction. 413 /// 414 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 415 MachineInstr &MI, 416 LiveVariables *LV) const { 417 return nullptr; 418 } 419 420 // This constant can be used as an input value of operand index passed to 421 // the method findCommutedOpIndices() to tell the method that the 422 // corresponding operand index is not pre-defined and that the method 423 // can pick any commutable operand. 424 static const unsigned CommuteAnyOperandIndex = ~0U; 425 426 /// This method commutes the operands of the given machine instruction MI. 427 /// 428 /// The operands to be commuted are specified by their indices OpIdx1 and 429 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 430 /// 'CommuteAnyOperandIndex', which means that the method is free to choose 431 /// any arbitrarily chosen commutable operand. If both arguments are set to 432 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable 433 /// operands; then commutes them if such operands could be found. 434 /// 435 /// If NewMI is false, MI is modified in place and returned; otherwise, a 436 /// new machine instruction is created and returned. 437 /// 438 /// Do not call this method for a non-commutable instruction or 439 /// for non-commuable operands. 440 /// Even though the instruction is commutable, the method may still 441 /// fail to commute the operands, null pointer is returned in such cases. 442 MachineInstr * 443 commuteInstruction(MachineInstr &MI, bool NewMI = false, 444 unsigned OpIdx1 = CommuteAnyOperandIndex, 445 unsigned OpIdx2 = CommuteAnyOperandIndex) const; 446 447 /// Returns true iff the routine could find two commutable operands in the 448 /// given machine instruction. 449 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. 450 /// If any of the INPUT values is set to the special value 451 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable 452 /// operand, then returns its index in the corresponding argument. 453 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method 454 /// looks for 2 commutable operands. 455 /// If INPUT values refer to some operands of MI, then the method simply 456 /// returns true if the corresponding operands are commutable and returns 457 /// false otherwise. 458 /// 459 /// For example, calling this method this way: 460 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 461 /// findCommutedOpIndices(MI, Op1, Op2); 462 /// can be interpreted as a query asking to find an operand that would be 463 /// commutable with the operand#1. 464 virtual bool findCommutedOpIndices(const MachineInstr &MI, 465 unsigned &SrcOpIdx1, 466 unsigned &SrcOpIdx2) const; 467 468 /// Returns true if the target has a preference on the operands order of 469 /// the given machine instruction. And specify if \p Commute is required to 470 /// get the desired operands order. 471 virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const { 472 return false; 473 } 474 475 /// A pair composed of a register and a sub-register index. 476 /// Used to give some type checking when modeling Reg:SubReg. 477 struct RegSubRegPair { 478 Register Reg; 479 unsigned SubReg; 480 481 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0) 482 : Reg(Reg), SubReg(SubReg) {} 483 484 bool operator==(const RegSubRegPair& P) const { 485 return Reg == P.Reg && SubReg == P.SubReg; 486 } 487 bool operator!=(const RegSubRegPair& P) const { 488 return !(*this == P); 489 } 490 }; 491 492 /// A pair composed of a pair of a register and a sub-register index, 493 /// and another sub-register index. 494 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2. 495 struct RegSubRegPairAndIdx : RegSubRegPair { 496 unsigned SubIdx; 497 498 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0, 499 unsigned SubIdx = 0) 500 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} 501 }; 502 503 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 504 /// and \p DefIdx. 505 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 506 /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef 507 /// flag are not added to this list. 508 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 509 /// two elements: 510 /// - %1:sub1, sub0 511 /// - %2<:0>, sub1 512 /// 513 /// \returns true if it is possible to build such an input sequence 514 /// with the pair \p MI, \p DefIdx. False otherwise. 515 /// 516 /// \pre MI.isRegSequence() or MI.isRegSequenceLike(). 517 /// 518 /// \note The generic implementation does not provide any support for 519 /// MI.isRegSequenceLike(). In other words, one has to override 520 /// getRegSequenceLikeInputs for target specific instructions. 521 bool 522 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, 523 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const; 524 525 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 526 /// and \p DefIdx. 527 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 528 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 529 /// - %1:sub1, sub0 530 /// 531 /// \returns true if it is possible to build such an input sequence 532 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 533 /// False otherwise. 534 /// 535 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). 536 /// 537 /// \note The generic implementation does not provide any support for 538 /// MI.isExtractSubregLike(). In other words, one has to override 539 /// getExtractSubregLikeInputs for target specific instructions. 540 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, 541 RegSubRegPairAndIdx &InputReg) const; 542 543 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 544 /// and \p DefIdx. 545 /// \p [out] BaseReg and \p [out] InsertedReg contain 546 /// the equivalent inputs of INSERT_SUBREG. 547 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 548 /// - BaseReg: %0:sub0 549 /// - InsertedReg: %1:sub1, sub3 550 /// 551 /// \returns true if it is possible to build such an input sequence 552 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 553 /// False otherwise. 554 /// 555 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). 556 /// 557 /// \note The generic implementation does not provide any support for 558 /// MI.isInsertSubregLike(). In other words, one has to override 559 /// getInsertSubregLikeInputs for target specific instructions. 560 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, 561 RegSubRegPair &BaseReg, 562 RegSubRegPairAndIdx &InsertedReg) const; 563 564 /// Return true if two machine instructions would produce identical values. 565 /// By default, this is only true when the two instructions 566 /// are deemed identical except for defs. If this function is called when the 567 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 568 /// aggressive checks. 569 virtual bool produceSameValue(const MachineInstr &MI0, 570 const MachineInstr &MI1, 571 const MachineRegisterInfo *MRI = nullptr) const; 572 573 /// \returns true if a branch from an instruction with opcode \p BranchOpc 574 /// bytes is capable of jumping to a position \p BrOffset bytes away. 575 virtual bool isBranchOffsetInRange(unsigned BranchOpc, 576 int64_t BrOffset) const { 577 llvm_unreachable("target did not implement"); 578 } 579 580 /// \returns The block that branch instruction \p MI jumps to. 581 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const { 582 llvm_unreachable("target did not implement"); 583 } 584 585 /// Insert an unconditional indirect branch at the end of \p MBB to \p 586 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to 587 /// the offset of the position to insert the new branch. 588 /// 589 /// \returns The number of bytes added to the block. 590 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, 591 MachineBasicBlock &NewDestBB, 592 const DebugLoc &DL, 593 int64_t BrOffset = 0, 594 RegScavenger *RS = nullptr) const { 595 llvm_unreachable("target did not implement"); 596 } 597 598 /// Analyze the branching code at the end of MBB, returning 599 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 600 /// implemented for a target). Upon success, this returns false and returns 601 /// with the following information in various cases: 602 /// 603 /// 1. If this block ends with no branches (it just falls through to its succ) 604 /// just return false, leaving TBB/FBB null. 605 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 606 /// the destination block. 607 /// 3. If this block ends with a conditional branch and it falls through to a 608 /// successor block, it sets TBB to be the branch destination block and a 609 /// list of operands that evaluate the condition. These operands can be 610 /// passed to other TargetInstrInfo methods to create new branches. 611 /// 4. If this block ends with a conditional branch followed by an 612 /// unconditional branch, it returns the 'true' destination in TBB, the 613 /// 'false' destination in FBB, and a list of operands that evaluate the 614 /// condition. These operands can be passed to other TargetInstrInfo 615 /// methods to create new branches. 616 /// 617 /// Note that removeBranch and insertBranch must be implemented to support 618 /// cases where this method returns success. 619 /// 620 /// If AllowModify is true, then this routine is allowed to modify the basic 621 /// block (e.g. delete instructions after the unconditional branch). 622 /// 623 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 624 /// before calling this function. 625 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 626 MachineBasicBlock *&FBB, 627 SmallVectorImpl<MachineOperand> &Cond, 628 bool AllowModify = false) const { 629 return true; 630 } 631 632 /// Represents a predicate at the MachineFunction level. The control flow a 633 /// MachineBranchPredicate represents is: 634 /// 635 /// Reg = LHS `Predicate` RHS == ConditionDef 636 /// if Reg then goto TrueDest else goto FalseDest 637 /// 638 struct MachineBranchPredicate { 639 enum ComparePredicate { 640 PRED_EQ, // True if two values are equal 641 PRED_NE, // True if two values are not equal 642 PRED_INVALID // Sentinel value 643 }; 644 645 ComparePredicate Predicate = PRED_INVALID; 646 MachineOperand LHS = MachineOperand::CreateImm(0); 647 MachineOperand RHS = MachineOperand::CreateImm(0); 648 MachineBasicBlock *TrueDest = nullptr; 649 MachineBasicBlock *FalseDest = nullptr; 650 MachineInstr *ConditionDef = nullptr; 651 652 /// SingleUseCondition is true if ConditionDef is dead except for the 653 /// branch(es) at the end of the basic block. 654 /// 655 bool SingleUseCondition = false; 656 657 explicit MachineBranchPredicate() = default; 658 }; 659 660 /// Analyze the branching code at the end of MBB and parse it into the 661 /// MachineBranchPredicate structure if possible. Returns false on success 662 /// and true on failure. 663 /// 664 /// If AllowModify is true, then this routine is allowed to modify the basic 665 /// block (e.g. delete instructions after the unconditional branch). 666 /// 667 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, 668 MachineBranchPredicate &MBP, 669 bool AllowModify = false) const { 670 return true; 671 } 672 673 /// Remove the branching code at the end of the specific MBB. 674 /// This is only invoked in cases where analyzeBranch returns success. It 675 /// returns the number of instructions that were removed. 676 /// If \p BytesRemoved is non-null, report the change in code size from the 677 /// removed instructions. 678 virtual unsigned removeBranch(MachineBasicBlock &MBB, 679 int *BytesRemoved = nullptr) const { 680 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!"); 681 } 682 683 /// Insert branch code into the end of the specified MachineBasicBlock. The 684 /// operands to this method are the same as those returned by analyzeBranch. 685 /// This is only invoked in cases where analyzeBranch returns success. It 686 /// returns the number of instructions inserted. If \p BytesAdded is non-null, 687 /// report the change in code size from the added instructions. 688 /// 689 /// It is also invoked by tail merging to add unconditional branches in 690 /// cases where analyzeBranch doesn't apply because there was no original 691 /// branch to analyze. At least this much must be implemented, else tail 692 /// merging needs to be disabled. 693 /// 694 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 695 /// before calling this function. 696 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 697 MachineBasicBlock *FBB, 698 ArrayRef<MachineOperand> Cond, 699 const DebugLoc &DL, 700 int *BytesAdded = nullptr) const { 701 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!"); 702 } 703 704 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, 705 MachineBasicBlock *DestBB, 706 const DebugLoc &DL, 707 int *BytesAdded = nullptr) const { 708 return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL, 709 BytesAdded); 710 } 711 712 /// Object returned by analyzeLoopForPipelining. Allows software pipelining 713 /// implementations to query attributes of the loop being pipelined and to 714 /// apply target-specific updates to the loop once pipelining is complete. 715 class PipelinerLoopInfo { 716 public: 717 virtual ~PipelinerLoopInfo(); 718 /// Return true if the given instruction should not be pipelined and should 719 /// be ignored. An example could be a loop comparison, or induction variable 720 /// update with no users being pipelined. 721 virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0; 722 723 /// Create a condition to determine if the trip count of the loop is greater 724 /// than TC. 725 /// 726 /// If the trip count is statically known to be greater than TC, return 727 /// true. If the trip count is statically known to be not greater than TC, 728 /// return false. Otherwise return nullopt and fill out Cond with the test 729 /// condition. 730 virtual Optional<bool> 731 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, 732 SmallVectorImpl<MachineOperand> &Cond) = 0; 733 734 /// Modify the loop such that the trip count is 735 /// OriginalTC + TripCountAdjust. 736 virtual void adjustTripCount(int TripCountAdjust) = 0; 737 738 /// Called when the loop's preheader has been modified to NewPreheader. 739 virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0; 740 741 /// Called when the loop is being removed. Any instructions in the preheader 742 /// should be removed. 743 /// 744 /// Once this function is called, no other functions on this object are 745 /// valid; the loop has been removed. 746 virtual void disposed() = 0; 747 }; 748 749 /// Analyze loop L, which must be a single-basic-block loop, and if the 750 /// conditions can be understood enough produce a PipelinerLoopInfo object. 751 virtual std::unique_ptr<PipelinerLoopInfo> 752 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { 753 return nullptr; 754 } 755 756 /// Analyze the loop code, return true if it cannot be understood. Upon 757 /// success, this function returns false and returns information about the 758 /// induction variable and compare instruction used at the end. 759 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, 760 MachineInstr *&CmpInst) const { 761 return true; 762 } 763 764 /// Generate code to reduce the loop iteration by one and check if the loop 765 /// is finished. Return the value/register of the new loop count. We need 766 /// this function when peeling off one or more iterations of a loop. This 767 /// function assumes the nth iteration is peeled first. 768 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, 769 MachineBasicBlock &PreHeader, 770 MachineInstr *IndVar, MachineInstr &Cmp, 771 SmallVectorImpl<MachineOperand> &Cond, 772 SmallVectorImpl<MachineInstr *> &PrevInsts, 773 unsigned Iter, unsigned MaxIter) const { 774 llvm_unreachable("Target didn't implement ReduceLoopCount"); 775 } 776 777 /// Delete the instruction OldInst and everything after it, replacing it with 778 /// an unconditional branch to NewDest. This is used by the tail merging pass. 779 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 780 MachineBasicBlock *NewDest) const; 781 782 /// Return true if it's legal to split the given basic 783 /// block at the specified instruction (i.e. instruction would be the start 784 /// of a new basic block). 785 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 786 MachineBasicBlock::iterator MBBI) const { 787 return true; 788 } 789 790 /// Return true if it's profitable to predicate 791 /// instructions with accumulated instruction latency of "NumCycles" 792 /// of the specified basic block, where the probability of the instructions 793 /// being executed is given by Probability, and Confidence is a measure 794 /// of our confidence that it will be properly predicted. 795 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 796 unsigned ExtraPredCycles, 797 BranchProbability Probability) const { 798 return false; 799 } 800 801 /// Second variant of isProfitableToIfCvt. This one 802 /// checks for the case where two basic blocks from true and false path 803 /// of a if-then-else (diamond) are predicated on mutually exclusive 804 /// predicates, where the probability of the true path being taken is given 805 /// by Probability, and Confidence is a measure of our confidence that it 806 /// will be properly predicted. 807 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, 808 unsigned ExtraTCycles, 809 MachineBasicBlock &FMBB, unsigned NumFCycles, 810 unsigned ExtraFCycles, 811 BranchProbability Probability) const { 812 return false; 813 } 814 815 /// Return true if it's profitable for if-converter to duplicate instructions 816 /// of specified accumulated instruction latencies in the specified MBB to 817 /// enable if-conversion. 818 /// The probability of the instructions being executed is given by 819 /// Probability, and Confidence is a measure of our confidence that it 820 /// will be properly predicted. 821 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 822 unsigned NumCycles, 823 BranchProbability Probability) const { 824 return false; 825 } 826 827 /// Return the increase in code size needed to predicate a contiguous run of 828 /// NumInsts instructions. 829 virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 830 unsigned NumInsts) const { 831 return 0; 832 } 833 834 /// Return an estimate for the code size reduction (in bytes) which will be 835 /// caused by removing the given branch instruction during if-conversion. 836 virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const { 837 return getInstSizeInBytes(MI); 838 } 839 840 /// Return true if it's profitable to unpredicate 841 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 842 /// exclusive predicates. 843 /// e.g. 844 /// subeq r0, r1, #1 845 /// addne r0, r1, #1 846 /// => 847 /// sub r0, r1, #1 848 /// addne r0, r1, #1 849 /// 850 /// This may be profitable is conditional instructions are always executed. 851 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 852 MachineBasicBlock &FMBB) const { 853 return false; 854 } 855 856 /// Return true if it is possible to insert a select 857 /// instruction that chooses between TrueReg and FalseReg based on the 858 /// condition code in Cond. 859 /// 860 /// When successful, also return the latency in cycles from TrueReg, 861 /// FalseReg, and Cond to the destination register. In most cases, a select 862 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 863 /// 864 /// Some x86 implementations have 2-cycle cmov instructions. 865 /// 866 /// @param MBB Block where select instruction would be inserted. 867 /// @param Cond Condition returned by analyzeBranch. 868 /// @param DstReg Virtual dest register that the result should write to. 869 /// @param TrueReg Virtual register to select when Cond is true. 870 /// @param FalseReg Virtual register to select when Cond is false. 871 /// @param CondCycles Latency from Cond+Branch to select output. 872 /// @param TrueCycles Latency from TrueReg to select output. 873 /// @param FalseCycles Latency from FalseReg to select output. 874 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 875 ArrayRef<MachineOperand> Cond, Register DstReg, 876 Register TrueReg, Register FalseReg, 877 int &CondCycles, int &TrueCycles, 878 int &FalseCycles) const { 879 return false; 880 } 881 882 /// Insert a select instruction into MBB before I that will copy TrueReg to 883 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. 884 /// 885 /// This function can only be called after canInsertSelect() returned true. 886 /// The condition in Cond comes from analyzeBranch, and it can be assumed 887 /// that the same flags or registers required by Cond are available at the 888 /// insertion point. 889 /// 890 /// @param MBB Block where select instruction should be inserted. 891 /// @param I Insertion point. 892 /// @param DL Source location for debugging. 893 /// @param DstReg Virtual register to be defined by select instruction. 894 /// @param Cond Condition as computed by analyzeBranch. 895 /// @param TrueReg Virtual register to copy when Cond is true. 896 /// @param FalseReg Virtual register to copy when Cons is false. 897 virtual void insertSelect(MachineBasicBlock &MBB, 898 MachineBasicBlock::iterator I, const DebugLoc &DL, 899 Register DstReg, ArrayRef<MachineOperand> Cond, 900 Register TrueReg, Register FalseReg) const { 901 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 902 } 903 904 /// Analyze the given select instruction, returning true if 905 /// it cannot be understood. It is assumed that MI->isSelect() is true. 906 /// 907 /// When successful, return the controlling condition and the operands that 908 /// determine the true and false result values. 909 /// 910 /// Result = SELECT Cond, TrueOp, FalseOp 911 /// 912 /// Some targets can optimize select instructions, for example by predicating 913 /// the instruction defining one of the operands. Such targets should set 914 /// Optimizable. 915 /// 916 /// @param MI Select instruction to analyze. 917 /// @param Cond Condition controlling the select. 918 /// @param TrueOp Operand number of the value selected when Cond is true. 919 /// @param FalseOp Operand number of the value selected when Cond is false. 920 /// @param Optimizable Returned as true if MI is optimizable. 921 /// @returns False on success. 922 virtual bool analyzeSelect(const MachineInstr &MI, 923 SmallVectorImpl<MachineOperand> &Cond, 924 unsigned &TrueOp, unsigned &FalseOp, 925 bool &Optimizable) const { 926 assert(MI.getDesc().isSelect() && "MI must be a select instruction"); 927 return true; 928 } 929 930 /// Given a select instruction that was understood by 931 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 932 /// merging it with one of its operands. Returns NULL on failure. 933 /// 934 /// When successful, returns the new select instruction. The client is 935 /// responsible for deleting MI. 936 /// 937 /// If both sides of the select can be optimized, PreferFalse is used to pick 938 /// a side. 939 /// 940 /// @param MI Optimizable select instruction. 941 /// @param NewMIs Set that record all MIs in the basic block up to \p 942 /// MI. Has to be updated with any newly created MI or deleted ones. 943 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 944 /// @returns Optimized instruction or NULL. 945 virtual MachineInstr *optimizeSelect(MachineInstr &MI, 946 SmallPtrSetImpl<MachineInstr *> &NewMIs, 947 bool PreferFalse = false) const { 948 // This function must be implemented if Optimizable is ever set. 949 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 950 } 951 952 /// Emit instructions to copy a pair of physical registers. 953 /// 954 /// This function should support copies within any legal register class as 955 /// well as any cross-class copies created during instruction selection. 956 /// 957 /// The source and destination registers may overlap, which may require a 958 /// careful implementation when multiple copy instructions are required for 959 /// large registers. See for example the ARM target. 960 virtual void copyPhysReg(MachineBasicBlock &MBB, 961 MachineBasicBlock::iterator MI, const DebugLoc &DL, 962 MCRegister DestReg, MCRegister SrcReg, 963 bool KillSrc) const { 964 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 965 } 966 967 /// Allow targets to tell MachineVerifier whether a specific register 968 /// MachineOperand can be used as part of PC-relative addressing. 969 /// PC-relative addressing modes in many CISC architectures contain 970 /// (non-PC) registers as offsets or scaling values, which inherently 971 /// tags the corresponding MachineOperand with OPERAND_PCREL. 972 /// 973 /// @param MO The MachineOperand in question. MO.isReg() should always 974 /// be true. 975 /// @return Whether this operand is allowed to be used PC-relatively. 976 virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const { 977 return false; 978 } 979 980 protected: 981 /// Target-dependent implementation for IsCopyInstr. 982 /// If the specific machine instruction is a instruction that moves/copies 983 /// value from one register to another register return destination and source 984 /// registers as machine operands. 985 virtual Optional<DestSourcePair> 986 isCopyInstrImpl(const MachineInstr &MI) const { 987 return None; 988 } 989 990 /// Return true if the given terminator MI is not expected to spill. This 991 /// sets the live interval as not spillable and adjusts phi node lowering to 992 /// not introduce copies after the terminator. Use with care, these are 993 /// currently used for hardware loop intrinsics in very controlled situations, 994 /// created prior to registry allocation in loops that only have single phi 995 /// users for the terminators value. They may run out of registers if not used 996 /// carefully. 997 virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const { 998 return false; 999 } 1000 1001 public: 1002 /// If the specific machine instruction is a instruction that moves/copies 1003 /// value from one register to another register return destination and source 1004 /// registers as machine operands. 1005 /// For COPY-instruction the method naturally returns destination and source 1006 /// registers as machine operands, for all other instructions the method calls 1007 /// target-dependent implementation. 1008 Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const { 1009 if (MI.isCopy()) { 1010 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 1011 } 1012 return isCopyInstrImpl(MI); 1013 } 1014 1015 /// If the specific machine instruction is an instruction that adds an 1016 /// immediate value and a physical register, and stores the result in 1017 /// the given physical register \c Reg, return a pair of the source 1018 /// register and the offset which has been added. 1019 virtual Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 1020 Register Reg) const { 1021 return None; 1022 } 1023 1024 /// Returns true if MI is an instruction that defines Reg to have a constant 1025 /// value and the value is recorded in ImmVal. The ImmVal is a result that 1026 /// should be interpreted as modulo size of Reg. 1027 virtual bool getConstValDefinedInReg(const MachineInstr &MI, 1028 const Register Reg, 1029 int64_t &ImmVal) const { 1030 return false; 1031 } 1032 1033 /// Store the specified register of the given register class to the specified 1034 /// stack frame index. The store instruction is to be added to the given 1035 /// machine basic block before the specified machine instruction. If isKill 1036 /// is true, the register operand is the last use and must be marked kill. 1037 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 1038 MachineBasicBlock::iterator MI, 1039 Register SrcReg, bool isKill, int FrameIndex, 1040 const TargetRegisterClass *RC, 1041 const TargetRegisterInfo *TRI) const { 1042 llvm_unreachable("Target didn't implement " 1043 "TargetInstrInfo::storeRegToStackSlot!"); 1044 } 1045 1046 /// Load the specified register of the given register class from the specified 1047 /// stack frame index. The load instruction is to be added to the given 1048 /// machine basic block before the specified machine instruction. 1049 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 1050 MachineBasicBlock::iterator MI, 1051 Register DestReg, int FrameIndex, 1052 const TargetRegisterClass *RC, 1053 const TargetRegisterInfo *TRI) const { 1054 llvm_unreachable("Target didn't implement " 1055 "TargetInstrInfo::loadRegFromStackSlot!"); 1056 } 1057 1058 /// This function is called for all pseudo instructions 1059 /// that remain after register allocation. Many pseudo instructions are 1060 /// created to help register allocation. This is the place to convert them 1061 /// into real instructions. The target can edit MI in place, or it can insert 1062 /// new instructions and erase MI. The function should return true if 1063 /// anything was changed. 1064 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; } 1065 1066 /// Check whether the target can fold a load that feeds a subreg operand 1067 /// (or a subreg operand that feeds a store). 1068 /// For example, X86 may want to return true if it can fold 1069 /// movl (%esp), %eax 1070 /// subb, %al, ... 1071 /// Into: 1072 /// subb (%esp), ... 1073 /// 1074 /// Ideally, we'd like the target implementation of foldMemoryOperand() to 1075 /// reject subregs - but since this behavior used to be enforced in the 1076 /// target-independent code, moving this responsibility to the targets 1077 /// has the potential of causing nasty silent breakage in out-of-tree targets. 1078 virtual bool isSubregFoldable() const { return false; } 1079 1080 /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of 1081 /// operands which can't be folded into stack references. Operands outside 1082 /// of the range are most likely foldable but it is not guaranteed. 1083 /// These instructions are unique in that stack references for some operands 1084 /// have the same execution cost (e.g. none) as the unfolded register forms. 1085 /// The ranged return is guaranteed to include all operands which can't be 1086 /// folded at zero cost. 1087 virtual std::pair<unsigned, unsigned> 1088 getPatchpointUnfoldableRange(const MachineInstr &MI) const; 1089 1090 /// Attempt to fold a load or store of the specified stack 1091 /// slot into the specified machine instruction for the specified operand(s). 1092 /// If this is possible, a new instruction is returned with the specified 1093 /// operand folded, otherwise NULL is returned. 1094 /// The new instruction is inserted before MI, and the client is responsible 1095 /// for removing the old instruction. 1096 /// If VRM is passed, the assigned physregs can be inspected by target to 1097 /// decide on using an opcode (note that those assignments can still change). 1098 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1099 int FI, 1100 LiveIntervals *LIS = nullptr, 1101 VirtRegMap *VRM = nullptr) const; 1102 1103 /// Same as the previous version except it allows folding of any load and 1104 /// store from / to any address, not just from a specific stack slot. 1105 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1106 MachineInstr &LoadMI, 1107 LiveIntervals *LIS = nullptr) const; 1108 1109 /// Return true when there is potentially a faster code sequence 1110 /// for an instruction chain ending in \p Root. All potential patterns are 1111 /// returned in the \p Pattern vector. Pattern should be sorted in priority 1112 /// order since the pattern evaluator stops checking as soon as it finds a 1113 /// faster sequence. 1114 /// \param Root - Instruction that could be combined with one of its operands 1115 /// \param Patterns - Vector of possible combination patterns 1116 virtual bool 1117 getMachineCombinerPatterns(MachineInstr &Root, 1118 SmallVectorImpl<MachineCombinerPattern> &Patterns, 1119 bool DoRegPressureReduce) const; 1120 1121 /// Return true if target supports reassociation of instructions in machine 1122 /// combiner pass to reduce register pressure for a given BB. 1123 virtual bool 1124 shouldReduceRegisterPressure(MachineBasicBlock *MBB, 1125 RegisterClassInfo *RegClassInfo) const { 1126 return false; 1127 } 1128 1129 /// Fix up the placeholder we may add in genAlternativeCodeSequence(). 1130 virtual void 1131 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 1132 SmallVectorImpl<MachineInstr *> &InsInstrs) const {} 1133 1134 /// Return true when a code sequence can improve throughput. It 1135 /// should be called only for instructions in loops. 1136 /// \param Pattern - combiner pattern 1137 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const; 1138 1139 /// Return true if the input \P Inst is part of a chain of dependent ops 1140 /// that are suitable for reassociation, otherwise return false. 1141 /// If the instruction's operands must be commuted to have a previous 1142 /// instruction of the same type define the first source operand, \P Commuted 1143 /// will be set to true. 1144 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const; 1145 1146 /// Return true when \P Inst is both associative and commutative. 1147 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const { 1148 return false; 1149 } 1150 1151 /// Return true when \P Inst has reassociable operands in the same \P MBB. 1152 virtual bool hasReassociableOperands(const MachineInstr &Inst, 1153 const MachineBasicBlock *MBB) const; 1154 1155 /// Return true when \P Inst has reassociable sibling. 1156 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const; 1157 1158 /// When getMachineCombinerPatterns() finds patterns, this function generates 1159 /// the instructions that could replace the original code sequence. The client 1160 /// has to decide whether the actual replacement is beneficial or not. 1161 /// \param Root - Instruction that could be combined with one of its operands 1162 /// \param Pattern - Combination pattern for Root 1163 /// \param InsInstrs - Vector of new instructions that implement P 1164 /// \param DelInstrs - Old instructions, including Root, that could be 1165 /// replaced by InsInstr 1166 /// \param InstIdxForVirtReg - map of virtual register to instruction in 1167 /// InsInstr that defines it 1168 virtual void genAlternativeCodeSequence( 1169 MachineInstr &Root, MachineCombinerPattern Pattern, 1170 SmallVectorImpl<MachineInstr *> &InsInstrs, 1171 SmallVectorImpl<MachineInstr *> &DelInstrs, 1172 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const; 1173 1174 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to 1175 /// reduce critical path length. 1176 void reassociateOps(MachineInstr &Root, MachineInstr &Prev, 1177 MachineCombinerPattern Pattern, 1178 SmallVectorImpl<MachineInstr *> &InsInstrs, 1179 SmallVectorImpl<MachineInstr *> &DelInstrs, 1180 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 1181 1182 /// The limit on resource length extension we accept in MachineCombiner Pass. 1183 virtual int getExtendResourceLenLimit() const { return 0; } 1184 1185 /// This is an architecture-specific helper function of reassociateOps. 1186 /// Set special operand attributes for new instructions after reassociation. 1187 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 1188 MachineInstr &NewMI1, 1189 MachineInstr &NewMI2) const {} 1190 1191 virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const {} 1192 1193 /// Return true when a target supports MachineCombiner. 1194 virtual bool useMachineCombiner() const { return false; } 1195 1196 /// Return true if the given SDNode can be copied during scheduling 1197 /// even if it has glue. 1198 virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; } 1199 1200 protected: 1201 /// Target-dependent implementation for foldMemoryOperand. 1202 /// Target-independent code in foldMemoryOperand will 1203 /// take care of adding a MachineMemOperand to the newly created instruction. 1204 /// The instruction and any auxiliary instructions necessary will be inserted 1205 /// at InsertPt. 1206 virtual MachineInstr * 1207 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 1208 ArrayRef<unsigned> Ops, 1209 MachineBasicBlock::iterator InsertPt, int FrameIndex, 1210 LiveIntervals *LIS = nullptr, 1211 VirtRegMap *VRM = nullptr) const { 1212 return nullptr; 1213 } 1214 1215 /// Target-dependent implementation for foldMemoryOperand. 1216 /// Target-independent code in foldMemoryOperand will 1217 /// take care of adding a MachineMemOperand to the newly created instruction. 1218 /// The instruction and any auxiliary instructions necessary will be inserted 1219 /// at InsertPt. 1220 virtual MachineInstr *foldMemoryOperandImpl( 1221 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 1222 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 1223 LiveIntervals *LIS = nullptr) const { 1224 return nullptr; 1225 } 1226 1227 /// Target-dependent implementation of getRegSequenceInputs. 1228 /// 1229 /// \returns true if it is possible to build the equivalent 1230 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise. 1231 /// 1232 /// \pre MI.isRegSequenceLike(). 1233 /// 1234 /// \see TargetInstrInfo::getRegSequenceInputs. 1235 virtual bool getRegSequenceLikeInputs( 1236 const MachineInstr &MI, unsigned DefIdx, 1237 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { 1238 return false; 1239 } 1240 1241 /// Target-dependent implementation of getExtractSubregInputs. 1242 /// 1243 /// \returns true if it is possible to build the equivalent 1244 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1245 /// 1246 /// \pre MI.isExtractSubregLike(). 1247 /// 1248 /// \see TargetInstrInfo::getExtractSubregInputs. 1249 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, 1250 unsigned DefIdx, 1251 RegSubRegPairAndIdx &InputReg) const { 1252 return false; 1253 } 1254 1255 /// Target-dependent implementation of getInsertSubregInputs. 1256 /// 1257 /// \returns true if it is possible to build the equivalent 1258 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1259 /// 1260 /// \pre MI.isInsertSubregLike(). 1261 /// 1262 /// \see TargetInstrInfo::getInsertSubregInputs. 1263 virtual bool 1264 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 1265 RegSubRegPair &BaseReg, 1266 RegSubRegPairAndIdx &InsertedReg) const { 1267 return false; 1268 } 1269 1270 public: 1271 /// getAddressSpaceForPseudoSourceKind - Given the kind of memory 1272 /// (e.g. stack) the target returns the corresponding address space. 1273 virtual unsigned 1274 getAddressSpaceForPseudoSourceKind(unsigned Kind) const { 1275 return 0; 1276 } 1277 1278 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 1279 /// a store or a load and a store into two or more instruction. If this is 1280 /// possible, returns true as well as the new instructions by reference. 1281 virtual bool 1282 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 1283 bool UnfoldLoad, bool UnfoldStore, 1284 SmallVectorImpl<MachineInstr *> &NewMIs) const { 1285 return false; 1286 } 1287 1288 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 1289 SmallVectorImpl<SDNode *> &NewNodes) const { 1290 return false; 1291 } 1292 1293 /// Returns the opcode of the would be new 1294 /// instruction after load / store are unfolded from an instruction of the 1295 /// specified opcode. It returns zero if the specified unfolding is not 1296 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 1297 /// index of the operand which will hold the register holding the loaded 1298 /// value. 1299 virtual unsigned 1300 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 1301 unsigned *LoadRegIndex = nullptr) const { 1302 return 0; 1303 } 1304 1305 /// This is used by the pre-regalloc scheduler to determine if two loads are 1306 /// loading from the same base address. It should only return true if the base 1307 /// pointers are the same and the only differences between the two addresses 1308 /// are the offset. It also returns the offsets by reference. 1309 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1310 int64_t &Offset1, 1311 int64_t &Offset2) const { 1312 return false; 1313 } 1314 1315 /// This is a used by the pre-regalloc scheduler to determine (in conjunction 1316 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together. 1317 /// On some targets if two loads are loading from 1318 /// addresses in the same cache line, it's better if they are scheduled 1319 /// together. This function takes two integers that represent the load offsets 1320 /// from the common base address. It returns true if it decides it's desirable 1321 /// to schedule the two loads together. "NumLoads" is the number of loads that 1322 /// have already been scheduled after Load1. 1323 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1324 int64_t Offset1, int64_t Offset2, 1325 unsigned NumLoads) const { 1326 return false; 1327 } 1328 1329 /// Get the base operand and byte offset of an instruction that reads/writes 1330 /// memory. This is a convenience function for callers that are only prepared 1331 /// to handle a single base operand. 1332 bool getMemOperandWithOffset(const MachineInstr &MI, 1333 const MachineOperand *&BaseOp, int64_t &Offset, 1334 bool &OffsetIsScalable, 1335 const TargetRegisterInfo *TRI) const; 1336 1337 /// Get zero or more base operands and the byte offset of an instruction that 1338 /// reads/writes memory. Note that there may be zero base operands if the 1339 /// instruction accesses a constant address. 1340 /// It returns false if MI does not read/write memory. 1341 /// It returns false if base operands and offset could not be determined. 1342 /// It is not guaranteed to always recognize base operands and offsets in all 1343 /// cases. 1344 virtual bool getMemOperandsWithOffsetWidth( 1345 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, 1346 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 1347 const TargetRegisterInfo *TRI) const { 1348 return false; 1349 } 1350 1351 /// Return true if the instruction contains a base register and offset. If 1352 /// true, the function also sets the operand position in the instruction 1353 /// for the base register and offset. 1354 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, 1355 unsigned &BasePos, 1356 unsigned &OffsetPos) const { 1357 return false; 1358 } 1359 1360 /// Target dependent implementation to get the values constituting the address 1361 /// MachineInstr that is accessing memory. These values are returned as a 1362 /// struct ExtAddrMode which contains all relevant information to make up the 1363 /// address. 1364 virtual Optional<ExtAddrMode> 1365 getAddrModeFromMemoryOp(const MachineInstr &MemI, 1366 const TargetRegisterInfo *TRI) const { 1367 return None; 1368 } 1369 1370 /// Returns true if MI's Def is NullValueReg, and the MI 1371 /// does not change the Zero value. i.e. cases such as rax = shr rax, X where 1372 /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this 1373 /// function can return true even if becomes zero. Specifically cases such as 1374 /// NullValueReg = shl NullValueReg, 63. 1375 virtual bool preservesZeroValueInReg(const MachineInstr *MI, 1376 const Register NullValueReg, 1377 const TargetRegisterInfo *TRI) const { 1378 return false; 1379 } 1380 1381 /// If the instruction is an increment of a constant value, return the amount. 1382 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const { 1383 return false; 1384 } 1385 1386 /// Returns true if the two given memory operations should be scheduled 1387 /// adjacent. Note that you have to add: 1388 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 1389 /// or 1390 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 1391 /// to TargetPassConfig::createMachineScheduler() to have an effect. 1392 /// 1393 /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations. 1394 /// \p NumLoads is the number of loads that will be in the cluster if this 1395 /// hook returns true. 1396 /// \p NumBytes is the number of bytes that will be loaded from all the 1397 /// clustered loads if this hook returns true. 1398 virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 1399 ArrayRef<const MachineOperand *> BaseOps2, 1400 unsigned NumLoads, unsigned NumBytes) const { 1401 llvm_unreachable("target did not implement shouldClusterMemOps()"); 1402 } 1403 1404 /// Reverses the branch condition of the specified condition list, 1405 /// returning false on success and true if it cannot be reversed. 1406 virtual bool 1407 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 1408 return true; 1409 } 1410 1411 /// Insert a noop into the instruction stream at the specified point. 1412 virtual void insertNoop(MachineBasicBlock &MBB, 1413 MachineBasicBlock::iterator MI) const; 1414 1415 /// Insert noops into the instruction stream at the specified point. 1416 virtual void insertNoops(MachineBasicBlock &MBB, 1417 MachineBasicBlock::iterator MI, 1418 unsigned Quantity) const; 1419 1420 /// Return the noop instruction to use for a noop. 1421 virtual MCInst getNop() const; 1422 1423 /// Return true for post-incremented instructions. 1424 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; } 1425 1426 /// Returns true if the instruction is already predicated. 1427 virtual bool isPredicated(const MachineInstr &MI) const { return false; } 1428 1429 // Returns a MIRPrinter comment for this machine operand. 1430 virtual std::string 1431 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 1432 unsigned OpIdx, const TargetRegisterInfo *TRI) const; 1433 1434 /// Returns true if the instruction is a 1435 /// terminator instruction that has not been predicated. 1436 bool isUnpredicatedTerminator(const MachineInstr &MI) const; 1437 1438 /// Returns true if MI is an unconditional tail call. 1439 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const { 1440 return false; 1441 } 1442 1443 /// Returns true if the tail call can be made conditional on BranchCond. 1444 virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 1445 const MachineInstr &TailCall) const { 1446 return false; 1447 } 1448 1449 /// Replace the conditional branch in MBB with a conditional tail call. 1450 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, 1451 SmallVectorImpl<MachineOperand> &Cond, 1452 const MachineInstr &TailCall) const { 1453 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!"); 1454 } 1455 1456 /// Convert the instruction into a predicated instruction. 1457 /// It returns true if the operation was successful. 1458 virtual bool PredicateInstruction(MachineInstr &MI, 1459 ArrayRef<MachineOperand> Pred) const; 1460 1461 /// Returns true if the first specified predicate 1462 /// subsumes the second, e.g. GE subsumes GT. 1463 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 1464 ArrayRef<MachineOperand> Pred2) const { 1465 return false; 1466 } 1467 1468 /// If the specified instruction defines any predicate 1469 /// or condition code register(s) used for predication, returns true as well 1470 /// as the definition predicate(s) by reference. 1471 /// SkipDead should be set to false at any point that dead 1472 /// predicate instructions should be considered as being defined. 1473 /// A dead predicate instruction is one that is guaranteed to be removed 1474 /// after a call to PredicateInstruction. 1475 virtual bool ClobbersPredicate(MachineInstr &MI, 1476 std::vector<MachineOperand> &Pred, 1477 bool SkipDead) const { 1478 return false; 1479 } 1480 1481 /// Return true if the specified instruction can be predicated. 1482 /// By default, this returns true for every instruction with a 1483 /// PredicateOperand. 1484 virtual bool isPredicable(const MachineInstr &MI) const { 1485 return MI.getDesc().isPredicable(); 1486 } 1487 1488 /// Return true if it's safe to move a machine 1489 /// instruction that defines the specified register class. 1490 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 1491 return true; 1492 } 1493 1494 /// Test if the given instruction should be considered a scheduling boundary. 1495 /// This primarily includes labels and terminators. 1496 virtual bool isSchedulingBoundary(const MachineInstr &MI, 1497 const MachineBasicBlock *MBB, 1498 const MachineFunction &MF) const; 1499 1500 /// Measure the specified inline asm to determine an approximation of its 1501 /// length. 1502 virtual unsigned getInlineAsmLength( 1503 const char *Str, const MCAsmInfo &MAI, 1504 const TargetSubtargetInfo *STI = nullptr) const; 1505 1506 /// Allocate and return a hazard recognizer to use for this target when 1507 /// scheduling the machine instructions before register allocation. 1508 virtual ScheduleHazardRecognizer * 1509 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 1510 const ScheduleDAG *DAG) const; 1511 1512 /// Allocate and return a hazard recognizer to use for this target when 1513 /// scheduling the machine instructions before register allocation. 1514 virtual ScheduleHazardRecognizer * 1515 CreateTargetMIHazardRecognizer(const InstrItineraryData *, 1516 const ScheduleDAGMI *DAG) const; 1517 1518 /// Allocate and return a hazard recognizer to use for this target when 1519 /// scheduling the machine instructions after register allocation. 1520 virtual ScheduleHazardRecognizer * 1521 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, 1522 const ScheduleDAG *DAG) const; 1523 1524 /// Allocate and return a hazard recognizer to use for by non-scheduling 1525 /// passes. 1526 virtual ScheduleHazardRecognizer * 1527 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const { 1528 return nullptr; 1529 } 1530 1531 /// Provide a global flag for disabling the PreRA hazard recognizer that 1532 /// targets may choose to honor. 1533 bool usePreRAHazardRecognizer() const; 1534 1535 /// For a comparison instruction, return the source registers 1536 /// in SrcReg and SrcReg2 if having two register operands, and the value it 1537 /// compares against in CmpValue. Return true if the comparison instruction 1538 /// can be analyzed. 1539 virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 1540 Register &SrcReg2, int &Mask, int &Value) const { 1541 return false; 1542 } 1543 1544 /// See if the comparison instruction can be converted 1545 /// into something more efficient. E.g., on ARM most instructions can set the 1546 /// flags register, obviating the need for a separate CMP. 1547 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 1548 Register SrcReg2, int Mask, int Value, 1549 const MachineRegisterInfo *MRI) const { 1550 return false; 1551 } 1552 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; } 1553 1554 /// Try to remove the load by folding it to a register operand at the use. 1555 /// We fold the load instructions if and only if the 1556 /// def and use are in the same BB. We only look at one load and see 1557 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 1558 /// defined by the load we are trying to fold. DefMI returns the machine 1559 /// instruction that defines FoldAsLoadDefReg, and the function returns 1560 /// the machine instruction generated due to folding. 1561 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI, 1562 const MachineRegisterInfo *MRI, 1563 Register &FoldAsLoadDefReg, 1564 MachineInstr *&DefMI) const { 1565 return nullptr; 1566 } 1567 1568 /// 'Reg' is known to be defined by a move immediate instruction, 1569 /// try to fold the immediate into the use instruction. 1570 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 1571 /// then the caller may assume that DefMI has been erased from its parent 1572 /// block. The caller may assume that it will not be erased by this 1573 /// function otherwise. 1574 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 1575 Register Reg, MachineRegisterInfo *MRI) const { 1576 return false; 1577 } 1578 1579 /// Return the number of u-operations the given machine 1580 /// instruction will be decoded to on the target cpu. The itinerary's 1581 /// IssueWidth is the number of microops that can be dispatched each 1582 /// cycle. An instruction with zero microops takes no dispatch resources. 1583 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1584 const MachineInstr &MI) const; 1585 1586 /// Return true for pseudo instructions that don't consume any 1587 /// machine resources in their current form. These are common cases that the 1588 /// scheduler should consider free, rather than conservatively handling them 1589 /// as instructions with no itinerary. 1590 bool isZeroCost(unsigned Opcode) const { 1591 return Opcode <= TargetOpcode::COPY; 1592 } 1593 1594 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1595 SDNode *DefNode, unsigned DefIdx, 1596 SDNode *UseNode, unsigned UseIdx) const; 1597 1598 /// Compute and return the use operand latency of a given pair of def and use. 1599 /// In most cases, the static scheduling itinerary was enough to determine the 1600 /// operand latency. But it may not be possible for instructions with variable 1601 /// number of defs / uses. 1602 /// 1603 /// This is a raw interface to the itinerary that may be directly overridden 1604 /// by a target. Use computeOperandLatency to get the best estimate of 1605 /// latency. 1606 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1607 const MachineInstr &DefMI, unsigned DefIdx, 1608 const MachineInstr &UseMI, 1609 unsigned UseIdx) const; 1610 1611 /// Compute the instruction latency of a given instruction. 1612 /// If the instruction has higher cost when predicated, it's returned via 1613 /// PredCost. 1614 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1615 const MachineInstr &MI, 1616 unsigned *PredCost = nullptr) const; 1617 1618 virtual unsigned getPredicationCost(const MachineInstr &MI) const; 1619 1620 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1621 SDNode *Node) const; 1622 1623 /// Return the default expected latency for a def based on its opcode. 1624 unsigned defaultDefLatency(const MCSchedModel &SchedModel, 1625 const MachineInstr &DefMI) const; 1626 1627 int computeDefOperandLatency(const InstrItineraryData *ItinData, 1628 const MachineInstr &DefMI) const; 1629 1630 /// Return true if this opcode has high latency to its result. 1631 virtual bool isHighLatencyDef(int opc) const { return false; } 1632 1633 /// Compute operand latency between a def of 'Reg' 1634 /// and a use in the current loop. Return true if the target considered 1635 /// it 'high'. This is used by optimization passes such as machine LICM to 1636 /// determine whether it makes sense to hoist an instruction out even in a 1637 /// high register pressure situation. 1638 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 1639 const MachineRegisterInfo *MRI, 1640 const MachineInstr &DefMI, unsigned DefIdx, 1641 const MachineInstr &UseMI, 1642 unsigned UseIdx) const { 1643 return false; 1644 } 1645 1646 /// Compute operand latency of a def of 'Reg'. Return true 1647 /// if the target considered it 'low'. 1648 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, 1649 const MachineInstr &DefMI, 1650 unsigned DefIdx) const; 1651 1652 /// Perform target-specific instruction verification. 1653 virtual bool verifyInstruction(const MachineInstr &MI, 1654 StringRef &ErrInfo) const { 1655 return true; 1656 } 1657 1658 /// Return the current execution domain and bit mask of 1659 /// possible domains for instruction. 1660 /// 1661 /// Some micro-architectures have multiple execution domains, and multiple 1662 /// opcodes that perform the same operation in different domains. For 1663 /// example, the x86 architecture provides the por, orps, and orpd 1664 /// instructions that all do the same thing. There is a latency penalty if a 1665 /// register is written in one domain and read in another. 1666 /// 1667 /// This function returns a pair (domain, mask) containing the execution 1668 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 1669 /// function can be used to change the opcode to one of the domains in the 1670 /// bit mask. Instructions whose execution domain can't be changed should 1671 /// return a 0 mask. 1672 /// 1673 /// The execution domain numbers don't have any special meaning except domain 1674 /// 0 is used for instructions that are not associated with any interesting 1675 /// execution domain. 1676 /// 1677 virtual std::pair<uint16_t, uint16_t> 1678 getExecutionDomain(const MachineInstr &MI) const { 1679 return std::make_pair(0, 0); 1680 } 1681 1682 /// Change the opcode of MI to execute in Domain. 1683 /// 1684 /// The bit (1 << Domain) must be set in the mask returned from 1685 /// getExecutionDomain(MI). 1686 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {} 1687 1688 /// Returns the preferred minimum clearance 1689 /// before an instruction with an unwanted partial register update. 1690 /// 1691 /// Some instructions only write part of a register, and implicitly need to 1692 /// read the other parts of the register. This may cause unwanted stalls 1693 /// preventing otherwise unrelated instructions from executing in parallel in 1694 /// an out-of-order CPU. 1695 /// 1696 /// For example, the x86 instruction cvtsi2ss writes its result to bits 1697 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 1698 /// the instruction needs to wait for the old value of the register to become 1699 /// available: 1700 /// 1701 /// addps %xmm1, %xmm0 1702 /// movaps %xmm0, (%rax) 1703 /// cvtsi2ss %rbx, %xmm0 1704 /// 1705 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 1706 /// instruction before it can issue, even though the high bits of %xmm0 1707 /// probably aren't needed. 1708 /// 1709 /// This hook returns the preferred clearance before MI, measured in 1710 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 1711 /// instructions before MI. It should only return a positive value for 1712 /// unwanted dependencies. If the old bits of the defined register have 1713 /// useful values, or if MI is determined to otherwise read the dependency, 1714 /// the hook should return 0. 1715 /// 1716 /// The unwanted dependency may be handled by: 1717 /// 1718 /// 1. Allocating the same register for an MI def and use. That makes the 1719 /// unwanted dependency identical to a required dependency. 1720 /// 1721 /// 2. Allocating a register for the def that has no defs in the previous N 1722 /// instructions. 1723 /// 1724 /// 3. Calling breakPartialRegDependency() with the same arguments. This 1725 /// allows the target to insert a dependency breaking instruction. 1726 /// 1727 virtual unsigned 1728 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 1729 const TargetRegisterInfo *TRI) const { 1730 // The default implementation returns 0 for no partial register dependency. 1731 return 0; 1732 } 1733 1734 /// Return the minimum clearance before an instruction that reads an 1735 /// unused register. 1736 /// 1737 /// For example, AVX instructions may copy part of a register operand into 1738 /// the unused high bits of the destination register. 1739 /// 1740 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14 1741 /// 1742 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 1743 /// false dependence on any previous write to %xmm0. 1744 /// 1745 /// This hook works similarly to getPartialRegUpdateClearance, except that it 1746 /// does not take an operand index. Instead sets \p OpNum to the index of the 1747 /// unused register. 1748 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 1749 const TargetRegisterInfo *TRI) const { 1750 // The default implementation returns 0 for no undef register dependency. 1751 return 0; 1752 } 1753 1754 /// Insert a dependency-breaking instruction 1755 /// before MI to eliminate an unwanted dependency on OpNum. 1756 /// 1757 /// If it wasn't possible to avoid a def in the last N instructions before MI 1758 /// (see getPartialRegUpdateClearance), this hook will be called to break the 1759 /// unwanted dependency. 1760 /// 1761 /// On x86, an xorps instruction can be used as a dependency breaker: 1762 /// 1763 /// addps %xmm1, %xmm0 1764 /// movaps %xmm0, (%rax) 1765 /// xorps %xmm0, %xmm0 1766 /// cvtsi2ss %rbx, %xmm0 1767 /// 1768 /// An <imp-kill> operand should be added to MI if an instruction was 1769 /// inserted. This ties the instructions together in the post-ra scheduler. 1770 /// 1771 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 1772 const TargetRegisterInfo *TRI) const {} 1773 1774 /// Create machine specific model for scheduling. 1775 virtual DFAPacketizer * 1776 CreateTargetScheduleState(const TargetSubtargetInfo &) const { 1777 return nullptr; 1778 } 1779 1780 /// Sometimes, it is possible for the target 1781 /// to tell, even without aliasing information, that two MIs access different 1782 /// memory addresses. This function returns true if two MIs access different 1783 /// memory addresses and false otherwise. 1784 /// 1785 /// Assumes any physical registers used to compute addresses have the same 1786 /// value for both instructions. (This is the most useful assumption for 1787 /// post-RA scheduling.) 1788 /// 1789 /// See also MachineInstr::mayAlias, which is implemented on top of this 1790 /// function. 1791 virtual bool 1792 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 1793 const MachineInstr &MIb) const { 1794 assert(MIa.mayLoadOrStore() && 1795 "MIa must load from or modify a memory location"); 1796 assert(MIb.mayLoadOrStore() && 1797 "MIb must load from or modify a memory location"); 1798 return false; 1799 } 1800 1801 /// Return the value to use for the MachineCSE's LookAheadLimit, 1802 /// which is a heuristic used for CSE'ing phys reg defs. 1803 virtual unsigned getMachineCSELookAheadLimit() const { 1804 // The default lookahead is small to prevent unprofitable quadratic 1805 // behavior. 1806 return 5; 1807 } 1808 1809 /// Return the maximal number of alias checks on memory operands. For 1810 /// instructions with more than one memory operands, the alias check on a 1811 /// single MachineInstr pair has quadratic overhead and results in 1812 /// unacceptable performance in the worst case. The limit here is to clamp 1813 /// that maximal checks performed. Usually, that's the product of memory 1814 /// operand numbers from that pair of MachineInstr to be checked. For 1815 /// instance, with two MachineInstrs with 4 and 5 memory operands 1816 /// correspondingly, a total of 20 checks are required. With this limit set to 1817 /// 16, their alias check is skipped. We choose to limit the product instead 1818 /// of the individual instruction as targets may have special MachineInstrs 1819 /// with a considerably high number of memory operands, such as `ldm` in ARM. 1820 /// Setting this limit per MachineInstr would result in either too high 1821 /// overhead or too rigid restriction. 1822 virtual unsigned getMemOperandAACheckLimit() const { return 16; } 1823 1824 /// Return an array that contains the ids of the target indices (used for the 1825 /// TargetIndex machine operand) and their names. 1826 /// 1827 /// MIR Serialization is able to serialize only the target indices that are 1828 /// defined by this method. 1829 virtual ArrayRef<std::pair<int, const char *>> 1830 getSerializableTargetIndices() const { 1831 return None; 1832 } 1833 1834 /// Decompose the machine operand's target flags into two values - the direct 1835 /// target flag value and any of bit flags that are applied. 1836 virtual std::pair<unsigned, unsigned> 1837 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const { 1838 return std::make_pair(0u, 0u); 1839 } 1840 1841 /// Return an array that contains the direct target flag values and their 1842 /// names. 1843 /// 1844 /// MIR Serialization is able to serialize only the target flags that are 1845 /// defined by this method. 1846 virtual ArrayRef<std::pair<unsigned, const char *>> 1847 getSerializableDirectMachineOperandTargetFlags() const { 1848 return None; 1849 } 1850 1851 /// Return an array that contains the bitmask target flag values and their 1852 /// names. 1853 /// 1854 /// MIR Serialization is able to serialize only the target flags that are 1855 /// defined by this method. 1856 virtual ArrayRef<std::pair<unsigned, const char *>> 1857 getSerializableBitmaskMachineOperandTargetFlags() const { 1858 return None; 1859 } 1860 1861 /// Return an array that contains the MMO target flag values and their 1862 /// names. 1863 /// 1864 /// MIR Serialization is able to serialize only the MMO target flags that are 1865 /// defined by this method. 1866 virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> 1867 getSerializableMachineMemOperandTargetFlags() const { 1868 return None; 1869 } 1870 1871 /// Determines whether \p Inst is a tail call instruction. Override this 1872 /// method on targets that do not properly set MCID::Return and MCID::Call on 1873 /// tail call instructions." 1874 virtual bool isTailCall(const MachineInstr &Inst) const { 1875 return Inst.isReturn() && Inst.isCall(); 1876 } 1877 1878 /// True if the instruction is bound to the top of its basic block and no 1879 /// other instructions shall be inserted before it. This can be implemented 1880 /// to prevent register allocator to insert spills before such instructions. 1881 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const { 1882 return false; 1883 } 1884 1885 /// During PHI eleimination lets target to make necessary checks and 1886 /// insert the copy to the PHI destination register in a target specific 1887 /// manner. 1888 virtual MachineInstr *createPHIDestinationCopy( 1889 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, 1890 const DebugLoc &DL, Register Src, Register Dst) const { 1891 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1892 .addReg(Src); 1893 } 1894 1895 /// During PHI eleimination lets target to make necessary checks and 1896 /// insert the copy to the PHI destination register in a target specific 1897 /// manner. 1898 virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB, 1899 MachineBasicBlock::iterator InsPt, 1900 const DebugLoc &DL, Register Src, 1901 unsigned SrcSubReg, 1902 Register Dst) const { 1903 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1904 .addReg(Src, 0, SrcSubReg); 1905 } 1906 1907 /// Returns a \p outliner::OutlinedFunction struct containing target-specific 1908 /// information for a set of outlining candidates. 1909 virtual outliner::OutlinedFunction getOutliningCandidateInfo( 1910 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { 1911 llvm_unreachable( 1912 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!"); 1913 } 1914 1915 /// Returns how or if \p MI should be outlined. 1916 virtual outliner::InstrType 1917 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { 1918 llvm_unreachable( 1919 "Target didn't implement TargetInstrInfo::getOutliningType!"); 1920 } 1921 1922 /// Optional target hook that returns true if \p MBB is safe to outline from, 1923 /// and returns any target-specific information in \p Flags. 1924 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 1925 unsigned &Flags) const { 1926 return true; 1927 } 1928 1929 /// Insert a custom frame for outlined functions. 1930 virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 1931 const outliner::OutlinedFunction &OF) const { 1932 llvm_unreachable( 1933 "Target didn't implement TargetInstrInfo::buildOutlinedFrame!"); 1934 } 1935 1936 /// Insert a call to an outlined function into the program. 1937 /// Returns an iterator to the spot where we inserted the call. This must be 1938 /// implemented by the target. 1939 virtual MachineBasicBlock::iterator 1940 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 1941 MachineBasicBlock::iterator &It, MachineFunction &MF, 1942 const outliner::Candidate &C) const { 1943 llvm_unreachable( 1944 "Target didn't implement TargetInstrInfo::insertOutlinedCall!"); 1945 } 1946 1947 /// Return true if the function can safely be outlined from. 1948 /// A function \p MF is considered safe for outlining if an outlined function 1949 /// produced from instructions in F will produce a program which produces the 1950 /// same output for any set of given inputs. 1951 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 1952 bool OutlineFromLinkOnceODRs) const { 1953 llvm_unreachable("Target didn't implement " 1954 "TargetInstrInfo::isFunctionSafeToOutlineFrom!"); 1955 } 1956 1957 /// Return true if the function should be outlined from by default. 1958 virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const { 1959 return false; 1960 } 1961 1962 /// Produce the expression describing the \p MI loading a value into 1963 /// the physical register \p Reg. This hook should only be used with 1964 /// \p MIs belonging to VReg-less functions. 1965 virtual Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 1966 Register Reg) const; 1967 1968 /// Given the generic extension instruction \p ExtMI, returns true if this 1969 /// extension is a likely candidate for being folded into an another 1970 /// instruction. 1971 virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, 1972 MachineRegisterInfo &MRI) const { 1973 return false; 1974 } 1975 1976 /// Return MIR formatter to format/parse MIR operands. Target can override 1977 /// this virtual function and return target specific MIR formatter. 1978 virtual const MIRFormatter *getMIRFormatter() const { 1979 if (!Formatter.get()) 1980 Formatter = std::make_unique<MIRFormatter>(); 1981 return Formatter.get(); 1982 } 1983 1984 /// Returns the target-specific default value for tail duplication. 1985 /// This value will be used if the tail-dup-placement-threshold argument is 1986 /// not provided. 1987 virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const { 1988 return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2; 1989 } 1990 1991 /// Returns the callee operand from the given \p MI. 1992 virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const { 1993 return MI.getOperand(0); 1994 } 1995 1996 private: 1997 mutable std::unique_ptr<MIRFormatter> Formatter; 1998 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode; 1999 unsigned CatchRetOpcode; 2000 unsigned ReturnOpcode; 2001 }; 2002 2003 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair. 2004 template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> { 2005 using RegInfo = DenseMapInfo<unsigned>; 2006 2007 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() { 2008 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(), 2009 RegInfo::getEmptyKey()); 2010 } 2011 2012 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() { 2013 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(), 2014 RegInfo::getTombstoneKey()); 2015 } 2016 2017 /// Reuse getHashValue implementation from 2018 /// std::pair<unsigned, unsigned>. 2019 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) { 2020 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg); 2021 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal); 2022 } 2023 2024 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, 2025 const TargetInstrInfo::RegSubRegPair &RHS) { 2026 return RegInfo::isEqual(LHS.Reg, RHS.Reg) && 2027 RegInfo::isEqual(LHS.SubReg, RHS.SubReg); 2028 } 2029 }; 2030 2031 } // end namespace llvm 2032 2033 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H 2034