1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes the target machine instruction set to the code generator. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 14 #define LLVM_TARGET_TARGETINSTRINFO_H 15 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/DenseMapInfo.h" 19 #include "llvm/ADT/None.h" 20 #include "llvm/CodeGen/MIRFormatter.h" 21 #include "llvm/CodeGen/MachineBasicBlock.h" 22 #include "llvm/CodeGen/MachineCombinerPattern.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstr.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineOutliner.h" 28 #include "llvm/CodeGen/RegisterClassInfo.h" 29 #include "llvm/CodeGen/VirtRegMap.h" 30 #include "llvm/MC/MCInstrInfo.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include <cassert> 34 #include <cstddef> 35 #include <cstdint> 36 #include <utility> 37 #include <vector> 38 39 namespace llvm { 40 41 class AAResults; 42 class DFAPacketizer; 43 class InstrItineraryData; 44 class LiveIntervals; 45 class LiveVariables; 46 class MachineLoop; 47 class MachineMemOperand; 48 class MachineRegisterInfo; 49 class MCAsmInfo; 50 class MCInst; 51 struct MCSchedModel; 52 class Module; 53 class ScheduleDAG; 54 class ScheduleDAGMI; 55 class ScheduleHazardRecognizer; 56 class SDNode; 57 class SelectionDAG; 58 class RegScavenger; 59 class TargetRegisterClass; 60 class TargetRegisterInfo; 61 class TargetSchedModel; 62 class TargetSubtargetInfo; 63 64 template <class T> class SmallVectorImpl; 65 66 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>; 67 68 struct DestSourcePair { 69 const MachineOperand *Destination; 70 const MachineOperand *Source; 71 72 DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src) 73 : Destination(&Dest), Source(&Src) {} 74 }; 75 76 /// Used to describe a register and immediate addition. 77 struct RegImmPair { 78 Register Reg; 79 int64_t Imm; 80 81 RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {} 82 }; 83 84 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare. 85 /// It holds the register values, the scale value and the displacement. 86 struct ExtAddrMode { 87 Register BaseReg; 88 Register ScaledReg; 89 int64_t Scale; 90 int64_t Displacement; 91 }; 92 93 //--------------------------------------------------------------------------- 94 /// 95 /// TargetInstrInfo - Interface to description of machine instruction set 96 /// 97 class TargetInstrInfo : public MCInstrInfo { 98 public: 99 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, 100 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u) 101 : CallFrameSetupOpcode(CFSetupOpcode), 102 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode), 103 ReturnOpcode(ReturnOpcode) {} 104 TargetInstrInfo(const TargetInstrInfo &) = delete; 105 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete; 106 virtual ~TargetInstrInfo(); 107 108 static bool isGenericOpcode(unsigned Opc) { 109 return Opc <= TargetOpcode::GENERIC_OP_END; 110 } 111 112 /// Given a machine instruction descriptor, returns the register 113 /// class constraint for OpNum, or NULL. 114 virtual 115 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 116 const TargetRegisterInfo *TRI, 117 const MachineFunction &MF) const; 118 119 /// Return true if the instruction is trivially rematerializable, meaning it 120 /// has no side effects and requires no operands that aren't always available. 121 /// This means the only allowed uses are constants and unallocatable physical 122 /// registers so that the instructions result is independent of the place 123 /// in the function. 124 bool isTriviallyReMaterializable(const MachineInstr &MI, 125 AAResults *AA = nullptr) const { 126 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF || 127 (MI.getDesc().isRematerializable() && 128 (isReallyTriviallyReMaterializable(MI, AA) || 129 isReallyTriviallyReMaterializableGeneric(MI, AA))); 130 } 131 132 protected: 133 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 134 /// set, this hook lets the target specify whether the instruction is actually 135 /// trivially rematerializable, taking into consideration its operands. This 136 /// predicate must return false if the instruction has any side effects other 137 /// than producing a value, or if it requres any address registers that are 138 /// not always available. 139 /// Requirements must be check as stated in isTriviallyReMaterializable() . 140 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 141 AAResults *AA) const { 142 return false; 143 } 144 145 /// This method commutes the operands of the given machine instruction MI. 146 /// The operands to be commuted are specified by their indices OpIdx1 and 147 /// OpIdx2. 148 /// 149 /// If a target has any instructions that are commutable but require 150 /// converting to different instructions or making non-trivial changes 151 /// to commute them, this method can be overloaded to do that. 152 /// The default implementation simply swaps the commutable operands. 153 /// 154 /// If NewMI is false, MI is modified in place and returned; otherwise, a 155 /// new machine instruction is created and returned. 156 /// 157 /// Do not call this method for a non-commutable instruction. 158 /// Even though the instruction is commutable, the method may still 159 /// fail to commute the operands, null pointer is returned in such cases. 160 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 161 unsigned OpIdx1, 162 unsigned OpIdx2) const; 163 164 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable 165 /// operand indices to (ResultIdx1, ResultIdx2). 166 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be 167 /// predefined to some indices or be undefined (designated by the special 168 /// value 'CommuteAnyOperandIndex'). 169 /// The predefined result indices cannot be re-defined. 170 /// The function returns true iff after the result pair redefinition 171 /// the fixed result pair is equal to or equivalent to the source pair of 172 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that 173 /// the pairs (x,y) and (y,x) are equivalent. 174 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, 175 unsigned CommutableOpIdx1, 176 unsigned CommutableOpIdx2); 177 178 private: 179 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is 180 /// set and the target hook isReallyTriviallyReMaterializable returns false, 181 /// this function does target-independent tests to determine if the 182 /// instruction is really trivially rematerializable. 183 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI, 184 AAResults *AA) const; 185 186 public: 187 /// These methods return the opcode of the frame setup/destroy instructions 188 /// if they exist (-1 otherwise). Some targets use pseudo instructions in 189 /// order to abstract away the difference between operating with a frame 190 /// pointer and operating without, through the use of these two instructions. 191 /// 192 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 193 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 194 195 /// Returns true if the argument is a frame pseudo instruction. 196 bool isFrameInstr(const MachineInstr &I) const { 197 return I.getOpcode() == getCallFrameSetupOpcode() || 198 I.getOpcode() == getCallFrameDestroyOpcode(); 199 } 200 201 /// Returns true if the argument is a frame setup pseudo instruction. 202 bool isFrameSetup(const MachineInstr &I) const { 203 return I.getOpcode() == getCallFrameSetupOpcode(); 204 } 205 206 /// Returns size of the frame associated with the given frame instruction. 207 /// For frame setup instruction this is frame that is set up space set up 208 /// after the instruction. For frame destroy instruction this is the frame 209 /// freed by the caller. 210 /// Note, in some cases a call frame (or a part of it) may be prepared prior 211 /// to the frame setup instruction. It occurs in the calls that involve 212 /// inalloca arguments. This function reports only the size of the frame part 213 /// that is set up between the frame setup and destroy pseudo instructions. 214 int64_t getFrameSize(const MachineInstr &I) const { 215 assert(isFrameInstr(I) && "Not a frame instruction"); 216 assert(I.getOperand(0).getImm() >= 0); 217 return I.getOperand(0).getImm(); 218 } 219 220 /// Returns the total frame size, which is made up of the space set up inside 221 /// the pair of frame start-stop instructions and the space that is set up 222 /// prior to the pair. 223 int64_t getFrameTotalSize(const MachineInstr &I) const { 224 if (isFrameSetup(I)) { 225 assert(I.getOperand(1).getImm() >= 0 && 226 "Frame size must not be negative"); 227 return getFrameSize(I) + I.getOperand(1).getImm(); 228 } 229 return getFrameSize(I); 230 } 231 232 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; } 233 unsigned getReturnOpcode() const { return ReturnOpcode; } 234 235 /// Returns the actual stack pointer adjustment made by an instruction 236 /// as part of a call sequence. By default, only call frame setup/destroy 237 /// instructions adjust the stack, but targets may want to override this 238 /// to enable more fine-grained adjustment, or adjust by a different value. 239 virtual int getSPAdjust(const MachineInstr &MI) const; 240 241 /// Return true if the instruction is a "coalescable" extension instruction. 242 /// That is, it's like a copy where it's legal for the source to overlap the 243 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's 244 /// expected the pre-extension value is available as a subreg of the result 245 /// register. This also returns the sub-register index in SubIdx. 246 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 247 Register &DstReg, unsigned &SubIdx) const { 248 return false; 249 } 250 251 /// If the specified machine instruction is a direct 252 /// load from a stack slot, return the virtual or physical register number of 253 /// the destination along with the FrameIndex of the loaded stack slot. If 254 /// not, return 0. This predicate must return 0 if the instruction has 255 /// any side effects other than loading from the stack slot. 256 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 257 int &FrameIndex) const { 258 return 0; 259 } 260 261 /// Optional extension of isLoadFromStackSlot that returns the number of 262 /// bytes loaded from the stack. This must be implemented if a backend 263 /// supports partial stack slot spills/loads to further disambiguate 264 /// what the load does. 265 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, 266 int &FrameIndex, 267 unsigned &MemBytes) const { 268 MemBytes = 0; 269 return isLoadFromStackSlot(MI, FrameIndex); 270 } 271 272 /// Check for post-frame ptr elimination stack locations as well. 273 /// This uses a heuristic so it isn't reliable for correctness. 274 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 275 int &FrameIndex) const { 276 return 0; 277 } 278 279 /// If the specified machine instruction has a load from a stack slot, 280 /// return true along with the FrameIndices of the loaded stack slot and the 281 /// machine mem operands containing the reference. 282 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for 283 /// any instructions that loads from the stack. This is just a hint, as some 284 /// cases may be missed. 285 virtual bool hasLoadFromStackSlot( 286 const MachineInstr &MI, 287 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 288 289 /// If the specified machine instruction is a direct 290 /// store to a stack slot, return the virtual or physical register number of 291 /// the source reg along with the FrameIndex of the loaded stack slot. If 292 /// not, return 0. This predicate must return 0 if the instruction has 293 /// any side effects other than storing to the stack slot. 294 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 295 int &FrameIndex) const { 296 return 0; 297 } 298 299 /// Optional extension of isStoreToStackSlot that returns the number of 300 /// bytes stored to the stack. This must be implemented if a backend 301 /// supports partial stack slot spills/loads to further disambiguate 302 /// what the store does. 303 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, 304 int &FrameIndex, 305 unsigned &MemBytes) const { 306 MemBytes = 0; 307 return isStoreToStackSlot(MI, FrameIndex); 308 } 309 310 /// Check for post-frame ptr elimination stack locations as well. 311 /// This uses a heuristic, so it isn't reliable for correctness. 312 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 313 int &FrameIndex) const { 314 return 0; 315 } 316 317 /// If the specified machine instruction has a store to a stack slot, 318 /// return true along with the FrameIndices of the loaded stack slot and the 319 /// machine mem operands containing the reference. 320 /// If not, return false. Unlike isStoreToStackSlot, 321 /// this returns true for any instructions that stores to the 322 /// stack. This is just a hint, as some cases may be missed. 323 virtual bool hasStoreToStackSlot( 324 const MachineInstr &MI, 325 SmallVectorImpl<const MachineMemOperand *> &Accesses) const; 326 327 /// Return true if the specified machine instruction 328 /// is a copy of one stack slot to another and has no other effect. 329 /// Provide the identity of the two frame indices. 330 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, 331 int &SrcFrameIndex) const { 332 return false; 333 } 334 335 /// Compute the size in bytes and offset within a stack slot of a spilled 336 /// register or subregister. 337 /// 338 /// \param [out] Size in bytes of the spilled value. 339 /// \param [out] Offset in bytes within the stack slot. 340 /// \returns true if both Size and Offset are successfully computed. 341 /// 342 /// Not all subregisters have computable spill slots. For example, 343 /// subregisters registers may not be byte-sized, and a pair of discontiguous 344 /// subregisters has no single offset. 345 /// 346 /// Targets with nontrivial bigendian implementations may need to override 347 /// this, particularly to support spilled vector registers. 348 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 349 unsigned &Size, unsigned &Offset, 350 const MachineFunction &MF) const; 351 352 /// Return true if the given instruction is terminator that is unspillable, 353 /// according to isUnspillableTerminatorImpl. 354 bool isUnspillableTerminator(const MachineInstr *MI) const { 355 return MI->isTerminator() && isUnspillableTerminatorImpl(MI); 356 } 357 358 /// Returns the size in bytes of the specified MachineInstr, or ~0U 359 /// when this function is not implemented by a target. 360 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const { 361 return ~0U; 362 } 363 364 /// Return true if the instruction is as cheap as a move instruction. 365 /// 366 /// Targets for different archs need to override this, and different 367 /// micro-architectures can also be finely tuned inside. 368 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const { 369 return MI.isAsCheapAsAMove(); 370 } 371 372 /// Return true if the instruction should be sunk by MachineSink. 373 /// 374 /// MachineSink determines on its own whether the instruction is safe to sink; 375 /// this gives the target a hook to override the default behavior with regards 376 /// to which instructions should be sunk. 377 virtual bool shouldSink(const MachineInstr &MI) const { return true; } 378 379 /// Re-issue the specified 'original' instruction at the 380 /// specific location targeting a new destination register. 381 /// The register in Orig->getOperand(0).getReg() will be substituted by 382 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 383 /// SubIdx. 384 virtual void reMaterialize(MachineBasicBlock &MBB, 385 MachineBasicBlock::iterator MI, Register DestReg, 386 unsigned SubIdx, const MachineInstr &Orig, 387 const TargetRegisterInfo &TRI) const; 388 389 /// Clones instruction or the whole instruction bundle \p Orig and 390 /// insert into \p MBB before \p InsertBefore. The target may update operands 391 /// that are required to be unique. 392 /// 393 /// \p Orig must not return true for MachineInstr::isNotDuplicable(). 394 virtual MachineInstr &duplicate(MachineBasicBlock &MBB, 395 MachineBasicBlock::iterator InsertBefore, 396 const MachineInstr &Orig) const; 397 398 /// This method must be implemented by targets that 399 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 400 /// may be able to convert a two-address instruction into one or more true 401 /// three-address instructions on demand. This allows the X86 target (for 402 /// example) to convert ADD and SHL instructions into LEA instructions if they 403 /// would require register copies due to two-addressness. 404 /// 405 /// This method returns a null pointer if the transformation cannot be 406 /// performed, otherwise it returns the last new instruction. 407 /// 408 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 409 MachineInstr &MI, 410 LiveVariables *LV) const { 411 return nullptr; 412 } 413 414 // This constant can be used as an input value of operand index passed to 415 // the method findCommutedOpIndices() to tell the method that the 416 // corresponding operand index is not pre-defined and that the method 417 // can pick any commutable operand. 418 static const unsigned CommuteAnyOperandIndex = ~0U; 419 420 /// This method commutes the operands of the given machine instruction MI. 421 /// 422 /// The operands to be commuted are specified by their indices OpIdx1 and 423 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 424 /// 'CommuteAnyOperandIndex', which means that the method is free to choose 425 /// any arbitrarily chosen commutable operand. If both arguments are set to 426 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable 427 /// operands; then commutes them if such operands could be found. 428 /// 429 /// If NewMI is false, MI is modified in place and returned; otherwise, a 430 /// new machine instruction is created and returned. 431 /// 432 /// Do not call this method for a non-commutable instruction or 433 /// for non-commuable operands. 434 /// Even though the instruction is commutable, the method may still 435 /// fail to commute the operands, null pointer is returned in such cases. 436 MachineInstr * 437 commuteInstruction(MachineInstr &MI, bool NewMI = false, 438 unsigned OpIdx1 = CommuteAnyOperandIndex, 439 unsigned OpIdx2 = CommuteAnyOperandIndex) const; 440 441 /// Returns true iff the routine could find two commutable operands in the 442 /// given machine instruction. 443 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. 444 /// If any of the INPUT values is set to the special value 445 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable 446 /// operand, then returns its index in the corresponding argument. 447 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method 448 /// looks for 2 commutable operands. 449 /// If INPUT values refer to some operands of MI, then the method simply 450 /// returns true if the corresponding operands are commutable and returns 451 /// false otherwise. 452 /// 453 /// For example, calling this method this way: 454 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 455 /// findCommutedOpIndices(MI, Op1, Op2); 456 /// can be interpreted as a query asking to find an operand that would be 457 /// commutable with the operand#1. 458 virtual bool findCommutedOpIndices(const MachineInstr &MI, 459 unsigned &SrcOpIdx1, 460 unsigned &SrcOpIdx2) const; 461 462 /// A pair composed of a register and a sub-register index. 463 /// Used to give some type checking when modeling Reg:SubReg. 464 struct RegSubRegPair { 465 Register Reg; 466 unsigned SubReg; 467 468 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0) 469 : Reg(Reg), SubReg(SubReg) {} 470 471 bool operator==(const RegSubRegPair& P) const { 472 return Reg == P.Reg && SubReg == P.SubReg; 473 } 474 bool operator!=(const RegSubRegPair& P) const { 475 return !(*this == P); 476 } 477 }; 478 479 /// A pair composed of a pair of a register and a sub-register index, 480 /// and another sub-register index. 481 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2. 482 struct RegSubRegPairAndIdx : RegSubRegPair { 483 unsigned SubIdx; 484 485 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0, 486 unsigned SubIdx = 0) 487 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} 488 }; 489 490 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 491 /// and \p DefIdx. 492 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 493 /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef 494 /// flag are not added to this list. 495 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 496 /// two elements: 497 /// - %1:sub1, sub0 498 /// - %2<:0>, sub1 499 /// 500 /// \returns true if it is possible to build such an input sequence 501 /// with the pair \p MI, \p DefIdx. False otherwise. 502 /// 503 /// \pre MI.isRegSequence() or MI.isRegSequenceLike(). 504 /// 505 /// \note The generic implementation does not provide any support for 506 /// MI.isRegSequenceLike(). In other words, one has to override 507 /// getRegSequenceLikeInputs for target specific instructions. 508 bool 509 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, 510 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const; 511 512 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 513 /// and \p DefIdx. 514 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 515 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 516 /// - %1:sub1, sub0 517 /// 518 /// \returns true if it is possible to build such an input sequence 519 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 520 /// False otherwise. 521 /// 522 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). 523 /// 524 /// \note The generic implementation does not provide any support for 525 /// MI.isExtractSubregLike(). In other words, one has to override 526 /// getExtractSubregLikeInputs for target specific instructions. 527 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, 528 RegSubRegPairAndIdx &InputReg) const; 529 530 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 531 /// and \p DefIdx. 532 /// \p [out] BaseReg and \p [out] InsertedReg contain 533 /// the equivalent inputs of INSERT_SUBREG. 534 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 535 /// - BaseReg: %0:sub0 536 /// - InsertedReg: %1:sub1, sub3 537 /// 538 /// \returns true if it is possible to build such an input sequence 539 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. 540 /// False otherwise. 541 /// 542 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). 543 /// 544 /// \note The generic implementation does not provide any support for 545 /// MI.isInsertSubregLike(). In other words, one has to override 546 /// getInsertSubregLikeInputs for target specific instructions. 547 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, 548 RegSubRegPair &BaseReg, 549 RegSubRegPairAndIdx &InsertedReg) const; 550 551 /// Return true if two machine instructions would produce identical values. 552 /// By default, this is only true when the two instructions 553 /// are deemed identical except for defs. If this function is called when the 554 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 555 /// aggressive checks. 556 virtual bool produceSameValue(const MachineInstr &MI0, 557 const MachineInstr &MI1, 558 const MachineRegisterInfo *MRI = nullptr) const; 559 560 /// \returns true if a branch from an instruction with opcode \p BranchOpc 561 /// bytes is capable of jumping to a position \p BrOffset bytes away. 562 virtual bool isBranchOffsetInRange(unsigned BranchOpc, 563 int64_t BrOffset) const { 564 llvm_unreachable("target did not implement"); 565 } 566 567 /// \returns The block that branch instruction \p MI jumps to. 568 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const { 569 llvm_unreachable("target did not implement"); 570 } 571 572 /// Insert an unconditional indirect branch at the end of \p MBB to \p 573 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to 574 /// the offset of the position to insert the new branch. 575 /// 576 /// \returns The number of bytes added to the block. 577 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, 578 MachineBasicBlock &NewDestBB, 579 const DebugLoc &DL, 580 int64_t BrOffset = 0, 581 RegScavenger *RS = nullptr) const { 582 llvm_unreachable("target did not implement"); 583 } 584 585 /// Analyze the branching code at the end of MBB, returning 586 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 587 /// implemented for a target). Upon success, this returns false and returns 588 /// with the following information in various cases: 589 /// 590 /// 1. If this block ends with no branches (it just falls through to its succ) 591 /// just return false, leaving TBB/FBB null. 592 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 593 /// the destination block. 594 /// 3. If this block ends with a conditional branch and it falls through to a 595 /// successor block, it sets TBB to be the branch destination block and a 596 /// list of operands that evaluate the condition. These operands can be 597 /// passed to other TargetInstrInfo methods to create new branches. 598 /// 4. If this block ends with a conditional branch followed by an 599 /// unconditional branch, it returns the 'true' destination in TBB, the 600 /// 'false' destination in FBB, and a list of operands that evaluate the 601 /// condition. These operands can be passed to other TargetInstrInfo 602 /// methods to create new branches. 603 /// 604 /// Note that removeBranch and insertBranch must be implemented to support 605 /// cases where this method returns success. 606 /// 607 /// If AllowModify is true, then this routine is allowed to modify the basic 608 /// block (e.g. delete instructions after the unconditional branch). 609 /// 610 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 611 /// before calling this function. 612 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 613 MachineBasicBlock *&FBB, 614 SmallVectorImpl<MachineOperand> &Cond, 615 bool AllowModify = false) const { 616 return true; 617 } 618 619 /// Represents a predicate at the MachineFunction level. The control flow a 620 /// MachineBranchPredicate represents is: 621 /// 622 /// Reg = LHS `Predicate` RHS == ConditionDef 623 /// if Reg then goto TrueDest else goto FalseDest 624 /// 625 struct MachineBranchPredicate { 626 enum ComparePredicate { 627 PRED_EQ, // True if two values are equal 628 PRED_NE, // True if two values are not equal 629 PRED_INVALID // Sentinel value 630 }; 631 632 ComparePredicate Predicate = PRED_INVALID; 633 MachineOperand LHS = MachineOperand::CreateImm(0); 634 MachineOperand RHS = MachineOperand::CreateImm(0); 635 MachineBasicBlock *TrueDest = nullptr; 636 MachineBasicBlock *FalseDest = nullptr; 637 MachineInstr *ConditionDef = nullptr; 638 639 /// SingleUseCondition is true if ConditionDef is dead except for the 640 /// branch(es) at the end of the basic block. 641 /// 642 bool SingleUseCondition = false; 643 644 explicit MachineBranchPredicate() = default; 645 }; 646 647 /// Analyze the branching code at the end of MBB and parse it into the 648 /// MachineBranchPredicate structure if possible. Returns false on success 649 /// and true on failure. 650 /// 651 /// If AllowModify is true, then this routine is allowed to modify the basic 652 /// block (e.g. delete instructions after the unconditional branch). 653 /// 654 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, 655 MachineBranchPredicate &MBP, 656 bool AllowModify = false) const { 657 return true; 658 } 659 660 /// Remove the branching code at the end of the specific MBB. 661 /// This is only invoked in cases where analyzeBranch returns success. It 662 /// returns the number of instructions that were removed. 663 /// If \p BytesRemoved is non-null, report the change in code size from the 664 /// removed instructions. 665 virtual unsigned removeBranch(MachineBasicBlock &MBB, 666 int *BytesRemoved = nullptr) const { 667 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!"); 668 } 669 670 /// Insert branch code into the end of the specified MachineBasicBlock. The 671 /// operands to this method are the same as those returned by analyzeBranch. 672 /// This is only invoked in cases where analyzeBranch returns success. It 673 /// returns the number of instructions inserted. If \p BytesAdded is non-null, 674 /// report the change in code size from the added instructions. 675 /// 676 /// It is also invoked by tail merging to add unconditional branches in 677 /// cases where analyzeBranch doesn't apply because there was no original 678 /// branch to analyze. At least this much must be implemented, else tail 679 /// merging needs to be disabled. 680 /// 681 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid 682 /// before calling this function. 683 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 684 MachineBasicBlock *FBB, 685 ArrayRef<MachineOperand> Cond, 686 const DebugLoc &DL, 687 int *BytesAdded = nullptr) const { 688 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!"); 689 } 690 691 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, 692 MachineBasicBlock *DestBB, 693 const DebugLoc &DL, 694 int *BytesAdded = nullptr) const { 695 return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL, 696 BytesAdded); 697 } 698 699 /// Object returned by analyzeLoopForPipelining. Allows software pipelining 700 /// implementations to query attributes of the loop being pipelined and to 701 /// apply target-specific updates to the loop once pipelining is complete. 702 class PipelinerLoopInfo { 703 public: 704 virtual ~PipelinerLoopInfo(); 705 /// Return true if the given instruction should not be pipelined and should 706 /// be ignored. An example could be a loop comparison, or induction variable 707 /// update with no users being pipelined. 708 virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0; 709 710 /// Create a condition to determine if the trip count of the loop is greater 711 /// than TC. 712 /// 713 /// If the trip count is statically known to be greater than TC, return 714 /// true. If the trip count is statically known to be not greater than TC, 715 /// return false. Otherwise return nullopt and fill out Cond with the test 716 /// condition. 717 virtual Optional<bool> 718 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, 719 SmallVectorImpl<MachineOperand> &Cond) = 0; 720 721 /// Modify the loop such that the trip count is 722 /// OriginalTC + TripCountAdjust. 723 virtual void adjustTripCount(int TripCountAdjust) = 0; 724 725 /// Called when the loop's preheader has been modified to NewPreheader. 726 virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0; 727 728 /// Called when the loop is being removed. Any instructions in the preheader 729 /// should be removed. 730 /// 731 /// Once this function is called, no other functions on this object are 732 /// valid; the loop has been removed. 733 virtual void disposed() = 0; 734 }; 735 736 /// Analyze loop L, which must be a single-basic-block loop, and if the 737 /// conditions can be understood enough produce a PipelinerLoopInfo object. 738 virtual std::unique_ptr<PipelinerLoopInfo> 739 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { 740 return nullptr; 741 } 742 743 /// Analyze the loop code, return true if it cannot be understood. Upon 744 /// success, this function returns false and returns information about the 745 /// induction variable and compare instruction used at the end. 746 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, 747 MachineInstr *&CmpInst) const { 748 return true; 749 } 750 751 /// Generate code to reduce the loop iteration by one and check if the loop 752 /// is finished. Return the value/register of the new loop count. We need 753 /// this function when peeling off one or more iterations of a loop. This 754 /// function assumes the nth iteration is peeled first. 755 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, 756 MachineBasicBlock &PreHeader, 757 MachineInstr *IndVar, MachineInstr &Cmp, 758 SmallVectorImpl<MachineOperand> &Cond, 759 SmallVectorImpl<MachineInstr *> &PrevInsts, 760 unsigned Iter, unsigned MaxIter) const { 761 llvm_unreachable("Target didn't implement ReduceLoopCount"); 762 } 763 764 /// Delete the instruction OldInst and everything after it, replacing it with 765 /// an unconditional branch to NewDest. This is used by the tail merging pass. 766 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 767 MachineBasicBlock *NewDest) const; 768 769 /// Return true if it's legal to split the given basic 770 /// block at the specified instruction (i.e. instruction would be the start 771 /// of a new basic block). 772 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 773 MachineBasicBlock::iterator MBBI) const { 774 return true; 775 } 776 777 /// Return true if it's profitable to predicate 778 /// instructions with accumulated instruction latency of "NumCycles" 779 /// of the specified basic block, where the probability of the instructions 780 /// being executed is given by Probability, and Confidence is a measure 781 /// of our confidence that it will be properly predicted. 782 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 783 unsigned ExtraPredCycles, 784 BranchProbability Probability) const { 785 return false; 786 } 787 788 /// Second variant of isProfitableToIfCvt. This one 789 /// checks for the case where two basic blocks from true and false path 790 /// of a if-then-else (diamond) are predicated on mutually exclusive 791 /// predicates, where the probability of the true path being taken is given 792 /// by Probability, and Confidence is a measure of our confidence that it 793 /// will be properly predicted. 794 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, 795 unsigned ExtraTCycles, 796 MachineBasicBlock &FMBB, unsigned NumFCycles, 797 unsigned ExtraFCycles, 798 BranchProbability Probability) const { 799 return false; 800 } 801 802 /// Return true if it's profitable for if-converter to duplicate instructions 803 /// of specified accumulated instruction latencies in the specified MBB to 804 /// enable if-conversion. 805 /// The probability of the instructions being executed is given by 806 /// Probability, and Confidence is a measure of our confidence that it 807 /// will be properly predicted. 808 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 809 unsigned NumCycles, 810 BranchProbability Probability) const { 811 return false; 812 } 813 814 /// Return the increase in code size needed to predicate a contiguous run of 815 /// NumInsts instructions. 816 virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 817 unsigned NumInsts) const { 818 return 0; 819 } 820 821 /// Return an estimate for the code size reduction (in bytes) which will be 822 /// caused by removing the given branch instruction during if-conversion. 823 virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const { 824 return getInstSizeInBytes(MI); 825 } 826 827 /// Return true if it's profitable to unpredicate 828 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 829 /// exclusive predicates. 830 /// e.g. 831 /// subeq r0, r1, #1 832 /// addne r0, r1, #1 833 /// => 834 /// sub r0, r1, #1 835 /// addne r0, r1, #1 836 /// 837 /// This may be profitable is conditional instructions are always executed. 838 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 839 MachineBasicBlock &FMBB) const { 840 return false; 841 } 842 843 /// Return true if it is possible to insert a select 844 /// instruction that chooses between TrueReg and FalseReg based on the 845 /// condition code in Cond. 846 /// 847 /// When successful, also return the latency in cycles from TrueReg, 848 /// FalseReg, and Cond to the destination register. In most cases, a select 849 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 850 /// 851 /// Some x86 implementations have 2-cycle cmov instructions. 852 /// 853 /// @param MBB Block where select instruction would be inserted. 854 /// @param Cond Condition returned by analyzeBranch. 855 /// @param DstReg Virtual dest register that the result should write to. 856 /// @param TrueReg Virtual register to select when Cond is true. 857 /// @param FalseReg Virtual register to select when Cond is false. 858 /// @param CondCycles Latency from Cond+Branch to select output. 859 /// @param TrueCycles Latency from TrueReg to select output. 860 /// @param FalseCycles Latency from FalseReg to select output. 861 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 862 ArrayRef<MachineOperand> Cond, Register DstReg, 863 Register TrueReg, Register FalseReg, 864 int &CondCycles, int &TrueCycles, 865 int &FalseCycles) const { 866 return false; 867 } 868 869 /// Insert a select instruction into MBB before I that will copy TrueReg to 870 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. 871 /// 872 /// This function can only be called after canInsertSelect() returned true. 873 /// The condition in Cond comes from analyzeBranch, and it can be assumed 874 /// that the same flags or registers required by Cond are available at the 875 /// insertion point. 876 /// 877 /// @param MBB Block where select instruction should be inserted. 878 /// @param I Insertion point. 879 /// @param DL Source location for debugging. 880 /// @param DstReg Virtual register to be defined by select instruction. 881 /// @param Cond Condition as computed by analyzeBranch. 882 /// @param TrueReg Virtual register to copy when Cond is true. 883 /// @param FalseReg Virtual register to copy when Cons is false. 884 virtual void insertSelect(MachineBasicBlock &MBB, 885 MachineBasicBlock::iterator I, const DebugLoc &DL, 886 Register DstReg, ArrayRef<MachineOperand> Cond, 887 Register TrueReg, Register FalseReg) const { 888 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 889 } 890 891 /// Analyze the given select instruction, returning true if 892 /// it cannot be understood. It is assumed that MI->isSelect() is true. 893 /// 894 /// When successful, return the controlling condition and the operands that 895 /// determine the true and false result values. 896 /// 897 /// Result = SELECT Cond, TrueOp, FalseOp 898 /// 899 /// Some targets can optimize select instructions, for example by predicating 900 /// the instruction defining one of the operands. Such targets should set 901 /// Optimizable. 902 /// 903 /// @param MI Select instruction to analyze. 904 /// @param Cond Condition controlling the select. 905 /// @param TrueOp Operand number of the value selected when Cond is true. 906 /// @param FalseOp Operand number of the value selected when Cond is false. 907 /// @param Optimizable Returned as true if MI is optimizable. 908 /// @returns False on success. 909 virtual bool analyzeSelect(const MachineInstr &MI, 910 SmallVectorImpl<MachineOperand> &Cond, 911 unsigned &TrueOp, unsigned &FalseOp, 912 bool &Optimizable) const { 913 assert(MI.getDesc().isSelect() && "MI must be a select instruction"); 914 return true; 915 } 916 917 /// Given a select instruction that was understood by 918 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 919 /// merging it with one of its operands. Returns NULL on failure. 920 /// 921 /// When successful, returns the new select instruction. The client is 922 /// responsible for deleting MI. 923 /// 924 /// If both sides of the select can be optimized, PreferFalse is used to pick 925 /// a side. 926 /// 927 /// @param MI Optimizable select instruction. 928 /// @param NewMIs Set that record all MIs in the basic block up to \p 929 /// MI. Has to be updated with any newly created MI or deleted ones. 930 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 931 /// @returns Optimized instruction or NULL. 932 virtual MachineInstr *optimizeSelect(MachineInstr &MI, 933 SmallPtrSetImpl<MachineInstr *> &NewMIs, 934 bool PreferFalse = false) const { 935 // This function must be implemented if Optimizable is ever set. 936 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 937 } 938 939 /// Emit instructions to copy a pair of physical registers. 940 /// 941 /// This function should support copies within any legal register class as 942 /// well as any cross-class copies created during instruction selection. 943 /// 944 /// The source and destination registers may overlap, which may require a 945 /// careful implementation when multiple copy instructions are required for 946 /// large registers. See for example the ARM target. 947 virtual void copyPhysReg(MachineBasicBlock &MBB, 948 MachineBasicBlock::iterator MI, const DebugLoc &DL, 949 MCRegister DestReg, MCRegister SrcReg, 950 bool KillSrc) const { 951 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 952 } 953 954 protected: 955 /// Target-dependent implementation for IsCopyInstr. 956 /// If the specific machine instruction is a instruction that moves/copies 957 /// value from one register to another register return destination and source 958 /// registers as machine operands. 959 virtual Optional<DestSourcePair> 960 isCopyInstrImpl(const MachineInstr &MI) const { 961 return None; 962 } 963 964 /// Return true if the given terminator MI is not expected to spill. This 965 /// sets the live interval as not spillable and adjusts phi node lowering to 966 /// not introduce copies after the terminator. Use with care, these are 967 /// currently used for hardware loop intrinsics in very controlled situations, 968 /// created prior to registry allocation in loops that only have single phi 969 /// users for the terminators value. They may run out of registers if not used 970 /// carefully. 971 virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const { 972 return false; 973 } 974 975 public: 976 /// If the specific machine instruction is a instruction that moves/copies 977 /// value from one register to another register return destination and source 978 /// registers as machine operands. 979 /// For COPY-instruction the method naturally returns destination and source 980 /// registers as machine operands, for all other instructions the method calls 981 /// target-dependent implementation. 982 Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const { 983 if (MI.isCopy()) { 984 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 985 } 986 return isCopyInstrImpl(MI); 987 } 988 989 /// If the specific machine instruction is an instruction that adds an 990 /// immediate value and a physical register, and stores the result in 991 /// the given physical register \c Reg, return a pair of the source 992 /// register and the offset which has been added. 993 virtual Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 994 Register Reg) const { 995 return None; 996 } 997 998 /// Returns true if MI is an instruction that defines Reg to have a constant 999 /// value and the value is recorded in ImmVal. The ImmVal is a result that 1000 /// should be interpreted as modulo size of Reg. 1001 virtual bool getConstValDefinedInReg(const MachineInstr &MI, 1002 const Register Reg, 1003 int64_t &ImmVal) const { 1004 return false; 1005 } 1006 1007 /// Store the specified register of the given register class to the specified 1008 /// stack frame index. The store instruction is to be added to the given 1009 /// machine basic block before the specified machine instruction. If isKill 1010 /// is true, the register operand is the last use and must be marked kill. 1011 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 1012 MachineBasicBlock::iterator MI, 1013 Register SrcReg, bool isKill, int FrameIndex, 1014 const TargetRegisterClass *RC, 1015 const TargetRegisterInfo *TRI) const { 1016 llvm_unreachable("Target didn't implement " 1017 "TargetInstrInfo::storeRegToStackSlot!"); 1018 } 1019 1020 /// Load the specified register of the given register class from the specified 1021 /// stack frame index. The load instruction is to be added to the given 1022 /// machine basic block before the specified machine instruction. 1023 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 1024 MachineBasicBlock::iterator MI, 1025 Register DestReg, int FrameIndex, 1026 const TargetRegisterClass *RC, 1027 const TargetRegisterInfo *TRI) const { 1028 llvm_unreachable("Target didn't implement " 1029 "TargetInstrInfo::loadRegFromStackSlot!"); 1030 } 1031 1032 /// This function is called for all pseudo instructions 1033 /// that remain after register allocation. Many pseudo instructions are 1034 /// created to help register allocation. This is the place to convert them 1035 /// into real instructions. The target can edit MI in place, or it can insert 1036 /// new instructions and erase MI. The function should return true if 1037 /// anything was changed. 1038 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; } 1039 1040 /// Check whether the target can fold a load that feeds a subreg operand 1041 /// (or a subreg operand that feeds a store). 1042 /// For example, X86 may want to return true if it can fold 1043 /// movl (%esp), %eax 1044 /// subb, %al, ... 1045 /// Into: 1046 /// subb (%esp), ... 1047 /// 1048 /// Ideally, we'd like the target implementation of foldMemoryOperand() to 1049 /// reject subregs - but since this behavior used to be enforced in the 1050 /// target-independent code, moving this responsibility to the targets 1051 /// has the potential of causing nasty silent breakage in out-of-tree targets. 1052 virtual bool isSubregFoldable() const { return false; } 1053 1054 /// Attempt to fold a load or store of the specified stack 1055 /// slot into the specified machine instruction for the specified operand(s). 1056 /// If this is possible, a new instruction is returned with the specified 1057 /// operand folded, otherwise NULL is returned. 1058 /// The new instruction is inserted before MI, and the client is responsible 1059 /// for removing the old instruction. 1060 /// If VRM is passed, the assigned physregs can be inspected by target to 1061 /// decide on using an opcode (note that those assignments can still change). 1062 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1063 int FI, 1064 LiveIntervals *LIS = nullptr, 1065 VirtRegMap *VRM = nullptr) const; 1066 1067 /// Same as the previous version except it allows folding of any load and 1068 /// store from / to any address, not just from a specific stack slot. 1069 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, 1070 MachineInstr &LoadMI, 1071 LiveIntervals *LIS = nullptr) const; 1072 1073 /// Return true when there is potentially a faster code sequence 1074 /// for an instruction chain ending in \p Root. All potential patterns are 1075 /// returned in the \p Pattern vector. Pattern should be sorted in priority 1076 /// order since the pattern evaluator stops checking as soon as it finds a 1077 /// faster sequence. 1078 /// \param Root - Instruction that could be combined with one of its operands 1079 /// \param Patterns - Vector of possible combination patterns 1080 virtual bool 1081 getMachineCombinerPatterns(MachineInstr &Root, 1082 SmallVectorImpl<MachineCombinerPattern> &Patterns, 1083 bool DoRegPressureReduce) const; 1084 1085 /// Return true if target supports reassociation of instructions in machine 1086 /// combiner pass to reduce register pressure for a given BB. 1087 virtual bool 1088 shouldReduceRegisterPressure(MachineBasicBlock *MBB, 1089 RegisterClassInfo *RegClassInfo) const { 1090 return false; 1091 } 1092 1093 /// Fix up the placeholder we may add in genAlternativeCodeSequence(). 1094 virtual void 1095 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 1096 SmallVectorImpl<MachineInstr *> &InsInstrs) const {} 1097 1098 /// Return true when a code sequence can improve throughput. It 1099 /// should be called only for instructions in loops. 1100 /// \param Pattern - combiner pattern 1101 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const; 1102 1103 /// Return true if the input \P Inst is part of a chain of dependent ops 1104 /// that are suitable for reassociation, otherwise return false. 1105 /// If the instruction's operands must be commuted to have a previous 1106 /// instruction of the same type define the first source operand, \P Commuted 1107 /// will be set to true. 1108 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const; 1109 1110 /// Return true when \P Inst is both associative and commutative. 1111 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const { 1112 return false; 1113 } 1114 1115 /// Return true when \P Inst has reassociable operands in the same \P MBB. 1116 virtual bool hasReassociableOperands(const MachineInstr &Inst, 1117 const MachineBasicBlock *MBB) const; 1118 1119 /// Return true when \P Inst has reassociable sibling. 1120 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const; 1121 1122 /// When getMachineCombinerPatterns() finds patterns, this function generates 1123 /// the instructions that could replace the original code sequence. The client 1124 /// has to decide whether the actual replacement is beneficial or not. 1125 /// \param Root - Instruction that could be combined with one of its operands 1126 /// \param Pattern - Combination pattern for Root 1127 /// \param InsInstrs - Vector of new instructions that implement P 1128 /// \param DelInstrs - Old instructions, including Root, that could be 1129 /// replaced by InsInstr 1130 /// \param InstIdxForVirtReg - map of virtual register to instruction in 1131 /// InsInstr that defines it 1132 virtual void genAlternativeCodeSequence( 1133 MachineInstr &Root, MachineCombinerPattern Pattern, 1134 SmallVectorImpl<MachineInstr *> &InsInstrs, 1135 SmallVectorImpl<MachineInstr *> &DelInstrs, 1136 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const; 1137 1138 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to 1139 /// reduce critical path length. 1140 void reassociateOps(MachineInstr &Root, MachineInstr &Prev, 1141 MachineCombinerPattern Pattern, 1142 SmallVectorImpl<MachineInstr *> &InsInstrs, 1143 SmallVectorImpl<MachineInstr *> &DelInstrs, 1144 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 1145 1146 /// The limit on resource length extension we accept in MachineCombiner Pass. 1147 virtual int getExtendResourceLenLimit() const { return 0; } 1148 1149 /// This is an architecture-specific helper function of reassociateOps. 1150 /// Set special operand attributes for new instructions after reassociation. 1151 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 1152 MachineInstr &NewMI1, 1153 MachineInstr &NewMI2) const {} 1154 1155 virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const {} 1156 1157 /// Return true when a target supports MachineCombiner. 1158 virtual bool useMachineCombiner() const { return false; } 1159 1160 /// Return true if the given SDNode can be copied during scheduling 1161 /// even if it has glue. 1162 virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; } 1163 1164 protected: 1165 /// Target-dependent implementation for foldMemoryOperand. 1166 /// Target-independent code in foldMemoryOperand will 1167 /// take care of adding a MachineMemOperand to the newly created instruction. 1168 /// The instruction and any auxiliary instructions necessary will be inserted 1169 /// at InsertPt. 1170 virtual MachineInstr * 1171 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 1172 ArrayRef<unsigned> Ops, 1173 MachineBasicBlock::iterator InsertPt, int FrameIndex, 1174 LiveIntervals *LIS = nullptr, 1175 VirtRegMap *VRM = nullptr) const { 1176 return nullptr; 1177 } 1178 1179 /// Target-dependent implementation for foldMemoryOperand. 1180 /// Target-independent code in foldMemoryOperand will 1181 /// take care of adding a MachineMemOperand to the newly created instruction. 1182 /// The instruction and any auxiliary instructions necessary will be inserted 1183 /// at InsertPt. 1184 virtual MachineInstr *foldMemoryOperandImpl( 1185 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 1186 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 1187 LiveIntervals *LIS = nullptr) const { 1188 return nullptr; 1189 } 1190 1191 /// Target-dependent implementation of getRegSequenceInputs. 1192 /// 1193 /// \returns true if it is possible to build the equivalent 1194 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise. 1195 /// 1196 /// \pre MI.isRegSequenceLike(). 1197 /// 1198 /// \see TargetInstrInfo::getRegSequenceInputs. 1199 virtual bool getRegSequenceLikeInputs( 1200 const MachineInstr &MI, unsigned DefIdx, 1201 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { 1202 return false; 1203 } 1204 1205 /// Target-dependent implementation of getExtractSubregInputs. 1206 /// 1207 /// \returns true if it is possible to build the equivalent 1208 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1209 /// 1210 /// \pre MI.isExtractSubregLike(). 1211 /// 1212 /// \see TargetInstrInfo::getExtractSubregInputs. 1213 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, 1214 unsigned DefIdx, 1215 RegSubRegPairAndIdx &InputReg) const { 1216 return false; 1217 } 1218 1219 /// Target-dependent implementation of getInsertSubregInputs. 1220 /// 1221 /// \returns true if it is possible to build the equivalent 1222 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. 1223 /// 1224 /// \pre MI.isInsertSubregLike(). 1225 /// 1226 /// \see TargetInstrInfo::getInsertSubregInputs. 1227 virtual bool 1228 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 1229 RegSubRegPair &BaseReg, 1230 RegSubRegPairAndIdx &InsertedReg) const { 1231 return false; 1232 } 1233 1234 public: 1235 /// getAddressSpaceForPseudoSourceKind - Given the kind of memory 1236 /// (e.g. stack) the target returns the corresponding address space. 1237 virtual unsigned 1238 getAddressSpaceForPseudoSourceKind(unsigned Kind) const { 1239 return 0; 1240 } 1241 1242 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 1243 /// a store or a load and a store into two or more instruction. If this is 1244 /// possible, returns true as well as the new instructions by reference. 1245 virtual bool 1246 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 1247 bool UnfoldLoad, bool UnfoldStore, 1248 SmallVectorImpl<MachineInstr *> &NewMIs) const { 1249 return false; 1250 } 1251 1252 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 1253 SmallVectorImpl<SDNode *> &NewNodes) const { 1254 return false; 1255 } 1256 1257 /// Returns the opcode of the would be new 1258 /// instruction after load / store are unfolded from an instruction of the 1259 /// specified opcode. It returns zero if the specified unfolding is not 1260 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 1261 /// index of the operand which will hold the register holding the loaded 1262 /// value. 1263 virtual unsigned 1264 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 1265 unsigned *LoadRegIndex = nullptr) const { 1266 return 0; 1267 } 1268 1269 /// This is used by the pre-regalloc scheduler to determine if two loads are 1270 /// loading from the same base address. It should only return true if the base 1271 /// pointers are the same and the only differences between the two addresses 1272 /// are the offset. It also returns the offsets by reference. 1273 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1274 int64_t &Offset1, 1275 int64_t &Offset2) const { 1276 return false; 1277 } 1278 1279 /// This is a used by the pre-regalloc scheduler to determine (in conjunction 1280 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together. 1281 /// On some targets if two loads are loading from 1282 /// addresses in the same cache line, it's better if they are scheduled 1283 /// together. This function takes two integers that represent the load offsets 1284 /// from the common base address. It returns true if it decides it's desirable 1285 /// to schedule the two loads together. "NumLoads" is the number of loads that 1286 /// have already been scheduled after Load1. 1287 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1288 int64_t Offset1, int64_t Offset2, 1289 unsigned NumLoads) const { 1290 return false; 1291 } 1292 1293 /// Get the base operand and byte offset of an instruction that reads/writes 1294 /// memory. This is a convenience function for callers that are only prepared 1295 /// to handle a single base operand. 1296 bool getMemOperandWithOffset(const MachineInstr &MI, 1297 const MachineOperand *&BaseOp, int64_t &Offset, 1298 bool &OffsetIsScalable, 1299 const TargetRegisterInfo *TRI) const; 1300 1301 /// Get zero or more base operands and the byte offset of an instruction that 1302 /// reads/writes memory. Note that there may be zero base operands if the 1303 /// instruction accesses a constant address. 1304 /// It returns false if MI does not read/write memory. 1305 /// It returns false if base operands and offset could not be determined. 1306 /// It is not guaranteed to always recognize base operands and offsets in all 1307 /// cases. 1308 virtual bool getMemOperandsWithOffsetWidth( 1309 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, 1310 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, 1311 const TargetRegisterInfo *TRI) const { 1312 return false; 1313 } 1314 1315 /// Return true if the instruction contains a base register and offset. If 1316 /// true, the function also sets the operand position in the instruction 1317 /// for the base register and offset. 1318 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, 1319 unsigned &BasePos, 1320 unsigned &OffsetPos) const { 1321 return false; 1322 } 1323 1324 /// Target dependent implementation to get the values constituting the address 1325 /// MachineInstr that is accessing memory. These values are returned as a 1326 /// struct ExtAddrMode which contains all relevant information to make up the 1327 /// address. 1328 virtual Optional<ExtAddrMode> 1329 getAddrModeFromMemoryOp(const MachineInstr &MemI, 1330 const TargetRegisterInfo *TRI) const { 1331 return None; 1332 } 1333 1334 /// Returns true if MI's Def is NullValueReg, and the MI 1335 /// does not change the Zero value. i.e. cases such as rax = shr rax, X where 1336 /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this 1337 /// function can return true even if becomes zero. Specifically cases such as 1338 /// NullValueReg = shl NullValueReg, 63. 1339 virtual bool preservesZeroValueInReg(const MachineInstr *MI, 1340 const Register NullValueReg, 1341 const TargetRegisterInfo *TRI) const { 1342 return false; 1343 } 1344 1345 /// If the instruction is an increment of a constant value, return the amount. 1346 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const { 1347 return false; 1348 } 1349 1350 /// Returns true if the two given memory operations should be scheduled 1351 /// adjacent. Note that you have to add: 1352 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 1353 /// or 1354 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 1355 /// to TargetPassConfig::createMachineScheduler() to have an effect. 1356 /// 1357 /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations. 1358 /// \p NumLoads is the number of loads that will be in the cluster if this 1359 /// hook returns true. 1360 /// \p NumBytes is the number of bytes that will be loaded from all the 1361 /// clustered loads if this hook returns true. 1362 virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 1363 ArrayRef<const MachineOperand *> BaseOps2, 1364 unsigned NumLoads, unsigned NumBytes) const { 1365 llvm_unreachable("target did not implement shouldClusterMemOps()"); 1366 } 1367 1368 /// Reverses the branch condition of the specified condition list, 1369 /// returning false on success and true if it cannot be reversed. 1370 virtual bool 1371 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 1372 return true; 1373 } 1374 1375 /// Insert a noop into the instruction stream at the specified point. 1376 virtual void insertNoop(MachineBasicBlock &MBB, 1377 MachineBasicBlock::iterator MI) const; 1378 1379 /// Insert noops into the instruction stream at the specified point. 1380 virtual void insertNoops(MachineBasicBlock &MBB, 1381 MachineBasicBlock::iterator MI, 1382 unsigned Quantity) const; 1383 1384 /// Return the noop instruction to use for a noop. 1385 virtual void getNoop(MCInst &NopInst) const; 1386 1387 /// Return true for post-incremented instructions. 1388 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; } 1389 1390 /// Returns true if the instruction is already predicated. 1391 virtual bool isPredicated(const MachineInstr &MI) const { return false; } 1392 1393 // Returns a MIRPrinter comment for this machine operand. 1394 virtual std::string 1395 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 1396 unsigned OpIdx, const TargetRegisterInfo *TRI) const; 1397 1398 /// Returns true if the instruction is a 1399 /// terminator instruction that has not been predicated. 1400 bool isUnpredicatedTerminator(const MachineInstr &MI) const; 1401 1402 /// Returns true if MI is an unconditional tail call. 1403 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const { 1404 return false; 1405 } 1406 1407 /// Returns true if the tail call can be made conditional on BranchCond. 1408 virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 1409 const MachineInstr &TailCall) const { 1410 return false; 1411 } 1412 1413 /// Replace the conditional branch in MBB with a conditional tail call. 1414 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, 1415 SmallVectorImpl<MachineOperand> &Cond, 1416 const MachineInstr &TailCall) const { 1417 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!"); 1418 } 1419 1420 /// Convert the instruction into a predicated instruction. 1421 /// It returns true if the operation was successful. 1422 virtual bool PredicateInstruction(MachineInstr &MI, 1423 ArrayRef<MachineOperand> Pred) const; 1424 1425 /// Returns true if the first specified predicate 1426 /// subsumes the second, e.g. GE subsumes GT. 1427 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 1428 ArrayRef<MachineOperand> Pred2) const { 1429 return false; 1430 } 1431 1432 /// If the specified instruction defines any predicate 1433 /// or condition code register(s) used for predication, returns true as well 1434 /// as the definition predicate(s) by reference. 1435 /// SkipDead should be set to false at any point that dead 1436 /// predicate instructions should be considered as being defined. 1437 /// A dead predicate instruction is one that is guaranteed to be removed 1438 /// after a call to PredicateInstruction. 1439 virtual bool ClobbersPredicate(MachineInstr &MI, 1440 std::vector<MachineOperand> &Pred, 1441 bool SkipDead) const { 1442 return false; 1443 } 1444 1445 /// Return true if the specified instruction can be predicated. 1446 /// By default, this returns true for every instruction with a 1447 /// PredicateOperand. 1448 virtual bool isPredicable(const MachineInstr &MI) const { 1449 return MI.getDesc().isPredicable(); 1450 } 1451 1452 /// Return true if it's safe to move a machine 1453 /// instruction that defines the specified register class. 1454 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 1455 return true; 1456 } 1457 1458 /// Test if the given instruction should be considered a scheduling boundary. 1459 /// This primarily includes labels and terminators. 1460 virtual bool isSchedulingBoundary(const MachineInstr &MI, 1461 const MachineBasicBlock *MBB, 1462 const MachineFunction &MF) const; 1463 1464 /// Measure the specified inline asm to determine an approximation of its 1465 /// length. 1466 virtual unsigned getInlineAsmLength( 1467 const char *Str, const MCAsmInfo &MAI, 1468 const TargetSubtargetInfo *STI = nullptr) const; 1469 1470 /// Allocate and return a hazard recognizer to use for this target when 1471 /// scheduling the machine instructions before register allocation. 1472 virtual ScheduleHazardRecognizer * 1473 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 1474 const ScheduleDAG *DAG) const; 1475 1476 /// Allocate and return a hazard recognizer to use for this target when 1477 /// scheduling the machine instructions before register allocation. 1478 virtual ScheduleHazardRecognizer * 1479 CreateTargetMIHazardRecognizer(const InstrItineraryData *, 1480 const ScheduleDAGMI *DAG) const; 1481 1482 /// Allocate and return a hazard recognizer to use for this target when 1483 /// scheduling the machine instructions after register allocation. 1484 virtual ScheduleHazardRecognizer * 1485 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, 1486 const ScheduleDAG *DAG) const; 1487 1488 /// Allocate and return a hazard recognizer to use for by non-scheduling 1489 /// passes. 1490 virtual ScheduleHazardRecognizer * 1491 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const { 1492 return nullptr; 1493 } 1494 1495 /// Provide a global flag for disabling the PreRA hazard recognizer that 1496 /// targets may choose to honor. 1497 bool usePreRAHazardRecognizer() const; 1498 1499 /// For a comparison instruction, return the source registers 1500 /// in SrcReg and SrcReg2 if having two register operands, and the value it 1501 /// compares against in CmpValue. Return true if the comparison instruction 1502 /// can be analyzed. 1503 virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 1504 Register &SrcReg2, int &Mask, int &Value) const { 1505 return false; 1506 } 1507 1508 /// See if the comparison instruction can be converted 1509 /// into something more efficient. E.g., on ARM most instructions can set the 1510 /// flags register, obviating the need for a separate CMP. 1511 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 1512 Register SrcReg2, int Mask, int Value, 1513 const MachineRegisterInfo *MRI) const { 1514 return false; 1515 } 1516 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; } 1517 1518 /// Try to remove the load by folding it to a register operand at the use. 1519 /// We fold the load instructions if and only if the 1520 /// def and use are in the same BB. We only look at one load and see 1521 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 1522 /// defined by the load we are trying to fold. DefMI returns the machine 1523 /// instruction that defines FoldAsLoadDefReg, and the function returns 1524 /// the machine instruction generated due to folding. 1525 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI, 1526 const MachineRegisterInfo *MRI, 1527 Register &FoldAsLoadDefReg, 1528 MachineInstr *&DefMI) const { 1529 return nullptr; 1530 } 1531 1532 /// 'Reg' is known to be defined by a move immediate instruction, 1533 /// try to fold the immediate into the use instruction. 1534 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 1535 /// then the caller may assume that DefMI has been erased from its parent 1536 /// block. The caller may assume that it will not be erased by this 1537 /// function otherwise. 1538 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 1539 Register Reg, MachineRegisterInfo *MRI) const { 1540 return false; 1541 } 1542 1543 /// Return the number of u-operations the given machine 1544 /// instruction will be decoded to on the target cpu. The itinerary's 1545 /// IssueWidth is the number of microops that can be dispatched each 1546 /// cycle. An instruction with zero microops takes no dispatch resources. 1547 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 1548 const MachineInstr &MI) const; 1549 1550 /// Return true for pseudo instructions that don't consume any 1551 /// machine resources in their current form. These are common cases that the 1552 /// scheduler should consider free, rather than conservatively handling them 1553 /// as instructions with no itinerary. 1554 bool isZeroCost(unsigned Opcode) const { 1555 return Opcode <= TargetOpcode::COPY; 1556 } 1557 1558 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1559 SDNode *DefNode, unsigned DefIdx, 1560 SDNode *UseNode, unsigned UseIdx) const; 1561 1562 /// Compute and return the use operand latency of a given pair of def and use. 1563 /// In most cases, the static scheduling itinerary was enough to determine the 1564 /// operand latency. But it may not be possible for instructions with variable 1565 /// number of defs / uses. 1566 /// 1567 /// This is a raw interface to the itinerary that may be directly overridden 1568 /// by a target. Use computeOperandLatency to get the best estimate of 1569 /// latency. 1570 virtual int getOperandLatency(const InstrItineraryData *ItinData, 1571 const MachineInstr &DefMI, unsigned DefIdx, 1572 const MachineInstr &UseMI, 1573 unsigned UseIdx) const; 1574 1575 /// Compute the instruction latency of a given instruction. 1576 /// If the instruction has higher cost when predicated, it's returned via 1577 /// PredCost. 1578 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 1579 const MachineInstr &MI, 1580 unsigned *PredCost = nullptr) const; 1581 1582 virtual unsigned getPredicationCost(const MachineInstr &MI) const; 1583 1584 virtual int getInstrLatency(const InstrItineraryData *ItinData, 1585 SDNode *Node) const; 1586 1587 /// Return the default expected latency for a def based on its opcode. 1588 unsigned defaultDefLatency(const MCSchedModel &SchedModel, 1589 const MachineInstr &DefMI) const; 1590 1591 int computeDefOperandLatency(const InstrItineraryData *ItinData, 1592 const MachineInstr &DefMI) const; 1593 1594 /// Return true if this opcode has high latency to its result. 1595 virtual bool isHighLatencyDef(int opc) const { return false; } 1596 1597 /// Compute operand latency between a def of 'Reg' 1598 /// and a use in the current loop. Return true if the target considered 1599 /// it 'high'. This is used by optimization passes such as machine LICM to 1600 /// determine whether it makes sense to hoist an instruction out even in a 1601 /// high register pressure situation. 1602 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 1603 const MachineRegisterInfo *MRI, 1604 const MachineInstr &DefMI, unsigned DefIdx, 1605 const MachineInstr &UseMI, 1606 unsigned UseIdx) const { 1607 return false; 1608 } 1609 1610 /// Compute operand latency of a def of 'Reg'. Return true 1611 /// if the target considered it 'low'. 1612 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, 1613 const MachineInstr &DefMI, 1614 unsigned DefIdx) const; 1615 1616 /// Perform target-specific instruction verification. 1617 virtual bool verifyInstruction(const MachineInstr &MI, 1618 StringRef &ErrInfo) const { 1619 return true; 1620 } 1621 1622 /// Return the current execution domain and bit mask of 1623 /// possible domains for instruction. 1624 /// 1625 /// Some micro-architectures have multiple execution domains, and multiple 1626 /// opcodes that perform the same operation in different domains. For 1627 /// example, the x86 architecture provides the por, orps, and orpd 1628 /// instructions that all do the same thing. There is a latency penalty if a 1629 /// register is written in one domain and read in another. 1630 /// 1631 /// This function returns a pair (domain, mask) containing the execution 1632 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 1633 /// function can be used to change the opcode to one of the domains in the 1634 /// bit mask. Instructions whose execution domain can't be changed should 1635 /// return a 0 mask. 1636 /// 1637 /// The execution domain numbers don't have any special meaning except domain 1638 /// 0 is used for instructions that are not associated with any interesting 1639 /// execution domain. 1640 /// 1641 virtual std::pair<uint16_t, uint16_t> 1642 getExecutionDomain(const MachineInstr &MI) const { 1643 return std::make_pair(0, 0); 1644 } 1645 1646 /// Change the opcode of MI to execute in Domain. 1647 /// 1648 /// The bit (1 << Domain) must be set in the mask returned from 1649 /// getExecutionDomain(MI). 1650 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {} 1651 1652 /// Returns the preferred minimum clearance 1653 /// before an instruction with an unwanted partial register update. 1654 /// 1655 /// Some instructions only write part of a register, and implicitly need to 1656 /// read the other parts of the register. This may cause unwanted stalls 1657 /// preventing otherwise unrelated instructions from executing in parallel in 1658 /// an out-of-order CPU. 1659 /// 1660 /// For example, the x86 instruction cvtsi2ss writes its result to bits 1661 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 1662 /// the instruction needs to wait for the old value of the register to become 1663 /// available: 1664 /// 1665 /// addps %xmm1, %xmm0 1666 /// movaps %xmm0, (%rax) 1667 /// cvtsi2ss %rbx, %xmm0 1668 /// 1669 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 1670 /// instruction before it can issue, even though the high bits of %xmm0 1671 /// probably aren't needed. 1672 /// 1673 /// This hook returns the preferred clearance before MI, measured in 1674 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 1675 /// instructions before MI. It should only return a positive value for 1676 /// unwanted dependencies. If the old bits of the defined register have 1677 /// useful values, or if MI is determined to otherwise read the dependency, 1678 /// the hook should return 0. 1679 /// 1680 /// The unwanted dependency may be handled by: 1681 /// 1682 /// 1. Allocating the same register for an MI def and use. That makes the 1683 /// unwanted dependency identical to a required dependency. 1684 /// 1685 /// 2. Allocating a register for the def that has no defs in the previous N 1686 /// instructions. 1687 /// 1688 /// 3. Calling breakPartialRegDependency() with the same arguments. This 1689 /// allows the target to insert a dependency breaking instruction. 1690 /// 1691 virtual unsigned 1692 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 1693 const TargetRegisterInfo *TRI) const { 1694 // The default implementation returns 0 for no partial register dependency. 1695 return 0; 1696 } 1697 1698 /// Return the minimum clearance before an instruction that reads an 1699 /// unused register. 1700 /// 1701 /// For example, AVX instructions may copy part of a register operand into 1702 /// the unused high bits of the destination register. 1703 /// 1704 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14 1705 /// 1706 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 1707 /// false dependence on any previous write to %xmm0. 1708 /// 1709 /// This hook works similarly to getPartialRegUpdateClearance, except that it 1710 /// does not take an operand index. Instead sets \p OpNum to the index of the 1711 /// unused register. 1712 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 1713 const TargetRegisterInfo *TRI) const { 1714 // The default implementation returns 0 for no undef register dependency. 1715 return 0; 1716 } 1717 1718 /// Insert a dependency-breaking instruction 1719 /// before MI to eliminate an unwanted dependency on OpNum. 1720 /// 1721 /// If it wasn't possible to avoid a def in the last N instructions before MI 1722 /// (see getPartialRegUpdateClearance), this hook will be called to break the 1723 /// unwanted dependency. 1724 /// 1725 /// On x86, an xorps instruction can be used as a dependency breaker: 1726 /// 1727 /// addps %xmm1, %xmm0 1728 /// movaps %xmm0, (%rax) 1729 /// xorps %xmm0, %xmm0 1730 /// cvtsi2ss %rbx, %xmm0 1731 /// 1732 /// An <imp-kill> operand should be added to MI if an instruction was 1733 /// inserted. This ties the instructions together in the post-ra scheduler. 1734 /// 1735 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 1736 const TargetRegisterInfo *TRI) const {} 1737 1738 /// Create machine specific model for scheduling. 1739 virtual DFAPacketizer * 1740 CreateTargetScheduleState(const TargetSubtargetInfo &) const { 1741 return nullptr; 1742 } 1743 1744 /// Sometimes, it is possible for the target 1745 /// to tell, even without aliasing information, that two MIs access different 1746 /// memory addresses. This function returns true if two MIs access different 1747 /// memory addresses and false otherwise. 1748 /// 1749 /// Assumes any physical registers used to compute addresses have the same 1750 /// value for both instructions. (This is the most useful assumption for 1751 /// post-RA scheduling.) 1752 /// 1753 /// See also MachineInstr::mayAlias, which is implemented on top of this 1754 /// function. 1755 virtual bool 1756 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 1757 const MachineInstr &MIb) const { 1758 assert(MIa.mayLoadOrStore() && 1759 "MIa must load from or modify a memory location"); 1760 assert(MIb.mayLoadOrStore() && 1761 "MIb must load from or modify a memory location"); 1762 return false; 1763 } 1764 1765 /// Return the value to use for the MachineCSE's LookAheadLimit, 1766 /// which is a heuristic used for CSE'ing phys reg defs. 1767 virtual unsigned getMachineCSELookAheadLimit() const { 1768 // The default lookahead is small to prevent unprofitable quadratic 1769 // behavior. 1770 return 5; 1771 } 1772 1773 /// Return the maximal number of alias checks on memory operands. For 1774 /// instructions with more than one memory operands, the alias check on a 1775 /// single MachineInstr pair has quadratic overhead and results in 1776 /// unacceptable performance in the worst case. The limit here is to clamp 1777 /// that maximal checks performed. Usually, that's the product of memory 1778 /// operand numbers from that pair of MachineInstr to be checked. For 1779 /// instance, with two MachineInstrs with 4 and 5 memory operands 1780 /// correspondingly, a total of 20 checks are required. With this limit set to 1781 /// 16, their alias check is skipped. We choose to limit the product instead 1782 /// of the individual instruction as targets may have special MachineInstrs 1783 /// with a considerably high number of memory operands, such as `ldm` in ARM. 1784 /// Setting this limit per MachineInstr would result in either too high 1785 /// overhead or too rigid restriction. 1786 virtual unsigned getMemOperandAACheckLimit() const { return 16; } 1787 1788 /// Return an array that contains the ids of the target indices (used for the 1789 /// TargetIndex machine operand) and their names. 1790 /// 1791 /// MIR Serialization is able to serialize only the target indices that are 1792 /// defined by this method. 1793 virtual ArrayRef<std::pair<int, const char *>> 1794 getSerializableTargetIndices() const { 1795 return None; 1796 } 1797 1798 /// Decompose the machine operand's target flags into two values - the direct 1799 /// target flag value and any of bit flags that are applied. 1800 virtual std::pair<unsigned, unsigned> 1801 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const { 1802 return std::make_pair(0u, 0u); 1803 } 1804 1805 /// Return an array that contains the direct target flag values and their 1806 /// names. 1807 /// 1808 /// MIR Serialization is able to serialize only the target flags that are 1809 /// defined by this method. 1810 virtual ArrayRef<std::pair<unsigned, const char *>> 1811 getSerializableDirectMachineOperandTargetFlags() const { 1812 return None; 1813 } 1814 1815 /// Return an array that contains the bitmask target flag values and their 1816 /// names. 1817 /// 1818 /// MIR Serialization is able to serialize only the target flags that are 1819 /// defined by this method. 1820 virtual ArrayRef<std::pair<unsigned, const char *>> 1821 getSerializableBitmaskMachineOperandTargetFlags() const { 1822 return None; 1823 } 1824 1825 /// Return an array that contains the MMO target flag values and their 1826 /// names. 1827 /// 1828 /// MIR Serialization is able to serialize only the MMO target flags that are 1829 /// defined by this method. 1830 virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> 1831 getSerializableMachineMemOperandTargetFlags() const { 1832 return None; 1833 } 1834 1835 /// Determines whether \p Inst is a tail call instruction. Override this 1836 /// method on targets that do not properly set MCID::Return and MCID::Call on 1837 /// tail call instructions." 1838 virtual bool isTailCall(const MachineInstr &Inst) const { 1839 return Inst.isReturn() && Inst.isCall(); 1840 } 1841 1842 /// True if the instruction is bound to the top of its basic block and no 1843 /// other instructions shall be inserted before it. This can be implemented 1844 /// to prevent register allocator to insert spills before such instructions. 1845 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const { 1846 return false; 1847 } 1848 1849 /// During PHI eleimination lets target to make necessary checks and 1850 /// insert the copy to the PHI destination register in a target specific 1851 /// manner. 1852 virtual MachineInstr *createPHIDestinationCopy( 1853 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, 1854 const DebugLoc &DL, Register Src, Register Dst) const { 1855 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1856 .addReg(Src); 1857 } 1858 1859 /// During PHI eleimination lets target to make necessary checks and 1860 /// insert the copy to the PHI destination register in a target specific 1861 /// manner. 1862 virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB, 1863 MachineBasicBlock::iterator InsPt, 1864 const DebugLoc &DL, Register Src, 1865 unsigned SrcSubReg, 1866 Register Dst) const { 1867 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) 1868 .addReg(Src, 0, SrcSubReg); 1869 } 1870 1871 /// Returns a \p outliner::OutlinedFunction struct containing target-specific 1872 /// information for a set of outlining candidates. 1873 virtual outliner::OutlinedFunction getOutliningCandidateInfo( 1874 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { 1875 llvm_unreachable( 1876 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!"); 1877 } 1878 1879 /// Returns how or if \p MI should be outlined. 1880 virtual outliner::InstrType 1881 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { 1882 llvm_unreachable( 1883 "Target didn't implement TargetInstrInfo::getOutliningType!"); 1884 } 1885 1886 /// Optional target hook that returns true if \p MBB is safe to outline from, 1887 /// and returns any target-specific information in \p Flags. 1888 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 1889 unsigned &Flags) const { 1890 return true; 1891 } 1892 1893 /// Insert a custom frame for outlined functions. 1894 virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 1895 const outliner::OutlinedFunction &OF) const { 1896 llvm_unreachable( 1897 "Target didn't implement TargetInstrInfo::buildOutlinedFrame!"); 1898 } 1899 1900 /// Insert a call to an outlined function into the program. 1901 /// Returns an iterator to the spot where we inserted the call. This must be 1902 /// implemented by the target. 1903 virtual MachineBasicBlock::iterator 1904 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 1905 MachineBasicBlock::iterator &It, MachineFunction &MF, 1906 const outliner::Candidate &C) const { 1907 llvm_unreachable( 1908 "Target didn't implement TargetInstrInfo::insertOutlinedCall!"); 1909 } 1910 1911 /// Return true if the function can safely be outlined from. 1912 /// A function \p MF is considered safe for outlining if an outlined function 1913 /// produced from instructions in F will produce a program which produces the 1914 /// same output for any set of given inputs. 1915 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 1916 bool OutlineFromLinkOnceODRs) const { 1917 llvm_unreachable("Target didn't implement " 1918 "TargetInstrInfo::isFunctionSafeToOutlineFrom!"); 1919 } 1920 1921 /// Return true if the function should be outlined from by default. 1922 virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const { 1923 return false; 1924 } 1925 1926 /// Produce the expression describing the \p MI loading a value into 1927 /// the physical register \p Reg. This hook should only be used with 1928 /// \p MIs belonging to VReg-less functions. 1929 virtual Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 1930 Register Reg) const; 1931 1932 /// Return MIR formatter to format/parse MIR operands. Target can override 1933 /// this virtual function and return target specific MIR formatter. 1934 virtual const MIRFormatter *getMIRFormatter() const { 1935 if (!Formatter.get()) 1936 Formatter = std::make_unique<MIRFormatter>(); 1937 return Formatter.get(); 1938 } 1939 1940 private: 1941 mutable std::unique_ptr<MIRFormatter> Formatter; 1942 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode; 1943 unsigned CatchRetOpcode; 1944 unsigned ReturnOpcode; 1945 }; 1946 1947 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair. 1948 template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> { 1949 using RegInfo = DenseMapInfo<unsigned>; 1950 1951 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() { 1952 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(), 1953 RegInfo::getEmptyKey()); 1954 } 1955 1956 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() { 1957 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(), 1958 RegInfo::getTombstoneKey()); 1959 } 1960 1961 /// Reuse getHashValue implementation from 1962 /// std::pair<unsigned, unsigned>. 1963 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) { 1964 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg); 1965 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal); 1966 } 1967 1968 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, 1969 const TargetInstrInfo::RegSubRegPair &RHS) { 1970 return RegInfo::isEqual(LHS.Reg, RHS.Reg) && 1971 RegInfo::isEqual(LHS.SubReg, RHS.SubReg); 1972 } 1973 }; 1974 1975 } // end namespace llvm 1976 1977 #endif // LLVM_TARGET_TARGETINSTRINFO_H 1978