1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MCOperandInfo and MCInstrDesc classes, which 10 // are used to describe target instructions and their operands. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_MC_MCINSTRDESC_H 15 #define LLVM_MC_MCINSTRDESC_H 16 17 #include "llvm/MC/MCRegisterInfo.h" 18 #include "llvm/Support/DataTypes.h" 19 #include <string> 20 21 namespace llvm { 22 23 class MCInst; 24 25 //===----------------------------------------------------------------------===// 26 // Machine Operand Flags and Description 27 //===----------------------------------------------------------------------===// 28 29 namespace MCOI { 30 // Operand constraints 31 enum OperandConstraint { 32 TIED_TO = 0, // Must be allocated the same register as. 33 EARLY_CLOBBER // Operand is an early clobber register operand 34 }; 35 36 /// These are flags set on operands, but should be considered 37 /// private, all access should go through the MCOperandInfo accessors. 38 /// See the accessors for a description of what these are. 39 enum OperandFlags { 40 LookupPtrRegClass = 0, 41 Predicate, 42 OptionalDef, 43 BranchTarget 44 }; 45 46 /// Operands are tagged with one of the values of this enum. 47 enum OperandType { 48 OPERAND_UNKNOWN = 0, 49 OPERAND_IMMEDIATE = 1, 50 OPERAND_REGISTER = 2, 51 OPERAND_MEMORY = 3, 52 OPERAND_PCREL = 4, 53 54 OPERAND_FIRST_GENERIC = 6, 55 OPERAND_GENERIC_0 = 6, 56 OPERAND_GENERIC_1 = 7, 57 OPERAND_GENERIC_2 = 8, 58 OPERAND_GENERIC_3 = 9, 59 OPERAND_GENERIC_4 = 10, 60 OPERAND_GENERIC_5 = 11, 61 OPERAND_LAST_GENERIC = 11, 62 63 OPERAND_FIRST_GENERIC_IMM = 12, 64 OPERAND_GENERIC_IMM_0 = 12, 65 OPERAND_LAST_GENERIC_IMM = 12, 66 67 OPERAND_FIRST_TARGET = 13, 68 }; 69 70 } 71 72 /// This holds information about one operand of a machine instruction, 73 /// indicating the register class for register operands, etc. 74 class MCOperandInfo { 75 public: 76 /// This specifies the register class enumeration of the operand 77 /// if the operand is a register. If isLookupPtrRegClass is set, then this is 78 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 79 /// get a dynamic register class. 80 int16_t RegClass; 81 82 /// These are flags from the MCOI::OperandFlags enum. 83 uint8_t Flags; 84 85 /// Information about the type of the operand. 86 uint8_t OperandType; 87 /// The lower 16 bits are used to specify which constraints are set. 88 /// The higher 16 bits are used to specify the value of constraints (4 bits 89 /// each). 90 uint32_t Constraints; 91 92 /// Set if this operand is a pointer value and it requires a callback 93 /// to look up its register class. 94 bool isLookupPtrRegClass() const { 95 return Flags & (1 << MCOI::LookupPtrRegClass); 96 } 97 98 /// Set if this is one of the operands that made up of the predicate 99 /// operand that controls an isPredicable() instruction. 100 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 101 102 /// Set if this operand is a optional def. 103 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 104 105 /// Set if this operand is a branch target. 106 bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); } 107 108 bool isGenericType() const { 109 return OperandType >= MCOI::OPERAND_FIRST_GENERIC && 110 OperandType <= MCOI::OPERAND_LAST_GENERIC; 111 } 112 113 unsigned getGenericTypeIndex() const { 114 assert(isGenericType() && "non-generic types don't have an index"); 115 return OperandType - MCOI::OPERAND_FIRST_GENERIC; 116 } 117 118 bool isGenericImm() const { 119 return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM && 120 OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM; 121 } 122 123 unsigned getGenericImmIndex() const { 124 assert(isGenericImm() && "non-generic immediates don't have an index"); 125 return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM; 126 } 127 }; 128 129 //===----------------------------------------------------------------------===// 130 // Machine Instruction Flags and Description 131 //===----------------------------------------------------------------------===// 132 133 namespace MCID { 134 /// These should be considered private to the implementation of the 135 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc, 136 /// not use these directly. These all correspond to bitfields in the 137 /// MCInstrDesc::Flags field. 138 enum Flag { 139 PreISelOpcode = 0, 140 Variadic, 141 HasOptionalDef, 142 Pseudo, 143 Return, 144 EHScopeReturn, 145 Call, 146 Barrier, 147 Terminator, 148 Branch, 149 IndirectBranch, 150 Compare, 151 MoveImm, 152 MoveReg, 153 Bitcast, 154 Select, 155 DelaySlot, 156 FoldableAsLoad, 157 MayLoad, 158 MayStore, 159 MayRaiseFPException, 160 Predicable, 161 NotDuplicable, 162 UnmodeledSideEffects, 163 Commutable, 164 ConvertibleTo3Addr, 165 UsesCustomInserter, 166 HasPostISelHook, 167 Rematerializable, 168 CheapAsAMove, 169 ExtraSrcRegAllocReq, 170 ExtraDefRegAllocReq, 171 RegSequence, 172 ExtractSubreg, 173 InsertSubreg, 174 Convergent, 175 Add, 176 Trap, 177 VariadicOpsAreDefs, 178 Authenticated, 179 }; 180 } 181 182 /// Describe properties that are true of each instruction in the target 183 /// description file. This captures information about side effects, register 184 /// use and many other things. There is one instance of this struct for each 185 /// target instruction class, and the MachineInstr class points to this struct 186 /// directly to describe itself. 187 class MCInstrDesc { 188 public: 189 unsigned short Opcode; // The opcode number 190 unsigned short NumOperands; // Num of args (may be more if variable_ops) 191 unsigned char NumDefs; // Num of args that are definitions 192 unsigned char Size; // Number of bytes in encoding. 193 unsigned short SchedClass; // enum identifying instr sched class 194 uint64_t Flags; // Flags identifying machine instr class 195 uint64_t TSFlags; // Target Specific Flag values 196 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr 197 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr 198 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 199 200 /// Returns the value of the specific constraint if 201 /// it is set. Returns -1 if it is not set. 202 int getOperandConstraint(unsigned OpNum, 203 MCOI::OperandConstraint Constraint) const { 204 if (OpNum < NumOperands && 205 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 206 unsigned Pos = 16 + Constraint * 4; 207 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 208 } 209 return -1; 210 } 211 212 /// Return the opcode number for this descriptor. 213 unsigned getOpcode() const { return Opcode; } 214 215 /// Return the number of declared MachineOperands for this 216 /// MachineInstruction. Note that variadic (isVariadic() returns true) 217 /// instructions may have additional operands at the end of the list, and note 218 /// that the machine instruction may include implicit register def/uses as 219 /// well. 220 unsigned getNumOperands() const { return NumOperands; } 221 222 using const_opInfo_iterator = const MCOperandInfo *; 223 224 const_opInfo_iterator opInfo_begin() const { return OpInfo; } 225 const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; } 226 227 iterator_range<const_opInfo_iterator> operands() const { 228 return make_range(opInfo_begin(), opInfo_end()); 229 } 230 231 /// Return the number of MachineOperands that are register 232 /// definitions. Register definitions always occur at the start of the 233 /// machine operand list. This is the number of "outs" in the .td file, 234 /// and does not include implicit defs. 235 unsigned getNumDefs() const { return NumDefs; } 236 237 /// Return flags of this instruction. 238 uint64_t getFlags() const { return Flags; } 239 240 /// \returns true if this instruction is emitted before instruction selection 241 /// and should be legalized/regbankselected/selected. 242 bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); } 243 244 /// Return true if this instruction can have a variable number of 245 /// operands. In this case, the variable operands will be after the normal 246 /// operands but before the implicit definitions and uses (if any are 247 /// present). 248 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); } 249 250 /// Set if this instruction has an optional definition, e.g. 251 /// ARM instructions which can set condition code if 's' bit is set. 252 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); } 253 254 /// Return true if this is a pseudo instruction that doesn't 255 /// correspond to a real machine instruction. 256 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); } 257 258 /// Return true if the instruction is a return. 259 bool isReturn() const { return Flags & (1ULL << MCID::Return); } 260 261 /// Return true if the instruction is an add instruction. 262 bool isAdd() const { return Flags & (1ULL << MCID::Add); } 263 264 /// Return true if this instruction is a trap. 265 bool isTrap() const { return Flags & (1ULL << MCID::Trap); } 266 267 /// Return true if the instruction is a register to register move. 268 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } 269 270 /// Return true if the instruction is a call. 271 bool isCall() const { return Flags & (1ULL << MCID::Call); } 272 273 /// Returns true if the specified instruction stops control flow 274 /// from executing the instruction immediately following it. Examples include 275 /// unconditional branches and return instructions. 276 bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); } 277 278 /// Returns true if this instruction part of the terminator for 279 /// a basic block. Typically this is things like return and branch 280 /// instructions. 281 /// 282 /// Various passes use this to insert code into the bottom of a basic block, 283 /// but before control flow occurs. 284 bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); } 285 286 /// Returns true if this is a conditional, unconditional, or 287 /// indirect branch. Predicates below can be used to discriminate between 288 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to 289 /// get more information. 290 bool isBranch() const { return Flags & (1ULL << MCID::Branch); } 291 292 /// Return true if this is an indirect branch, such as a 293 /// branch through a register. 294 bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); } 295 296 /// Return true if this is a branch which may fall 297 /// through to the next instruction or may transfer control flow to some other 298 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more 299 /// information about this branch. 300 bool isConditionalBranch() const { 301 return isBranch() && !isBarrier() && !isIndirectBranch(); 302 } 303 304 /// Return true if this is a branch which always 305 /// transfers control flow to some other block. The 306 /// TargetInstrInfo::analyzeBranch method can be used to get more information 307 /// about this branch. 308 bool isUnconditionalBranch() const { 309 return isBranch() && isBarrier() && !isIndirectBranch(); 310 } 311 312 /// Return true if this is a branch or an instruction which directly 313 /// writes to the program counter. Considered 'may' affect rather than 314 /// 'does' affect as things like predication are not taken into account. 315 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const; 316 317 /// Return true if this instruction has a predicate operand 318 /// that controls execution. It may be set to 'always', or may be set to other 319 /// values. There are various methods in TargetInstrInfo that can be used to 320 /// control and modify the predicate in this instruction. 321 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } 322 323 /// Return true if this instruction is a comparison. 324 bool isCompare() const { return Flags & (1ULL << MCID::Compare); } 325 326 /// Return true if this instruction is a move immediate 327 /// (including conditional moves) instruction. 328 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); } 329 330 /// Return true if this instruction is a bitcast instruction. 331 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); } 332 333 /// Return true if this is a select instruction. 334 bool isSelect() const { return Flags & (1ULL << MCID::Select); } 335 336 /// Return true if this instruction cannot be safely 337 /// duplicated. For example, if the instruction has a unique labels attached 338 /// to it, duplicating it would cause multiple definition errors. 339 bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); } 340 341 /// Returns true if the specified instruction has a delay slot which 342 /// must be filled by the code generator. 343 bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); } 344 345 /// Return true for instructions that can be folded as memory operands 346 /// in other instructions. The most common use for this is instructions that 347 /// are simple loads from memory that don't modify the loaded value in any 348 /// way, but it can also be used for instructions that can be expressed as 349 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be 350 /// folded when it is beneficial. This should only be set on instructions 351 /// that return a value in their only virtual register definition. 352 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); } 353 354 /// Return true if this instruction behaves 355 /// the same way as the generic REG_SEQUENCE instructions. 356 /// E.g., on ARM, 357 /// dX VMOVDRR rY, rZ 358 /// is equivalent to 359 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 360 /// 361 /// Note that for the optimizers to be able to take advantage of 362 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 363 /// override accordingly. 364 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); } 365 366 /// Return true if this instruction behaves 367 /// the same way as the generic EXTRACT_SUBREG instructions. 368 /// E.g., on ARM, 369 /// rX, rY VMOVRRD dZ 370 /// is equivalent to two EXTRACT_SUBREG: 371 /// rX = EXTRACT_SUBREG dZ, ssub_0 372 /// rY = EXTRACT_SUBREG dZ, ssub_1 373 /// 374 /// Note that for the optimizers to be able to take advantage of 375 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 376 /// override accordingly. 377 bool isExtractSubregLike() const { 378 return Flags & (1ULL << MCID::ExtractSubreg); 379 } 380 381 /// Return true if this instruction behaves 382 /// the same way as the generic INSERT_SUBREG instructions. 383 /// E.g., on ARM, 384 /// dX = VSETLNi32 dY, rZ, Imm 385 /// is equivalent to a INSERT_SUBREG: 386 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 387 /// 388 /// Note that for the optimizers to be able to take advantage of 389 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 390 /// override accordingly. 391 bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); } 392 393 394 /// Return true if this instruction is convergent. 395 /// 396 /// Convergent instructions may not be made control-dependent on any 397 /// additional values. 398 bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); } 399 400 /// Return true if variadic operands of this instruction are definitions. 401 bool variadicOpsAreDefs() const { 402 return Flags & (1ULL << MCID::VariadicOpsAreDefs); 403 } 404 405 /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx 406 /// from ARMv8.3, which perform loads/branches with authentication). 407 /// 408 /// An authenticated instruction may fail in an ABI-defined manner when 409 /// operating on an invalid signed pointer. 410 bool isAuthenticated() const { 411 return Flags & (1ULL << MCID::Authenticated); 412 } 413 414 //===--------------------------------------------------------------------===// 415 // Side Effect Analysis 416 //===--------------------------------------------------------------------===// 417 418 /// Return true if this instruction could possibly read memory. 419 /// Instructions with this flag set are not necessarily simple load 420 /// instructions, they may load a value and modify it, for example. 421 bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); } 422 423 /// Return true if this instruction could possibly modify memory. 424 /// Instructions with this flag set are not necessarily simple store 425 /// instructions, they may store a modified value based on their operands, or 426 /// may not actually modify anything, for example. 427 bool mayStore() const { return Flags & (1ULL << MCID::MayStore); } 428 429 /// Return true if this instruction may raise a floating-point exception. 430 bool mayRaiseFPException() const { 431 return Flags & (1ULL << MCID::MayRaiseFPException); 432 } 433 434 /// Return true if this instruction has side 435 /// effects that are not modeled by other flags. This does not return true 436 /// for instructions whose effects are captured by: 437 /// 438 /// 1. Their operand list and implicit definition/use list. Register use/def 439 /// info is explicit for instructions. 440 /// 2. Memory accesses. Use mayLoad/mayStore. 441 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 442 /// 443 /// Examples of side effects would be modifying 'invisible' machine state like 444 /// a control register, flushing a cache, modifying a register invisible to 445 /// LLVM, etc. 446 bool hasUnmodeledSideEffects() const { 447 return Flags & (1ULL << MCID::UnmodeledSideEffects); 448 } 449 450 //===--------------------------------------------------------------------===// 451 // Flags that indicate whether an instruction can be modified by a method. 452 //===--------------------------------------------------------------------===// 453 454 /// Return true if this may be a 2- or 3-address instruction (of the 455 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are 456 /// exchanged. If this flag is set, then the 457 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 458 /// instruction. 459 /// 460 /// Note that this flag may be set on instructions that are only commutable 461 /// sometimes. In these cases, the call to commuteInstruction will fail. 462 /// Also note that some instructions require non-trivial modification to 463 /// commute them. 464 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); } 465 466 /// Return true if this is a 2-address instruction which can be changed 467 /// into a 3-address instruction if needed. Doing this transformation can be 468 /// profitable in the register allocator, because it means that the 469 /// instruction can use a 2-address form if possible, but degrade into a less 470 /// efficient form if the source and dest register cannot be assigned to the 471 /// same register. For example, this allows the x86 backend to turn a "shl 472 /// reg, 3" instruction into an LEA instruction, which is the same speed as 473 /// the shift but has bigger code size. 474 /// 475 /// If this returns true, then the target must implement the 476 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 477 /// is allowed to fail if the transformation isn't valid for this specific 478 /// instruction (e.g. shl reg, 4 on x86). 479 /// 480 bool isConvertibleTo3Addr() const { 481 return Flags & (1ULL << MCID::ConvertibleTo3Addr); 482 } 483 484 /// Return true if this instruction requires custom insertion support 485 /// when the DAG scheduler is inserting it into a machine basic block. If 486 /// this is true for the instruction, it basically means that it is a pseudo 487 /// instruction used at SelectionDAG time that is expanded out into magic code 488 /// by the target when MachineInstrs are formed. 489 /// 490 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 491 /// is used to insert this into the MachineBasicBlock. 492 bool usesCustomInsertionHook() const { 493 return Flags & (1ULL << MCID::UsesCustomInserter); 494 } 495 496 /// Return true if this instruction requires *adjustment* after 497 /// instruction selection by calling a target hook. For example, this can be 498 /// used to fill in ARM 's' optional operand depending on whether the 499 /// conditional flag register is used. 500 bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); } 501 502 /// Returns true if this instruction is a candidate for remat. This 503 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable. 504 /// 505 /// If this flag is set, the isReallyTriviallyReMaterializable() 506 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify 507 /// the instruction is really rematable. 508 bool isRematerializable() const { 509 return Flags & (1ULL << MCID::Rematerializable); 510 } 511 512 /// Returns true if this instruction has the same cost (or less) than a 513 /// move instruction. This is useful during certain types of optimizations 514 /// (e.g., remat during two-address conversion or machine licm) where we would 515 /// like to remat or hoist the instruction, but not if it costs more than 516 /// moving the instruction into the appropriate register. Note, we are not 517 /// marking copies from and to the same register class with this flag. 518 /// 519 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove 520 /// for different subtargets. 521 bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); } 522 523 /// Returns true if this instruction source operands have special 524 /// register allocation requirements that are not captured by the operand 525 /// register classes. e.g. ARM::STRD's two source registers must be an even / 526 /// odd pair, ARM::STM registers have to be in ascending order. Post-register 527 /// allocation passes should not attempt to change allocations for sources of 528 /// instructions with this flag. 529 bool hasExtraSrcRegAllocReq() const { 530 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq); 531 } 532 533 /// Returns true if this instruction def operands have special register 534 /// allocation requirements that are not captured by the operand register 535 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, 536 /// ARM::LDM registers have to be in ascending order. Post-register 537 /// allocation passes should not attempt to change allocations for definitions 538 /// of instructions with this flag. 539 bool hasExtraDefRegAllocReq() const { 540 return Flags & (1ULL << MCID::ExtraDefRegAllocReq); 541 } 542 543 /// Return a list of registers that are potentially read by any 544 /// instance of this machine instruction. For example, on X86, the "adc" 545 /// instruction adds two register operands and adds the carry bit in from the 546 /// flags register. In this case, the instruction is marked as implicitly 547 /// reading the flags. Likewise, the variable shift instruction on X86 is 548 /// marked as implicitly reading the 'CL' register, which it always does. 549 /// 550 /// This method returns null if the instruction has no implicit uses. 551 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } 552 553 /// Return the number of implicit uses this instruction has. 554 unsigned getNumImplicitUses() const { 555 if (!ImplicitUses) 556 return 0; 557 unsigned i = 0; 558 for (; ImplicitUses[i]; ++i) /*empty*/ 559 ; 560 return i; 561 } 562 563 /// Return a list of registers that are potentially written by any 564 /// instance of this machine instruction. For example, on X86, many 565 /// instructions implicitly set the flags register. In this case, they are 566 /// marked as setting the FLAGS. Likewise, many instructions always deposit 567 /// their result in a physical register. For example, the X86 divide 568 /// instruction always deposits the quotient and remainder in the EAX/EDX 569 /// registers. For that instruction, this will return a list containing the 570 /// EAX/EDX/EFLAGS registers. 571 /// 572 /// This method returns null if the instruction has no implicit defs. 573 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } 574 575 /// Return the number of implicit defs this instruct has. 576 unsigned getNumImplicitDefs() const { 577 if (!ImplicitDefs) 578 return 0; 579 unsigned i = 0; 580 for (; ImplicitDefs[i]; ++i) /*empty*/ 581 ; 582 return i; 583 } 584 585 /// Return true if this instruction implicitly 586 /// uses the specified physical register. 587 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 588 if (const MCPhysReg *ImpUses = ImplicitUses) 589 for (; *ImpUses; ++ImpUses) 590 if (*ImpUses == Reg) 591 return true; 592 return false; 593 } 594 595 /// Return true if this instruction implicitly 596 /// defines the specified physical register. 597 bool hasImplicitDefOfPhysReg(unsigned Reg, 598 const MCRegisterInfo *MRI = nullptr) const; 599 600 /// Return the scheduling class for this instruction. The 601 /// scheduling class is an index into the InstrItineraryData table. This 602 /// returns zero if there is no known scheduling information for the 603 /// instruction. 604 unsigned getSchedClass() const { return SchedClass; } 605 606 /// Return the number of bytes in the encoding of this instruction, 607 /// or zero if the encoding size cannot be known from the opcode. 608 unsigned getSize() const { return Size; } 609 610 /// Find the index of the first operand in the 611 /// operand list that is used to represent the predicate. It returns -1 if 612 /// none is found. 613 int findFirstPredOperandIdx() const { 614 if (isPredicable()) { 615 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 616 if (OpInfo[i].isPredicate()) 617 return i; 618 } 619 return -1; 620 } 621 622 /// Return true if this instruction defines the specified physical 623 /// register, either explicitly or implicitly. 624 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 625 const MCRegisterInfo &RI) const; 626 }; 627 628 } // end namespace llvm 629 630 #endif 631