1 //===----------------------- DispatchStage.h --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// This file models the dispatch component of an instruction pipeline. 11 /// 12 /// The DispatchStage is responsible for updating instruction dependencies 13 /// and communicating to the simulated instruction scheduler that an instruction 14 /// is ready to be scheduled for execution. 15 /// 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_MCA_DISPATCH_STAGE_H 19 #define LLVM_MCA_DISPATCH_STAGE_H 20 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/MCA/HWEventListener.h" 24 #include "llvm/MCA/HardwareUnits/RegisterFile.h" 25 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h" 26 #include "llvm/MCA/Instruction.h" 27 #include "llvm/MCA/Stages/Stage.h" 28 29 namespace llvm { 30 namespace mca { 31 32 // Implements the hardware dispatch logic. 33 // 34 // This class is responsible for the dispatch stage, in which instructions are 35 // dispatched in groups to the Scheduler. An instruction can be dispatched if 36 // the following conditions are met: 37 // 1) There are enough entries in the reorder buffer (see class 38 // RetireControlUnit) to write the opcodes associated with the instruction. 39 // 2) There are enough physical registers to rename output register operands. 40 // 3) There are enough entries available in the used buffered resource(s). 41 // 42 // The number of micro opcodes that can be dispatched in one cycle is limited by 43 // the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when 44 // processor resources are not available. Dispatch stall events are counted 45 // during the entire execution of the code, and displayed by the performance 46 // report when flag '-dispatch-stats' is specified. 47 // 48 // If the number of micro opcodes exceedes DispatchWidth, then the instruction 49 // is dispatched in multiple cycles. 50 class DispatchStage final : public Stage { 51 unsigned DispatchWidth; 52 unsigned AvailableEntries; 53 unsigned CarryOver; 54 InstRef CarriedOver; 55 const MCSubtargetInfo &STI; 56 RetireControlUnit &RCU; 57 RegisterFile &PRF; 58 59 bool checkRCU(const InstRef &IR) const; 60 bool checkPRF(const InstRef &IR) const; 61 bool canDispatch(const InstRef &IR) const; 62 Error dispatch(InstRef IR); 63 64 void notifyInstructionDispatched(const InstRef &IR, 65 ArrayRef<unsigned> UsedPhysRegs, 66 unsigned uOps) const; 67 68 public: 69 DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, 70 unsigned MaxDispatchWidth, RetireControlUnit &R, 71 RegisterFile &F); 72 73 bool isAvailable(const InstRef &IR) const override; 74 75 // The dispatch logic internally doesn't buffer instructions. So there is 76 // never work to do at the beginning of every cycle. 77 bool hasWorkToComplete() const override { return false; } 78 Error cycleStart() override; 79 Error execute(InstRef &IR) override; 80 81 #ifndef NDEBUG 82 void dump() const; 83 #endif 84 }; 85 } // namespace mca 86 } // namespace llvm 87 88 #endif // LLVM_MCA_DISPATCH_STAGE_H 89