1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces used by SelectionDAG 10// instruction selection generators. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Selection DAG Type Constraint definitions. 16// 17// Note that the semantics of these constraints are hard coded into tblgen. To 18// modify or add constraints, you have to hack tblgen. 19// 20 21class SDTypeConstraint<int opnum> { 22 int OperandNum = opnum; 23} 24 25// SDTCisVT - The specified operand has exactly this VT. 26class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 27 ValueType VT = vt; 28} 29 30class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 31 32// SDTCisInt - The specified operand has integer type. 33class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 34 35// SDTCisFP - The specified operand has floating-point type. 36class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 37 38// SDTCisVec - The specified operand has a vector type. 39class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 40 41// SDTCisSameAs - The two specified operands have identical types. 42class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 43 int OtherOperandNum = OtherOp; 44} 45 46// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 47// smaller than the 'Other' operand. 48class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 49 int OtherOperandNum = OtherOp; 50} 51 52class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 53 int BigOperandNum = BigOp; 54} 55 56/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 57/// type as the element type of OtherOp, which is a vector type. 58class SDTCisEltOfVec<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 64/// with length less that of OtherOp, which is a vector type. 65class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70// SDTCVecEltisVT - The specified operand is vector type with element type 71// of VT. 72class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 73 ValueType VT = vt; 74} 75 76// SDTCisSameNumEltsAs - The two specified operands have identical number 77// of elements. 78class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 79 int OtherOperandNum = OtherOp; 80} 81 82// SDTCisSameSizeAs - The two specified operands have identical size. 83class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 84 int OtherOperandNum = OtherOp; 85} 86 87//===----------------------------------------------------------------------===// 88// Selection DAG Type Profile definitions. 89// 90// These use the constraints defined above to describe the type requirements of 91// the various nodes. These are not hard coded into tblgen, allowing targets to 92// add their own if needed. 93// 94 95// SDTypeProfile - This profile describes the type requirements of a Selection 96// DAG node. 97class SDTypeProfile<int numresults, int numoperands, 98 list<SDTypeConstraint> constraints> { 99 int NumResults = numresults; 100 int NumOperands = numoperands; 101 list<SDTypeConstraint> Constraints = constraints; 102} 103 104// Builtin profiles. 105def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 106def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 107def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 108def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 109def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 110def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 111 112def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 114]>; 115def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 116 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 117]>; 118def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr 119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 120]>; 121def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 122 SDTCisSameAs<0, 1>, SDTCisInt<2> 123]>; 124def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 126]>; 127def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc 128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 129]>; 130 131def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 132 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 133]>; 134def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 135 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 136]>; 137def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 139]>; 140def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse 141 SDTCisSameAs<0, 1>, SDTCisInt<0> 142]>; 143def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 144 SDTCisInt<0>, SDTCisInt<1> 145]>; 146def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 147 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 148]>; 149def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 151]>; 152def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 153 SDTCisSameAs<0, 1>, SDTCisFP<0> 154]>; 155def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fpround 156 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 157]>; 158def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fpextend 159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 160]>; 161def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 162 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 163]>; 164def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 165 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 166]>; 167def SDTFPToIntSatOp : SDTypeProfile<1, 2, [ // fp_to_[su]int_sat 168 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, OtherVT> 169]>; 170def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 171 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 172 SDTCisVTSmallerThanOp<2, 1> 173]>; 174def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 175 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 176 SDTCisOpSmallerThanOp<1, 0> 177]>; 178 179def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 180 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 181]>; 182 183def SDTSelect : SDTypeProfile<1, 3, [ // select 184 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 185]>; 186 187def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 188 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 189]>; 190 191def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 192 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 193 SDTCisVT<5, OtherVT> 194]>; 195 196def SDTBr : SDTypeProfile<0, 1, [ // br 197 SDTCisVT<0, OtherVT> 198]>; 199 200def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 201 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 202]>; 203 204def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 205 SDTCisInt<0>, SDTCisVT<1, OtherVT> 206]>; 207 208def SDTBrind : SDTypeProfile<0, 1, [ // brind 209 SDTCisPtrTy<0> 210]>; 211 212def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 213 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 214]>; 215 216def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 217 218def SDTUBSANTrap : SDTypeProfile<0, 1, []>; // ubsantrap 219 220def SDTLoad : SDTypeProfile<1, 1, [ // load 221 SDTCisPtrTy<1> 222]>; 223 224def SDTStore : SDTypeProfile<0, 2, [ // store 225 SDTCisPtrTy<1> 226]>; 227 228def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 229 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 230]>; 231 232def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store 233 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3> 234]>; 235 236def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load 237 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>, 238 SDTCisSameNumEltsAs<0, 3> 239]>; 240 241def SDTVecShuffle : SDTypeProfile<1, 2, [ 242 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 243]>; 244def SDTVecSlice : SDTypeProfile<1, 3, [ // vector splice 245 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisInt<3> 246]>; 247def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 248 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 249]>; 250def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 251 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 252]>; 253def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction 254 SDTCisInt<0>, SDTCisVec<1> 255]>; 256def SDTFPVecReduce : SDTypeProfile<1, 1, [ // FP vector reduction 257 SDTCisFP<0>, SDTCisVec<1> 258]>; 259 260def SDTVecReverse : SDTypeProfile<1, 1, [ // vector reverse 261 SDTCisVec<0>, SDTCisSameAs<0,1> 262]>; 263 264def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 265 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 266]>; 267def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 268 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 269]>; 270 271def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 272 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 273]>; 274 275def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 276 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 277 SDTCisInt<0> 278]>; 279def SDTAtomicFence : SDTypeProfile<0, 2, [ 280 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 281]>; 282def SDTAtomic3 : SDTypeProfile<1, 3, [ 283 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 284]>; 285def SDTAtomic2 : SDTypeProfile<1, 2, [ 286 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 287]>; 288 289def SDTFPAtomic2 : SDTypeProfile<1, 2, [ 290 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1> 291]>; 292 293def SDTAtomicStore : SDTypeProfile<0, 2, [ 294 SDTCisPtrTy<0>, SDTCisInt<1> 295]>; 296def SDTAtomicLoad : SDTypeProfile<1, 1, [ 297 SDTCisInt<0>, SDTCisPtrTy<1> 298]>; 299 300class SDCallSeqStart<list<SDTypeConstraint> constraints> : 301 SDTypeProfile<0, 2, constraints>; 302class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 303 SDTypeProfile<0, 2, constraints>; 304 305//===----------------------------------------------------------------------===// 306// Selection DAG Node definitions. 307// 308class SDNode<string opcode, SDTypeProfile typeprof, 309 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 310 : SDPatternOperator { 311 string Opcode = opcode; 312 string SDClass = sdclass; 313 let Properties = props; 314 SDTypeProfile TypeProfile = typeprof; 315} 316 317// Special TableGen-recognized dag nodes 318def set; 319def implicit; 320def node; 321def srcvalue; 322 323def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 324def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 325def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 326def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 327def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 328def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 329def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 330def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>; 331def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 332 "GlobalAddressSDNode">; 333def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 334 "GlobalAddressSDNode">; 335def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 336 "GlobalAddressSDNode">; 337def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 338 "GlobalAddressSDNode">; 339def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 340 "ConstantPoolSDNode">; 341def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 342 "ConstantPoolSDNode">; 343def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 344 "JumpTableSDNode">; 345def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 346 "JumpTableSDNode">; 347def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 348 "FrameIndexSDNode">; 349def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 350 "FrameIndexSDNode">; 351def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 352 "ExternalSymbolSDNode">; 353def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 354 "ExternalSymbolSDNode">; 355def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 356def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 357 "BlockAddressSDNode">; 358def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 359 "BlockAddressSDNode">; 360 361def add : SDNode<"ISD::ADD" , SDTIntBinOp , 362 [SDNPCommutative, SDNPAssociative]>; 363def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 364def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 365 [SDNPCommutative, SDNPAssociative]>; 366def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 367def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 368def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>; 369def abdu : SDNode<"ISD::ABDU" , SDTIntBinOp, [SDNPCommutative]>; 370def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 371def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 372def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 373def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 374def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 375def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 376def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 377def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 378def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 379def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 380def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 381def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 382def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 383def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>; 384def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>; 385def and : SDNode<"ISD::AND" , SDTIntBinOp, 386 [SDNPCommutative, SDNPAssociative]>; 387def or : SDNode<"ISD::OR" , SDTIntBinOp, 388 [SDNPCommutative, SDNPAssociative]>; 389def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 392 [SDNPCommutative, SDNPOutGlue]>; 393def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 394 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 395def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 396 [SDNPOutGlue]>; 397def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 398 [SDNPOutGlue, SDNPInGlue]>; 399def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 400 [SDNPCommutative, SDNPAssociative]>; 401def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 402 [SDNPCommutative, SDNPAssociative]>; 403def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 404 [SDNPCommutative, SDNPAssociative]>; 405def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 406 [SDNPCommutative, SDNPAssociative]>; 407 408def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 409def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 410def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>; 411def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>; 412def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>; 413def ushlsat : SDNode<"ISD::USHLSAT" , SDTIntBinOp>; 414 415def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 416def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 417def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 418def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 419def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>; 420def sdivfixsat : SDNode<"ISD::SDIVFIXSAT", SDTIntScaledBinOp>; 421def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>; 422def udivfixsat : SDNode<"ISD::UDIVFIXSAT", SDTIntScaledBinOp>; 423 424def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 425def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 426def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 427 428def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 429def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 430def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 431def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>; 432def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>; 433def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>; 434def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 435def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 436def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 437def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 438def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 439def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 440def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 441def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 442def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 443def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 444 445def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; 446def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; 447def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; 448def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; 449def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; 450def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>; 451 452def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 453def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 454def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 455def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 456def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 457def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>; 458def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>; 459def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 460def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 461 [SDNPCommutative, SDNPAssociative]>; 462def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 463 [SDNPCommutative, SDNPAssociative]>; 464def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, 465 [SDNPCommutative]>; 466def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, 467 [SDNPCommutative]>; 468def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp, 469 [SDNPCommutative, SDNPAssociative]>; 470def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp, 471 [SDNPCommutative, SDNPAssociative]>; 472def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 473def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 474def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 475def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 476def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 477def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 478def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 479def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 480def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 481def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 482def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 483def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 484def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 485def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 486def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 487def froundeven : SDNode<"ISD::FROUNDEVEN" , SDTFPUnaryOp>; 488 489def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; 490def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; 491def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>; 492def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>; 493 494def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 495def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 496def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 497 498def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 499def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 500def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 501def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 502def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>; 503def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>; 504def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 505def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 506 507def strict_fadd : SDNode<"ISD::STRICT_FADD", 508 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 509def strict_fsub : SDNode<"ISD::STRICT_FSUB", 510 SDTFPBinOp, [SDNPHasChain]>; 511def strict_fmul : SDNode<"ISD::STRICT_FMUL", 512 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 513def strict_fdiv : SDNode<"ISD::STRICT_FDIV", 514 SDTFPBinOp, [SDNPHasChain]>; 515def strict_frem : SDNode<"ISD::STRICT_FREM", 516 SDTFPBinOp, [SDNPHasChain]>; 517def strict_fma : SDNode<"ISD::STRICT_FMA", 518 SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>; 519def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", 520 SDTFPUnaryOp, [SDNPHasChain]>; 521def strict_fsin : SDNode<"ISD::STRICT_FSIN", 522 SDTFPUnaryOp, [SDNPHasChain]>; 523def strict_fcos : SDNode<"ISD::STRICT_FCOS", 524 SDTFPUnaryOp, [SDNPHasChain]>; 525def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", 526 SDTFPUnaryOp, [SDNPHasChain]>; 527def strict_fpow : SDNode<"ISD::STRICT_FPOW", 528 SDTFPBinOp, [SDNPHasChain]>; 529def strict_flog2 : SDNode<"ISD::STRICT_FLOG2", 530 SDTFPUnaryOp, [SDNPHasChain]>; 531def strict_frint : SDNode<"ISD::STRICT_FRINT", 532 SDTFPUnaryOp, [SDNPHasChain]>; 533def strict_lrint : SDNode<"ISD::STRICT_LRINT", 534 SDTFPToIntOp, [SDNPHasChain]>; 535def strict_llrint : SDNode<"ISD::STRICT_LLRINT", 536 SDTFPToIntOp, [SDNPHasChain]>; 537def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT", 538 SDTFPUnaryOp, [SDNPHasChain]>; 539def strict_fceil : SDNode<"ISD::STRICT_FCEIL", 540 SDTFPUnaryOp, [SDNPHasChain]>; 541def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR", 542 SDTFPUnaryOp, [SDNPHasChain]>; 543def strict_lround : SDNode<"ISD::STRICT_LROUND", 544 SDTFPToIntOp, [SDNPHasChain]>; 545def strict_llround : SDNode<"ISD::STRICT_LLROUND", 546 SDTFPToIntOp, [SDNPHasChain]>; 547def strict_fround : SDNode<"ISD::STRICT_FROUND", 548 SDTFPUnaryOp, [SDNPHasChain]>; 549def strict_froundeven : SDNode<"ISD::STRICT_FROUNDEVEN", 550 SDTFPUnaryOp, [SDNPHasChain]>; 551def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC", 552 SDTFPUnaryOp, [SDNPHasChain]>; 553def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM", 554 SDTFPBinOp, [SDNPHasChain, 555 SDNPCommutative, SDNPAssociative]>; 556def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM", 557 SDTFPBinOp, [SDNPHasChain, 558 SDNPCommutative, SDNPAssociative]>; 559def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM", 560 SDTFPBinOp, [SDNPHasChain, 561 SDNPCommutative, SDNPAssociative]>; 562def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM", 563 SDTFPBinOp, [SDNPHasChain, 564 SDNPCommutative, SDNPAssociative]>; 565def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND", 566 SDTFPRoundOp, [SDNPHasChain]>; 567def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND", 568 SDTFPExtendOp, [SDNPHasChain]>; 569def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT", 570 SDTFPToIntOp, [SDNPHasChain]>; 571def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT", 572 SDTFPToIntOp, [SDNPHasChain]>; 573def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP", 574 SDTIntToFPOp, [SDNPHasChain]>; 575def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP", 576 SDTIntToFPOp, [SDNPHasChain]>; 577def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>; 578def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>; 579 580def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 581def select : SDNode<"ISD::SELECT" , SDTSelect>; 582def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 583def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 584 585def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 586def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 587def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 588def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 589def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 590 [SDNPHasChain, SDNPSideEffect]>; 591def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 592 593def trap : SDNode<"ISD::TRAP" , SDTNone, 594 [SDNPHasChain, SDNPSideEffect]>; 595def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 596 [SDNPHasChain, SDNPSideEffect]>; 597def ubsantrap : SDNode<"ISD::UBSANTRAP" , SDTUBSANTrap, 598 [SDNPHasChain, SDNPSideEffect]>; 599 600def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 601 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 602 SDNPMemOperand]>; 603 604def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 605 [SDNPHasChain, SDNPSideEffect]>; 606 607def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 608 [SDNPHasChain, SDNPSideEffect]>; 609 610def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 611 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 612def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 613 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 614def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 615 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 616def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 617 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 618def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 619 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 620def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2, 621 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 622def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 623 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 624def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 625 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 626def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 627 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 628def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 629 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 630def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 631 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 632def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 633 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 634def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 635 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 636def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2, 637 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 638def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2, 639 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 640 641def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 642 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 643def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 644 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 645 646def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore, 647 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 648def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad, 649 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 650 651// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 652// and truncst (see below). 653def ld : SDNode<"ISD::LOAD" , SDTLoad, 654 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 655def st : SDNode<"ISD::STORE" , SDTStore, 656 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 657def ist : SDNode<"ISD::STORE" , SDTIStore, 658 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 659 660def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 661def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>; 662def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>; 663def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 664def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>; 665def step_vector : SDNode<"ISD::STEP_VECTOR", SDTypeProfile<1, 1, 666 [SDTCisVec<0>, SDTCisInt<1>]>, []>; 667def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 668 []>; 669 670// vector_extract/vector_insert are deprecated. extractelt/insertelt 671// are preferred. 672def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 673 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 674def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 675 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 676def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 677 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 678 679// This operator does not do subvector type checking. The ARM 680// backend, at least, needs it. 681def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 682 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 683 []>; 684 685// This operator does subvector type checking. 686def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 687def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 688 689// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 690// these internally. Don't reference these directly. 691def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 692 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 693 [SDNPHasChain]>; 694def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 695 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 696 [SDNPHasChain]>; 697def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 698 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 699 700def SDT_assert : SDTypeProfile<1, 1, 701 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 702def assertsext : SDNode<"ISD::AssertSext", SDT_assert>; 703def assertzext : SDNode<"ISD::AssertZext", SDT_assert>; 704def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>; 705 706//===----------------------------------------------------------------------===// 707// Selection DAG Condition Codes 708 709class CondCode<string fcmpName = "", string icmpName = ""> { 710 string ICmpPredicate = icmpName; 711 string FCmpPredicate = fcmpName; 712} 713 714// ISD::CondCode enums, and mapping to CmpInst::Predicate names 715def SETOEQ : CondCode<"FCMP_OEQ">; 716def SETOGT : CondCode<"FCMP_OGT">; 717def SETOGE : CondCode<"FCMP_OGE">; 718def SETOLT : CondCode<"FCMP_OLT">; 719def SETOLE : CondCode<"FCMP_OLE">; 720def SETONE : CondCode<"FCMP_ONE">; 721def SETO : CondCode<"FCMP_ORD">; 722def SETUO : CondCode<"FCMP_UNO">; 723def SETUEQ : CondCode<"FCMP_UEQ">; 724def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">; 725def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">; 726def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">; 727def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">; 728def SETUNE : CondCode<"FCMP_UNE">; 729def SETEQ : CondCode<"", "ICMP_EQ">; 730def SETGT : CondCode<"", "ICMP_SGT">; 731def SETGE : CondCode<"", "ICMP_SGE">; 732def SETLT : CondCode<"", "ICMP_SLT">; 733def SETLE : CondCode<"", "ICMP_SLE">; 734def SETNE : CondCode<"", "ICMP_NE">; 735 736//===----------------------------------------------------------------------===// 737// Selection DAG Node Transformation Functions. 738// 739// This mechanism allows targets to manipulate nodes in the output DAG once a 740// match has been formed. This is typically used to manipulate immediate 741// values. 742// 743class SDNodeXForm<SDNode opc, code xformFunction> { 744 SDNode Opcode = opc; 745 code XFormFunction = xformFunction; 746} 747 748def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 749 750//===----------------------------------------------------------------------===// 751// Selection DAG Pattern Fragments. 752// 753// Pattern fragments are reusable chunks of dags that match specific things. 754// They can take arguments and have C++ predicates that control whether they 755// match. They are intended to make the patterns for common instructions more 756// compact and readable. 757// 758 759/// PatFrags - Represents a set of pattern fragments. Each single fragment 760/// can match something on the DAG, from a single node to multiple nested other 761/// fragments. The whole set of fragments matches if any of the single 762/// fragments match. This allows e.g. matching and "add with overflow" and 763/// a regular "add" with the same fragment set. 764/// 765class PatFrags<dag ops, list<dag> frags, code pred = [{}], 766 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 767 dag Operands = ops; 768 list<dag> Fragments = frags; 769 code PredicateCode = pred; 770 code GISelPredicateCode = [{}]; 771 code ImmediateCode = [{}]; 772 SDNodeXForm OperandTransform = xform; 773 774 // When this is set, the PredicateCode may refer to a constant Operands 775 // vector which contains the captured nodes of the DAG, in the order listed 776 // by the Operands field above. 777 // 778 // This is useful when Fragments involves associative / commutative 779 // operators: a single piece of code can easily refer to all operands even 780 // when re-associated / commuted variants of the fragment are matched. 781 bit PredicateCodeUsesOperands = false; 782 783 // Define a few pre-packaged predicates. This helps GlobalISel import 784 // existing rules from SelectionDAG for many common cases. 785 // They will be tested prior to the code in pred and must not be used in 786 // ImmLeaf and its subclasses. 787 788 // Is the desired pre-packaged predicate for a load? 789 bit IsLoad = ?; 790 // Is the desired pre-packaged predicate for a store? 791 bit IsStore = ?; 792 // Is the desired pre-packaged predicate for an atomic? 793 bit IsAtomic = ?; 794 795 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 796 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 797 bit IsUnindexed = ?; 798 799 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 800 bit IsNonExtLoad = ?; 801 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 802 bit IsAnyExtLoad = ?; 803 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 804 bit IsSignExtLoad = ?; 805 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 806 bit IsZeroExtLoad = ?; 807 // !cast<StoreSDNode>(N)->isTruncatingStore(); 808 // cast<StoreSDNode>(N)->isTruncatingStore(); 809 bit IsTruncStore = ?; 810 811 // cast<MemSDNode>(N)->getAddressSpace() == 812 // If this empty, accept any address space. 813 list<int> AddressSpaces = ?; 814 815 // cast<MemSDNode>(N)->getAlignment() >= 816 // If this is empty, accept any alignment. 817 int MinAlignment = ?; 818 819 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic 820 bit IsAtomicOrderingMonotonic = ?; 821 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire 822 bit IsAtomicOrderingAcquire = ?; 823 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release 824 bit IsAtomicOrderingRelease = ?; 825 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease 826 bit IsAtomicOrderingAcquireRelease = ?; 827 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent 828 bit IsAtomicOrderingSequentiallyConsistent = ?; 829 830 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 831 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 832 bit IsAtomicOrderingAcquireOrStronger = ?; 833 834 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 835 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 836 bit IsAtomicOrderingReleaseOrStronger = ?; 837 838 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 839 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 840 ValueType MemoryVT = ?; 841 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 842 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 843 ValueType ScalarMemoryVT = ?; 844} 845 846// PatFrag - A version of PatFrags matching only a single fragment. 847class PatFrag<dag ops, dag frag, code pred = [{}], 848 SDNodeXForm xform = NOOP_SDNodeXForm> 849 : PatFrags<ops, [frag], pred, xform>; 850 851// OutPatFrag is a pattern fragment that is used as part of an output pattern 852// (not an input pattern). These do not have predicates or transforms, but are 853// used to avoid repeated subexpressions in output patterns. 854class OutPatFrag<dag ops, dag frag> 855 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 856 857// PatLeaf's are pattern fragments that have no operands. This is just a helper 858// to define immediates and other common things concisely. 859class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 860 : PatFrag<(ops), frag, pred, xform>; 861 862 863// ImmLeaf is a pattern fragment with a constraint on the immediate. The 864// constraint is a function that is run on the immediate (always with the value 865// sign extended out to an int64_t) as Imm. For example: 866// 867// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 868// 869// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 870// is preferred over using PatLeaf because it allows the code generator to 871// reason more about the constraint. 872// 873// If FastIsel should ignore all instructions that have an operand of this type, 874// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 875// the code size of the generated fast instruction selector. 876class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 877 SDNode ImmNode = imm> 878 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 879 let ImmediateCode = pred; 880 bit FastIselShouldIgnore = false; 881 882 // Is the data type of the immediate an APInt? 883 bit IsAPInt = false; 884 885 // Is the data type of the immediate an APFloat? 886 bit IsAPFloat = false; 887} 888 889// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead 890// of imm/Constant. 891class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 892 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>; 893 894// An ImmLeaf except that Imm is an APInt. This is useful when you need to 895// zero-extend the immediate instead of sign-extend it. 896// 897// Note that FastISel does not currently understand IntImmLeaf and will not 898// generate code for rules that make use of it. As such, it does not make sense 899// to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 900// IntImmLeaf will allow GlobalISel to import the rule. 901class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 902 : ImmLeaf<vt, pred, xform> { 903 let IsAPInt = true; 904 let FastIselShouldIgnore = true; 905} 906 907// An ImmLeaf except that Imm is an APFloat. 908// 909// Note that FastISel does not currently understand FPImmLeaf and will not 910// generate code for rules that make use of it. 911class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 912 : ImmLeaf<vt, pred, xform, fpimm> { 913 let IsAPFloat = true; 914 let FastIselShouldIgnore = true; 915} 916 917// Leaf fragments. 918 919def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 920def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 921 922// Use ISD::isConstantSplatVectorAllOnes or ISD::isConstantSplatVectorAllZeros 923// to look for the corresponding build_vector or splat_vector. Will look through 924// bitcasts and check for either opcode, except when used as a pattern root. 925// When used as a pattern root, only fixed-length build_vector and scalable 926// splat_vector are supported. 927def immAllOnesV : SDPatternOperator; // ISD::isConstantSplatVectorAllOnes 928def immAllZerosV : SDPatternOperator; // ISD::isConstantSplatVectorAllZeros 929 930// Other helper fragments. 931def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 932def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 933def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 934 935def zanyext : PatFrags<(ops node:$op), 936 [(zext node:$op), 937 (anyext node:$op)]>; 938 939// null_frag - The null pattern operator is used in multiclass instantiations 940// which accept an SDPatternOperator for use in matching patterns for internal 941// definitions. When expanding a pattern, if the null fragment is referenced 942// in the expansion, the pattern is discarded and it is as-if '[]' had been 943// specified. This allows multiclasses to have the isel patterns be optional. 944def null_frag : SDPatternOperator; 945 946// load fragments. 947def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 948 let IsLoad = true; 949 let IsUnindexed = true; 950} 951def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 952 let IsLoad = true; 953 let IsNonExtLoad = true; 954} 955 956// extending load fragments. 957def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 958 let IsLoad = true; 959 let IsAnyExtLoad = true; 960} 961def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 962 let IsLoad = true; 963 let IsSignExtLoad = true; 964} 965def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 966 let IsLoad = true; 967 let IsZeroExtLoad = true; 968} 969 970def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 971 let IsLoad = true; 972 let MemoryVT = i1; 973} 974def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 975 let IsLoad = true; 976 let MemoryVT = i8; 977} 978def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 979 let IsLoad = true; 980 let MemoryVT = i16; 981} 982def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 983 let IsLoad = true; 984 let MemoryVT = i32; 985} 986def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 987 let IsLoad = true; 988 let MemoryVT = f16; 989} 990def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 991 let IsLoad = true; 992 let MemoryVT = f32; 993} 994def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 995 let IsLoad = true; 996 let MemoryVT = f64; 997} 998 999def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1000 let IsLoad = true; 1001 let MemoryVT = i1; 1002} 1003def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1004 let IsLoad = true; 1005 let MemoryVT = i8; 1006} 1007def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1008 let IsLoad = true; 1009 let MemoryVT = i16; 1010} 1011def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1012 let IsLoad = true; 1013 let MemoryVT = i32; 1014} 1015 1016def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1017 let IsLoad = true; 1018 let MemoryVT = i1; 1019} 1020def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1021 let IsLoad = true; 1022 let MemoryVT = i8; 1023} 1024def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1025 let IsLoad = true; 1026 let MemoryVT = i16; 1027} 1028def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1029 let IsLoad = true; 1030 let MemoryVT = i32; 1031} 1032 1033def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1034 let IsLoad = true; 1035 let ScalarMemoryVT = i1; 1036} 1037def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1038 let IsLoad = true; 1039 let ScalarMemoryVT = i8; 1040} 1041def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1042 let IsLoad = true; 1043 let ScalarMemoryVT = i16; 1044} 1045def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1046 let IsLoad = true; 1047 let ScalarMemoryVT = i32; 1048} 1049def extloadvf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1050 let IsLoad = true; 1051 let ScalarMemoryVT = f16; 1052} 1053def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1054 let IsLoad = true; 1055 let ScalarMemoryVT = f32; 1056} 1057def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1058 let IsLoad = true; 1059 let ScalarMemoryVT = f64; 1060} 1061 1062def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1063 let IsLoad = true; 1064 let ScalarMemoryVT = i1; 1065} 1066def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1067 let IsLoad = true; 1068 let ScalarMemoryVT = i8; 1069} 1070def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1071 let IsLoad = true; 1072 let ScalarMemoryVT = i16; 1073} 1074def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1075 let IsLoad = true; 1076 let ScalarMemoryVT = i32; 1077} 1078 1079def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1080 let IsLoad = true; 1081 let ScalarMemoryVT = i1; 1082} 1083def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1084 let IsLoad = true; 1085 let ScalarMemoryVT = i8; 1086} 1087def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1088 let IsLoad = true; 1089 let ScalarMemoryVT = i16; 1090} 1091def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1092 let IsLoad = true; 1093 let ScalarMemoryVT = i32; 1094} 1095 1096// store fragments. 1097def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 1098 (st node:$val, node:$ptr)> { 1099 let IsStore = true; 1100 let IsUnindexed = true; 1101} 1102def store : PatFrag<(ops node:$val, node:$ptr), 1103 (unindexedstore node:$val, node:$ptr)> { 1104 let IsStore = true; 1105 let IsTruncStore = false; 1106} 1107 1108// truncstore fragments. 1109def truncstore : PatFrag<(ops node:$val, node:$ptr), 1110 (unindexedstore node:$val, node:$ptr)> { 1111 let IsStore = true; 1112 let IsTruncStore = true; 1113} 1114def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 1115 (truncstore node:$val, node:$ptr)> { 1116 let IsStore = true; 1117 let MemoryVT = i8; 1118 let IsTruncStore = true; 1119} 1120def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 1121 (truncstore node:$val, node:$ptr)> { 1122 let IsStore = true; 1123 let MemoryVT = i16; 1124 let IsTruncStore = true; 1125} 1126def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 1127 (truncstore node:$val, node:$ptr)> { 1128 let IsStore = true; 1129 let MemoryVT = i32; 1130 let IsTruncStore = true; 1131} 1132def truncstoref16 : PatFrag<(ops node:$val, node:$ptr), 1133 (truncstore node:$val, node:$ptr)> { 1134 let IsStore = true; 1135 let MemoryVT = f16; 1136} 1137def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 1138 (truncstore node:$val, node:$ptr)> { 1139 let IsStore = true; 1140 let MemoryVT = f32; 1141} 1142def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 1143 (truncstore node:$val, node:$ptr)> { 1144 let IsStore = true; 1145 let MemoryVT = f64; 1146} 1147 1148def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 1149 (truncstore node:$val, node:$ptr)> { 1150 let IsStore = true; 1151 let ScalarMemoryVT = i8; 1152} 1153 1154def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 1155 (truncstore node:$val, node:$ptr)> { 1156 let IsStore = true; 1157 let ScalarMemoryVT = i16; 1158} 1159 1160def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 1161 (truncstore node:$val, node:$ptr)> { 1162 let IsStore = true; 1163 let ScalarMemoryVT = i32; 1164} 1165 1166// indexed store fragments. 1167def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 1168 (ist node:$val, node:$base, node:$offset)> { 1169 let IsStore = true; 1170 let IsTruncStore = false; 1171} 1172 1173def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 1174 (istore node:$val, node:$base, node:$offset), [{ 1175 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1176 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1177}]>; 1178 1179def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 1180 (ist node:$val, node:$base, node:$offset)> { 1181 let IsStore = true; 1182 let IsTruncStore = true; 1183} 1184def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1185 (itruncstore node:$val, node:$base, node:$offset), [{ 1186 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1187 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1188}]>; 1189def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1190 (pre_truncst node:$val, node:$base, node:$offset)> { 1191 let IsStore = true; 1192 let MemoryVT = i1; 1193} 1194def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1195 (pre_truncst node:$val, node:$base, node:$offset)> { 1196 let IsStore = true; 1197 let MemoryVT = i8; 1198} 1199def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1200 (pre_truncst node:$val, node:$base, node:$offset)> { 1201 let IsStore = true; 1202 let MemoryVT = i16; 1203} 1204def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1205 (pre_truncst node:$val, node:$base, node:$offset)> { 1206 let IsStore = true; 1207 let MemoryVT = i32; 1208} 1209def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1210 (pre_truncst node:$val, node:$base, node:$offset)> { 1211 let IsStore = true; 1212 let MemoryVT = f32; 1213} 1214def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1215 (pre_truncst node:$val, node:$base, node:$offset)> { 1216 let IsStore = true; 1217 let ScalarMemoryVT = i8; 1218} 1219def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1220 (pre_truncst node:$val, node:$base, node:$offset)> { 1221 let IsStore = true; 1222 let ScalarMemoryVT = i16; 1223} 1224 1225def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1226 (istore node:$val, node:$ptr, node:$offset), [{ 1227 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1228 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1229}]>; 1230 1231def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1232 (itruncstore node:$val, node:$base, node:$offset), [{ 1233 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1234 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1235}]>; 1236def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1237 (post_truncst node:$val, node:$base, node:$offset)> { 1238 let IsStore = true; 1239 let MemoryVT = i1; 1240} 1241def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1242 (post_truncst node:$val, node:$base, node:$offset)> { 1243 let IsStore = true; 1244 let MemoryVT = i8; 1245} 1246def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1247 (post_truncst node:$val, node:$base, node:$offset)> { 1248 let IsStore = true; 1249 let MemoryVT = i16; 1250} 1251def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1252 (post_truncst node:$val, node:$base, node:$offset)> { 1253 let IsStore = true; 1254 let MemoryVT = i32; 1255} 1256def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1257 (post_truncst node:$val, node:$base, node:$offset)> { 1258 let IsStore = true; 1259 let MemoryVT = f32; 1260} 1261def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1262 (post_truncst node:$val, node:$base, node:$offset)> { 1263 let IsStore = true; 1264 let ScalarMemoryVT = i8; 1265} 1266def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1267 (post_truncst node:$val, node:$base, node:$offset)> { 1268 let IsStore = true; 1269 let ScalarMemoryVT = i16; 1270} 1271 1272// TODO: Split these into volatile and unordered flavors to enable 1273// selectively legal optimizations for each. (See D66309) 1274def simple_load : PatFrag<(ops node:$ptr), 1275 (load node:$ptr), [{ 1276 return cast<LoadSDNode>(N)->isSimple(); 1277}]>; 1278def simple_store : PatFrag<(ops node:$val, node:$ptr), 1279 (store node:$val, node:$ptr), [{ 1280 return cast<StoreSDNode>(N)->isSimple(); 1281}]>; 1282 1283// nontemporal store fragments. 1284def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1285 (store node:$val, node:$ptr), [{ 1286 return cast<StoreSDNode>(N)->isNonTemporal(); 1287}]>; 1288 1289def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1290 (nontemporalstore node:$val, node:$ptr), [{ 1291 StoreSDNode *St = cast<StoreSDNode>(N); 1292 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 1293}]>; 1294 1295def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1296 (nontemporalstore node:$val, node:$ptr), [{ 1297 StoreSDNode *St = cast<StoreSDNode>(N); 1298 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1299}]>; 1300 1301// nontemporal load fragments. 1302def nontemporalload : PatFrag<(ops node:$ptr), 1303 (load node:$ptr), [{ 1304 return cast<LoadSDNode>(N)->isNonTemporal(); 1305}]>; 1306 1307def alignednontemporalload : PatFrag<(ops node:$ptr), 1308 (nontemporalload node:$ptr), [{ 1309 LoadSDNode *Ld = cast<LoadSDNode>(N); 1310 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1311}]>; 1312 1313// setcc convenience fragments. 1314def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1315 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1316def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1317 (setcc node:$lhs, node:$rhs, SETOGT)>; 1318def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1319 (setcc node:$lhs, node:$rhs, SETOGE)>; 1320def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1321 (setcc node:$lhs, node:$rhs, SETOLT)>; 1322def setole : PatFrag<(ops node:$lhs, node:$rhs), 1323 (setcc node:$lhs, node:$rhs, SETOLE)>; 1324def setone : PatFrag<(ops node:$lhs, node:$rhs), 1325 (setcc node:$lhs, node:$rhs, SETONE)>; 1326def seto : PatFrag<(ops node:$lhs, node:$rhs), 1327 (setcc node:$lhs, node:$rhs, SETO)>; 1328def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1329 (setcc node:$lhs, node:$rhs, SETUO)>; 1330def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1331 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1332def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1333 (setcc node:$lhs, node:$rhs, SETUGT)>; 1334def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1335 (setcc node:$lhs, node:$rhs, SETUGE)>; 1336def setult : PatFrag<(ops node:$lhs, node:$rhs), 1337 (setcc node:$lhs, node:$rhs, SETULT)>; 1338def setule : PatFrag<(ops node:$lhs, node:$rhs), 1339 (setcc node:$lhs, node:$rhs, SETULE)>; 1340def setune : PatFrag<(ops node:$lhs, node:$rhs), 1341 (setcc node:$lhs, node:$rhs, SETUNE)>; 1342def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1343 (setcc node:$lhs, node:$rhs, SETEQ)>; 1344def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1345 (setcc node:$lhs, node:$rhs, SETGT)>; 1346def setge : PatFrag<(ops node:$lhs, node:$rhs), 1347 (setcc node:$lhs, node:$rhs, SETGE)>; 1348def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1349 (setcc node:$lhs, node:$rhs, SETLT)>; 1350def setle : PatFrag<(ops node:$lhs, node:$rhs), 1351 (setcc node:$lhs, node:$rhs, SETLE)>; 1352def setne : PatFrag<(ops node:$lhs, node:$rhs), 1353 (setcc node:$lhs, node:$rhs, SETNE)>; 1354 1355// We don't have strict FP extended loads as single DAG nodes, but we can 1356// still provide convenience fragments to match those operations. 1357def strict_extloadf32 : PatFrag<(ops node:$ptr), 1358 (strict_fpextend (f32 (load node:$ptr)))>; 1359def strict_extloadf64 : PatFrag<(ops node:$ptr), 1360 (strict_fpextend (f64 (load node:$ptr)))>; 1361 1362// Convenience fragments to match both strict and non-strict fp operations 1363def any_fadd : PatFrags<(ops node:$lhs, node:$rhs), 1364 [(strict_fadd node:$lhs, node:$rhs), 1365 (fadd node:$lhs, node:$rhs)]>; 1366def any_fsub : PatFrags<(ops node:$lhs, node:$rhs), 1367 [(strict_fsub node:$lhs, node:$rhs), 1368 (fsub node:$lhs, node:$rhs)]>; 1369def any_fmul : PatFrags<(ops node:$lhs, node:$rhs), 1370 [(strict_fmul node:$lhs, node:$rhs), 1371 (fmul node:$lhs, node:$rhs)]>; 1372def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs), 1373 [(strict_fdiv node:$lhs, node:$rhs), 1374 (fdiv node:$lhs, node:$rhs)]>; 1375def any_frem : PatFrags<(ops node:$lhs, node:$rhs), 1376 [(strict_frem node:$lhs, node:$rhs), 1377 (frem node:$lhs, node:$rhs)]>; 1378def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3), 1379 [(strict_fma node:$src1, node:$src2, node:$src3), 1380 (fma node:$src1, node:$src2, node:$src3)]>; 1381def any_fsqrt : PatFrags<(ops node:$src), 1382 [(strict_fsqrt node:$src), 1383 (fsqrt node:$src)]>; 1384def any_fsin : PatFrags<(ops node:$src), 1385 [(strict_fsin node:$src), 1386 (fsin node:$src)]>; 1387def any_fcos : PatFrags<(ops node:$src), 1388 [(strict_fcos node:$src), 1389 (fcos node:$src)]>; 1390def any_fexp2 : PatFrags<(ops node:$src), 1391 [(strict_fexp2 node:$src), 1392 (fexp2 node:$src)]>; 1393def any_fpow : PatFrags<(ops node:$lhs, node:$rhs), 1394 [(strict_fpow node:$lhs, node:$rhs), 1395 (fpow node:$lhs, node:$rhs)]>; 1396def any_flog2 : PatFrags<(ops node:$src), 1397 [(strict_flog2 node:$src), 1398 (flog2 node:$src)]>; 1399def any_frint : PatFrags<(ops node:$src), 1400 [(strict_frint node:$src), 1401 (frint node:$src)]>; 1402def any_lrint : PatFrags<(ops node:$src), 1403 [(strict_lrint node:$src), 1404 (lrint node:$src)]>; 1405def any_llrint : PatFrags<(ops node:$src), 1406 [(strict_llrint node:$src), 1407 (llrint node:$src)]>; 1408def any_fnearbyint : PatFrags<(ops node:$src), 1409 [(strict_fnearbyint node:$src), 1410 (fnearbyint node:$src)]>; 1411def any_fceil : PatFrags<(ops node:$src), 1412 [(strict_fceil node:$src), 1413 (fceil node:$src)]>; 1414def any_ffloor : PatFrags<(ops node:$src), 1415 [(strict_ffloor node:$src), 1416 (ffloor node:$src)]>; 1417def any_lround : PatFrags<(ops node:$src), 1418 [(strict_lround node:$src), 1419 (lround node:$src)]>; 1420def any_llround : PatFrags<(ops node:$src), 1421 [(strict_llround node:$src), 1422 (llround node:$src)]>; 1423def any_fround : PatFrags<(ops node:$src), 1424 [(strict_fround node:$src), 1425 (fround node:$src)]>; 1426def any_froundeven : PatFrags<(ops node:$src), 1427 [(strict_froundeven node:$src), 1428 (froundeven node:$src)]>; 1429def any_ftrunc : PatFrags<(ops node:$src), 1430 [(strict_ftrunc node:$src), 1431 (ftrunc node:$src)]>; 1432def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs), 1433 [(strict_fmaxnum node:$lhs, node:$rhs), 1434 (fmaxnum node:$lhs, node:$rhs)]>; 1435def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs), 1436 [(strict_fminnum node:$lhs, node:$rhs), 1437 (fminnum node:$lhs, node:$rhs)]>; 1438def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs), 1439 [(strict_fmaximum node:$lhs, node:$rhs), 1440 (fmaximum node:$lhs, node:$rhs)]>; 1441def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs), 1442 [(strict_fminimum node:$lhs, node:$rhs), 1443 (fminimum node:$lhs, node:$rhs)]>; 1444def any_fpround : PatFrags<(ops node:$src), 1445 [(strict_fpround node:$src), 1446 (fpround node:$src)]>; 1447def any_fpextend : PatFrags<(ops node:$src), 1448 [(strict_fpextend node:$src), 1449 (fpextend node:$src)]>; 1450def any_extloadf32 : PatFrags<(ops node:$ptr), 1451 [(strict_extloadf32 node:$ptr), 1452 (extloadf32 node:$ptr)]>; 1453def any_extloadf64 : PatFrags<(ops node:$ptr), 1454 [(strict_extloadf64 node:$ptr), 1455 (extloadf64 node:$ptr)]>; 1456def any_fp_to_sint : PatFrags<(ops node:$src), 1457 [(strict_fp_to_sint node:$src), 1458 (fp_to_sint node:$src)]>; 1459def any_fp_to_uint : PatFrags<(ops node:$src), 1460 [(strict_fp_to_uint node:$src), 1461 (fp_to_uint node:$src)]>; 1462def any_sint_to_fp : PatFrags<(ops node:$src), 1463 [(strict_sint_to_fp node:$src), 1464 (sint_to_fp node:$src)]>; 1465def any_uint_to_fp : PatFrags<(ops node:$src), 1466 [(strict_uint_to_fp node:$src), 1467 (uint_to_fp node:$src)]>; 1468def any_fsetcc : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1469 [(strict_fsetcc node:$lhs, node:$rhs, node:$pred), 1470 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1471def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1472 [(strict_fsetccs node:$lhs, node:$rhs, node:$pred), 1473 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1474 1475multiclass binary_atomic_op_ord { 1476 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1477 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1478 let IsAtomic = true; 1479 let IsAtomicOrderingMonotonic = true; 1480 } 1481 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1482 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1483 let IsAtomic = true; 1484 let IsAtomicOrderingAcquire = true; 1485 } 1486 def NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1487 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1488 let IsAtomic = true; 1489 let IsAtomicOrderingRelease = true; 1490 } 1491 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1492 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1493 let IsAtomic = true; 1494 let IsAtomicOrderingAcquireRelease = true; 1495 } 1496 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1497 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1498 let IsAtomic = true; 1499 let IsAtomicOrderingSequentiallyConsistent = true; 1500 } 1501} 1502 1503multiclass ternary_atomic_op_ord { 1504 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1505 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1506 let IsAtomic = true; 1507 let IsAtomicOrderingMonotonic = true; 1508 } 1509 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1510 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1511 let IsAtomic = true; 1512 let IsAtomicOrderingAcquire = true; 1513 } 1514 def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1515 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1516 let IsAtomic = true; 1517 let IsAtomicOrderingRelease = true; 1518 } 1519 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1520 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1521 let IsAtomic = true; 1522 let IsAtomicOrderingAcquireRelease = true; 1523 } 1524 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1525 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1526 let IsAtomic = true; 1527 let IsAtomicOrderingSequentiallyConsistent = true; 1528 } 1529} 1530 1531multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> { 1532 def _8 : PatFrag<(ops node:$ptr, node:$val), 1533 (atomic_op node:$ptr, node:$val)> { 1534 let IsAtomic = true; 1535 let MemoryVT = !if(IsInt, i8, ?); 1536 } 1537 def _16 : PatFrag<(ops node:$ptr, node:$val), 1538 (atomic_op node:$ptr, node:$val)> { 1539 let IsAtomic = true; 1540 let MemoryVT = !if(IsInt, i16, f16); 1541 } 1542 def _32 : PatFrag<(ops node:$ptr, node:$val), 1543 (atomic_op node:$ptr, node:$val)> { 1544 let IsAtomic = true; 1545 let MemoryVT = !if(IsInt, i32, f32); 1546 } 1547 def _64 : PatFrag<(ops node:$ptr, node:$val), 1548 (atomic_op node:$ptr, node:$val)> { 1549 let IsAtomic = true; 1550 let MemoryVT = !if(IsInt, i64, f64); 1551 } 1552 1553 defm NAME#_8 : binary_atomic_op_ord; 1554 defm NAME#_16 : binary_atomic_op_ord; 1555 defm NAME#_32 : binary_atomic_op_ord; 1556 defm NAME#_64 : binary_atomic_op_ord; 1557} 1558 1559multiclass ternary_atomic_op<SDNode atomic_op> { 1560 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1561 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1562 let IsAtomic = true; 1563 let MemoryVT = i8; 1564 } 1565 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1566 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1567 let IsAtomic = true; 1568 let MemoryVT = i16; 1569 } 1570 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1571 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1572 let IsAtomic = true; 1573 let MemoryVT = i32; 1574 } 1575 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1576 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1577 let IsAtomic = true; 1578 let MemoryVT = i64; 1579 } 1580 1581 defm NAME#_8 : ternary_atomic_op_ord; 1582 defm NAME#_16 : ternary_atomic_op_ord; 1583 defm NAME#_32 : ternary_atomic_op_ord; 1584 defm NAME#_64 : ternary_atomic_op_ord; 1585} 1586 1587defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1588defm atomic_swap : binary_atomic_op<atomic_swap>; 1589defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1590defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1591defm atomic_load_clr : binary_atomic_op<atomic_load_clr>; 1592defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1593defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1594defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1595defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1596defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1597defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1598defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1599defm atomic_store : binary_atomic_op<atomic_store>; 1600defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1601 1602def atomic_load_8 : 1603 PatFrag<(ops node:$ptr), 1604 (atomic_load node:$ptr)> { 1605 let IsAtomic = true; 1606 let MemoryVT = i8; 1607} 1608def atomic_load_16 : 1609 PatFrag<(ops node:$ptr), 1610 (atomic_load node:$ptr)> { 1611 let IsAtomic = true; 1612 let MemoryVT = i16; 1613} 1614def atomic_load_32 : 1615 PatFrag<(ops node:$ptr), 1616 (atomic_load node:$ptr)> { 1617 let IsAtomic = true; 1618 let MemoryVT = i32; 1619} 1620def atomic_load_64 : 1621 PatFrag<(ops node:$ptr), 1622 (atomic_load node:$ptr)> { 1623 let IsAtomic = true; 1624 let MemoryVT = i64; 1625} 1626 1627//===----------------------------------------------------------------------===// 1628// Selection DAG Pattern Support. 1629// 1630// Patterns are what are actually matched against by the target-flavored 1631// instruction selection DAG. Instructions defined by the target implicitly 1632// define patterns in most cases, but patterns can also be explicitly added when 1633// an operation is defined by a sequence of instructions (e.g. loading a large 1634// immediate value on RISC targets that do not support immediates as large as 1635// their GPRs). 1636// 1637 1638class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1639 dag PatternToMatch = patternToMatch; 1640 list<dag> ResultInstrs = resultInstrs; 1641 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1642 int AddedComplexity = 0; // See class Instruction in Target.td. 1643} 1644 1645// Pat - A simple (but common) form of a pattern, which produces a simple result 1646// not needing a full list. 1647class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1648 1649//===----------------------------------------------------------------------===// 1650// Complex pattern definitions. 1651// 1652 1653// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1654// in C++. NumOperands is the number of operands returned by the select function; 1655// SelectFunc is the name of the function used to pattern match the max. pattern; 1656// RootNodes are the list of possible root nodes of the sub-dags to match. 1657// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1658// 1659class ComplexPattern<ValueType ty, int numops, string fn, 1660 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1661 int complexity = -1> { 1662 ValueType Ty = ty; 1663 int NumOperands = numops; 1664 string SelectFunc = fn; 1665 list<SDNode> RootNodes = roots; 1666 list<SDNodeProperty> Properties = props; 1667 int Complexity = complexity; 1668} 1669