10b57cec5SDimitry Andric //===-- FunctionLoweringInfo.cpp ------------------------------------------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This implements routines for translating functions from LLVM IR into 100b57cec5SDimitry Andric // Machine IR. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #include "llvm/CodeGen/FunctionLoweringInfo.h" 155ffd83dbSDimitry Andric #include "llvm/ADT/APInt.h" 168bcb0991SDimitry Andric #include "llvm/Analysis/LegacyDivergenceAnalysis.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/Analysis.h" 180b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFrameInfo.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 200b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetFrameLowering.h" 230b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 240b57cec5SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 250b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 260b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h" 270b57cec5SDimitry Andric #include "llvm/CodeGen/WasmEHFuncInfo.h" 280b57cec5SDimitry Andric #include "llvm/CodeGen/WinEHFuncInfo.h" 290b57cec5SDimitry Andric #include "llvm/IR/DataLayout.h" 300b57cec5SDimitry Andric #include "llvm/IR/DerivedTypes.h" 310b57cec5SDimitry Andric #include "llvm/IR/Function.h" 320b57cec5SDimitry Andric #include "llvm/IR/Instructions.h" 330b57cec5SDimitry Andric #include "llvm/IR/IntrinsicInst.h" 340b57cec5SDimitry Andric #include "llvm/IR/LLVMContext.h" 350b57cec5SDimitry Andric #include "llvm/IR/Module.h" 360b57cec5SDimitry Andric #include "llvm/Support/Debug.h" 370b57cec5SDimitry Andric #include "llvm/Support/ErrorHandling.h" 380b57cec5SDimitry Andric #include "llvm/Support/MathExtras.h" 390b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h" 400b57cec5SDimitry Andric #include "llvm/Target/TargetOptions.h" 410b57cec5SDimitry Andric #include <algorithm> 420b57cec5SDimitry Andric using namespace llvm; 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric #define DEBUG_TYPE "function-lowering-info" 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by 470b57cec5SDimitry Andric /// PHI nodes or outside of the basic block that defines it, or used by a 480b57cec5SDimitry Andric /// switch or atomic instruction, which may expand to multiple basic blocks. 490b57cec5SDimitry Andric static bool isUsedOutsideOfDefiningBlock(const Instruction *I) { 500b57cec5SDimitry Andric if (I->use_empty()) return false; 510b57cec5SDimitry Andric if (isa<PHINode>(I)) return true; 520b57cec5SDimitry Andric const BasicBlock *BB = I->getParent(); 530b57cec5SDimitry Andric for (const User *U : I->users()) 540b57cec5SDimitry Andric if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U)) 550b57cec5SDimitry Andric return true; 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric return false; 580b57cec5SDimitry Andric } 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric static ISD::NodeType getPreferredExtendForValue(const Value *V) { 610b57cec5SDimitry Andric // For the users of the source value being used for compare instruction, if 620b57cec5SDimitry Andric // the number of signed predicate is greater than unsigned predicate, we 630b57cec5SDimitry Andric // prefer to use SIGN_EXTEND. 640b57cec5SDimitry Andric // 650b57cec5SDimitry Andric // With this optimization, we would be able to reduce some redundant sign or 660b57cec5SDimitry Andric // zero extension instruction, and eventually more machine CSE opportunities 670b57cec5SDimitry Andric // can be exposed. 680b57cec5SDimitry Andric ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 690b57cec5SDimitry Andric unsigned NumOfSigned = 0, NumOfUnsigned = 0; 700b57cec5SDimitry Andric for (const User *U : V->users()) { 710b57cec5SDimitry Andric if (const auto *CI = dyn_cast<CmpInst>(U)) { 720b57cec5SDimitry Andric NumOfSigned += CI->isSigned(); 730b57cec5SDimitry Andric NumOfUnsigned += CI->isUnsigned(); 740b57cec5SDimitry Andric } 750b57cec5SDimitry Andric } 760b57cec5SDimitry Andric if (NumOfSigned > NumOfUnsigned) 770b57cec5SDimitry Andric ExtendKind = ISD::SIGN_EXTEND; 780b57cec5SDimitry Andric 790b57cec5SDimitry Andric return ExtendKind; 800b57cec5SDimitry Andric } 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, 830b57cec5SDimitry Andric SelectionDAG *DAG) { 840b57cec5SDimitry Andric Fn = &fn; 850b57cec5SDimitry Andric MF = &mf; 860b57cec5SDimitry Andric TLI = MF->getSubtarget().getTargetLowering(); 870b57cec5SDimitry Andric RegInfo = &MF->getRegInfo(); 880b57cec5SDimitry Andric const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); 890b57cec5SDimitry Andric DA = DAG->getDivergenceAnalysis(); 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric // Check whether the function can return without sret-demotion. 920b57cec5SDimitry Andric SmallVector<ISD::OutputArg, 4> Outs; 930b57cec5SDimitry Andric CallingConv::ID CC = Fn->getCallingConv(); 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI, 960b57cec5SDimitry Andric mf.getDataLayout()); 970b57cec5SDimitry Andric CanLowerReturn = 980b57cec5SDimitry Andric TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext()); 990b57cec5SDimitry Andric 1000b57cec5SDimitry Andric // If this personality uses funclets, we need to do a bit more work. 1010b57cec5SDimitry Andric DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects; 1020b57cec5SDimitry Andric EHPersonality Personality = classifyEHPersonality( 1030b57cec5SDimitry Andric Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr); 1040b57cec5SDimitry Andric if (isFuncletEHPersonality(Personality)) { 1050b57cec5SDimitry Andric // Calculate state numbers if we haven't already. 1060b57cec5SDimitry Andric WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 1070b57cec5SDimitry Andric if (Personality == EHPersonality::MSVC_CXX) 1080b57cec5SDimitry Andric calculateWinCXXEHStateNumbers(&fn, EHInfo); 1090b57cec5SDimitry Andric else if (isAsynchronousEHPersonality(Personality)) 1100b57cec5SDimitry Andric calculateSEHStateNumbers(&fn, EHInfo); 1110b57cec5SDimitry Andric else if (Personality == EHPersonality::CoreCLR) 1120b57cec5SDimitry Andric calculateClrEHStateNumbers(&fn, EHInfo); 1130b57cec5SDimitry Andric 1140b57cec5SDimitry Andric // Map all BB references in the WinEH data to MBBs. 1150b57cec5SDimitry Andric for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 1160b57cec5SDimitry Andric for (WinEHHandlerType &H : TBME.HandlerArray) { 1170b57cec5SDimitry Andric if (const AllocaInst *AI = H.CatchObj.Alloca) 1180b57cec5SDimitry Andric CatchObjects.insert({AI, {}}).first->second.push_back( 1190b57cec5SDimitry Andric &H.CatchObj.FrameIndex); 1200b57cec5SDimitry Andric else 1210b57cec5SDimitry Andric H.CatchObj.FrameIndex = INT_MAX; 1220b57cec5SDimitry Andric } 1230b57cec5SDimitry Andric } 1240b57cec5SDimitry Andric } 1250b57cec5SDimitry Andric if (Personality == EHPersonality::Wasm_CXX) { 1260b57cec5SDimitry Andric WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); 1270b57cec5SDimitry Andric calculateWasmEHInfo(&fn, EHInfo); 1280b57cec5SDimitry Andric } 1290b57cec5SDimitry Andric 1300b57cec5SDimitry Andric // Initialize the mapping of values to registers. This is only set up for 1310b57cec5SDimitry Andric // instruction values that are used outside of the block that defines 1320b57cec5SDimitry Andric // them. 1335ffd83dbSDimitry Andric const Align StackAlign = TFI->getStackAlign(); 1340b57cec5SDimitry Andric for (const BasicBlock &BB : *Fn) { 1350b57cec5SDimitry Andric for (const Instruction &I : BB) { 1360b57cec5SDimitry Andric if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) { 1370b57cec5SDimitry Andric Type *Ty = AI->getAllocatedType(); 1385ffd83dbSDimitry Andric Align TyPrefAlign = MF->getDataLayout().getPrefTypeAlign(Ty); 1395ffd83dbSDimitry Andric // The "specified" alignment is the alignment written on the alloca, 1405ffd83dbSDimitry Andric // or the preferred alignment of the type if none is specified. 1415ffd83dbSDimitry Andric // 1425ffd83dbSDimitry Andric // (Unspecified alignment on allocas will be going away soon.) 1435ffd83dbSDimitry Andric Align SpecifiedAlign = AI->getAlign(); 1445ffd83dbSDimitry Andric 1455ffd83dbSDimitry Andric // If the preferred alignment of the type is higher than the specified 1465ffd83dbSDimitry Andric // alignment of the alloca, promote the alignment, as long as it doesn't 1475ffd83dbSDimitry Andric // require realigning the stack. 1485ffd83dbSDimitry Andric // 1495ffd83dbSDimitry Andric // FIXME: Do we really want to second-guess the IR in isel? 1505ffd83dbSDimitry Andric Align Alignment = 1515ffd83dbSDimitry Andric std::max(std::min(TyPrefAlign, StackAlign), SpecifiedAlign); 1520b57cec5SDimitry Andric 1530b57cec5SDimitry Andric // Static allocas can be folded into the initial stack frame 1540b57cec5SDimitry Andric // adjustment. For targets that don't realign the stack, don't 1550b57cec5SDimitry Andric // do this if there is an extra alignment requirement. 1560b57cec5SDimitry Andric if (AI->isStaticAlloca() && 1575ffd83dbSDimitry Andric (TFI->isStackRealignable() || (Alignment <= StackAlign))) { 1580b57cec5SDimitry Andric const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize()); 159480093f4SDimitry Andric uint64_t TySize = 160480093f4SDimitry Andric MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinSize(); 1610b57cec5SDimitry Andric 1620b57cec5SDimitry Andric TySize *= CUI->getZExtValue(); // Get total allocated size. 1630b57cec5SDimitry Andric if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. 1640b57cec5SDimitry Andric int FrameIndex = INT_MAX; 1650b57cec5SDimitry Andric auto Iter = CatchObjects.find(AI); 1660b57cec5SDimitry Andric if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) { 1670b57cec5SDimitry Andric FrameIndex = MF->getFrameInfo().CreateFixedObject( 1680b57cec5SDimitry Andric TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true); 1695ffd83dbSDimitry Andric MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment); 1700b57cec5SDimitry Andric } else { 1715ffd83dbSDimitry Andric FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment, 1725ffd83dbSDimitry Andric false, AI); 1730b57cec5SDimitry Andric } 1740b57cec5SDimitry Andric 175480093f4SDimitry Andric // Scalable vectors may need a special StackID to distinguish 176480093f4SDimitry Andric // them from other (fixed size) stack objects. 1775ffd83dbSDimitry Andric if (isa<ScalableVectorType>(Ty)) 178480093f4SDimitry Andric MF->getFrameInfo().setStackID(FrameIndex, 179480093f4SDimitry Andric TFI->getStackIDForScalableVectors()); 180480093f4SDimitry Andric 1810b57cec5SDimitry Andric StaticAllocaMap[AI] = FrameIndex; 1820b57cec5SDimitry Andric // Update the catch handler information. 1830b57cec5SDimitry Andric if (Iter != CatchObjects.end()) { 1840b57cec5SDimitry Andric for (int *CatchObjPtr : Iter->second) 1850b57cec5SDimitry Andric *CatchObjPtr = FrameIndex; 1860b57cec5SDimitry Andric } 1870b57cec5SDimitry Andric } else { 1880b57cec5SDimitry Andric // FIXME: Overaligned static allocas should be grouped into 1890b57cec5SDimitry Andric // a single dynamic allocation instead of using a separate 1900b57cec5SDimitry Andric // stack allocation for each one. 1910b57cec5SDimitry Andric // Inform the Frame Information that we have variable-sized objects. 1925ffd83dbSDimitry Andric MF->getFrameInfo().CreateVariableSizedObject( 1935ffd83dbSDimitry Andric Alignment <= StackAlign ? Align(1) : Alignment, AI); 1940b57cec5SDimitry Andric } 1950b57cec5SDimitry Andric } 1960b57cec5SDimitry Andric 1970b57cec5SDimitry Andric // Look for inline asm that clobbers the SP register. 1985ffd83dbSDimitry Andric if (auto *Call = dyn_cast<CallBase>(&I)) { 1995ffd83dbSDimitry Andric if (Call->isInlineAsm()) { 200e8d8bef9SDimitry Andric Register SP = TLI->getStackPointerRegisterToSaveRestore(); 2010b57cec5SDimitry Andric const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 2020b57cec5SDimitry Andric std::vector<TargetLowering::AsmOperandInfo> Ops = 2035ffd83dbSDimitry Andric TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, 2045ffd83dbSDimitry Andric *Call); 2050b57cec5SDimitry Andric for (TargetLowering::AsmOperandInfo &Op : Ops) { 2060b57cec5SDimitry Andric if (Op.Type == InlineAsm::isClobber) { 2070b57cec5SDimitry Andric // Clobbers don't have SDValue operands, hence SDValue(). 2080b57cec5SDimitry Andric TLI->ComputeConstraintToUse(Op, SDValue(), DAG); 2090b57cec5SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> PhysReg = 2100b57cec5SDimitry Andric TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode, 2110b57cec5SDimitry Andric Op.ConstraintVT); 2120b57cec5SDimitry Andric if (PhysReg.first == SP) 2130b57cec5SDimitry Andric MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 2140b57cec5SDimitry Andric } 2150b57cec5SDimitry Andric } 2160b57cec5SDimitry Andric } 2170b57cec5SDimitry Andric } 2180b57cec5SDimitry Andric 2190b57cec5SDimitry Andric // Look for calls to the @llvm.va_start intrinsic. We can omit some 2200b57cec5SDimitry Andric // prologue boilerplate for variadic functions that don't examine their 2210b57cec5SDimitry Andric // arguments. 2220b57cec5SDimitry Andric if (const auto *II = dyn_cast<IntrinsicInst>(&I)) { 2230b57cec5SDimitry Andric if (II->getIntrinsicID() == Intrinsic::vastart) 2240b57cec5SDimitry Andric MF->getFrameInfo().setHasVAStart(true); 2250b57cec5SDimitry Andric } 2260b57cec5SDimitry Andric 2270b57cec5SDimitry Andric // If we have a musttail call in a variadic function, we need to ensure we 2280b57cec5SDimitry Andric // forward implicit register parameters. 2290b57cec5SDimitry Andric if (const auto *CI = dyn_cast<CallInst>(&I)) { 2300b57cec5SDimitry Andric if (CI->isMustTailCall() && Fn->isVarArg()) 2310b57cec5SDimitry Andric MF->getFrameInfo().setHasMustTailInVarArgFunc(true); 2320b57cec5SDimitry Andric } 2330b57cec5SDimitry Andric 2340b57cec5SDimitry Andric // Mark values used outside their block as exported, by allocating 2350b57cec5SDimitry Andric // a virtual register for them. 2360b57cec5SDimitry Andric if (isUsedOutsideOfDefiningBlock(&I)) 2370b57cec5SDimitry Andric if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I))) 2380b57cec5SDimitry Andric InitializeRegForValue(&I); 2390b57cec5SDimitry Andric 2400b57cec5SDimitry Andric // Decide the preferred extend type for a value. 2410b57cec5SDimitry Andric PreferredExtendType[&I] = getPreferredExtendForValue(&I); 2420b57cec5SDimitry Andric } 2430b57cec5SDimitry Andric } 2440b57cec5SDimitry Andric 2450b57cec5SDimitry Andric // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This 2460b57cec5SDimitry Andric // also creates the initial PHI MachineInstrs, though none of the input 2470b57cec5SDimitry Andric // operands are populated. 2480b57cec5SDimitry Andric for (const BasicBlock &BB : *Fn) { 2490b57cec5SDimitry Andric // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks 2500b57cec5SDimitry Andric // are really data, and no instructions can live here. 2510b57cec5SDimitry Andric if (BB.isEHPad()) { 2520b57cec5SDimitry Andric const Instruction *PadInst = BB.getFirstNonPHI(); 2530b57cec5SDimitry Andric // If this is a non-landingpad EH pad, mark this function as using 2540b57cec5SDimitry Andric // funclets. 2550b57cec5SDimitry Andric // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid 2560b57cec5SDimitry Andric // setting this in such cases in order to improve frame layout. 2570b57cec5SDimitry Andric if (!isa<LandingPadInst>(PadInst)) { 2580b57cec5SDimitry Andric MF->setHasEHScopes(true); 2590b57cec5SDimitry Andric MF->setHasEHFunclets(true); 2600b57cec5SDimitry Andric MF->getFrameInfo().setHasOpaqueSPAdjustment(true); 2610b57cec5SDimitry Andric } 2620b57cec5SDimitry Andric if (isa<CatchSwitchInst>(PadInst)) { 2630b57cec5SDimitry Andric assert(&*BB.begin() == PadInst && 2640b57cec5SDimitry Andric "WinEHPrepare failed to remove PHIs from imaginary BBs"); 2650b57cec5SDimitry Andric continue; 2660b57cec5SDimitry Andric } 2670b57cec5SDimitry Andric if (isa<FuncletPadInst>(PadInst)) 2680b57cec5SDimitry Andric assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs"); 2690b57cec5SDimitry Andric } 2700b57cec5SDimitry Andric 2710b57cec5SDimitry Andric MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB); 2720b57cec5SDimitry Andric MBBMap[&BB] = MBB; 2730b57cec5SDimitry Andric MF->push_back(MBB); 2740b57cec5SDimitry Andric 2750b57cec5SDimitry Andric // Transfer the address-taken flag. This is necessary because there could 2760b57cec5SDimitry Andric // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only 2770b57cec5SDimitry Andric // the first one should be marked. 2780b57cec5SDimitry Andric if (BB.hasAddressTaken()) 2790b57cec5SDimitry Andric MBB->setHasAddressTaken(); 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andric // Mark landing pad blocks. 2820b57cec5SDimitry Andric if (BB.isEHPad()) 2830b57cec5SDimitry Andric MBB->setIsEHPad(); 2840b57cec5SDimitry Andric 2850b57cec5SDimitry Andric // Create Machine PHI nodes for LLVM PHI nodes, lowering them as 2860b57cec5SDimitry Andric // appropriate. 2870b57cec5SDimitry Andric for (const PHINode &PN : BB.phis()) { 2880b57cec5SDimitry Andric if (PN.use_empty()) 2890b57cec5SDimitry Andric continue; 2900b57cec5SDimitry Andric 2910b57cec5SDimitry Andric // Skip empty types 2920b57cec5SDimitry Andric if (PN.getType()->isEmptyTy()) 2930b57cec5SDimitry Andric continue; 2940b57cec5SDimitry Andric 2950b57cec5SDimitry Andric DebugLoc DL = PN.getDebugLoc(); 2960b57cec5SDimitry Andric unsigned PHIReg = ValueMap[&PN]; 2970b57cec5SDimitry Andric assert(PHIReg && "PHI node does not have an assigned virtual register!"); 2980b57cec5SDimitry Andric 2990b57cec5SDimitry Andric SmallVector<EVT, 4> ValueVTs; 3000b57cec5SDimitry Andric ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs); 3010b57cec5SDimitry Andric for (EVT VT : ValueVTs) { 3020b57cec5SDimitry Andric unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 3030b57cec5SDimitry Andric const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 3040b57cec5SDimitry Andric for (unsigned i = 0; i != NumRegisters; ++i) 3050b57cec5SDimitry Andric BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); 3060b57cec5SDimitry Andric PHIReg += NumRegisters; 3070b57cec5SDimitry Andric } 3080b57cec5SDimitry Andric } 3090b57cec5SDimitry Andric } 3100b57cec5SDimitry Andric 3110b57cec5SDimitry Andric if (isFuncletEHPersonality(Personality)) { 3120b57cec5SDimitry Andric WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo(); 3130b57cec5SDimitry Andric 3140b57cec5SDimitry Andric // Map all BB references in the WinEH data to MBBs. 3150b57cec5SDimitry Andric for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) { 3160b57cec5SDimitry Andric for (WinEHHandlerType &H : TBME.HandlerArray) { 3170b57cec5SDimitry Andric if (H.Handler) 3180b57cec5SDimitry Andric H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()]; 3190b57cec5SDimitry Andric } 3200b57cec5SDimitry Andric } 3210b57cec5SDimitry Andric for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap) 3220b57cec5SDimitry Andric if (UME.Cleanup) 3230b57cec5SDimitry Andric UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()]; 3240b57cec5SDimitry Andric for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) { 3250b57cec5SDimitry Andric const auto *BB = UME.Handler.get<const BasicBlock *>(); 3260b57cec5SDimitry Andric UME.Handler = MBBMap[BB]; 3270b57cec5SDimitry Andric } 3280b57cec5SDimitry Andric for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) { 3290b57cec5SDimitry Andric const auto *BB = CME.Handler.get<const BasicBlock *>(); 3300b57cec5SDimitry Andric CME.Handler = MBBMap[BB]; 3310b57cec5SDimitry Andric } 3320b57cec5SDimitry Andric } 3330b57cec5SDimitry Andric 3340b57cec5SDimitry Andric else if (Personality == EHPersonality::Wasm_CXX) { 3350b57cec5SDimitry Andric WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo(); 3360b57cec5SDimitry Andric // Map all BB references in the WinEH data to MBBs. 3370b57cec5SDimitry Andric DenseMap<BBOrMBB, BBOrMBB> NewMap; 3380b57cec5SDimitry Andric for (auto &KV : EHInfo.EHPadUnwindMap) { 3390b57cec5SDimitry Andric const auto *Src = KV.first.get<const BasicBlock *>(); 3400b57cec5SDimitry Andric const auto *Dst = KV.second.get<const BasicBlock *>(); 3410b57cec5SDimitry Andric NewMap[MBBMap[Src]] = MBBMap[Dst]; 3420b57cec5SDimitry Andric } 3430b57cec5SDimitry Andric EHInfo.EHPadUnwindMap = std::move(NewMap); 3440b57cec5SDimitry Andric } 3450b57cec5SDimitry Andric } 3460b57cec5SDimitry Andric 3470b57cec5SDimitry Andric /// clear - Clear out all the function-specific state. This returns this 3480b57cec5SDimitry Andric /// FunctionLoweringInfo to an empty state, ready to be used for a 3490b57cec5SDimitry Andric /// different function. 3500b57cec5SDimitry Andric void FunctionLoweringInfo::clear() { 3510b57cec5SDimitry Andric MBBMap.clear(); 3520b57cec5SDimitry Andric ValueMap.clear(); 3530b57cec5SDimitry Andric VirtReg2Value.clear(); 3540b57cec5SDimitry Andric StaticAllocaMap.clear(); 3550b57cec5SDimitry Andric LiveOutRegInfo.clear(); 3560b57cec5SDimitry Andric VisitedBBs.clear(); 3570b57cec5SDimitry Andric ArgDbgValues.clear(); 3580b57cec5SDimitry Andric DescribedArgs.clear(); 3590b57cec5SDimitry Andric ByValArgFrameIndexMap.clear(); 3600b57cec5SDimitry Andric RegFixups.clear(); 3610b57cec5SDimitry Andric RegsWithFixups.clear(); 3620b57cec5SDimitry Andric StatepointStackSlots.clear(); 363e8d8bef9SDimitry Andric StatepointRelocationMaps.clear(); 3640b57cec5SDimitry Andric PreferredExtendType.clear(); 3650b57cec5SDimitry Andric } 3660b57cec5SDimitry Andric 3670b57cec5SDimitry Andric /// CreateReg - Allocate a single virtual register for the given type. 3685ffd83dbSDimitry Andric Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { 3690b57cec5SDimitry Andric return RegInfo->createVirtualRegister( 3700b57cec5SDimitry Andric MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); 3710b57cec5SDimitry Andric } 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andric /// CreateRegs - Allocate the appropriate number of virtual registers of 3740b57cec5SDimitry Andric /// the correctly promoted or expanded types. Assign these registers 3750b57cec5SDimitry Andric /// consecutive vreg numbers and return the first assigned number. 3760b57cec5SDimitry Andric /// 3770b57cec5SDimitry Andric /// In the case that the given value has struct or array type, this function 3780b57cec5SDimitry Andric /// will assign registers for each member or element. 3790b57cec5SDimitry Andric /// 3805ffd83dbSDimitry Andric Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { 3810b57cec5SDimitry Andric const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); 3820b57cec5SDimitry Andric 3830b57cec5SDimitry Andric SmallVector<EVT, 4> ValueVTs; 3840b57cec5SDimitry Andric ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 3850b57cec5SDimitry Andric 3865ffd83dbSDimitry Andric Register FirstReg; 3870b57cec5SDimitry Andric for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 3880b57cec5SDimitry Andric EVT ValueVT = ValueVTs[Value]; 3890b57cec5SDimitry Andric MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); 3900b57cec5SDimitry Andric 3910b57cec5SDimitry Andric unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); 3920b57cec5SDimitry Andric for (unsigned i = 0; i != NumRegs; ++i) { 3935ffd83dbSDimitry Andric Register R = CreateReg(RegisterVT, isDivergent); 3940b57cec5SDimitry Andric if (!FirstReg) FirstReg = R; 3950b57cec5SDimitry Andric } 3960b57cec5SDimitry Andric } 3970b57cec5SDimitry Andric return FirstReg; 3980b57cec5SDimitry Andric } 3990b57cec5SDimitry Andric 4005ffd83dbSDimitry Andric Register FunctionLoweringInfo::CreateRegs(const Value *V) { 4015ffd83dbSDimitry Andric return CreateRegs(V->getType(), DA && DA->isDivergent(V) && 4025ffd83dbSDimitry Andric !TLI->requiresUniformRegister(*MF, V)); 4030b57cec5SDimitry Andric } 4040b57cec5SDimitry Andric 4050b57cec5SDimitry Andric /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 4060b57cec5SDimitry Andric /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If 4070b57cec5SDimitry Andric /// the register's LiveOutInfo is for a smaller bit width, it is extended to 4080b57cec5SDimitry Andric /// the larger bit width by zero extension. The bit width must be no smaller 4090b57cec5SDimitry Andric /// than the LiveOutInfo's existing bit width. 4100b57cec5SDimitry Andric const FunctionLoweringInfo::LiveOutInfo * 4115ffd83dbSDimitry Andric FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) { 4120b57cec5SDimitry Andric if (!LiveOutRegInfo.inBounds(Reg)) 4130b57cec5SDimitry Andric return nullptr; 4140b57cec5SDimitry Andric 4150b57cec5SDimitry Andric LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 4160b57cec5SDimitry Andric if (!LOI->IsValid) 4170b57cec5SDimitry Andric return nullptr; 4180b57cec5SDimitry Andric 4190b57cec5SDimitry Andric if (BitWidth > LOI->Known.getBitWidth()) { 4200b57cec5SDimitry Andric LOI->NumSignBits = 1; 4215ffd83dbSDimitry Andric LOI->Known = LOI->Known.anyext(BitWidth); 4220b57cec5SDimitry Andric } 4230b57cec5SDimitry Andric 4240b57cec5SDimitry Andric return LOI; 4250b57cec5SDimitry Andric } 4260b57cec5SDimitry Andric 4270b57cec5SDimitry Andric /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination 4280b57cec5SDimitry Andric /// register based on the LiveOutInfo of its operands. 4290b57cec5SDimitry Andric void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { 4300b57cec5SDimitry Andric Type *Ty = PN->getType(); 4310b57cec5SDimitry Andric if (!Ty->isIntegerTy() || Ty->isVectorTy()) 4320b57cec5SDimitry Andric return; 4330b57cec5SDimitry Andric 4340b57cec5SDimitry Andric SmallVector<EVT, 1> ValueVTs; 4350b57cec5SDimitry Andric ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); 4360b57cec5SDimitry Andric assert(ValueVTs.size() == 1 && 4370b57cec5SDimitry Andric "PHIs with non-vector integer types should have a single VT."); 4380b57cec5SDimitry Andric EVT IntVT = ValueVTs[0]; 4390b57cec5SDimitry Andric 4400b57cec5SDimitry Andric if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) 4410b57cec5SDimitry Andric return; 4420b57cec5SDimitry Andric IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); 4430b57cec5SDimitry Andric unsigned BitWidth = IntVT.getSizeInBits(); 4440b57cec5SDimitry Andric 4455ffd83dbSDimitry Andric Register DestReg = ValueMap[PN]; 4468bcb0991SDimitry Andric if (!Register::isVirtualRegister(DestReg)) 4470b57cec5SDimitry Andric return; 4480b57cec5SDimitry Andric LiveOutRegInfo.grow(DestReg); 4490b57cec5SDimitry Andric LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg]; 4500b57cec5SDimitry Andric 4510b57cec5SDimitry Andric Value *V = PN->getIncomingValue(0); 4520b57cec5SDimitry Andric if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 4530b57cec5SDimitry Andric DestLOI.NumSignBits = 1; 4540b57cec5SDimitry Andric DestLOI.Known = KnownBits(BitWidth); 4550b57cec5SDimitry Andric return; 4560b57cec5SDimitry Andric } 4570b57cec5SDimitry Andric 4580b57cec5SDimitry Andric if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 4590b57cec5SDimitry Andric APInt Val = CI->getValue().zextOrTrunc(BitWidth); 4600b57cec5SDimitry Andric DestLOI.NumSignBits = Val.getNumSignBits(); 461e8d8bef9SDimitry Andric DestLOI.Known = KnownBits::makeConstant(Val); 4620b57cec5SDimitry Andric } else { 4630b57cec5SDimitry Andric assert(ValueMap.count(V) && "V should have been placed in ValueMap when its" 4640b57cec5SDimitry Andric "CopyToReg node was created."); 4655ffd83dbSDimitry Andric Register SrcReg = ValueMap[V]; 4668bcb0991SDimitry Andric if (!Register::isVirtualRegister(SrcReg)) { 4670b57cec5SDimitry Andric DestLOI.IsValid = false; 4680b57cec5SDimitry Andric return; 4690b57cec5SDimitry Andric } 4700b57cec5SDimitry Andric const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 4710b57cec5SDimitry Andric if (!SrcLOI) { 4720b57cec5SDimitry Andric DestLOI.IsValid = false; 4730b57cec5SDimitry Andric return; 4740b57cec5SDimitry Andric } 4750b57cec5SDimitry Andric DestLOI = *SrcLOI; 4760b57cec5SDimitry Andric } 4770b57cec5SDimitry Andric 4780b57cec5SDimitry Andric assert(DestLOI.Known.Zero.getBitWidth() == BitWidth && 4790b57cec5SDimitry Andric DestLOI.Known.One.getBitWidth() == BitWidth && 4800b57cec5SDimitry Andric "Masks should have the same bit width as the type."); 4810b57cec5SDimitry Andric 4820b57cec5SDimitry Andric for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) { 4830b57cec5SDimitry Andric Value *V = PN->getIncomingValue(i); 4840b57cec5SDimitry Andric if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) { 4850b57cec5SDimitry Andric DestLOI.NumSignBits = 1; 4860b57cec5SDimitry Andric DestLOI.Known = KnownBits(BitWidth); 4870b57cec5SDimitry Andric return; 4880b57cec5SDimitry Andric } 4890b57cec5SDimitry Andric 4900b57cec5SDimitry Andric if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 4910b57cec5SDimitry Andric APInt Val = CI->getValue().zextOrTrunc(BitWidth); 4920b57cec5SDimitry Andric DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits()); 4930b57cec5SDimitry Andric DestLOI.Known.Zero &= ~Val; 4940b57cec5SDimitry Andric DestLOI.Known.One &= Val; 4950b57cec5SDimitry Andric continue; 4960b57cec5SDimitry Andric } 4970b57cec5SDimitry Andric 4980b57cec5SDimitry Andric assert(ValueMap.count(V) && "V should have been placed in ValueMap when " 4990b57cec5SDimitry Andric "its CopyToReg node was created."); 5005ffd83dbSDimitry Andric Register SrcReg = ValueMap[V]; 5015ffd83dbSDimitry Andric if (!SrcReg.isVirtual()) { 5020b57cec5SDimitry Andric DestLOI.IsValid = false; 5030b57cec5SDimitry Andric return; 5040b57cec5SDimitry Andric } 5050b57cec5SDimitry Andric const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 5060b57cec5SDimitry Andric if (!SrcLOI) { 5070b57cec5SDimitry Andric DestLOI.IsValid = false; 5080b57cec5SDimitry Andric return; 5090b57cec5SDimitry Andric } 5100b57cec5SDimitry Andric DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits); 511e8d8bef9SDimitry Andric DestLOI.Known = KnownBits::commonBits(DestLOI.Known, SrcLOI->Known); 5120b57cec5SDimitry Andric } 5130b57cec5SDimitry Andric } 5140b57cec5SDimitry Andric 5150b57cec5SDimitry Andric /// setArgumentFrameIndex - Record frame index for the byval 5160b57cec5SDimitry Andric /// argument. This overrides previous frame index entry for this argument, 5170b57cec5SDimitry Andric /// if any. 5180b57cec5SDimitry Andric void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A, 5190b57cec5SDimitry Andric int FI) { 5200b57cec5SDimitry Andric ByValArgFrameIndexMap[A] = FI; 5210b57cec5SDimitry Andric } 5220b57cec5SDimitry Andric 5230b57cec5SDimitry Andric /// getArgumentFrameIndex - Get frame index for the byval argument. 5240b57cec5SDimitry Andric /// If the argument does not have any assigned frame index then 0 is 5250b57cec5SDimitry Andric /// returned. 5260b57cec5SDimitry Andric int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) { 5270b57cec5SDimitry Andric auto I = ByValArgFrameIndexMap.find(A); 5280b57cec5SDimitry Andric if (I != ByValArgFrameIndexMap.end()) 5290b57cec5SDimitry Andric return I->second; 5300b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n"); 5310b57cec5SDimitry Andric return INT_MAX; 5320b57cec5SDimitry Andric } 5330b57cec5SDimitry Andric 5345ffd83dbSDimitry Andric Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg( 5350b57cec5SDimitry Andric const Value *CPI, const TargetRegisterClass *RC) { 5360b57cec5SDimitry Andric MachineRegisterInfo &MRI = MF->getRegInfo(); 5370b57cec5SDimitry Andric auto I = CatchPadExceptionPointers.insert({CPI, 0}); 5385ffd83dbSDimitry Andric Register &VReg = I.first->second; 5390b57cec5SDimitry Andric if (I.second) 5400b57cec5SDimitry Andric VReg = MRI.createVirtualRegister(RC); 5410b57cec5SDimitry Andric assert(VReg && "null vreg in exception pointer table!"); 5420b57cec5SDimitry Andric return VReg; 5430b57cec5SDimitry Andric } 5440b57cec5SDimitry Andric 5450b57cec5SDimitry Andric const Value * 5465ffd83dbSDimitry Andric FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) { 5470b57cec5SDimitry Andric if (VirtReg2Value.empty()) { 5480b57cec5SDimitry Andric SmallVector<EVT, 4> ValueVTs; 5490b57cec5SDimitry Andric for (auto &P : ValueMap) { 5500b57cec5SDimitry Andric ValueVTs.clear(); 5510b57cec5SDimitry Andric ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(), 5520b57cec5SDimitry Andric P.first->getType(), ValueVTs); 5530b57cec5SDimitry Andric unsigned Reg = P.second; 5540b57cec5SDimitry Andric for (EVT VT : ValueVTs) { 5550b57cec5SDimitry Andric unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); 5560b57cec5SDimitry Andric for (unsigned i = 0, e = NumRegisters; i != e; ++i) 5570b57cec5SDimitry Andric VirtReg2Value[Reg++] = P.first; 5580b57cec5SDimitry Andric } 5590b57cec5SDimitry Andric } 5600b57cec5SDimitry Andric } 5610b57cec5SDimitry Andric return VirtReg2Value.lookup(Vreg); 5620b57cec5SDimitry Andric } 563