1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing.
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// AArch64 Subtarget features.
20//
21
22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
23                                       "Enable ARMv8 FP">;
24
25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
26  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
27
28def FeatureSM4 : SubtargetFeature<
29    "sm4", "HasSM4", "true",
30    "Enable SM3 and SM4 support", [FeatureNEON]>;
31
32def FeatureSHA2 : SubtargetFeature<
33    "sha2", "HasSHA2", "true",
34    "Enable SHA1 and SHA256 support", [FeatureNEON]>;
35
36def FeatureSHA3 : SubtargetFeature<
37    "sha3", "HasSHA3", "true",
38    "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
39
40def FeatureAES : SubtargetFeature<
41    "aes", "HasAES", "true",
42    "Enable AES support", [FeatureNEON]>;
43
44// Crypto has been split up and any combination is now valid (see the
45// crypto definitions above). Also, crypto is now context sensitive:
46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
47// Therefore, we rely on Clang, the user interacing tool, to pass on the
48// appropriate crypto options. But here in the backend, crypto has very little
49// meaning anymore. We kept the Crypto definition here for backward
50// compatibility, and now imply features SHA2 and AES, which was the
51// "traditional" meaning of Crypto.
52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
53  "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
54
55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
56  "Enable ARMv8 CRC-32 checksum instructions">;
57
58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
59  "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
60
61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
62  "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
63
64def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
65  "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">;
66
67def FeatureLDAPR : SubtargetFeature<"ldapr", "HasLDAPR", "true",
68  "Use LDAPR to lower atomic loads; experimental until we "
69  "have more testing/a formal correctness proof">;
70
71def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
72  "Enable out of line atomics to support LSE instructions">;
73
74def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
75  "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
76
77def FeaturePAN : SubtargetFeature<
78    "pan", "HasPAN", "true",
79    "Enables ARM v8.1 Privileged Access-Never extension">;
80
81def FeatureLOR : SubtargetFeature<
82    "lor", "HasLOR", "true",
83    "Enables ARM v8.1 Limited Ordering Regions extension">;
84
85def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
86    "true", "Enable RW operand CONTEXTIDR_EL2" >;
87
88def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
89    "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
90
91def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
92  "Enable ARMv8 PMUv3 Performance Monitors extension">;
93
94def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
95  "Full FP16", [FeatureFPARMv8]>;
96
97def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
98  "Enable FP16 FML instructions", [FeatureFullFP16]>;
99
100def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
101  "Enable Statistical Profiling extension">;
102
103def FeaturePAN_RWV : SubtargetFeature<
104    "pan-rwv", "HasPAN_RWV", "true",
105    "Enable v8.2 PAN s1e1R and s1e1W Variants",
106    [FeaturePAN]>;
107
108// UAO PState
109def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
110    "Enable v8.2 UAO PState">;
111
112def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
113    "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
114
115def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
116  "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
117
118// This flag is currently still labeled as Experimental, but when fully
119// implemented this should tell the compiler to use the zeroing pseudos to
120// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
121// lanes are known to be zero. The pseudos will then be expanded using the
122// MOVPRFX instruction to zero the inactive lanes. This feature should only be
123// enabled if MOVPRFX instructions are known to merge with the destructive
124// operations they prefix.
125//
126// This feature could similarly be extended to support cheap merging of _any_
127// value into the inactive lanes using the MOVPRFX instruction that uses
128// merging-predication.
129def FeatureExperimentalZeroingPseudos
130    : SubtargetFeature<"use-experimental-zeroing-pseudos",
131                       "UseExperimentalZeroingPseudos", "true",
132                       "Hint to the compiler that the MOVPRFX instruction is "
133                       "merged with destructive operations",
134                       []>;
135
136def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
137  "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
138
139def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
140  "Enable Scalable Vector Extension 2 (SVE2) instructions",
141  [FeatureSVE, FeatureUseScalarIncVL]>;
142
143def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
144  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
145
146def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
147  "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
148
149def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
150  "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
151
152def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
153  "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
154
155def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
156                                        "Has zero-cycle register moves">;
157
158def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
159                                        "Has zero-cycle zeroing instructions for generic registers">;
160
161// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
162// as movi is more efficient across all cores. Newer cores can eliminate
163// fmovs early and there is no difference with movi, but this not true for
164// all implementations.
165def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
166                                        "Has no zero-cycle zeroing instructions for FP registers">;
167
168def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
169                                        "Has zero-cycle zeroing instructions",
170                                        [FeatureZCZeroingGP]>;
171
172/// ... but the floating-point version doesn't quite work in rare cases on older
173/// CPUs.
174def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
175    "HasZeroCycleZeroingFPWorkaround", "true",
176    "The zero-cycle floating-point zeroing instruction has a bug">;
177
178def FeatureStrictAlign : SubtargetFeature<"strict-align",
179                                          "RequiresStrictAlign", "true",
180                                          "Disallow all unaligned memory "
181                                          "access">;
182
183foreach i = {1-7,9-15,18,20-28,30} in
184    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
185                                             "Reserve X"#i#", making it unavailable "
186                                             "as a GPR">;
187
188foreach i = {8-15,18} in
189    def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
190         "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
191
192def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
193    "true",
194    "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
195
196def FeaturePredictableSelectIsExpensive : SubtargetFeature<
197    "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
198    "Prefer likely predicted branches over selects">;
199
200def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
201    "HasCustomCheapAsMoveHandling", "true",
202    "Use custom handling of cheap instructions">;
203
204def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
205    "HasExynosCheapAsMoveHandling", "true",
206    "Use Exynos specific handling of cheap instructions",
207    [FeatureCustomCheapAsMoveHandling]>;
208
209def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
210    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
211
212def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
213    "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;
214
215def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
216    "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;
217
218def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
219    "IsStoreAddressAscend", "true",
220    "Schedule vector stores by ascending address">;
221
222def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
223    "true", "STR of Q register with register offset is slow">;
224
225def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
226    "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
227    "true", "Use alternative pattern for sextload convert to f32">;
228
229def FeatureArithmeticBccFusion : SubtargetFeature<
230    "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
231    "CPU fuses arithmetic+bcc operations">;
232
233def FeatureArithmeticCbzFusion : SubtargetFeature<
234    "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
235    "CPU fuses arithmetic + cbz/cbnz operations">;
236
237def FeatureCmpBccFusion : SubtargetFeature<
238    "cmp-bcc-fusion", "HasCmpBccFusion", "true",
239    "CPU fuses cmp+bcc operations">;
240
241def FeatureFuseAddress : SubtargetFeature<
242    "fuse-address", "HasFuseAddress", "true",
243    "CPU fuses address generation and memory operations">;
244
245def FeatureFuseAES : SubtargetFeature<
246    "fuse-aes", "HasFuseAES", "true",
247    "CPU fuses AES crypto operations">;
248
249def FeatureFuseArithmeticLogic : SubtargetFeature<
250    "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
251    "CPU fuses arithmetic and logic operations">;
252
253def FeatureFuseCCSelect : SubtargetFeature<
254    "fuse-csel", "HasFuseCCSelect", "true",
255    "CPU fuses conditional select operations">;
256
257def FeatureFuseCryptoEOR : SubtargetFeature<
258    "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
259    "CPU fuses AES/PMULL and EOR operations">;
260
261def FeatureFuseAdrpAdd : SubtargetFeature<
262    "fuse-adrp-add", "HasFuseAdrpAdd", "true",
263    "CPU fuses adrp+add operations">;
264
265def FeatureFuseLiterals : SubtargetFeature<
266    "fuse-literals", "HasFuseLiterals", "true",
267    "CPU fuses literal generation operations">;
268
269def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
270    "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
271    "Disable latency scheduling heuristic">;
272
273def FeatureForce32BitJumpTables
274   : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
275                      "Force jump table entries to be 32-bits wide except at MinSize">;
276
277def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
278                                   "Enable support for RCPC extension">;
279
280def FeatureUseRSqrt : SubtargetFeature<
281    "use-reciprocal-square-root", "UseRSqrt", "true",
282    "Use the reciprocal square root approximation">;
283
284def FeatureDotProd : SubtargetFeature<
285    "dotprod", "HasDotProd", "true",
286    "Enable dot product support">;
287
288def FeaturePAuth : SubtargetFeature<
289    "pauth", "HasPAuth", "true",
290    "Enable v8.3-A Pointer Authentication extension">;
291
292def FeatureJS : SubtargetFeature<
293    "jsconv", "HasJS", "true",
294    "Enable v8.3-A JavaScript FP conversion instructions",
295    [FeatureFPARMv8]>;
296
297def FeatureCCIDX : SubtargetFeature<
298    "ccidx", "HasCCIDX", "true",
299    "Enable v8.3-A Extend of the CCSIDR number of sets">;
300
301def FeatureComplxNum : SubtargetFeature<
302    "complxnum", "HasComplxNum", "true",
303    "Enable v8.3-A Floating-point complex number support",
304    [FeatureNEON]>;
305
306def FeatureNV : SubtargetFeature<
307    "nv", "HasNV", "true",
308    "Enable v8.4-A Nested Virtualization Enchancement">;
309
310def FeatureMPAM : SubtargetFeature<
311    "mpam", "HasMPAM", "true",
312    "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
313
314def FeatureDIT : SubtargetFeature<
315    "dit", "HasDIT", "true",
316    "Enable v8.4-A Data Independent Timing instructions">;
317
318def FeatureTRACEV8_4 : SubtargetFeature<
319    "tracev8.4", "HasTRACEV8_4", "true",
320    "Enable v8.4-A Trace extension">;
321
322def FeatureAM : SubtargetFeature<
323    "am", "HasAM", "true",
324    "Enable v8.4-A Activity Monitors extension">;
325
326def FeatureAMVS : SubtargetFeature<
327    "amvs", "HasAMVS", "true",
328    "Enable v8.6-A Activity Monitors Virtualization support",
329    [FeatureAM]>;
330
331def FeatureSEL2 : SubtargetFeature<
332    "sel2", "HasSEL2", "true",
333    "Enable v8.4-A Secure Exception Level 2 extension">;
334
335def FeatureTLB_RMI : SubtargetFeature<
336    "tlb-rmi", "HasTLB_RMI", "true",
337    "Enable v8.4-A TLB Range and Maintenance Instructions">;
338
339def FeatureFlagM : SubtargetFeature<
340    "flagm", "HasFlagM", "true",
341    "Enable v8.4-A Flag Manipulation Instructions">;
342
343// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
344def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
345    "Enable v8.4-A RCPC instructions with Immediate Offsets",
346    [FeatureRCPC]>;
347
348def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
349                                        "NegativeImmediates", "false",
350                                        "Convert immediates and instructions "
351                                        "to their negated or complemented "
352                                        "equivalent when the immediate does "
353                                        "not fit in the encoding.">;
354
355def FeatureLSLFast : SubtargetFeature<
356    "lsl-fast", "HasLSLFast", "true",
357    "CPU has a fastpath logical shift of up to 3 places">;
358
359def FeatureAggressiveFMA :
360  SubtargetFeature<"aggressive-fma",
361                   "HasAggressiveFMA",
362                   "true",
363                   "Enable Aggressive FMA for floating-point.">;
364
365def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
366  "Enable alternative NZCV format for floating point comparisons">;
367
368def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
369  "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
370  "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
371
372def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
373  "true", "Enable architectural speculation restriction" >;
374
375def FeatureSB : SubtargetFeature<"sb", "HasSB",
376  "true", "Enable v8.5 Speculation Barrier" >;
377
378def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
379  "true", "Enable Speculative Store Bypass Safe bit" >;
380
381def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
382  "Enable v8.5a execution and data prediction invalidation instructions" >;
383
384def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
385    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
386
387def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
388    "true", "Enable Branch Target Identification" >;
389
390def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
391    "true", "Enable Random Number generation instructions" >;
392
393def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
394    "true", "Enable Memory Tagging Extension" >;
395
396def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
397    "true", "Enable Trace Buffer Extension">;
398
399def FeatureETE : SubtargetFeature<"ete", "HasETE",
400    "true", "Enable Embedded Trace Extension",
401    [FeatureTRBE]>;
402
403def FeatureTME : SubtargetFeature<"tme", "HasTME",
404    "true", "Enable Transactional Memory Extension" >;
405
406def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
407    "AllowTaggedGlobals",
408    "true", "Use an instruction sequence for taking the address of a global "
409    "that allows a memory tag in the upper address bits">;
410
411def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
412    "true", "Enable BFloat16 Extension" >;
413
414def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
415    "true", "Enable Matrix Multiply Int8 Extension">;
416
417def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
418    "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
419
420def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
421    "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
422
423def FeatureXS : SubtargetFeature<"xs", "HasXS",
424    "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
425
426def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
427    "true", "Enable Armv8.7-A WFET and WFIT instruction">;
428
429def FeatureHCX : SubtargetFeature<
430    "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
431
432def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
433    "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
434
435def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
436    "true", "Enable Armv8.8-A Hinted Conditional Branches Extension">;
437
438def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
439    "true", "Enable Armv8.8-A memcpy and memset acceleration instructions">;
440
441def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
442    "true", "Enable Branch Record Buffer Extension">;
443
444def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
445    "true", "Enable extra register in the Statistical Profiling Extension">;
446
447def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
448    "true", "Enable fine grained virtualization traps extension">;
449
450def FeatureEnhancedCounterVirtualization :
451      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
452      "true", "Enable enhanced counter virtualization extension">;
453
454def FeatureRME : SubtargetFeature<"rme", "HasRME",
455    "true", "Enable Realm Management Extension">;
456
457def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
458  "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
459
460def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
461  "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
462
463def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
464  "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;
465
466def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
467  "Apple A7 (the CPU formerly known as Cyclone)">;
468
469def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
470  "Enable Exception Level 2 Virtual Memory System Architecture">;
471
472def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
473  "Enable Exception Level 3">;
474
475def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
476  "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
477
478def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
479                                                 "NoBTIAtReturnTwice", "true",
480                                                 "Don't place a BTI instruction "
481                                                 "after a return-twice">;
482
483//===----------------------------------------------------------------------===//
484// Architectures.
485//
486def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
487  "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
488
489def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
490  "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
491  FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
492
493def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
494  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
495  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
496
497def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
498  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
499  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
500
501def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
502  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
503  FeatureNV, FeatureMPAM, FeatureDIT,
504  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
505  FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>;
506
507def HasV8_5aOps : SubtargetFeature<
508  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
509  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
510   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
511   FeatureBranchTargetId]>;
512
513def HasV8_6aOps : SubtargetFeature<
514  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
515  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
516   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
517
518def HasV8_7aOps : SubtargetFeature<
519  "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
520  [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
521
522def HasV8_8aOps : SubtargetFeature<
523  "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
524  [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
525
526def HasV9_0aOps : SubtargetFeature<
527  "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
528  [HasV8_5aOps, FeatureSVE2]>;
529
530def HasV9_1aOps : SubtargetFeature<
531  "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
532  [HasV8_6aOps, HasV9_0aOps]>;
533
534def HasV9_2aOps : SubtargetFeature<
535  "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
536  [HasV8_7aOps, HasV9_1aOps]>;
537
538def HasV9_3aOps : SubtargetFeature<
539  "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
540  [HasV8_8aOps, HasV9_2aOps]>;
541
542def HasV8_0rOps : SubtargetFeature<
543  "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
544  [//v8.1
545  FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
546  //v8.2
547  FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
548  //v8.3
549  FeatureComplxNum, FeatureCCIDX, FeatureJS,
550  FeaturePAuth, FeatureRCPC,
551  //v8.4
552  FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
553  FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
554  // Not mandatory in v8.0-R, but included here on the grounds that it
555  // only enables names of system registers
556  FeatureSpecRestrict
557  ]>;
558
559// Only intended to be used by disassemblers.
560def FeatureAll
561    : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;
562
563class AssemblerPredicateWithAll<dag cond, string name="">
564    : AssemblerPredicate<(any_of FeatureAll, cond), name>;
565
566//===----------------------------------------------------------------------===//
567// Register File Description
568//===----------------------------------------------------------------------===//
569
570include "AArch64RegisterInfo.td"
571include "AArch64RegisterBanks.td"
572include "AArch64CallingConvention.td"
573
574//===----------------------------------------------------------------------===//
575// Instruction Descriptions
576//===----------------------------------------------------------------------===//
577
578include "AArch64Schedule.td"
579include "AArch64InstrInfo.td"
580include "AArch64SchedPredicates.td"
581include "AArch64SchedPredExynos.td"
582include "AArch64SchedPredAmpere.td"
583include "AArch64Combine.td"
584
585def AArch64InstrInfo : InstrInfo;
586
587//===----------------------------------------------------------------------===//
588// Named operands for MRS/MSR/TLBI/...
589//===----------------------------------------------------------------------===//
590
591include "AArch64SystemOperands.td"
592
593//===----------------------------------------------------------------------===//
594// Access to privileged registers
595//===----------------------------------------------------------------------===//
596
597foreach i = 1-3 in
598def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
599  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
600
601//===----------------------------------------------------------------------===//
602// Control codegen mitigation against Straight Line Speculation vulnerability.
603//===----------------------------------------------------------------------===//
604
605def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
606  "HardenSlsRetBr", "true",
607  "Harden against straight line speculation across RET and BR instructions">;
608def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
609  "HardenSlsBlr", "true",
610  "Harden against straight line speculation across BLR instructions">;
611def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
612  "HardenSlsNoComdat", "true",
613  "Generate thunk code for SLS mitigation in the normal text section">;
614
615//===----------------------------------------------------------------------===//
616// AArch64 Processors supported.
617//
618
619//===----------------------------------------------------------------------===//
620// Unsupported features to disable for scheduling models
621//===----------------------------------------------------------------------===//
622
623class AArch64Unsupported { list<Predicate> F; }
624
625def SVEUnsupported : AArch64Unsupported {
626  let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
627           HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME];
628}
629
630def PAUnsupported : AArch64Unsupported {
631  let F = [HasPAuth];
632}
633
634def SMEUnsupported : AArch64Unsupported {
635  let F = [HasSME, HasSMEF64, HasSMEI64];
636}
637
638include "AArch64SchedA53.td"
639include "AArch64SchedA55.td"
640include "AArch64SchedA57.td"
641include "AArch64SchedCyclone.td"
642include "AArch64SchedFalkor.td"
643include "AArch64SchedKryo.td"
644include "AArch64SchedExynosM3.td"
645include "AArch64SchedExynosM4.td"
646include "AArch64SchedExynosM5.td"
647include "AArch64SchedThunderX.td"
648include "AArch64SchedThunderX2T99.td"
649include "AArch64SchedA64FX.td"
650include "AArch64SchedThunderX3T110.td"
651include "AArch64SchedTSV110.td"
652include "AArch64SchedAmpere1.td"
653include "AArch64SchedNeoverseN2.td"
654
655def TuneA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
656                                "Cortex-A35 ARM processors">;
657
658def TuneA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
659                                   "Cortex-A53 ARM processors", [
660                                   FeatureFuseAES,
661                                   FeatureBalanceFPOps,
662                                   FeatureCustomCheapAsMoveHandling,
663                                   FeaturePostRAScheduler]>;
664
665def TuneA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
666                                   "Cortex-A55 ARM processors", [
667                                   FeatureFuseAES,
668                                   FeaturePostRAScheduler,
669                                   FeatureFuseAddress]>;
670
671def TuneA510    : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
672                                   "Cortex-A510 ARM processors", [
673                                   FeatureFuseAES,
674                                   FeaturePostRAScheduler
675                                   ]>;
676
677def TuneA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
678                                   "Cortex-A57 ARM processors", [
679                                   FeatureFuseAES,
680                                   FeatureBalanceFPOps,
681                                   FeatureCustomCheapAsMoveHandling,
682                                   FeatureFuseAdrpAdd,
683                                   FeatureFuseLiterals,
684                                   FeaturePostRAScheduler,
685                                   FeaturePredictableSelectIsExpensive]>;
686
687def TuneA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
688                                   "Cortex-A65 ARM processors", [
689                                   FeatureFuseAES,
690                                   FeatureFuseAddress,
691                                   FeatureFuseAdrpAdd,
692                                   FeatureFuseLiterals]>;
693
694def TuneA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
695                                   "Cortex-A72 ARM processors", [
696                                   FeatureFuseAES,
697                                   FeatureFuseAdrpAdd,
698                                   FeatureFuseLiterals]>;
699
700def TuneA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
701                                   "Cortex-A73 ARM processors", [
702                                   FeatureFuseAES]>;
703
704def TuneA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
705                                   "Cortex-A75 ARM processors", [
706                                   FeatureFuseAES]>;
707
708def TuneA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
709                                   "Cortex-A76 ARM processors", [
710                                   FeatureFuseAES]>;
711
712def TuneA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
713                                   "Cortex-A77 ARM processors", [
714                                   FeatureCmpBccFusion,
715                                   FeatureFuseAES]>;
716
717def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
718                               "Cortex-A78 ARM processors", [
719                               FeatureCmpBccFusion,
720                               FeatureFuseAES,
721                               FeaturePostRAScheduler]>;
722
723def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
724                                "CortexA78C",
725                                "Cortex-A78C ARM processors", [
726                                FeatureCmpBccFusion,
727                                FeatureFuseAES,
728                                FeaturePostRAScheduler]>;
729
730def TuneA710    : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
731                                   "Cortex-A710 ARM processors", [
732                                   FeatureFuseAES,
733                                   FeaturePostRAScheduler,
734                                   FeatureCmpBccFusion]>;
735
736def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
737                               "CortexR82",
738                               "Cortex-R82 ARM processors", [
739                               FeaturePostRAScheduler]>;
740
741def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
742                                  "Cortex-X1 ARM processors", [
743                                  FeatureCmpBccFusion,
744                                  FeatureFuseAES,
745                                  FeaturePostRAScheduler]>;
746
747def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
748                                  "Cortex-X2 ARM processors", [
749                                  FeatureFuseAES,
750                                  FeaturePostRAScheduler,
751                                  FeatureCmpBccFusion]>;
752
753def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
754                                 "Fujitsu A64FX processors", [
755                                 FeaturePostRAScheduler,
756                                 FeatureAggressiveFMA,
757                                 FeatureArithmeticBccFusion,
758                                 FeaturePredictableSelectIsExpensive
759                                 ]>;
760
761def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
762                                  "Nvidia Carmel processors">;
763
764// Note that cyclone does not fuse AES instructions, but newer apple chips do
765// perform the fusion and cyclone is used by default when targetting apple OSes.
766def TuneAppleA7  : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
767                                    "Apple A7 (the CPU formerly known as Cyclone)", [
768                                    FeatureAlternateSExtLoadCVTF32Pattern,
769                                    FeatureArithmeticBccFusion,
770                                    FeatureArithmeticCbzFusion,
771                                    FeatureDisableLatencySchedHeuristic,
772                                    FeatureFuseAES, FeatureFuseCryptoEOR,
773                                    FeatureZCRegMove,
774                                    FeatureZCZeroing,
775                                    FeatureZCZeroingFPWorkaround]
776                                    >;
777
778def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
779                                    "Apple A10", [
780                                    FeatureAlternateSExtLoadCVTF32Pattern,
781                                    FeatureArithmeticBccFusion,
782                                    FeatureArithmeticCbzFusion,
783                                    FeatureDisableLatencySchedHeuristic,
784                                    FeatureFuseAES,
785                                    FeatureFuseCryptoEOR,
786                                    FeatureZCRegMove,
787                                    FeatureZCZeroing]
788                                    >;
789
790def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
791                                    "Apple A11", [
792                                    FeatureAlternateSExtLoadCVTF32Pattern,
793                                    FeatureArithmeticBccFusion,
794                                    FeatureArithmeticCbzFusion,
795                                    FeatureDisableLatencySchedHeuristic,
796                                    FeatureFuseAES,
797                                    FeatureFuseCryptoEOR,
798                                    FeatureZCRegMove,
799                                    FeatureZCZeroing]
800                                    >;
801
802def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
803                                    "Apple A12", [
804                                    FeatureAlternateSExtLoadCVTF32Pattern,
805                                    FeatureArithmeticBccFusion,
806                                    FeatureArithmeticCbzFusion,
807                                    FeatureDisableLatencySchedHeuristic,
808                                    FeatureFuseAES,
809                                    FeatureFuseCryptoEOR,
810                                    FeatureZCRegMove,
811                                    FeatureZCZeroing]
812                                    >;
813
814def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
815                                    "Apple A13", [
816                                    FeatureAlternateSExtLoadCVTF32Pattern,
817                                    FeatureArithmeticBccFusion,
818                                    FeatureArithmeticCbzFusion,
819                                    FeatureDisableLatencySchedHeuristic,
820                                    FeatureFuseAES,
821                                    FeatureFuseCryptoEOR,
822                                    FeatureZCRegMove,
823                                    FeatureZCZeroing]
824                                    >;
825
826def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
827                                    "Apple A14", [
828                                    FeatureAggressiveFMA,
829                                    FeatureAlternateSExtLoadCVTF32Pattern,
830                                    FeatureArithmeticBccFusion,
831                                    FeatureArithmeticCbzFusion,
832                                    FeatureDisableLatencySchedHeuristic,
833                                    FeatureFuseAddress,
834                                    FeatureFuseAES,
835                                    FeatureFuseArithmeticLogic,
836                                    FeatureFuseCCSelect,
837                                    FeatureFuseCryptoEOR,
838                                    FeatureFuseAdrpAdd,
839                                    FeatureFuseLiterals,
840                                    FeatureZCRegMove,
841                                    FeatureZCZeroing]>;
842
843def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
844                                    "Samsung Exynos-M3 processors",
845                                    [FeatureExynosCheapAsMoveHandling,
846                                     FeatureForce32BitJumpTables,
847                                     FeatureFuseAddress,
848                                     FeatureFuseAES,
849                                     FeatureFuseCCSelect,
850                                     FeatureFuseAdrpAdd,
851                                     FeatureFuseLiterals,
852                                     FeatureLSLFast,
853                                     FeaturePostRAScheduler,
854                                     FeaturePredictableSelectIsExpensive]>;
855
856// Re-uses some scheduling and tunings from the ExynosM3 proc family.
857def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
858                                    "Samsung Exynos-M4 processors",
859                                    [FeatureArithmeticBccFusion,
860                                     FeatureArithmeticCbzFusion,
861                                     FeatureExynosCheapAsMoveHandling,
862                                     FeatureForce32BitJumpTables,
863                                     FeatureFuseAddress,
864                                     FeatureFuseAES,
865                                     FeatureFuseArithmeticLogic,
866                                     FeatureFuseCCSelect,
867                                     FeatureFuseAdrpAdd,
868                                     FeatureFuseLiterals,
869                                     FeatureLSLFast,
870                                     FeaturePostRAScheduler,
871                                     FeatureZCZeroing]>;
872
873def TuneKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
874                                   "Qualcomm Kryo processors", [
875                                   FeatureCustomCheapAsMoveHandling,
876                                   FeaturePostRAScheduler,
877                                   FeaturePredictableSelectIsExpensive,
878                                   FeatureZCZeroing,
879                                   FeatureLSLFast]
880                                   >;
881
882def TuneFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
883                                   "Qualcomm Falkor processors", [
884                                   FeatureCustomCheapAsMoveHandling,
885                                   FeaturePostRAScheduler,
886                                   FeaturePredictableSelectIsExpensive,
887                                   FeatureZCZeroing,
888                                   FeatureLSLFast,
889                                   FeatureSlowSTRQro
890                                   ]>;
891
892def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1",
893                                      "Neoverse E1 ARM processors", [
894                                      FeaturePostRAScheduler,
895                                      FeatureFuseAES
896                                      ]>;
897
898def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1",
899                                      "Neoverse N1 ARM processors", [
900                                      FeaturePostRAScheduler,
901                                      FeatureFuseAES
902                                      ]>;
903
904def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2",
905                                      "Neoverse N2 ARM processors", [
906                                      FeaturePostRAScheduler,
907                                      FeatureFuseAES
908                                      ]>;
909def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
910                                      "Neoverse 512-TVB ARM processors", [
911                                      FeaturePostRAScheduler,
912                                      FeatureFuseAES
913                                      ]>;
914
915def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1",
916                                      "Neoverse V1 ARM processors", [
917                                      FeatureFuseAES,
918                                      FeaturePostRAScheduler]>;
919
920def TuneSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
921                                   "Qualcomm Saphira processors", [
922                                   FeatureCustomCheapAsMoveHandling,
923                                   FeaturePostRAScheduler,
924                                   FeaturePredictableSelectIsExpensive,
925                                   FeatureZCZeroing,
926                                   FeatureLSLFast]>;
927
928def TuneThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99",
929                                         "Cavium ThunderX2 processors", [
930                                          FeatureAggressiveFMA,
931                                          FeatureArithmeticBccFusion,
932                                          FeaturePostRAScheduler,
933                                          FeaturePredictableSelectIsExpensive]>;
934
935def TuneThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
936                                          "ThunderX3T110",
937                                          "Marvell ThunderX3 processors", [
938                                           FeatureAggressiveFMA,
939                                           FeatureArithmeticBccFusion,
940                                           FeaturePostRAScheduler,
941                                           FeaturePredictableSelectIsExpensive,
942                                           FeatureBalanceFPOps,
943                                           FeatureStrictAlign]>;
944
945def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
946                                    "Cavium ThunderX processors", [
947                                    FeaturePostRAScheduler,
948                                    FeaturePredictableSelectIsExpensive]>;
949
950def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
951                                       "ThunderXT88",
952                                       "Cavium ThunderX processors", [
953                                       FeaturePostRAScheduler,
954                                       FeaturePredictableSelectIsExpensive]>;
955
956def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
957                                       "ThunderXT81",
958                                       "Cavium ThunderX processors", [
959                                       FeaturePostRAScheduler,
960                                       FeaturePredictableSelectIsExpensive]>;
961
962def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
963                                       "ThunderXT83",
964                                       "Cavium ThunderX processors", [
965                                       FeaturePostRAScheduler,
966                                       FeaturePredictableSelectIsExpensive]>;
967
968def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
969                                  "HiSilicon TS-V110 processors", [
970                                  FeatureCustomCheapAsMoveHandling,
971                                  FeatureFuseAES,
972                                  FeaturePostRAScheduler]>;
973
974def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
975                                   "Ampere Computing Ampere-1 processors", [
976                                   FeaturePostRAScheduler,
977                                   FeatureFuseAES,
978                                   FeatureLSLFast,
979                                   FeatureAggressiveFMA,
980                                   FeatureArithmeticBccFusion,
981                                   FeatureCmpBccFusion,
982                                   FeatureFuseAddress,
983                                   FeatureFuseLiterals]>;
984
985def ProcessorFeatures {
986  list<SubtargetFeature> A53  = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
987                                 FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
988  list<SubtargetFeature> A55  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
989                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
990                                 FeatureRCPC, FeaturePerfMon];
991  list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
992                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
993                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
994                                 FeatureFP16FML];
995  list<SubtargetFeature> A65  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
996                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
997                                 FeatureRCPC, FeatureSSBS, FeatureRAS,
998                                 FeaturePerfMon];
999  list<SubtargetFeature> A76  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1000                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1001                                 FeatureRCPC, FeatureSSBS, FeaturePerfMon];
1002  list<SubtargetFeature> A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1003                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1004                                 FeatureRCPC, FeaturePerfMon, FeatureSSBS];
1005  list<SubtargetFeature> A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1006                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1007                                 FeatureRCPC, FeaturePerfMon, FeatureSPE,
1008                                 FeatureSSBS];
1009  list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1010                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1011                                 FeatureFlagM, FeatureFP16FML, FeaturePAuth,
1012                                 FeaturePerfMon, FeatureRCPC, FeatureSPE,
1013                                 FeatureSSBS];
1014  list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
1015                                 FeatureETE, FeatureMTE, FeatureFP16FML,
1016                                 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8];
1017  list<SubtargetFeature> R82  = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
1018                                 FeatureFP16FML, FeatureSSBS, FeaturePredRes,
1019                                 FeatureSB];
1020  list<SubtargetFeature> X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1021                                 FeatureNEON, FeatureRCPC, FeaturePerfMon,
1022                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
1023                                 FeatureSSBS];
1024  list<SubtargetFeature> X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1025                                 FeatureNEON, FeatureRCPC, FeaturePerfMon,
1026                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
1027                                 FeaturePAuth, FeatureSSBS];
1028  list<SubtargetFeature> X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
1029                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
1030                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
1031                                 FeatureFP16FML];
1032  list<SubtargetFeature> A64FX    = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
1033                                     FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
1034                                     FeatureSVE, FeatureComplxNum];
1035  list<SubtargetFeature> Carmel   = [HasV8_2aOps, FeatureNEON, FeatureCrypto,
1036                                     FeatureFullFP16];
1037  list<SubtargetFeature> AppleA7  = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1038                                     FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg];
1039  list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1040                                     FeatureNEON, FeaturePerfMon, FeatureCRC,
1041                                     FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];
1042  list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1043                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1044  list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8,
1045                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1046  list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1047                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16,
1048                                     FeatureFP16FML, FeatureSHA3];
1049  list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1050                                     FeatureNEON, FeaturePerfMon, FeatureFRInt3264,
1051                                     FeatureSpecRestrict, FeatureSSBS, FeatureSB,
1052                                     FeaturePredRes, FeatureCacheDeepPersist,
1053                                     FeatureFullFP16, FeatureFP16FML, FeatureSHA3,
1054                                     FeatureAltFPCmp];
1055  list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1056                                     FeaturePerfMon];
1057  list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1058                                     FeatureFullFP16, FeaturePerfMon];
1059  list<SubtargetFeature> Falkor   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1060                                     FeatureFPARMv8, FeatureNEON, FeaturePerfMon,
1061                                     FeatureRDM];
1062  list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1063                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1064                                       FeatureRCPC, FeatureSSBS, FeaturePerfMon];
1065  list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1066                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1067                                       FeatureRCPC, FeatureSPE, FeatureSSBS,
1068                                       FeaturePerfMon];
1069  list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
1070                                       FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
1071                                       FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto,
1072                                       FeaturePerfMon];
1073  list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1074                                           FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1075                                           FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1076                                           FeaturePerfMon, FeatureRandGen, FeatureSPE,
1077                                           FeatureSSBS, FeatureSVE];
1078  list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1079                                       FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1080                                       FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1081                                       FeaturePerfMon, FeatureRandGen, FeatureSPE,
1082                                       FeatureSSBS, FeatureSVE];
1083  list<SubtargetFeature> Saphira    = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1084                                       FeatureNEON, FeatureSPE, FeaturePerfMon];
1085  list<SubtargetFeature> ThunderX   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1086                                       FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
1087  list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
1088                                          FeatureFPARMv8, FeatureNEON, FeatureLSE];
1089  list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
1090                                          FeatureFPARMv8, FeatureNEON, FeatureLSE,
1091                                          FeaturePAuth, FeaturePerfMon];
1092  list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1093                                   FeatureNEON, FeaturePerfMon, FeatureSPE,
1094                                   FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
1095  list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
1096                                    FeatureMTE, FeatureSSBS];
1097
1098  // ETE and TRBE are future architecture extensions. We temporarily enable them
1099  // by default for users targeting generic AArch64. The extensions do not
1100  // affect code generated by the compiler and can be used only by explicitly
1101  // mentioning the new system register names in assembly.
1102  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
1103}
1104
1105// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
1106// optimizations.
1107def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
1108                     [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler]>;
1109def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
1110                     [TuneA35]>;
1111def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
1112                     [TuneA35]>;
1113def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
1114                     [TuneA53]>;
1115def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
1116                     [TuneA55]>;
1117def : ProcessorModel<"cortex-a510", CortexA55Model, ProcessorFeatures.A510,
1118                     [TuneA510]>;
1119def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53,
1120                     [TuneA57]>;
1121def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65,
1122                     [TuneA65]>;
1123def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65,
1124                     [TuneA65]>;
1125def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53,
1126                     [TuneA72]>;
1127def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53,
1128                     [TuneA73]>;
1129def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55,
1130                     [TuneA75]>;
1131def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76,
1132                     [TuneA76]>;
1133def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
1134                     [TuneA76]>;
1135def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
1136                     [TuneA77]>;
1137def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
1138                     [TuneA78]>;
1139def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
1140                     [TuneA78C]>;
1141def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710,
1142                     [TuneA710]>;
1143def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
1144                     [TuneR82]>;
1145def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
1146                     [TuneX1]>;
1147def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
1148                     [TuneX1]>;
1149def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2,
1150                     [TuneX2]>;
1151def : ProcessorModel<"neoverse-e1", CortexA53Model,
1152                     ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
1153def : ProcessorModel<"neoverse-n1", CortexA57Model,
1154                     ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
1155def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
1156                     ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
1157def : ProcessorModel<"neoverse-512tvb", NeoverseN2Model,
1158                     ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
1159def : ProcessorModel<"neoverse-v1", NeoverseN2Model,
1160                     ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
1161def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
1162                     [TuneExynosM3]>;
1163def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
1164                     [TuneExynosM4]>;
1165def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4,
1166                     [TuneExynosM4]>;
1167def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor,
1168                     [TuneFalkor]>;
1169def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira,
1170                     [TuneSaphira]>;
1171def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>;
1172
1173// Cavium ThunderX/ThunderX T8X  Processors
1174def : ProcessorModel<"thunderx", ThunderXT8XModel,  ProcessorFeatures.ThunderX,
1175                     [TuneThunderX]>;
1176def : ProcessorModel<"thunderxt88", ThunderXT8XModel,
1177                     ProcessorFeatures.ThunderX, [TuneThunderXT88]>;
1178def : ProcessorModel<"thunderxt81", ThunderXT8XModel,
1179                     ProcessorFeatures.ThunderX, [TuneThunderXT81]>;
1180def : ProcessorModel<"thunderxt83", ThunderXT8XModel,
1181                     ProcessorFeatures.ThunderX, [TuneThunderXT83]>;
1182// Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1183def : ProcessorModel<"thunderx2t99", ThunderX2T99Model,
1184                     ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>;
1185// Marvell ThunderX3T110 Processors.
1186def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
1187                     ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>;
1188def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
1189                     [TuneTSV110]>;
1190
1191// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1192def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
1193                     [TuneAppleA7]>;
1194
1195// iPhone and iPad CPUs
1196def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
1197                     [TuneAppleA7]>;
1198def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
1199                     [TuneAppleA7]>;
1200def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
1201                     [TuneAppleA7]>;
1202def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
1203                     [TuneAppleA10]>;
1204def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,
1205                     [TuneAppleA11]>;
1206def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
1207                     [TuneAppleA12]>;
1208def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
1209                     [TuneAppleA13]>;
1210def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
1211                     [TuneAppleA14]>;
1212
1213// Mac CPUs
1214def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
1215                     [TuneAppleA14]>;
1216
1217// watch CPUs.
1218def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
1219                     [TuneAppleA12]>;
1220def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
1221                     [TuneAppleA12]>;
1222
1223// Alias for the latest Apple processor model supported by LLVM.
1224def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA14,
1225                     [TuneAppleA14]>;
1226
1227// Fujitsu A64FX
1228def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX,
1229                     [TuneA64FX]>;
1230
1231// Nvidia Carmel
1232def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
1233                     [TuneCarmel]>;
1234
1235// Ampere Computing
1236def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
1237                     [TuneAmpere1]>;
1238
1239//===----------------------------------------------------------------------===//
1240// Assembly parser
1241//===----------------------------------------------------------------------===//
1242
1243def GenericAsmParserVariant : AsmParserVariant {
1244  int Variant = 0;
1245  string Name = "generic";
1246  string BreakCharacters = ".";
1247  string TokenizingCharacters = "[]*!/";
1248}
1249
1250def AppleAsmParserVariant : AsmParserVariant {
1251  int Variant = 1;
1252  string Name = "apple-neon";
1253  string BreakCharacters = ".";
1254  string TokenizingCharacters = "[]*!/";
1255}
1256
1257//===----------------------------------------------------------------------===//
1258// Assembly printer
1259//===----------------------------------------------------------------------===//
1260// AArch64 Uses the MC printer for asm output, so make sure the TableGen
1261// AsmWriter bits get associated with the correct class.
1262def GenericAsmWriter : AsmWriter {
1263  string AsmWriterClassName  = "InstPrinter";
1264  int PassSubtarget = 1;
1265  int Variant = 0;
1266  bit isMCAsmWriter = 1;
1267}
1268
1269def AppleAsmWriter : AsmWriter {
1270  let AsmWriterClassName = "AppleInstPrinter";
1271  int PassSubtarget = 1;
1272  int Variant = 1;
1273  int isMCAsmWriter = 1;
1274}
1275
1276//===----------------------------------------------------------------------===//
1277// Target Declaration
1278//===----------------------------------------------------------------------===//
1279
1280def AArch64 : Target {
1281  let InstructionSet = AArch64InstrInfo;
1282  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1283  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1284  let AllowRegisterRenaming = 1;
1285}
1286
1287//===----------------------------------------------------------------------===//
1288// Pfm Counters
1289//===----------------------------------------------------------------------===//
1290
1291include "AArch64PfmCounters.td"
1292