10b57cec5SDimitry Andric //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the interfaces that AArch64 uses to lower LLVM code into a 100b57cec5SDimitry Andric // selection DAG. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "AArch64.h" 18bdd1243dSDimitry Andric #include "Utils/AArch64SMEAttributes.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/CallingConvLower.h" 20fe6060f1SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/SelectionDAG.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 230b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h" 240b57cec5SDimitry Andric #include "llvm/IR/Instruction.h" 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric namespace llvm { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric namespace AArch64ISD { 290b57cec5SDimitry Andric 305ffd83dbSDimitry Andric // For predicated nodes where the result is a vector, the operation is 315ffd83dbSDimitry Andric // controlled by a governing predicate and the inactive lanes are explicitly 325ffd83dbSDimitry Andric // defined with a value, please stick the following naming convention: 335ffd83dbSDimitry Andric // 345ffd83dbSDimitry Andric // _MERGE_OP<n> The result value is a vector with inactive lanes equal 355ffd83dbSDimitry Andric // to source operand OP<n>. 365ffd83dbSDimitry Andric // 375ffd83dbSDimitry Andric // _MERGE_ZERO The result value is a vector with inactive lanes 385ffd83dbSDimitry Andric // actively zeroed. 395ffd83dbSDimitry Andric // 405ffd83dbSDimitry Andric // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal 415ffd83dbSDimitry Andric // to the last source operand which only purpose is being 425ffd83dbSDimitry Andric // a passthru value. 435ffd83dbSDimitry Andric // 445ffd83dbSDimitry Andric // For other cases where no explicit action is needed to set the inactive lanes, 455ffd83dbSDimitry Andric // or when the result is not a vector and it is needed or helpful to 465ffd83dbSDimitry Andric // distinguish a node from similar unpredicated nodes, use: 475ffd83dbSDimitry Andric // 485ffd83dbSDimitry Andric // _PRED 495ffd83dbSDimitry Andric // 500b57cec5SDimitry Andric enum NodeType : unsigned { 510b57cec5SDimitry Andric FIRST_NUMBER = ISD::BUILTIN_OP_END, 520b57cec5SDimitry Andric WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 530b57cec5SDimitry Andric CALL, // Function call. 540b57cec5SDimitry Andric 55fe6060f1SDimitry Andric // Pseudo for a OBJC call that gets emitted together with a special `mov 56fe6060f1SDimitry Andric // x29, x29` marker instruction. 57fe6060f1SDimitry Andric CALL_RVMARKER, 58fe6060f1SDimitry Andric 593a9a9c0cSDimitry Andric CALL_BTI, // Function call followed by a BTI instruction. 603a9a9c0cSDimitry Andric 61b3edf446SDimitry Andric COALESCER_BARRIER, 62b3edf446SDimitry Andric 63bdd1243dSDimitry Andric SMSTART, 64bdd1243dSDimitry Andric SMSTOP, 65bdd1243dSDimitry Andric RESTORE_ZA, 667a6dacacSDimitry Andric RESTORE_ZT, 677a6dacacSDimitry Andric SAVE_ZT, 687a6dacacSDimitry Andric 697a6dacacSDimitry Andric // A call with the callee in x16, i.e. "blr x16". 707a6dacacSDimitry Andric CALL_ARM64EC_TO_X64, 71bdd1243dSDimitry Andric 720b57cec5SDimitry Andric // Produces the full sequence of instructions for getting the thread pointer 730b57cec5SDimitry Andric // offset of a variable into X0, using the TLSDesc model. 740b57cec5SDimitry Andric TLSDESC_CALLSEQ, 750b57cec5SDimitry Andric ADRP, // Page address of a TargetGlobalAddress operand. 760b57cec5SDimitry Andric ADR, // ADR 770b57cec5SDimitry Andric ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 780b57cec5SDimitry Andric LOADgot, // Load from automatically generated descriptor (e.g. Global 790b57cec5SDimitry Andric // Offset Table, TLS record). 8006c3fb27SDimitry Andric RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand. 810b57cec5SDimitry Andric BRCOND, // Conditional branch instruction; "b.cond". 820b57cec5SDimitry Andric CSEL, 830b57cec5SDimitry Andric CSINV, // Conditional select invert. 840b57cec5SDimitry Andric CSNEG, // Conditional select negate. 850b57cec5SDimitry Andric CSINC, // Conditional select increment. 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 880b57cec5SDimitry Andric // ELF. 890b57cec5SDimitry Andric THREAD_POINTER, 900b57cec5SDimitry Andric ADC, 910b57cec5SDimitry Andric SBC, // adc, sbc instructions 920b57cec5SDimitry Andric 935f757f3fSDimitry Andric // To avoid stack clash, allocation is performed by block and each block is 945f757f3fSDimitry Andric // probed. 955f757f3fSDimitry Andric PROBED_ALLOCA, 965f757f3fSDimitry Andric 97e8d8bef9SDimitry Andric // Predicated instructions where inactive lanes produce undefined results. 9804eeddc0SDimitry Andric ABDS_PRED, 9904eeddc0SDimitry Andric ABDU_PRED, 1005ffd83dbSDimitry Andric FADD_PRED, 101e8d8bef9SDimitry Andric FDIV_PRED, 1025ffd83dbSDimitry Andric FMA_PRED, 103fe6060f1SDimitry Andric FMAX_PRED, 10404eeddc0SDimitry Andric FMAXNM_PRED, 105fe6060f1SDimitry Andric FMIN_PRED, 10604eeddc0SDimitry Andric FMINNM_PRED, 107e8d8bef9SDimitry Andric FMUL_PRED, 108e8d8bef9SDimitry Andric FSUB_PRED, 109bdd1243dSDimitry Andric HADDS_PRED, 110bdd1243dSDimitry Andric HADDU_PRED, 111e8d8bef9SDimitry Andric MUL_PRED, 112fe6060f1SDimitry Andric MULHS_PRED, 113fe6060f1SDimitry Andric MULHU_PRED, 114bdd1243dSDimitry Andric RHADDS_PRED, 115bdd1243dSDimitry Andric RHADDU_PRED, 116e8d8bef9SDimitry Andric SDIV_PRED, 117e8d8bef9SDimitry Andric SHL_PRED, 118e8d8bef9SDimitry Andric SMAX_PRED, 119e8d8bef9SDimitry Andric SMIN_PRED, 120e8d8bef9SDimitry Andric SRA_PRED, 121e8d8bef9SDimitry Andric SRL_PRED, 122e8d8bef9SDimitry Andric UDIV_PRED, 123e8d8bef9SDimitry Andric UMAX_PRED, 124e8d8bef9SDimitry Andric UMIN_PRED, 125e8d8bef9SDimitry Andric 126fe6060f1SDimitry Andric // Unpredicated vector instructions 127fe6060f1SDimitry Andric BIC, 128fe6060f1SDimitry Andric 1294824e7fdSDimitry Andric SRAD_MERGE_OP1, 1304824e7fdSDimitry Andric 131e8d8bef9SDimitry Andric // Predicated instructions with the result of inactive lanes provided by the 132e8d8bef9SDimitry Andric // last operand. 133e8d8bef9SDimitry Andric FABS_MERGE_PASSTHRU, 134e8d8bef9SDimitry Andric FCEIL_MERGE_PASSTHRU, 135e8d8bef9SDimitry Andric FFLOOR_MERGE_PASSTHRU, 136e8d8bef9SDimitry Andric FNEARBYINT_MERGE_PASSTHRU, 137e8d8bef9SDimitry Andric FNEG_MERGE_PASSTHRU, 138e8d8bef9SDimitry Andric FRECPX_MERGE_PASSTHRU, 139e8d8bef9SDimitry Andric FRINT_MERGE_PASSTHRU, 140e8d8bef9SDimitry Andric FROUND_MERGE_PASSTHRU, 141e8d8bef9SDimitry Andric FROUNDEVEN_MERGE_PASSTHRU, 142e8d8bef9SDimitry Andric FSQRT_MERGE_PASSTHRU, 143e8d8bef9SDimitry Andric FTRUNC_MERGE_PASSTHRU, 144e8d8bef9SDimitry Andric FP_ROUND_MERGE_PASSTHRU, 145e8d8bef9SDimitry Andric FP_EXTEND_MERGE_PASSTHRU, 146e8d8bef9SDimitry Andric UINT_TO_FP_MERGE_PASSTHRU, 147e8d8bef9SDimitry Andric SINT_TO_FP_MERGE_PASSTHRU, 148e8d8bef9SDimitry Andric FCVTZU_MERGE_PASSTHRU, 149e8d8bef9SDimitry Andric FCVTZS_MERGE_PASSTHRU, 150e8d8bef9SDimitry Andric SIGN_EXTEND_INREG_MERGE_PASSTHRU, 151e8d8bef9SDimitry Andric ZERO_EXTEND_INREG_MERGE_PASSTHRU, 152e8d8bef9SDimitry Andric ABS_MERGE_PASSTHRU, 153e8d8bef9SDimitry Andric NEG_MERGE_PASSTHRU, 1545ffd83dbSDimitry Andric 1555ffd83dbSDimitry Andric SETCC_MERGE_ZERO, 1565ffd83dbSDimitry Andric 1570b57cec5SDimitry Andric // Arithmetic instructions which write flags. 1580b57cec5SDimitry Andric ADDS, 1590b57cec5SDimitry Andric SUBS, 1600b57cec5SDimitry Andric ADCS, 1610b57cec5SDimitry Andric SBCS, 1620b57cec5SDimitry Andric ANDS, 1630b57cec5SDimitry Andric 1640b57cec5SDimitry Andric // Conditional compares. Operands: left,right,falsecc,cc,flags 1650b57cec5SDimitry Andric CCMP, 1660b57cec5SDimitry Andric CCMN, 1670b57cec5SDimitry Andric FCCMP, 1680b57cec5SDimitry Andric 1690b57cec5SDimitry Andric // Floating point comparison 1700b57cec5SDimitry Andric FCMP, 1710b57cec5SDimitry Andric 1720b57cec5SDimitry Andric // Scalar-to-vector duplication 1730b57cec5SDimitry Andric DUP, 1740b57cec5SDimitry Andric DUPLANE8, 1750b57cec5SDimitry Andric DUPLANE16, 1760b57cec5SDimitry Andric DUPLANE32, 1770b57cec5SDimitry Andric DUPLANE64, 17881ad6265SDimitry Andric DUPLANE128, 1790b57cec5SDimitry Andric 1800b57cec5SDimitry Andric // Vector immedate moves 1810b57cec5SDimitry Andric MOVI, 1820b57cec5SDimitry Andric MOVIshift, 1830b57cec5SDimitry Andric MOVIedit, 1840b57cec5SDimitry Andric MOVImsl, 1850b57cec5SDimitry Andric FMOV, 1860b57cec5SDimitry Andric MVNIshift, 1870b57cec5SDimitry Andric MVNImsl, 1880b57cec5SDimitry Andric 1890b57cec5SDimitry Andric // Vector immediate ops 1900b57cec5SDimitry Andric BICi, 1910b57cec5SDimitry Andric ORRi, 1920b57cec5SDimitry Andric 1935ffd83dbSDimitry Andric // Vector bitwise select: similar to ISD::VSELECT but not all bits within an 1940b57cec5SDimitry Andric // element must be identical. 1955ffd83dbSDimitry Andric BSP, 1960b57cec5SDimitry Andric 1970b57cec5SDimitry Andric // Vector shuffles 1980b57cec5SDimitry Andric ZIP1, 1990b57cec5SDimitry Andric ZIP2, 2000b57cec5SDimitry Andric UZP1, 2010b57cec5SDimitry Andric UZP2, 2020b57cec5SDimitry Andric TRN1, 2030b57cec5SDimitry Andric TRN2, 2040b57cec5SDimitry Andric REV16, 2050b57cec5SDimitry Andric REV32, 2060b57cec5SDimitry Andric REV64, 2070b57cec5SDimitry Andric EXT, 208fe6060f1SDimitry Andric SPLICE, 2090b57cec5SDimitry Andric 2100b57cec5SDimitry Andric // Vector shift by scalar 2110b57cec5SDimitry Andric VSHL, 2120b57cec5SDimitry Andric VLSHR, 2130b57cec5SDimitry Andric VASHR, 2140b57cec5SDimitry Andric 2150b57cec5SDimitry Andric // Vector shift by scalar (again) 2160b57cec5SDimitry Andric SQSHL_I, 2170b57cec5SDimitry Andric UQSHL_I, 2180b57cec5SDimitry Andric SQSHLU_I, 2190b57cec5SDimitry Andric SRSHR_I, 2200b57cec5SDimitry Andric URSHR_I, 2210b57cec5SDimitry Andric 2225f757f3fSDimitry Andric // Vector narrowing shift by immediate (bottom) 2235f757f3fSDimitry Andric RSHRNB_I, 2245f757f3fSDimitry Andric 2255ffd83dbSDimitry Andric // Vector shift by constant and insert 2265ffd83dbSDimitry Andric VSLI, 2275ffd83dbSDimitry Andric VSRI, 2285ffd83dbSDimitry Andric 2290b57cec5SDimitry Andric // Vector comparisons 2300b57cec5SDimitry Andric CMEQ, 2310b57cec5SDimitry Andric CMGE, 2320b57cec5SDimitry Andric CMGT, 2330b57cec5SDimitry Andric CMHI, 2340b57cec5SDimitry Andric CMHS, 2350b57cec5SDimitry Andric FCMEQ, 2360b57cec5SDimitry Andric FCMGE, 2370b57cec5SDimitry Andric FCMGT, 2380b57cec5SDimitry Andric 2390b57cec5SDimitry Andric // Vector zero comparisons 2400b57cec5SDimitry Andric CMEQz, 2410b57cec5SDimitry Andric CMGEz, 2420b57cec5SDimitry Andric CMGTz, 2430b57cec5SDimitry Andric CMLEz, 2440b57cec5SDimitry Andric CMLTz, 2450b57cec5SDimitry Andric FCMEQz, 2460b57cec5SDimitry Andric FCMGEz, 2470b57cec5SDimitry Andric FCMGTz, 2480b57cec5SDimitry Andric FCMLEz, 2490b57cec5SDimitry Andric FCMLTz, 2500b57cec5SDimitry Andric 2510b57cec5SDimitry Andric // Vector across-lanes addition 2520b57cec5SDimitry Andric // Only the lower result lane is defined. 2530b57cec5SDimitry Andric SADDV, 2540b57cec5SDimitry Andric UADDV, 2550b57cec5SDimitry Andric 2565f757f3fSDimitry Andric // Unsigned sum Long across Vector 2575f757f3fSDimitry Andric UADDLV, 2587a6dacacSDimitry Andric SADDLV, 2595f757f3fSDimitry Andric 26081ad6265SDimitry Andric // Add Pairwise of two vectors 26181ad6265SDimitry Andric ADDP, 26281ad6265SDimitry Andric // Add Long Pairwise 26381ad6265SDimitry Andric SADDLP, 264fe6060f1SDimitry Andric UADDLP, 265fe6060f1SDimitry Andric 266fe6060f1SDimitry Andric // udot/sdot instructions 267fe6060f1SDimitry Andric UDOT, 268fe6060f1SDimitry Andric SDOT, 269e8d8bef9SDimitry Andric 2700b57cec5SDimitry Andric // Vector across-lanes min/max 2710b57cec5SDimitry Andric // Only the lower result lane is defined. 2720b57cec5SDimitry Andric SMINV, 2730b57cec5SDimitry Andric UMINV, 2740b57cec5SDimitry Andric SMAXV, 2750b57cec5SDimitry Andric UMAXV, 2760b57cec5SDimitry Andric 277e8d8bef9SDimitry Andric SADDV_PRED, 278e8d8bef9SDimitry Andric UADDV_PRED, 279480093f4SDimitry Andric SMAXV_PRED, 280480093f4SDimitry Andric UMAXV_PRED, 281480093f4SDimitry Andric SMINV_PRED, 282480093f4SDimitry Andric UMINV_PRED, 283480093f4SDimitry Andric ORV_PRED, 284480093f4SDimitry Andric EORV_PRED, 285480093f4SDimitry Andric ANDV_PRED, 286480093f4SDimitry Andric 2875ffd83dbSDimitry Andric // Vector bitwise insertion 2880b57cec5SDimitry Andric BIT, 2890b57cec5SDimitry Andric 2900b57cec5SDimitry Andric // Compare-and-branch 2910b57cec5SDimitry Andric CBZ, 2920b57cec5SDimitry Andric CBNZ, 2930b57cec5SDimitry Andric TBZ, 2940b57cec5SDimitry Andric TBNZ, 2950b57cec5SDimitry Andric 2960b57cec5SDimitry Andric // Tail calls 2970b57cec5SDimitry Andric TC_RETURN, 2980b57cec5SDimitry Andric 2990b57cec5SDimitry Andric // Custom prefetch handling 3000b57cec5SDimitry Andric PREFETCH, 3010b57cec5SDimitry Andric 3020b57cec5SDimitry Andric // {s|u}int to FP within a FP register. 3030b57cec5SDimitry Andric SITOF, 3040b57cec5SDimitry Andric UITOF, 3050b57cec5SDimitry Andric 3060b57cec5SDimitry Andric /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 3070b57cec5SDimitry Andric /// world w.r.t vectors; which causes additional REV instructions to be 3080b57cec5SDimitry Andric /// generated to compensate for the byte-swapping. But sometimes we do 3090b57cec5SDimitry Andric /// need to re-interpret the data in SIMD vector registers in big-endian 3100b57cec5SDimitry Andric /// mode without emitting such REV instructions. 3110b57cec5SDimitry Andric NVCAST, 3120b57cec5SDimitry Andric 313fe6060f1SDimitry Andric MRS, // MRS, also sets the flags via a glue. 314fe6060f1SDimitry Andric 3150b57cec5SDimitry Andric SMULL, 3160b57cec5SDimitry Andric UMULL, 3170b57cec5SDimitry Andric 318bdd1243dSDimitry Andric PMULL, 319bdd1243dSDimitry Andric 3200b57cec5SDimitry Andric // Reciprocal estimates and steps. 3215ffd83dbSDimitry Andric FRECPE, 3225ffd83dbSDimitry Andric FRECPS, 3235ffd83dbSDimitry Andric FRSQRTE, 3245ffd83dbSDimitry Andric FRSQRTS, 3250b57cec5SDimitry Andric 3268bcb0991SDimitry Andric SUNPKHI, 3278bcb0991SDimitry Andric SUNPKLO, 3288bcb0991SDimitry Andric UUNPKHI, 3298bcb0991SDimitry Andric UUNPKLO, 3308bcb0991SDimitry Andric 331480093f4SDimitry Andric CLASTA_N, 332480093f4SDimitry Andric CLASTB_N, 333480093f4SDimitry Andric LASTA, 334480093f4SDimitry Andric LASTB, 335480093f4SDimitry Andric TBL, 336480093f4SDimitry Andric 3375ffd83dbSDimitry Andric // Floating-point reductions. 3385ffd83dbSDimitry Andric FADDA_PRED, 3395ffd83dbSDimitry Andric FADDV_PRED, 3405ffd83dbSDimitry Andric FMAXV_PRED, 3415ffd83dbSDimitry Andric FMAXNMV_PRED, 3425ffd83dbSDimitry Andric FMINV_PRED, 3435ffd83dbSDimitry Andric FMINNMV_PRED, 3445ffd83dbSDimitry Andric 345480093f4SDimitry Andric INSR, 346480093f4SDimitry Andric PTEST, 347bdd1243dSDimitry Andric PTEST_ANY, 348480093f4SDimitry Andric PTRUE, 349480093f4SDimitry Andric 3505f757f3fSDimitry Andric CTTZ_ELTS, 3515f757f3fSDimitry Andric 352e8d8bef9SDimitry Andric BITREVERSE_MERGE_PASSTHRU, 353e8d8bef9SDimitry Andric BSWAP_MERGE_PASSTHRU, 3540eae32dcSDimitry Andric REVH_MERGE_PASSTHRU, 3550eae32dcSDimitry Andric REVW_MERGE_PASSTHRU, 356e8d8bef9SDimitry Andric CTLZ_MERGE_PASSTHRU, 357e8d8bef9SDimitry Andric CTPOP_MERGE_PASSTHRU, 3585ffd83dbSDimitry Andric DUP_MERGE_PASSTHRU, 3595ffd83dbSDimitry Andric INDEX_VECTOR, 3605ffd83dbSDimitry Andric 361e8d8bef9SDimitry Andric // Cast between vectors of the same element type but differ in length. 3625ffd83dbSDimitry Andric REINTERPRET_CAST, 3635ffd83dbSDimitry Andric 3646e75b2fbSDimitry Andric // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa 3656e75b2fbSDimitry Andric LS64_BUILD, 3666e75b2fbSDimitry Andric LS64_EXTRACT, 3676e75b2fbSDimitry Andric 3685ffd83dbSDimitry Andric LD1_MERGE_ZERO, 3695ffd83dbSDimitry Andric LD1S_MERGE_ZERO, 3705ffd83dbSDimitry Andric LDNF1_MERGE_ZERO, 3715ffd83dbSDimitry Andric LDNF1S_MERGE_ZERO, 3725ffd83dbSDimitry Andric LDFF1_MERGE_ZERO, 3735ffd83dbSDimitry Andric LDFF1S_MERGE_ZERO, 3745ffd83dbSDimitry Andric LD1RQ_MERGE_ZERO, 3755ffd83dbSDimitry Andric LD1RO_MERGE_ZERO, 3765ffd83dbSDimitry Andric 3775ffd83dbSDimitry Andric // Structured loads. 3785ffd83dbSDimitry Andric SVE_LD2_MERGE_ZERO, 3795ffd83dbSDimitry Andric SVE_LD3_MERGE_ZERO, 3805ffd83dbSDimitry Andric SVE_LD4_MERGE_ZERO, 3815ffd83dbSDimitry Andric 382480093f4SDimitry Andric // Unsigned gather loads. 3835ffd83dbSDimitry Andric GLD1_MERGE_ZERO, 3845ffd83dbSDimitry Andric GLD1_SCALED_MERGE_ZERO, 3855ffd83dbSDimitry Andric GLD1_UXTW_MERGE_ZERO, 3865ffd83dbSDimitry Andric GLD1_SXTW_MERGE_ZERO, 3875ffd83dbSDimitry Andric GLD1_UXTW_SCALED_MERGE_ZERO, 3885ffd83dbSDimitry Andric GLD1_SXTW_SCALED_MERGE_ZERO, 3895ffd83dbSDimitry Andric GLD1_IMM_MERGE_ZERO, 3905f757f3fSDimitry Andric GLD1Q_MERGE_ZERO, 3915f757f3fSDimitry Andric GLD1Q_INDEX_MERGE_ZERO, 392480093f4SDimitry Andric 393480093f4SDimitry Andric // Signed gather loads 3945ffd83dbSDimitry Andric GLD1S_MERGE_ZERO, 3955ffd83dbSDimitry Andric GLD1S_SCALED_MERGE_ZERO, 3965ffd83dbSDimitry Andric GLD1S_UXTW_MERGE_ZERO, 3975ffd83dbSDimitry Andric GLD1S_SXTW_MERGE_ZERO, 3985ffd83dbSDimitry Andric GLD1S_UXTW_SCALED_MERGE_ZERO, 3995ffd83dbSDimitry Andric GLD1S_SXTW_SCALED_MERGE_ZERO, 4005ffd83dbSDimitry Andric GLD1S_IMM_MERGE_ZERO, 4015ffd83dbSDimitry Andric 4025ffd83dbSDimitry Andric // Unsigned gather loads. 4035ffd83dbSDimitry Andric GLDFF1_MERGE_ZERO, 4045ffd83dbSDimitry Andric GLDFF1_SCALED_MERGE_ZERO, 4055ffd83dbSDimitry Andric GLDFF1_UXTW_MERGE_ZERO, 4065ffd83dbSDimitry Andric GLDFF1_SXTW_MERGE_ZERO, 4075ffd83dbSDimitry Andric GLDFF1_UXTW_SCALED_MERGE_ZERO, 4085ffd83dbSDimitry Andric GLDFF1_SXTW_SCALED_MERGE_ZERO, 4095ffd83dbSDimitry Andric GLDFF1_IMM_MERGE_ZERO, 4105ffd83dbSDimitry Andric 4115ffd83dbSDimitry Andric // Signed gather loads. 4125ffd83dbSDimitry Andric GLDFF1S_MERGE_ZERO, 4135ffd83dbSDimitry Andric GLDFF1S_SCALED_MERGE_ZERO, 4145ffd83dbSDimitry Andric GLDFF1S_UXTW_MERGE_ZERO, 4155ffd83dbSDimitry Andric GLDFF1S_SXTW_MERGE_ZERO, 4165ffd83dbSDimitry Andric GLDFF1S_UXTW_SCALED_MERGE_ZERO, 4175ffd83dbSDimitry Andric GLDFF1S_SXTW_SCALED_MERGE_ZERO, 4185ffd83dbSDimitry Andric GLDFF1S_IMM_MERGE_ZERO, 4195ffd83dbSDimitry Andric 4205ffd83dbSDimitry Andric // Non-temporal gather loads 4215ffd83dbSDimitry Andric GLDNT1_MERGE_ZERO, 4225ffd83dbSDimitry Andric GLDNT1_INDEX_MERGE_ZERO, 4235ffd83dbSDimitry Andric GLDNT1S_MERGE_ZERO, 4245ffd83dbSDimitry Andric 4255ffd83dbSDimitry Andric // Contiguous masked store. 4265ffd83dbSDimitry Andric ST1_PRED, 4275ffd83dbSDimitry Andric 428480093f4SDimitry Andric // Scatter store 4295ffd83dbSDimitry Andric SST1_PRED, 4305ffd83dbSDimitry Andric SST1_SCALED_PRED, 4315ffd83dbSDimitry Andric SST1_UXTW_PRED, 4325ffd83dbSDimitry Andric SST1_SXTW_PRED, 4335ffd83dbSDimitry Andric SST1_UXTW_SCALED_PRED, 4345ffd83dbSDimitry Andric SST1_SXTW_SCALED_PRED, 4355ffd83dbSDimitry Andric SST1_IMM_PRED, 4365f757f3fSDimitry Andric SST1Q_PRED, 4375f757f3fSDimitry Andric SST1Q_INDEX_PRED, 4385ffd83dbSDimitry Andric 4395ffd83dbSDimitry Andric // Non-temporal scatter store 4405ffd83dbSDimitry Andric SSTNT1_PRED, 4415ffd83dbSDimitry Andric SSTNT1_INDEX_PRED, 442480093f4SDimitry Andric 44381ad6265SDimitry Andric // SME 44481ad6265SDimitry Andric RDSVL, 44581ad6265SDimitry Andric REVD_MERGE_PASSTHRU, 44681ad6265SDimitry Andric 447349cc55cSDimitry Andric // Asserts that a function argument (i32) is zero-extended to i8 by 448349cc55cSDimitry Andric // the caller 449349cc55cSDimitry Andric ASSERT_ZEXT_BOOL, 450349cc55cSDimitry Andric 451bdd1243dSDimitry Andric // 128-bit system register accesses 452bdd1243dSDimitry Andric // lo64, hi64, chain = MRRS(chain, sysregname) 453bdd1243dSDimitry Andric MRRS, 454bdd1243dSDimitry Andric // chain = MSRR(chain, sysregname, lo64, hi64) 455bdd1243dSDimitry Andric MSRR, 456bdd1243dSDimitry Andric 45747395794SDimitry Andric // Strict (exception-raising) floating point comparison 45847395794SDimitry Andric STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 45947395794SDimitry Andric STRICT_FCMPE, 46047395794SDimitry Andric 4615f757f3fSDimitry Andric // SME ZA loads and stores 4625f757f3fSDimitry Andric SME_ZA_LDR, 4635f757f3fSDimitry Andric SME_ZA_STR, 4645f757f3fSDimitry Andric 4650b57cec5SDimitry Andric // NEON Load/Store with post-increment base updates 4660b57cec5SDimitry Andric LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 4670b57cec5SDimitry Andric LD3post, 4680b57cec5SDimitry Andric LD4post, 4690b57cec5SDimitry Andric ST2post, 4700b57cec5SDimitry Andric ST3post, 4710b57cec5SDimitry Andric ST4post, 4720b57cec5SDimitry Andric LD1x2post, 4730b57cec5SDimitry Andric LD1x3post, 4740b57cec5SDimitry Andric LD1x4post, 4750b57cec5SDimitry Andric ST1x2post, 4760b57cec5SDimitry Andric ST1x3post, 4770b57cec5SDimitry Andric ST1x4post, 4780b57cec5SDimitry Andric LD1DUPpost, 4790b57cec5SDimitry Andric LD2DUPpost, 4800b57cec5SDimitry Andric LD3DUPpost, 4810b57cec5SDimitry Andric LD4DUPpost, 4820b57cec5SDimitry Andric LD1LANEpost, 4830b57cec5SDimitry Andric LD2LANEpost, 4840b57cec5SDimitry Andric LD3LANEpost, 4850b57cec5SDimitry Andric LD4LANEpost, 4860b57cec5SDimitry Andric ST2LANEpost, 4870b57cec5SDimitry Andric ST3LANEpost, 4880b57cec5SDimitry Andric ST4LANEpost, 4890b57cec5SDimitry Andric 4900b57cec5SDimitry Andric STG, 4910b57cec5SDimitry Andric STZG, 4920b57cec5SDimitry Andric ST2G, 493480093f4SDimitry Andric STZ2G, 4940b57cec5SDimitry Andric 495480093f4SDimitry Andric LDP, 49606c3fb27SDimitry Andric LDIAPP, 497bdd1243dSDimitry Andric LDNP, 4985ffd83dbSDimitry Andric STP, 49906c3fb27SDimitry Andric STILP, 500e8d8bef9SDimitry Andric STNP, 5011fd87a68SDimitry Andric 5021fd87a68SDimitry Andric // Memory Operations 5031fd87a68SDimitry Andric MOPS_MEMSET, 5041fd87a68SDimitry Andric MOPS_MEMSET_TAGGING, 5051fd87a68SDimitry Andric MOPS_MEMCOPY, 5061fd87a68SDimitry Andric MOPS_MEMMOVE, 5070b57cec5SDimitry Andric }; 5080b57cec5SDimitry Andric 5090b57cec5SDimitry Andric } // end namespace AArch64ISD 5100b57cec5SDimitry Andric 511fe6060f1SDimitry Andric namespace AArch64 { 512fe6060f1SDimitry Andric /// Possible values of current rounding mode, which is specified in bits 513fe6060f1SDimitry Andric /// 23:22 of FPCR. 514fe6060f1SDimitry Andric enum Rounding { 515fe6060f1SDimitry Andric RN = 0, // Round to Nearest 516fe6060f1SDimitry Andric RP = 1, // Round towards Plus infinity 517fe6060f1SDimitry Andric RM = 2, // Round towards Minus infinity 518fe6060f1SDimitry Andric RZ = 3, // Round towards Zero 519fe6060f1SDimitry Andric rmMask = 3 // Bit mask selecting rounding mode 520fe6060f1SDimitry Andric }; 521fe6060f1SDimitry Andric 522fe6060f1SDimitry Andric // Bit position of rounding mode bits in FPCR. 523fe6060f1SDimitry Andric const unsigned RoundingBitsPos = 22; 52406c3fb27SDimitry Andric 52506c3fb27SDimitry Andric // Registers used to pass function arguments. 5265f757f3fSDimitry Andric ArrayRef<MCPhysReg> getGPRArgRegs(); 5275f757f3fSDimitry Andric ArrayRef<MCPhysReg> getFPRArgRegs(); 5285f757f3fSDimitry Andric 5295f757f3fSDimitry Andric /// Maximum allowed number of unprobed bytes above SP at an ABI 5305f757f3fSDimitry Andric /// boundary. 5315f757f3fSDimitry Andric const unsigned StackProbeMaxUnprobedStack = 1024; 5325f757f3fSDimitry Andric 5335f757f3fSDimitry Andric /// Maximum number of iterations to unroll for a constant size probing loop. 5345f757f3fSDimitry Andric const unsigned StackProbeMaxLoopUnroll = 4; 53506c3fb27SDimitry Andric 536fe6060f1SDimitry Andric } // namespace AArch64 537fe6060f1SDimitry Andric 5380b57cec5SDimitry Andric class AArch64Subtarget; 5390b57cec5SDimitry Andric 5400b57cec5SDimitry Andric class AArch64TargetLowering : public TargetLowering { 5410b57cec5SDimitry Andric public: 5420b57cec5SDimitry Andric explicit AArch64TargetLowering(const TargetMachine &TM, 5430b57cec5SDimitry Andric const AArch64Subtarget &STI); 5440b57cec5SDimitry Andric 54581ad6265SDimitry Andric /// Control the following reassociation of operands: (op (op x, c1), y) -> (op 54681ad6265SDimitry Andric /// (op x, y), c1) where N0 is (op x, c1) and N1 is y. 54781ad6265SDimitry Andric bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 54881ad6265SDimitry Andric SDValue N1) const override; 54981ad6265SDimitry Andric 5500b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5510b57cec5SDimitry Andric CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 5520b57cec5SDimitry Andric 5530b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5540b57cec5SDimitry Andric CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 5550b57cec5SDimitry Andric 5560b57cec5SDimitry Andric /// Determine which of the bits specified in Mask are known to be either zero 5570b57cec5SDimitry Andric /// or one and return them in the KnownZero/KnownOne bitsets. 5580b57cec5SDimitry Andric void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 5590b57cec5SDimitry Andric const APInt &DemandedElts, 5600b57cec5SDimitry Andric const SelectionDAG &DAG, 5610b57cec5SDimitry Andric unsigned Depth = 0) const override; 5620b57cec5SDimitry Andric 56306c3fb27SDimitry Andric unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 56406c3fb27SDimitry Andric const APInt &DemandedElts, 56506c3fb27SDimitry Andric const SelectionDAG &DAG, 56606c3fb27SDimitry Andric unsigned Depth) const override; 56706c3fb27SDimitry Andric 5688bcb0991SDimitry Andric MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override { 5698bcb0991SDimitry Andric // Returning i64 unconditionally here (i.e. even for ILP32) means that the 5708bcb0991SDimitry Andric // *DAG* representation of pointers will always be 64-bits. They will be 5718bcb0991SDimitry Andric // truncated and extended when transferred to memory, but the 64-bit DAG 5728bcb0991SDimitry Andric // allows us to use AArch64's addressing modes much more easily. 5738bcb0991SDimitry Andric return MVT::getIntegerVT(64); 5748bcb0991SDimitry Andric } 5758bcb0991SDimitry Andric 5765ffd83dbSDimitry Andric bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 5775ffd83dbSDimitry Andric const APInt &DemandedElts, 5780b57cec5SDimitry Andric TargetLoweringOpt &TLO) const override; 5790b57cec5SDimitry Andric 5800b57cec5SDimitry Andric MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override; 5810b57cec5SDimitry Andric 5820b57cec5SDimitry Andric /// Returns true if the target allows unaligned memory accesses of the 5830b57cec5SDimitry Andric /// specified type. 5840b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses( 585fe6060f1SDimitry Andric EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 5860b57cec5SDimitry Andric MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 587bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5888bcb0991SDimitry Andric /// LLT variant. 5895ffd83dbSDimitry Andric bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, 5905ffd83dbSDimitry Andric Align Alignment, 5915ffd83dbSDimitry Andric MachineMemOperand::Flags Flags, 592bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 5930b57cec5SDimitry Andric 5940b57cec5SDimitry Andric /// Provide custom lowering hooks for some operations. 5950b57cec5SDimitry Andric SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 5960b57cec5SDimitry Andric 5970b57cec5SDimitry Andric const char *getTargetNodeName(unsigned Opcode) const override; 5980b57cec5SDimitry Andric 5990b57cec5SDimitry Andric SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 6000b57cec5SDimitry Andric 6010b57cec5SDimitry Andric /// This method returns a target specific FastISel object, or null if the 6020b57cec5SDimitry Andric /// target does not support "fast" ISel. 6030b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 6040b57cec5SDimitry Andric const TargetLibraryInfo *libInfo) const override; 6050b57cec5SDimitry Andric 6060b57cec5SDimitry Andric bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 6070b57cec5SDimitry Andric 6080b57cec5SDimitry Andric bool isFPImmLegal(const APFloat &Imm, EVT VT, 6090b57cec5SDimitry Andric bool ForCodeSize) const override; 6100b57cec5SDimitry Andric 6110b57cec5SDimitry Andric /// Return true if the given shuffle mask can be codegen'd directly, or if it 6120b57cec5SDimitry Andric /// should be stack expanded. 6130b57cec5SDimitry Andric bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 6140b57cec5SDimitry Andric 615fcaf7f86SDimitry Andric /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero' 616fcaf7f86SDimitry Andric /// shuffle mask can be codegen'd directly. 617fcaf7f86SDimitry Andric bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override; 618fcaf7f86SDimitry Andric 6190b57cec5SDimitry Andric /// Return the ISD::SETCC ValueType. 6200b57cec5SDimitry Andric EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 6210b57cec5SDimitry Andric EVT VT) const override; 6220b57cec5SDimitry Andric 6230b57cec5SDimitry Andric SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 6240b57cec5SDimitry Andric 6250b57cec5SDimitry Andric MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, 6260b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6270b57cec5SDimitry Andric 6280b57cec5SDimitry Andric MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, 6290b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6300b57cec5SDimitry Andric 6315f757f3fSDimitry Andric MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI, 6325f757f3fSDimitry Andric MachineBasicBlock *MBB) const; 6335f757f3fSDimitry Andric 63481ad6265SDimitry Andric MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg, 63581ad6265SDimitry Andric MachineInstr &MI, 63681ad6265SDimitry Andric MachineBasicBlock *BB) const; 63781ad6265SDimitry Andric MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const; 638bdd1243dSDimitry Andric MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg, 639bdd1243dSDimitry Andric MachineInstr &MI, MachineBasicBlock *BB, 640bdd1243dSDimitry Andric bool HasTile) const; 6415f757f3fSDimitry Andric MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, 6425f757f3fSDimitry Andric unsigned Opcode, bool Op0IsDef) const; 64381ad6265SDimitry Andric MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const; 64481ad6265SDimitry Andric 6450b57cec5SDimitry Andric MachineBasicBlock * 6460b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 6470b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 6480b57cec5SDimitry Andric 6490b57cec5SDimitry Andric bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 6500b57cec5SDimitry Andric MachineFunction &MF, 6510b57cec5SDimitry Andric unsigned Intrinsic) const override; 6520b57cec5SDimitry Andric 6530b57cec5SDimitry Andric bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 6540b57cec5SDimitry Andric EVT NewVT) const override; 6550b57cec5SDimitry Andric 65606c3fb27SDimitry Andric bool shouldRemoveRedundantExtend(SDValue Op) const override; 65706c3fb27SDimitry Andric 6580b57cec5SDimitry Andric bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 6590b57cec5SDimitry Andric bool isTruncateFree(EVT VT1, EVT VT2) const override; 6600b57cec5SDimitry Andric 6610b57cec5SDimitry Andric bool isProfitableToHoist(Instruction *I) const override; 6620b57cec5SDimitry Andric 6630b57cec5SDimitry Andric bool isZExtFree(Type *Ty1, Type *Ty2) const override; 6640b57cec5SDimitry Andric bool isZExtFree(EVT VT1, EVT VT2) const override; 6650b57cec5SDimitry Andric bool isZExtFree(SDValue Val, EVT VT2) const override; 6660b57cec5SDimitry Andric 6670b57cec5SDimitry Andric bool shouldSinkOperands(Instruction *I, 6680b57cec5SDimitry Andric SmallVectorImpl<Use *> &Ops) const override; 6690b57cec5SDimitry Andric 67006c3fb27SDimitry Andric bool optimizeExtendOrTruncateConversion( 67106c3fb27SDimitry Andric Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override; 672bdd1243dSDimitry Andric 6735ffd83dbSDimitry Andric bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override; 6740b57cec5SDimitry Andric getMaxSupportedInterleaveFactor()6750b57cec5SDimitry Andric unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 6760b57cec5SDimitry Andric 6770b57cec5SDimitry Andric bool lowerInterleavedLoad(LoadInst *LI, 6780b57cec5SDimitry Andric ArrayRef<ShuffleVectorInst *> Shuffles, 6790b57cec5SDimitry Andric ArrayRef<unsigned> Indices, 6800b57cec5SDimitry Andric unsigned Factor) const override; 6810b57cec5SDimitry Andric bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 6820b57cec5SDimitry Andric unsigned Factor) const override; 6830b57cec5SDimitry Andric 68406c3fb27SDimitry Andric bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, 68506c3fb27SDimitry Andric LoadInst *LI) const override; 68606c3fb27SDimitry Andric 68706c3fb27SDimitry Andric bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, 68806c3fb27SDimitry Andric StoreInst *SI) const override; 68906c3fb27SDimitry Andric 6900b57cec5SDimitry Andric bool isLegalAddImmediate(int64_t) const override; 6910b57cec5SDimitry Andric bool isLegalICmpImmediate(int64_t) const override; 6920b57cec5SDimitry Andric 69381ad6265SDimitry Andric bool isMulAddWithConstProfitable(SDValue AddNode, 69481ad6265SDimitry Andric SDValue ConstNode) const override; 695349cc55cSDimitry Andric 6960b57cec5SDimitry Andric bool shouldConsiderGEPOffsetSplit() const override; 6970b57cec5SDimitry Andric 6985ffd83dbSDimitry Andric EVT getOptimalMemOpType(const MemOp &Op, 6990b57cec5SDimitry Andric const AttributeList &FuncAttributes) const override; 7000b57cec5SDimitry Andric 7015ffd83dbSDimitry Andric LLT getOptimalMemOpLLT(const MemOp &Op, 7028bcb0991SDimitry Andric const AttributeList &FuncAttributes) const override; 7038bcb0991SDimitry Andric 7040b57cec5SDimitry Andric /// Return true if the addressing mode represented by AM is legal for this 7050b57cec5SDimitry Andric /// target, for a load/store of the specified type. 7060b57cec5SDimitry Andric bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 7070b57cec5SDimitry Andric unsigned AS, 7080b57cec5SDimitry Andric Instruction *I = nullptr) const override; 7090b57cec5SDimitry Andric 7105f757f3fSDimitry Andric int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, 7115f757f3fSDimitry Andric int64_t MaxOffset) const override; 7125f757f3fSDimitry Andric 7130b57cec5SDimitry Andric /// Return true if an FMA operation is faster than a pair of fmul and fadd 7140b57cec5SDimitry Andric /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 7150b57cec5SDimitry Andric /// returns true, otherwise fmuladd is expanded to fmul + fadd. 716480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 717480093f4SDimitry Andric EVT VT) const override; 718480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 7190b57cec5SDimitry Andric 720fe6060f1SDimitry Andric bool generateFMAsInMachineCombiner(EVT VT, 7215f757f3fSDimitry Andric CodeGenOptLevel OptLevel) const override; 722fe6060f1SDimitry Andric 7230b57cec5SDimitry Andric const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 72406c3fb27SDimitry Andric ArrayRef<MCPhysReg> getRoundingControlRegisters() const override; 7250b57cec5SDimitry Andric 7260b57cec5SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 7270b57cec5SDimitry Andric bool isDesirableToCommuteWithShift(const SDNode *N, 7280b57cec5SDimitry Andric CombineLevel Level) const override; 7290b57cec5SDimitry Andric isDesirableToPullExtFromShl(const MachineInstr & MI)7305f757f3fSDimitry Andric bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override { 7315f757f3fSDimitry Andric return false; 7325f757f3fSDimitry Andric } 7335f757f3fSDimitry Andric 734fcaf7f86SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 735fcaf7f86SDimitry Andric bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 736fcaf7f86SDimitry Andric 73781ad6265SDimitry Andric /// Return true if it is profitable to fold a pair of shifts into a mask. 73881ad6265SDimitry Andric bool shouldFoldConstantShiftPairToMask(const SDNode *N, 73981ad6265SDimitry Andric CombineLevel Level) const override; 74081ad6265SDimitry Andric 74106c3fb27SDimitry Andric bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 74206c3fb27SDimitry Andric EVT VT) const override; 74306c3fb27SDimitry Andric 7440b57cec5SDimitry Andric /// Returns true if it is beneficial to convert a load of a constant 7450b57cec5SDimitry Andric /// to just the constant itself. 7460b57cec5SDimitry Andric bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 7470b57cec5SDimitry Andric Type *Ty) const override; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 7500b57cec5SDimitry Andric /// with this index. 7510b57cec5SDimitry Andric bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 7520b57cec5SDimitry Andric unsigned Index) const override; 7530b57cec5SDimitry Andric shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed)7545ffd83dbSDimitry Andric bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 7555ffd83dbSDimitry Andric bool MathUsed) const override { 7565ffd83dbSDimitry Andric // Using overflow ops for overflow checks only should beneficial on 7575ffd83dbSDimitry Andric // AArch64. 7585ffd83dbSDimitry Andric return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 7595ffd83dbSDimitry Andric } 7605ffd83dbSDimitry Andric 761fe6060f1SDimitry Andric Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 7620b57cec5SDimitry Andric AtomicOrdering Ord) const override; 763fe6060f1SDimitry Andric Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 764fe6060f1SDimitry Andric AtomicOrdering Ord) const override; 7650b57cec5SDimitry Andric 766fe6060f1SDimitry Andric void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 7670b57cec5SDimitry Andric 768349cc55cSDimitry Andric bool isOpSuitableForLDPSTP(const Instruction *I) const; 76906c3fb27SDimitry Andric bool isOpSuitableForLSE128(const Instruction *I) const; 77006c3fb27SDimitry Andric bool isOpSuitableForRCPC3(const Instruction *I) const; 771349cc55cSDimitry Andric bool shouldInsertFencesForAtomic(const Instruction *I) const override; 772bdd1243dSDimitry Andric bool 773bdd1243dSDimitry Andric shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override; 774349cc55cSDimitry Andric 7750b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7760b57cec5SDimitry Andric shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 77781ad6265SDimitry Andric TargetLoweringBase::AtomicExpansionKind 77881ad6265SDimitry Andric shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 7790b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7800b57cec5SDimitry Andric shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 7810b57cec5SDimitry Andric 7820b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7830b57cec5SDimitry Andric shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 7840b57cec5SDimitry Andric 7850b57cec5SDimitry Andric bool useLoadStackGuardNode() const override; 7860b57cec5SDimitry Andric TargetLoweringBase::LegalizeTypeAction 7870b57cec5SDimitry Andric getPreferredVectorAction(MVT VT) const override; 7880b57cec5SDimitry Andric 7890b57cec5SDimitry Andric /// If the target has a standard location for the stack protector cookie, 7900b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 791fe6060f1SDimitry Andric Value *getIRStackGuard(IRBuilderBase &IRB) const override; 7920b57cec5SDimitry Andric 7930b57cec5SDimitry Andric void insertSSPDeclarations(Module &M) const override; 7940b57cec5SDimitry Andric Value *getSDagStackGuard(const Module &M) const override; 7950b57cec5SDimitry Andric Function *getSSPStackGuardCheck(const Module &M) const override; 7960b57cec5SDimitry Andric 7970b57cec5SDimitry Andric /// If the target has a standard location for the unsafe stack pointer, 7980b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 799fe6060f1SDimitry Andric Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; 8000b57cec5SDimitry Andric 8010b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8020b57cec5SDimitry Andric /// exception address on entry to an EH pad. 8035ffd83dbSDimitry Andric Register getExceptionPointerRegister(const Constant * PersonalityFn)8040b57cec5SDimitry Andric getExceptionPointerRegister(const Constant *PersonalityFn) const override { 8050b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8060b57cec5SDimitry Andric return AArch64::X0; 8070b57cec5SDimitry Andric } 8080b57cec5SDimitry Andric 8090b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8100b57cec5SDimitry Andric /// exception typeid on entry to a landing pad. 8115ffd83dbSDimitry Andric Register getExceptionSelectorRegister(const Constant * PersonalityFn)8120b57cec5SDimitry Andric getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 8130b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8140b57cec5SDimitry Andric return AArch64::X1; 8150b57cec5SDimitry Andric } 8160b57cec5SDimitry Andric 8170b57cec5SDimitry Andric bool isIntDivCheap(EVT VT, AttributeList Attr) const override; 8180b57cec5SDimitry Andric canMergeStoresTo(unsigned AddressSpace,EVT MemVT,const MachineFunction & MF)8190b57cec5SDimitry Andric bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 820349cc55cSDimitry Andric const MachineFunction &MF) const override { 8210b57cec5SDimitry Andric // Do not merge to float value size (128 bytes) if no implicit 8220b57cec5SDimitry Andric // float attribute is set. 8230b57cec5SDimitry Andric 824349cc55cSDimitry Andric bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat); 8250b57cec5SDimitry Andric 8260b57cec5SDimitry Andric if (NoFloat) 8270b57cec5SDimitry Andric return (MemVT.getSizeInBits() <= 64); 8280b57cec5SDimitry Andric return true; 8290b57cec5SDimitry Andric } 8300b57cec5SDimitry Andric isCheapToSpeculateCttz(Type *)831bdd1243dSDimitry Andric bool isCheapToSpeculateCttz(Type *) const override { 8320b57cec5SDimitry Andric return true; 8330b57cec5SDimitry Andric } 8340b57cec5SDimitry Andric isCheapToSpeculateCtlz(Type *)835bdd1243dSDimitry Andric bool isCheapToSpeculateCtlz(Type *) const override { 8360b57cec5SDimitry Andric return true; 8370b57cec5SDimitry Andric } 8380b57cec5SDimitry Andric 8390b57cec5SDimitry Andric bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 8400b57cec5SDimitry Andric hasAndNotCompare(SDValue V)8410b57cec5SDimitry Andric bool hasAndNotCompare(SDValue V) const override { 8420b57cec5SDimitry Andric // We can use bics for any scalar. 8430b57cec5SDimitry Andric return V.getValueType().isScalarInteger(); 8440b57cec5SDimitry Andric } 8450b57cec5SDimitry Andric hasAndNot(SDValue Y)8460b57cec5SDimitry Andric bool hasAndNot(SDValue Y) const override { 8470b57cec5SDimitry Andric EVT VT = Y.getValueType(); 8480b57cec5SDimitry Andric 8490b57cec5SDimitry Andric if (!VT.isVector()) 8500b57cec5SDimitry Andric return hasAndNotCompare(Y); 8510b57cec5SDimitry Andric 852349cc55cSDimitry Andric TypeSize TS = VT.getSizeInBits(); 853349cc55cSDimitry Andric // TODO: We should be able to use bic/bif too for SVE. 854349cc55cSDimitry Andric return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic' 8550b57cec5SDimitry Andric } 8560b57cec5SDimitry Andric 8578bcb0991SDimitry Andric bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 8588bcb0991SDimitry Andric SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 8598bcb0991SDimitry Andric unsigned OldShiftOpcode, unsigned NewShiftOpcode, 8608bcb0991SDimitry Andric SelectionDAG &DAG) const override; 8618bcb0991SDimitry Andric 862bdd1243dSDimitry Andric ShiftLegalizationStrategy 863bdd1243dSDimitry Andric preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 864bdd1243dSDimitry Andric unsigned ExpansionFactor) const override; 8650b57cec5SDimitry Andric shouldTransformSignedTruncationCheck(EVT XVT,unsigned KeptBits)8660b57cec5SDimitry Andric bool shouldTransformSignedTruncationCheck(EVT XVT, 8670b57cec5SDimitry Andric unsigned KeptBits) const override { 8680b57cec5SDimitry Andric // For vectors, we don't have a preference.. 8690b57cec5SDimitry Andric if (XVT.isVector()) 8700b57cec5SDimitry Andric return false; 8710b57cec5SDimitry Andric 8720b57cec5SDimitry Andric auto VTIsOk = [](EVT VT) -> bool { 8730b57cec5SDimitry Andric return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 8740b57cec5SDimitry Andric VT == MVT::i64; 8750b57cec5SDimitry Andric }; 8760b57cec5SDimitry Andric 8770b57cec5SDimitry Andric // We are ok with KeptBitsVT being byte/word/dword, what SXT supports. 8780b57cec5SDimitry Andric // XVT will be larger than KeptBitsVT. 8790b57cec5SDimitry Andric MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); 8800b57cec5SDimitry Andric return VTIsOk(XVT) && VTIsOk(KeptBitsVT); 8810b57cec5SDimitry Andric } 8820b57cec5SDimitry Andric 8830b57cec5SDimitry Andric bool preferIncOfAddToSubOfNot(EVT VT) const override; 8840b57cec5SDimitry Andric 8854824e7fdSDimitry Andric bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 8864824e7fdSDimitry Andric 887bdd1243dSDimitry Andric bool isComplexDeinterleavingSupported() const override; 888bdd1243dSDimitry Andric bool isComplexDeinterleavingOperationSupported( 889bdd1243dSDimitry Andric ComplexDeinterleavingOperation Operation, Type *Ty) const override; 890bdd1243dSDimitry Andric 891bdd1243dSDimitry Andric Value *createComplexDeinterleavingIR( 89206c3fb27SDimitry Andric IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 893bdd1243dSDimitry Andric ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 894bdd1243dSDimitry Andric Value *Accumulator = nullptr) const override; 895bdd1243dSDimitry Andric supportSplitCSR(MachineFunction * MF)8960b57cec5SDimitry Andric bool supportSplitCSR(MachineFunction *MF) const override { 8970b57cec5SDimitry Andric return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 8980b57cec5SDimitry Andric MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 8990b57cec5SDimitry Andric } 9000b57cec5SDimitry Andric void initializeSplitCSR(MachineBasicBlock *Entry) const override; 9010b57cec5SDimitry Andric void insertCopiesSplitCSR( 9020b57cec5SDimitry Andric MachineBasicBlock *Entry, 9030b57cec5SDimitry Andric const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 9040b57cec5SDimitry Andric supportSwiftError()9050b57cec5SDimitry Andric bool supportSwiftError() const override { 9060b57cec5SDimitry Andric return true; 9070b57cec5SDimitry Andric } 9080b57cec5SDimitry Andric supportKCFIBundles()909bdd1243dSDimitry Andric bool supportKCFIBundles() const override { return true; } 910bdd1243dSDimitry Andric 91106c3fb27SDimitry Andric MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB, 91206c3fb27SDimitry Andric MachineBasicBlock::instr_iterator &MBBI, 91306c3fb27SDimitry Andric const TargetInstrInfo *TII) const override; 91406c3fb27SDimitry Andric 9150b57cec5SDimitry Andric /// Enable aggressive FMA fusion on targets that want it. 9160b57cec5SDimitry Andric bool enableAggressiveFMAFusion(EVT VT) const override; 9170b57cec5SDimitry Andric 9180b57cec5SDimitry Andric /// Returns the size of the platform's va_list object. 9190b57cec5SDimitry Andric unsigned getVaListSizeInBits(const DataLayout &DL) const override; 9200b57cec5SDimitry Andric 9210b57cec5SDimitry Andric /// Returns true if \p VecTy is a legal interleaved access type. This 9220b57cec5SDimitry Andric /// function checks the vector element type and the overall width of the 9230b57cec5SDimitry Andric /// vector. 924349cc55cSDimitry Andric bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, 925349cc55cSDimitry Andric bool &UseScalable) const; 9260b57cec5SDimitry Andric 9270b57cec5SDimitry Andric /// Returns the number of interleaved accesses that will be generated when 9280b57cec5SDimitry Andric /// lowering accesses of the given type. 929349cc55cSDimitry Andric unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, 930349cc55cSDimitry Andric bool UseScalable) const; 9310b57cec5SDimitry Andric 9325ffd83dbSDimitry Andric MachineMemOperand::Flags getTargetMMOFlags( 9335ffd83dbSDimitry Andric const Instruction &I) const override; 9340b57cec5SDimitry Andric 935fe6060f1SDimitry Andric bool functionArgumentNeedsConsecutiveRegisters( 936fe6060f1SDimitry Andric Type *Ty, CallingConv::ID CallConv, bool isVarArg, 937fe6060f1SDimitry Andric const DataLayout &DL) const override; 938fe6060f1SDimitry Andric 9390b57cec5SDimitry Andric /// Used for exception handling on Win64. 9400b57cec5SDimitry Andric bool needsFixedCatchObjects() const override; 9415ffd83dbSDimitry Andric 9425ffd83dbSDimitry Andric bool fallBackToDAGISel(const Instruction &Inst) const override; 9435ffd83dbSDimitry Andric 9445ffd83dbSDimitry Andric /// SVE code generation for fixed length vectors does not custom lower 9455ffd83dbSDimitry Andric /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to 9465ffd83dbSDimitry Andric /// merge. However, merging them creates a BUILD_VECTOR that is just as 9475ffd83dbSDimitry Andric /// illegal as the original, thus leading to an infinite legalisation loop. 9485ffd83dbSDimitry Andric /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal 9495ffd83dbSDimitry Andric /// vector types this override can be removed. 950e8d8bef9SDimitry Andric bool mergeStoresAfterLegalization(EVT VT) const override; 9515ffd83dbSDimitry Andric 952fe6060f1SDimitry Andric // If the platform/function should have a redzone, return the size in bytes. getRedZoneSize(const Function & F)953fe6060f1SDimitry Andric unsigned getRedZoneSize(const Function &F) const { 954fe6060f1SDimitry Andric if (F.hasFnAttribute(Attribute::NoRedZone)) 955fe6060f1SDimitry Andric return 0; 956fe6060f1SDimitry Andric return 128; 957fe6060f1SDimitry Andric } 958fe6060f1SDimitry Andric 95904eeddc0SDimitry Andric bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const; 960fe6060f1SDimitry Andric EVT getPromotedVTForPredicate(EVT VT) const; 961fe6060f1SDimitry Andric 9626e75b2fbSDimitry Andric EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, 9636e75b2fbSDimitry Andric bool AllowUnknown = false) const override; 9646e75b2fbSDimitry Andric 9654824e7fdSDimitry Andric bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override; 9664824e7fdSDimitry Andric 9675f757f3fSDimitry Andric bool shouldExpandCttzElements(EVT VT) const override; 9685f757f3fSDimitry Andric 969bdd1243dSDimitry Andric /// If a change in streaming mode is required on entry to/return from a 970bdd1243dSDimitry Andric /// function call it emits and returns the corresponding SMSTART or SMSTOP node. 971bdd1243dSDimitry Andric /// \p Entry tells whether this is before/after the Call, which is necessary 972bdd1243dSDimitry Andric /// because PSTATE.SM is only queried once. 973bdd1243dSDimitry Andric SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, 97406c3fb27SDimitry Andric SDValue Chain, SDValue InGlue, 975bdd1243dSDimitry Andric SDValue PStateSM, bool Entry) const; 976bdd1243dSDimitry Andric isVScaleKnownToBeAPowerOfTwo()97706c3fb27SDimitry Andric bool isVScaleKnownToBeAPowerOfTwo() const override { return true; } 978bdd1243dSDimitry Andric 979bdd1243dSDimitry Andric // Normally SVE is only used for byte size vectors that do not fit within a 980bdd1243dSDimitry Andric // NEON vector. This changes when OverrideNEON is true, allowing SVE to be 981bdd1243dSDimitry Andric // used for 64bit and 128bit vectors as well. 982bdd1243dSDimitry Andric bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const; 983bdd1243dSDimitry Andric 9845f757f3fSDimitry Andric // Follow NEON ABI rules even when using SVE for fixed length vectors. 9855f757f3fSDimitry Andric MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 9865f757f3fSDimitry Andric EVT VT) const override; 9875f757f3fSDimitry Andric unsigned getNumRegistersForCallingConv(LLVMContext &Context, 9885f757f3fSDimitry Andric CallingConv::ID CC, 9895f757f3fSDimitry Andric EVT VT) const override; 9905f757f3fSDimitry Andric unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, 9915f757f3fSDimitry Andric CallingConv::ID CC, EVT VT, 9925f757f3fSDimitry Andric EVT &IntermediateVT, 9935f757f3fSDimitry Andric unsigned &NumIntermediates, 9945f757f3fSDimitry Andric MVT &RegisterVT) const override; 9955f757f3fSDimitry Andric 9965f757f3fSDimitry Andric /// True if stack clash protection is enabled for this functions. 9975f757f3fSDimitry Andric bool hasInlineStackProbe(const MachineFunction &MF) const override; 9985f757f3fSDimitry Andric 9990b57cec5SDimitry Andric private: 10000b57cec5SDimitry Andric /// Keep a pointer to the AArch64Subtarget around so that we can 10010b57cec5SDimitry Andric /// make the right decision when generating code for different targets. 10020b57cec5SDimitry Andric const AArch64Subtarget *Subtarget; 10030b57cec5SDimitry Andric 1004dfa39133SDimitry Andric llvm::BumpPtrAllocator BumpAlloc; 1005dfa39133SDimitry Andric llvm::StringSaver Saver{BumpAlloc}; 1006dfa39133SDimitry Andric 10070b57cec5SDimitry Andric bool isExtFreeImpl(const Instruction *Ext) const override; 10080b57cec5SDimitry Andric 1009fe6060f1SDimitry Andric void addTypeForNEON(MVT VT); 101006c3fb27SDimitry Andric void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE); 10110b57cec5SDimitry Andric void addDRTypeForNEON(MVT VT); 10120b57cec5SDimitry Andric void addQRTypeForNEON(MVT VT); 10130b57cec5SDimitry Andric 1014bdd1243dSDimitry Andric unsigned allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL, 1015bdd1243dSDimitry Andric SelectionDAG &DAG) const; 1016bdd1243dSDimitry Andric 10170b57cec5SDimitry Andric SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 10180b57cec5SDimitry Andric bool isVarArg, 10190b57cec5SDimitry Andric const SmallVectorImpl<ISD::InputArg> &Ins, 10200b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10210b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10220b57cec5SDimitry Andric 10235f757f3fSDimitry Andric void AdjustInstrPostInstrSelection(MachineInstr &MI, 10245f757f3fSDimitry Andric SDNode *Node) const override; 10255f757f3fSDimitry Andric 10260b57cec5SDimitry Andric SDValue LowerCall(CallLoweringInfo & /*CLI*/, 10270b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10280b57cec5SDimitry Andric 102906c3fb27SDimitry Andric SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 10300b57cec5SDimitry Andric CallingConv::ID CallConv, bool isVarArg, 1031f3fd488fSDimitry Andric const SmallVectorImpl<CCValAssign> &RVLocs, 10320b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10330b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 1034b3edf446SDimitry Andric SDValue ThisVal, bool RequiresSMChange) const; 10350b57cec5SDimitry Andric 1036fe6060f1SDimitry Andric SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 10370b57cec5SDimitry Andric SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1038349cc55cSDimitry Andric SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const; 1039e8d8bef9SDimitry Andric SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1040e8d8bef9SDimitry Andric 1041e8d8bef9SDimitry Andric SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 1042e8d8bef9SDimitry Andric SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 10430b57cec5SDimitry Andric 1044fe6060f1SDimitry Andric SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 1045fe6060f1SDimitry Andric 10461fd87a68SDimitry Andric SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 10470b57cec5SDimitry Andric SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1048bdd1243dSDimitry Andric SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 10490b57cec5SDimitry Andric 10503a9a9c0cSDimitry Andric bool 10513a9a9c0cSDimitry Andric isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const; 10520b57cec5SDimitry Andric 10530b57cec5SDimitry Andric /// Finds the incoming stack arguments which overlap the given fixed stack 10540b57cec5SDimitry Andric /// object and incorporates their load into the current chain. This prevents 10550b57cec5SDimitry Andric /// an upcoming store from clobbering the stack argument before it's used. 10560b57cec5SDimitry Andric SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 10570b57cec5SDimitry Andric MachineFrameInfo &MFI, int ClobberedFI) const; 10580b57cec5SDimitry Andric 10590b57cec5SDimitry Andric bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 10600b57cec5SDimitry Andric 10610b57cec5SDimitry Andric void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, 10620b57cec5SDimitry Andric SDValue &Chain) const; 10630b57cec5SDimitry Andric 10640b57cec5SDimitry Andric bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 10650b57cec5SDimitry Andric bool isVarArg, 10660b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10670b57cec5SDimitry Andric LLVMContext &Context) const override; 10680b57cec5SDimitry Andric 10690b57cec5SDimitry Andric SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 10700b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10710b57cec5SDimitry Andric const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 10720b57cec5SDimitry Andric SelectionDAG &DAG) const override; 10730b57cec5SDimitry Andric 10740b57cec5SDimitry Andric SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10750b57cec5SDimitry Andric unsigned Flag) const; 10760b57cec5SDimitry Andric SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 10770b57cec5SDimitry Andric unsigned Flag) const; 10780b57cec5SDimitry Andric SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 10790b57cec5SDimitry Andric unsigned Flag) const; 10800b57cec5SDimitry Andric SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 10810b57cec5SDimitry Andric unsigned Flag) const; 10827a6dacacSDimitry Andric SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 10837a6dacacSDimitry Andric unsigned Flag) const; 10840b57cec5SDimitry Andric template <class NodeTy> 10850b57cec5SDimitry Andric SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10860b57cec5SDimitry Andric template <class NodeTy> 10870b57cec5SDimitry Andric SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10880b57cec5SDimitry Andric template <class NodeTy> 10890b57cec5SDimitry Andric SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10900b57cec5SDimitry Andric template <class NodeTy> 10910b57cec5SDimitry Andric SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 10920b57cec5SDimitry Andric SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 10930b57cec5SDimitry Andric SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 10940b57cec5SDimitry Andric SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10950b57cec5SDimitry Andric SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 10960b57cec5SDimitry Andric SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1097480093f4SDimitry Andric SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase, 1098480093f4SDimitry Andric const SDLoc &DL, SelectionDAG &DAG) const; 10990b57cec5SDimitry Andric SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL, 11000b57cec5SDimitry Andric SelectionDAG &DAG) const; 11010b57cec5SDimitry Andric SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 11020b57cec5SDimitry Andric SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1103bdd1243dSDimitry Andric SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const; 11040b57cec5SDimitry Andric SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 11050b57cec5SDimitry Andric SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 11060b57cec5SDimitry Andric SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 11070b57cec5SDimitry Andric SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 11080b57cec5SDimitry Andric SDValue TVal, SDValue FVal, const SDLoc &dl, 11090b57cec5SDimitry Andric SelectionDAG &DAG) const; 11100b57cec5SDimitry Andric SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 11110b57cec5SDimitry Andric SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 11120b57cec5SDimitry Andric SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 11130b57cec5SDimitry Andric SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 11140b57cec5SDimitry Andric SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 11150b57cec5SDimitry Andric SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 11160b57cec5SDimitry Andric SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const; 11170b57cec5SDimitry Andric SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 11180b57cec5SDimitry Andric SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 11190b57cec5SDimitry Andric SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 11200b57cec5SDimitry Andric SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 11210b57cec5SDimitry Andric SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 11220b57cec5SDimitry Andric SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1123bdd1243dSDimitry Andric SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 1124fe6060f1SDimitry Andric SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 11250b57cec5SDimitry Andric SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11260b57cec5SDimitry Andric SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11270b57cec5SDimitry Andric SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1128bdd1243dSDimitry Andric SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 11290b57cec5SDimitry Andric SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 11308bcb0991SDimitry Andric SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const; 11315ffd83dbSDimitry Andric SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const; 113281ad6265SDimitry Andric SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, 113381ad6265SDimitry Andric unsigned NewOp) const; 1134e8d8bef9SDimitry Andric SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; 1135fe6060f1SDimitry Andric SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const; 11360b57cec5SDimitry Andric SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 11375ffd83dbSDimitry Andric SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 113806c3fb27SDimitry Andric SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 113906c3fb27SDimitry Andric SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 1140e8d8bef9SDimitry Andric SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const; 1141e8d8bef9SDimitry Andric SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 11420b57cec5SDimitry Andric SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 1143fe6060f1SDimitry Andric SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 11440b57cec5SDimitry Andric SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 1145fcaf7f86SDimitry Andric SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const; 1146e8d8bef9SDimitry Andric SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 1147fe6060f1SDimitry Andric SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const; 1148349cc55cSDimitry Andric SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 11490b57cec5SDimitry Andric SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 11500b57cec5SDimitry Andric SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 11510b57cec5SDimitry Andric SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 11520b57cec5SDimitry Andric SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1153349cc55cSDimitry Andric SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11540b57cec5SDimitry Andric SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1155fe6060f1SDimitry Andric SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11560b57cec5SDimitry Andric SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1157e8d8bef9SDimitry Andric SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 11580b57cec5SDimitry Andric SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 1159e8d8bef9SDimitry Andric SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const; 11600b57cec5SDimitry Andric SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 11610b57cec5SDimitry Andric SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 1162fe6060f1SDimitry Andric SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 11635ffd83dbSDimitry Andric SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const; 11645ffd83dbSDimitry Andric SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 11650b57cec5SDimitry Andric SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 11660b57cec5SDimitry Andric SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const; 11675f757f3fSDimitry Andric SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11685f757f3fSDimitry Andric SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11690b57cec5SDimitry Andric SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 11705f757f3fSDimitry Andric 117106c3fb27SDimitry Andric SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const; 11725ffd83dbSDimitry Andric 1173e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, 1174e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1175e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, 1176e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 11775ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1178fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1179e8d8bef9SDimitry Andric SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const; 1180e8d8bef9SDimitry Andric SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const; 1181e8d8bef9SDimitry Andric SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp, 1182e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1183e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const; 1184e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const; 11855ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const; 1186fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op, 1187fe6060f1SDimitry Andric SelectionDAG &DAG) const; 11885ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op, 11895ffd83dbSDimitry Andric SelectionDAG &DAG) const; 1190fe6060f1SDimitry Andric SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const; 1191fe6060f1SDimitry Andric SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const; 1192fe6060f1SDimitry Andric SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const; 1193fe6060f1SDimitry Andric SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op, 1194fe6060f1SDimitry Andric SelectionDAG &DAG) const; 1195fe6060f1SDimitry Andric SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const; 1196fe6060f1SDimitry Andric SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const; 1197fe6060f1SDimitry Andric SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const; 1198fe6060f1SDimitry Andric SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; 1199fe6060f1SDimitry Andric SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op, 1200fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12010b57cec5SDimitry Andric 12020b57cec5SDimitry Andric SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 12030b57cec5SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 120481ad6265SDimitry Andric SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 120581ad6265SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 12060b57cec5SDimitry Andric SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12070b57cec5SDimitry Andric int &ExtraSteps, bool &UseOneConst, 12080b57cec5SDimitry Andric bool Reciprocal) const override; 12090b57cec5SDimitry Andric SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12100b57cec5SDimitry Andric int &ExtraSteps) const override; 1211e8d8bef9SDimitry Andric SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1212e8d8bef9SDimitry Andric const DenormalMode &Mode) const override; 1213e8d8bef9SDimitry Andric SDValue getSqrtResultForDenormInput(SDValue Operand, 1214e8d8bef9SDimitry Andric SelectionDAG &DAG) const override; 12150b57cec5SDimitry Andric unsigned combineRepeatedFPDivisors() const override; 12160b57cec5SDimitry Andric 12170b57cec5SDimitry Andric ConstraintType getConstraintType(StringRef Constraint) const override; 1218480093f4SDimitry Andric Register getRegisterByName(const char* RegName, LLT VT, 12198bcb0991SDimitry Andric const MachineFunction &MF) const override; 12200b57cec5SDimitry Andric 12210b57cec5SDimitry Andric /// Examine constraint string and operand type and determine a weight value. 12220b57cec5SDimitry Andric /// The operand object must already have been set up with the operand type. 12230b57cec5SDimitry Andric ConstraintWeight 12240b57cec5SDimitry Andric getSingleConstraintMatchWeight(AsmOperandInfo &info, 12250b57cec5SDimitry Andric const char *constraint) const override; 12260b57cec5SDimitry Andric 12270b57cec5SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> 12280b57cec5SDimitry Andric getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 12290b57cec5SDimitry Andric StringRef Constraint, MVT VT) const override; 12300b57cec5SDimitry Andric 12310b57cec5SDimitry Andric const char *LowerXConstraint(EVT ConstraintVT) const override; 12320b57cec5SDimitry Andric 12335f757f3fSDimitry Andric void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 12340b57cec5SDimitry Andric std::vector<SDValue> &Ops, 12350b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12360b57cec5SDimitry Andric 12375f757f3fSDimitry Andric InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode)12385f757f3fSDimitry Andric getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 12390b57cec5SDimitry Andric if (ConstraintCode == "Q") 12405f757f3fSDimitry Andric return InlineAsm::ConstraintCode::Q; 12410b57cec5SDimitry Andric // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 12420b57cec5SDimitry Andric // followed by llvm_unreachable so we'll leave them unimplemented in 12430b57cec5SDimitry Andric // the backend for now. 12440b57cec5SDimitry Andric return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 12450b57cec5SDimitry Andric } 12460b57cec5SDimitry Andric 124706c3fb27SDimitry Andric /// Handle Lowering flag assembly outputs. 124806c3fb27SDimitry Andric SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, 124906c3fb27SDimitry Andric const SDLoc &DL, 125006c3fb27SDimitry Andric const AsmOperandInfo &Constraint, 125106c3fb27SDimitry Andric SelectionDAG &DAG) const override; 125206c3fb27SDimitry Andric 1253fe6060f1SDimitry Andric bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override; 12545f757f3fSDimitry Andric bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override; 1255480093f4SDimitry Andric bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 12560b57cec5SDimitry Andric bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 12570b57cec5SDimitry Andric bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1258bdd1243dSDimitry Andric bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 125906c3fb27SDimitry Andric SDValue &Offset, SelectionDAG &DAG) const; 12600b57cec5SDimitry Andric bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 12610b57cec5SDimitry Andric ISD::MemIndexedMode &AM, 12620b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12630b57cec5SDimitry Andric bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 12640b57cec5SDimitry Andric SDValue &Offset, ISD::MemIndexedMode &AM, 12650b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12665f757f3fSDimitry Andric bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, 12675f757f3fSDimitry Andric bool IsPre, MachineRegisterInfo &MRI) const override; 12680b57cec5SDimitry Andric 12690b57cec5SDimitry Andric void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 12700b57cec5SDimitry Andric SelectionDAG &DAG) const override; 1271fe6060f1SDimitry Andric void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1272fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12735ffd83dbSDimitry Andric void ReplaceExtractSubVectorResults(SDNode *N, 12745ffd83dbSDimitry Andric SmallVectorImpl<SDValue> &Results, 12755ffd83dbSDimitry Andric SelectionDAG &DAG) const; 12760b57cec5SDimitry Andric 12770b57cec5SDimitry Andric bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; 12780b57cec5SDimitry Andric 12790b57cec5SDimitry Andric void finalizeLowering(MachineFunction &MF) const override; 12805ffd83dbSDimitry Andric 12815ffd83dbSDimitry Andric bool shouldLocalize(const MachineInstr &MI, 12825ffd83dbSDimitry Andric const TargetTransformInfo *TTI) const override; 12835ffd83dbSDimitry Andric 1284fe6060f1SDimitry Andric bool SimplifyDemandedBitsForTargetNode(SDValue Op, 1285fe6060f1SDimitry Andric const APInt &OriginalDemandedBits, 1286fe6060f1SDimitry Andric const APInt &OriginalDemandedElts, 1287fe6060f1SDimitry Andric KnownBits &Known, 1288fe6060f1SDimitry Andric TargetLoweringOpt &TLO, 1289fe6060f1SDimitry Andric unsigned Depth) const override; 1290fe6060f1SDimitry Andric 129181ad6265SDimitry Andric bool isTargetCanonicalConstantNode(SDValue Op) const override; 129281ad6265SDimitry Andric 1293e8d8bef9SDimitry Andric // With the exception of data-predicate transitions, no instructions are 1294e8d8bef9SDimitry Andric // required to cast between legal scalable vector types. However: 1295e8d8bef9SDimitry Andric // 1. Packed and unpacked types have different bit lengths, meaning BITCAST 1296e8d8bef9SDimitry Andric // is not universally useable. 1297e8d8bef9SDimitry Andric // 2. Most unpacked integer types are not legal and thus integer extends 1298e8d8bef9SDimitry Andric // cannot be used to convert between unpacked and packed types. 1299e8d8bef9SDimitry Andric // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used 1300e8d8bef9SDimitry Andric // to transition between unpacked and packed types of the same element type, 1301e8d8bef9SDimitry Andric // with BITCAST used otherwise. 1302753f127fSDimitry Andric // This function does not handle predicate bitcasts. 1303e8d8bef9SDimitry Andric SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; 1304fe6060f1SDimitry Andric 13057a6dacacSDimitry Andric // Returns the runtime value for PSTATE.SM by generating a call to 13067a6dacacSDimitry Andric // __arm_sme_state. 13077a6dacacSDimitry Andric SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL, 13087a6dacacSDimitry Andric EVT VT) const; 1309bdd1243dSDimitry Andric 131006c3fb27SDimitry Andric bool preferScalarizeSplat(SDNode *N) const override; 13115f757f3fSDimitry Andric 13125f757f3fSDimitry Andric unsigned getMinimumJumpTableEntries() const override; 13130b57cec5SDimitry Andric }; 13140b57cec5SDimitry Andric 13150b57cec5SDimitry Andric namespace AArch64 { 13160b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 13170b57cec5SDimitry Andric const TargetLibraryInfo *libInfo); 13180b57cec5SDimitry Andric } // end namespace AArch64 13190b57cec5SDimitry Andric 13200b57cec5SDimitry Andric } // end namespace llvm 13210b57cec5SDimitry Andric 13220b57cec5SDimitry Andric #endif 1323