1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the AArch64 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H 14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H 15 16 #include "AArch64.h" 17 #include "AArch64RegisterInfo.h" 18 #include "llvm/ADT/Optional.h" 19 #include "llvm/CodeGen/MachineCombinerPattern.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 22 #define GET_INSTRINFO_HEADER 23 #include "AArch64GenInstrInfo.inc" 24 25 namespace llvm { 26 27 class AArch64Subtarget; 28 class AArch64TargetMachine; 29 30 static const MachineMemOperand::Flags MOSuppressPair = 31 MachineMemOperand::MOTargetFlag1; 32 static const MachineMemOperand::Flags MOStridedAccess = 33 MachineMemOperand::MOTargetFlag2; 34 35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access" 36 37 class AArch64InstrInfo final : public AArch64GenInstrInfo { 38 const AArch64RegisterInfo RI; 39 const AArch64Subtarget &Subtarget; 40 41 public: 42 explicit AArch64InstrInfo(const AArch64Subtarget &STI); 43 44 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 45 /// such, whenever a client has an instance of instruction info, it should 46 /// always be able to get register info as well (through this method). 47 const AArch64RegisterInfo &getRegisterInfo() const { return RI; } 48 49 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 50 51 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 52 53 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned &DstReg, unsigned &SubIdx) const override; 55 56 bool 57 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 58 const MachineInstr &MIb, 59 AliasAnalysis *AA = nullptr) const override; 60 61 unsigned isLoadFromStackSlot(const MachineInstr &MI, 62 int &FrameIndex) const override; 63 unsigned isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const override; 65 66 /// Does this instruction set its full destination register to zero? 67 static bool isGPRZero(const MachineInstr &MI); 68 69 /// Does this instruction rename a GPR without modifying bits? 70 static bool isGPRCopy(const MachineInstr &MI); 71 72 /// Does this instruction rename an FPR without modifying bits? 73 static bool isFPRCopy(const MachineInstr &MI); 74 75 /// Return true if pairing the given load or store is hinted to be 76 /// unprofitable. 77 static bool isLdStPairSuppressed(const MachineInstr &MI); 78 79 /// Return true if the given load or store is a strided memory access. 80 static bool isStridedAccess(const MachineInstr &MI); 81 82 /// Return true if this is an unscaled load/store. 83 static bool isUnscaledLdSt(unsigned Opc); 84 static bool isUnscaledLdSt(MachineInstr &MI) { 85 return isUnscaledLdSt(MI.getOpcode()); 86 } 87 88 /// Returns the unscaled load/store for the scaled load/store opcode, 89 /// if there is a corresponding unscaled variant available. 90 static Optional<unsigned> getUnscaledLdSt(unsigned Opc); 91 92 93 /// Returns the index for the immediate for a given instruction. 94 static unsigned getLoadStoreImmIdx(unsigned Opc); 95 96 /// Return true if pairing the given load or store may be paired with another. 97 static bool isPairableLdStInst(const MachineInstr &MI); 98 99 /// Return the opcode that set flags when possible. The caller is 100 /// responsible for ensuring the opc has a flag setting equivalent. 101 static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit); 102 103 /// Return true if this is a load/store that can be potentially paired/merged. 104 bool isCandidateToMergeOrPair(const MachineInstr &MI) const; 105 106 /// Hint that pairing the given load or store is unprofitable. 107 static void suppressLdStPair(MachineInstr &MI); 108 109 bool getMemOperandWithOffset(const MachineInstr &MI, 110 const MachineOperand *&BaseOp, 111 int64_t &Offset, 112 const TargetRegisterInfo *TRI) const override; 113 114 bool getMemOperandWithOffsetWidth(const MachineInstr &MI, 115 const MachineOperand *&BaseOp, 116 int64_t &Offset, unsigned &Width, 117 const TargetRegisterInfo *TRI) const; 118 119 /// Return the immediate offset of the base register in a load/store \p LdSt. 120 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const; 121 122 /// Returns true if opcode \p Opc is a memory operation. If it is, set 123 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly. 124 /// 125 /// For unscaled instructions, \p Scale is set to 1. 126 static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width, 127 int64_t &MinOffset, int64_t &MaxOffset); 128 129 bool shouldClusterMemOps(const MachineOperand &BaseOp1, 130 const MachineOperand &BaseOp2, 131 unsigned NumLoads) const override; 132 133 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 134 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 135 bool KillSrc, unsigned Opcode, 136 llvm::ArrayRef<unsigned> Indices) const; 137 void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 138 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 139 bool KillSrc, unsigned Opcode, unsigned ZeroReg, 140 llvm::ArrayRef<unsigned> Indices) const; 141 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 142 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 143 bool KillSrc) const override; 144 145 void storeRegToStackSlot(MachineBasicBlock &MBB, 146 MachineBasicBlock::iterator MBBI, unsigned SrcReg, 147 bool isKill, int FrameIndex, 148 const TargetRegisterClass *RC, 149 const TargetRegisterInfo *TRI) const override; 150 151 void loadRegFromStackSlot(MachineBasicBlock &MBB, 152 MachineBasicBlock::iterator MBBI, unsigned DestReg, 153 int FrameIndex, const TargetRegisterClass *RC, 154 const TargetRegisterInfo *TRI) const override; 155 156 // This tells target independent code that it is okay to pass instructions 157 // with subreg operands to foldMemoryOperandImpl. 158 bool isSubregFoldable() const override { return true; } 159 160 using TargetInstrInfo::foldMemoryOperandImpl; 161 MachineInstr * 162 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 163 ArrayRef<unsigned> Ops, 164 MachineBasicBlock::iterator InsertPt, int FrameIndex, 165 LiveIntervals *LIS = nullptr, 166 VirtRegMap *VRM = nullptr) const override; 167 168 /// \returns true if a branch from an instruction with opcode \p BranchOpc 169 /// bytes is capable of jumping to a position \p BrOffset bytes away. 170 bool isBranchOffsetInRange(unsigned BranchOpc, 171 int64_t BrOffset) const override; 172 173 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 174 175 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 176 MachineBasicBlock *&FBB, 177 SmallVectorImpl<MachineOperand> &Cond, 178 bool AllowModify = false) const override; 179 unsigned removeBranch(MachineBasicBlock &MBB, 180 int *BytesRemoved = nullptr) const override; 181 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 182 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 183 const DebugLoc &DL, 184 int *BytesAdded = nullptr) const override; 185 bool 186 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 187 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 188 unsigned, unsigned, int &, int &, int &) const override; 189 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 190 const DebugLoc &DL, unsigned DstReg, 191 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 192 unsigned FalseReg) const override; 193 void getNoop(MCInst &NopInst) const override; 194 195 bool isSchedulingBoundary(const MachineInstr &MI, 196 const MachineBasicBlock *MBB, 197 const MachineFunction &MF) const override; 198 199 /// analyzeCompare - For a comparison instruction, return the source registers 200 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 201 /// Return true if the comparison instruction can be analyzed. 202 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 203 unsigned &SrcReg2, int &CmpMask, 204 int &CmpValue) const override; 205 /// optimizeCompareInstr - Convert the instruction supplying the argument to 206 /// the comparison into one that sets the zero bit in the flags register. 207 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 208 unsigned SrcReg2, int CmpMask, int CmpValue, 209 const MachineRegisterInfo *MRI) const override; 210 bool optimizeCondBranch(MachineInstr &MI) const override; 211 212 /// Return true when a code sequence can improve throughput. It 213 /// should be called only for instructions in loops. 214 /// \param Pattern - combiner pattern 215 bool isThroughputPattern(MachineCombinerPattern Pattern) const override; 216 /// Return true when there is potentially a faster code sequence 217 /// for an instruction chain ending in ``Root``. All potential patterns are 218 /// listed in the ``Patterns`` array. 219 bool getMachineCombinerPatterns( 220 MachineInstr &Root, 221 SmallVectorImpl<MachineCombinerPattern> &Patterns) const override; 222 /// Return true when Inst is associative and commutative so that it can be 223 /// reassociated. 224 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 225 /// When getMachineCombinerPatterns() finds patterns, this function generates 226 /// the instructions that could replace the original code sequence 227 void genAlternativeCodeSequence( 228 MachineInstr &Root, MachineCombinerPattern Pattern, 229 SmallVectorImpl<MachineInstr *> &InsInstrs, 230 SmallVectorImpl<MachineInstr *> &DelInstrs, 231 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 232 /// AArch64 supports MachineCombiner. 233 bool useMachineCombiner() const override; 234 235 bool expandPostRAPseudo(MachineInstr &MI) const override; 236 237 std::pair<unsigned, unsigned> 238 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 239 ArrayRef<std::pair<unsigned, const char *>> 240 getSerializableDirectMachineOperandTargetFlags() const override; 241 ArrayRef<std::pair<unsigned, const char *>> 242 getSerializableBitmaskMachineOperandTargetFlags() const override; 243 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> 244 getSerializableMachineMemOperandTargetFlags() const override; 245 246 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 247 bool OutlineFromLinkOnceODRs) const override; 248 outliner::OutlinedFunction getOutliningCandidateInfo( 249 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 250 outliner::InstrType 251 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 252 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 253 unsigned &Flags) const override; 254 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 255 const outliner::OutlinedFunction &OF) const override; 256 MachineBasicBlock::iterator 257 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 258 MachineBasicBlock::iterator &It, MachineFunction &MF, 259 const outliner::Candidate &C) const override; 260 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 261 /// Returns true if the instruction has a shift by immediate that can be 262 /// executed in one cycle less. 263 static bool isFalkorShiftExtFast(const MachineInstr &MI); 264 /// Return true if the instructions is a SEH instruciton used for unwinding 265 /// on Windows. 266 static bool isSEHInstruction(const MachineInstr &MI); 267 268 #define GET_INSTRINFO_HELPER_DECLS 269 #include "AArch64GenInstrInfo.inc" 270 271 protected: 272 /// If the specific machine instruction is a instruction that moves/copies 273 /// value from one register to another register return true along with 274 /// @Source machine operand and @Destination machine operand. 275 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, 276 const MachineOperand *&Destination) const override; 277 278 private: 279 /// Sets the offsets on outlined instructions in \p MBB which use SP 280 /// so that they will be valid post-outlining. 281 /// 282 /// \param MBB A \p MachineBasicBlock in an outlined function. 283 void fixupPostOutline(MachineBasicBlock &MBB) const; 284 285 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL, 286 MachineBasicBlock *TBB, 287 ArrayRef<MachineOperand> Cond) const; 288 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg, 289 const MachineRegisterInfo *MRI) const; 290 291 /// Returns an unused general-purpose register which can be used for 292 /// constructing an outlined call if one exists. Returns 0 otherwise. 293 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 294 }; 295 296 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg 297 /// plus Offset. This is intended to be used from within the prolog/epilog 298 /// insertion (PEI) pass, where a virtual scratch register may be allocated 299 /// if necessary, to be replaced by the scavenger at the end of PEI. 300 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 301 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 302 int Offset, const TargetInstrInfo *TII, 303 MachineInstr::MIFlag = MachineInstr::NoFlags, 304 bool SetNZCV = false, bool NeedsWinCFI = false, 305 bool *HasWinCFI = nullptr); 306 307 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the 308 /// FP. Return false if the offset could not be handled directly in MI, and 309 /// return the left-over portion by reference. 310 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 311 unsigned FrameReg, int &Offset, 312 const AArch64InstrInfo *TII); 313 314 /// Use to report the frame offset status in isAArch64FrameOffsetLegal. 315 enum AArch64FrameOffsetStatus { 316 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply. 317 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal. 318 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly. 319 }; 320 321 /// Check if the @p Offset is a valid frame offset for @p MI. 322 /// The returned value reports the validity of the frame offset for @p MI. 323 /// It uses the values defined by AArch64FrameOffsetStatus for that. 324 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to 325 /// use an offset.eq 326 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be 327 /// rewritten in @p MI. 328 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the 329 /// amount that is off the limit of the legal offset. 330 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be 331 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp. 332 /// If set, @p EmittableOffset contains the amount that can be set in @p MI 333 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that 334 /// is a legal offset. 335 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, 336 bool *OutUseUnscaledOp = nullptr, 337 unsigned *OutUnscaledOp = nullptr, 338 int *EmittableOffset = nullptr); 339 340 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } 341 342 static inline bool isCondBranchOpcode(int Opc) { 343 switch (Opc) { 344 case AArch64::Bcc: 345 case AArch64::CBZW: 346 case AArch64::CBZX: 347 case AArch64::CBNZW: 348 case AArch64::CBNZX: 349 case AArch64::TBZW: 350 case AArch64::TBZX: 351 case AArch64::TBNZW: 352 case AArch64::TBNZX: 353 return true; 354 default: 355 return false; 356 } 357 } 358 359 static inline bool isIndirectBranchOpcode(int Opc) { 360 return Opc == AArch64::BR; 361 } 362 363 // struct TSFlags { 364 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits 365 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit 366 // } 367 368 namespace AArch64 { 369 370 enum ElementSizeType { 371 ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7), 372 ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0), 373 ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1), 374 ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2), 375 ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3), 376 ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4), 377 }; 378 379 enum DestructiveInstType { 380 DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1), 381 NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0), 382 Destructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1), 383 }; 384 385 #undef TSFLAG_ELEMENT_SIZE_TYPE 386 #undef TSFLAG_DESTRUCTIVE_INST_TYPE 387 } 388 389 } // end namespace llvm 390 391 #endif 392