106c3fb27SDimitry Andric//=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=// 206c3fb27SDimitry Andric// 306c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 506c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606c3fb27SDimitry Andric// 706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 806c3fb27SDimitry Andric// 906c3fb27SDimitry Andric// This file defines the scheduling model for the Arm Neoverse V2 processors. 1006c3fb27SDimitry Andric// All information is taken from the V2 Software Optimisation guide: 1106c3fb27SDimitry Andric// 1206c3fb27SDimitry Andric// https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2 1306c3fb27SDimitry Andric// 1406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 1506c3fb27SDimitry Andric 1606c3fb27SDimitry Andricdef NeoverseV2Model : SchedMachineModel { 1706c3fb27SDimitry Andric let IssueWidth = 16; // Micro-ops dispatched at a time. 1806c3fb27SDimitry Andric let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2. 1906c3fb27SDimitry Andric let LoadLatency = 4; // Optimistic load latency. 2006c3fb27SDimitry Andric let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2. 2106c3fb27SDimitry Andric let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. 2206c3fb27SDimitry Andric let CompleteModel = 1; 2306c3fb27SDimitry Andric 2406c3fb27SDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, 25*4c2d3b02SDimitry Andric [HasSVE2p1, HasCPA, 26*4c2d3b02SDimitry Andric HasCSSC]); 2706c3fb27SDimitry Andric} 2806c3fb27SDimitry Andric 2906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 3006c3fb27SDimitry Andric// Define each kind of processor resource and number available on Neoverse V2. 3106c3fb27SDimitry Andric// Instructions are first fetched and then decoded into internal macro-ops 3206c3fb27SDimitry Andric// (MOPs). From there, the MOPs proceed through register renaming and dispatch 3306c3fb27SDimitry Andric// stages. A MOP can be split into two micro-ops further down the pipeline 3406c3fb27SDimitry Andric// after the decode stage. Once dispatched, micro-ops wait for their operands 3506c3fb27SDimitry Andric// and issue out-of-order to one of seventeen issue pipelines. Each issue 3606c3fb27SDimitry Andric// pipeline can accept one micro-op per cycle. 3706c3fb27SDimitry Andric 3806c3fb27SDimitry Andriclet SchedModel = NeoverseV2Model in { 3906c3fb27SDimitry Andric 4006c3fb27SDimitry Andric// Define the (17) issue ports. 4106c3fb27SDimitry Andricdef V2UnitB : ProcResource<2>; // Branch 0/1 4206c3fb27SDimitry Andricdef V2UnitS0 : ProcResource<1>; // Integer single-cycle 0 4306c3fb27SDimitry Andricdef V2UnitS1 : ProcResource<1>; // Integer single-cycle 1 4406c3fb27SDimitry Andricdef V2UnitS2 : ProcResource<1>; // Integer single-cycle 2 4506c3fb27SDimitry Andricdef V2UnitS3 : ProcResource<1>; // Integer single-cycle 3 4606c3fb27SDimitry Andricdef V2UnitM0 : ProcResource<1>; // Integer single/multicycle 0 4706c3fb27SDimitry Andricdef V2UnitM1 : ProcResource<1>; // Integer single/multicycle 1 4806c3fb27SDimitry Andricdef V2UnitV0 : ProcResource<1>; // FP/ASIMD 0 4906c3fb27SDimitry Andricdef V2UnitV1 : ProcResource<1>; // FP/ASIMD 1 5006c3fb27SDimitry Andricdef V2UnitV2 : ProcResource<1>; // FP/ASIMD 2 5106c3fb27SDimitry Andricdef V2UnitV3 : ProcResource<1>; // FP/ASIMD 3 5206c3fb27SDimitry Andricdef V2UnitL01 : ProcResource<2>; // Load/Store 0/1 5306c3fb27SDimitry Andricdef V2UnitL2 : ProcResource<1>; // Load 2 5406c3fb27SDimitry Andricdef V2UnitD : ProcResource<2>; // Store data 0/1 5506c3fb27SDimitry Andric 5606c3fb27SDimitry Andricdef V2UnitR : ProcResGroup<[V2UnitS0, V2UnitS1]>; // Integer single-cycle 0/1 5706c3fb27SDimitry Andricdef V2UnitS : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3]>; // Integer single-cycle 0/1/2/3 5806c3fb27SDimitry Andricdef V2UnitF : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1 and single/multicycle 0/1 5906c3fb27SDimitry Andricdef V2UnitI : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1/2/3 and single/multicycle 0/1 6006c3fb27SDimitry Andricdef V2UnitM : ProcResGroup<[V2UnitM0, V2UnitM1]>; // Integer single/multicycle 0/1 6106c3fb27SDimitry Andricdef V2UnitL : ProcResGroup<[V2UnitL01, V2UnitL2]>; // Load/Store 0/1 and Load 2 6206c3fb27SDimitry Andricdef V2UnitV : ProcResGroup<[V2UnitV0, V2UnitV1, V2UnitV2, V2UnitV3]>; // FP/ASIMD 0/1/2/3 6306c3fb27SDimitry Andricdef V2UnitV01 : ProcResGroup<[V2UnitV0, V2UnitV1]>; // FP/ASIMD 0/1 6406c3fb27SDimitry Andricdef V2UnitV02 : ProcResGroup<[V2UnitV0, V2UnitV2]>; // FP/ASIMD 0/2 6506c3fb27SDimitry Andricdef V2UnitV13 : ProcResGroup<[V2UnitV1, V2UnitV3]>; // FP/ASIMD 1/3 6606c3fb27SDimitry Andricdef V2UnitV23 : ProcResGroup<[V2UnitV2, V2UnitV3]>; // FP/ASIMD 2/3 6706c3fb27SDimitry Andric 6806c3fb27SDimitry Andric// Define commonly used read types. 6906c3fb27SDimitry Andric 7006c3fb27SDimitry Andric// No forwarding is provided for these types. 7106c3fb27SDimitry Andricdef : ReadAdvance<ReadI, 0>; 7206c3fb27SDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 7306c3fb27SDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 7406c3fb27SDimitry Andricdef : ReadAdvance<ReadIM, 0>; 7506c3fb27SDimitry Andricdef : ReadAdvance<ReadIMA, 0>; 7606c3fb27SDimitry Andricdef : ReadAdvance<ReadID, 0>; 7706c3fb27SDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 7806c3fb27SDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 7906c3fb27SDimitry Andricdef : ReadAdvance<ReadST, 0>; 8006c3fb27SDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 8106c3fb27SDimitry Andric 8206c3fb27SDimitry Andric// NOTE: Copied from N2. 8306c3fb27SDimitry Andricdef : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 8406c3fb27SDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 8506c3fb27SDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 8606c3fb27SDimitry Andricdef : WriteRes<WriteLDHi, []> { let Latency = 4; } 8706c3fb27SDimitry Andric 8806c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 8906c3fb27SDimitry Andric// Define customized scheduler read/write types specific to the Neoverse V2. 9006c3fb27SDimitry Andric 9106c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 925f757f3fSDimitry Andric 935f757f3fSDimitry Andric// Define generic 0 micro-op types 945f757f3fSDimitry Andricdef V2Write_0cyc : SchedWriteRes<[]> { let Latency = 0; } 955f757f3fSDimitry Andric 9606c3fb27SDimitry Andric// Define generic 1 micro-op types 9706c3fb27SDimitry Andric 9806c3fb27SDimitry Andricdef V2Write_1cyc_1B : SchedWriteRes<[V2UnitB]> { let Latency = 1; } 9906c3fb27SDimitry Andricdef V2Write_1cyc_1F : SchedWriteRes<[V2UnitF]> { let Latency = 1; } 10006c3fb27SDimitry Andricdef V2Write_1cyc_1I : SchedWriteRes<[V2UnitI]> { let Latency = 1; } 10106c3fb27SDimitry Andricdef V2Write_1cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 1; } 10206c3fb27SDimitry Andricdef V2Write_1cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 1; } 10306c3fb27SDimitry Andricdef V2Write_1cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 1; } 10406c3fb27SDimitry Andricdef V2Write_2cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 2; } 10506c3fb27SDimitry Andricdef V2Write_3cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 3; } 10606c3fb27SDimitry Andricdef V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } 10706c3fb27SDimitry Andricdef V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; } 10806c3fb27SDimitry Andricdef V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; } 10906c3fb27SDimitry Andricdef V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12; 1105f757f3fSDimitry Andric let ReleaseAtCycles = [12]; } 11106c3fb27SDimitry Andricdef V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20; 1125f757f3fSDimitry Andric let ReleaseAtCycles = [20]; } 11306c3fb27SDimitry Andricdef V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; } 11406c3fb27SDimitry Andricdef V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; } 11506c3fb27SDimitry Andricdef V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; } 11606c3fb27SDimitry Andricdef V2Write_2cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 2; } 11706c3fb27SDimitry Andricdef V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; } 11806c3fb27SDimitry Andricdef V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; } 11906c3fb27SDimitry Andricdef V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 12006c3fb27SDimitry Andricdef V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3; 1215f757f3fSDimitry Andric let ReleaseAtCycles = [2]; } 12206c3fb27SDimitry Andricdef V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; } 12306c3fb27SDimitry Andricdef V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 12406c3fb27SDimitry Andricdef V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 12506c3fb27SDimitry Andricdef V2Write_6cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 6; } 12606c3fb27SDimitry Andricdef V2Write_12cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 12; } 12706c3fb27SDimitry Andricdef V2Write_3cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 3; } 12806c3fb27SDimitry Andricdef V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; } 12906c3fb27SDimitry Andricdef V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; } 13006c3fb27SDimitry Andricdef V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 13106c3fb27SDimitry Andricdef V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7; 1325f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 13306c3fb27SDimitry Andricdef V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7; 1345f757f3fSDimitry Andric let ReleaseAtCycles = [2]; } 13506c3fb27SDimitry Andricdef V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; } 13606c3fb27SDimitry Andricdef V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9; 1375f757f3fSDimitry Andric let ReleaseAtCycles = [2]; } 13806c3fb27SDimitry Andricdef V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; } 13906c3fb27SDimitry Andricdef V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10; 1405f757f3fSDimitry Andric let ReleaseAtCycles = [2]; } 14106c3fb27SDimitry Andricdef V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12; 1425f757f3fSDimitry Andric let ReleaseAtCycles = [11]; } 14306c3fb27SDimitry Andricdef V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; } 14406c3fb27SDimitry Andricdef V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; } 14506c3fb27SDimitry Andricdef V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15; 1465f757f3fSDimitry Andric let ReleaseAtCycles = [8]; } 14706c3fb27SDimitry Andricdef V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; } 14806c3fb27SDimitry Andricdef V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16; 1495f757f3fSDimitry Andric let ReleaseAtCycles = [8]; } 15006c3fb27SDimitry Andricdef V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20; 1515f757f3fSDimitry Andric let ReleaseAtCycles = [20]; } 15206c3fb27SDimitry Andricdef V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; } 15306c3fb27SDimitry Andricdef V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; } 15406c3fb27SDimitry Andricdef V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; } 15506c3fb27SDimitry Andricdef V2Write_4cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 4; } 15606c3fb27SDimitry Andricdef V2Write_4cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 15706c3fb27SDimitry Andricdef V2Write_6cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 6; } 15806c3fb27SDimitry Andricdef V2Write_10cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 10; } 15906c3fb27SDimitry Andricdef V2Write_6cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 6; } 16006c3fb27SDimitry Andric 16106c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 16206c3fb27SDimitry Andric// Define generic 2 micro-op types 16306c3fb27SDimitry Andric 16406c3fb27SDimitry Andricdef V2Write_1cyc_1B_1R : SchedWriteRes<[V2UnitB, V2UnitR]> { 16506c3fb27SDimitry Andric let Latency = 1; 16606c3fb27SDimitry Andric let NumMicroOps = 2; 16706c3fb27SDimitry Andric} 16806c3fb27SDimitry Andric 16906c3fb27SDimitry Andricdef V2Write_6cyc_1M0_1B : SchedWriteRes<[V2UnitM0, V2UnitB]> { 17006c3fb27SDimitry Andric let Latency = 6; 17106c3fb27SDimitry Andric let NumMicroOps = 2; 17206c3fb27SDimitry Andric} 17306c3fb27SDimitry Andric 17406c3fb27SDimitry Andricdef V2Write_9cyc_1M0_1L : SchedWriteRes<[V2UnitM0, V2UnitL]> { 17506c3fb27SDimitry Andric let Latency = 9; 17606c3fb27SDimitry Andric let NumMicroOps = 2; 17706c3fb27SDimitry Andric} 17806c3fb27SDimitry Andric 17906c3fb27SDimitry Andricdef V2Write_3cyc_1I_1M : SchedWriteRes<[V2UnitI, V2UnitM]> { 18006c3fb27SDimitry Andric let Latency = 3; 18106c3fb27SDimitry Andric let NumMicroOps = 2; 18206c3fb27SDimitry Andric} 18306c3fb27SDimitry Andric 18406c3fb27SDimitry Andricdef V2Write_1cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { 18506c3fb27SDimitry Andric let Latency = 1; 18606c3fb27SDimitry Andric let NumMicroOps = 2; 18706c3fb27SDimitry Andric} 18806c3fb27SDimitry Andric 18906c3fb27SDimitry Andricdef V2Write_3cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { 19006c3fb27SDimitry Andric let Latency = 3; 19106c3fb27SDimitry Andric let NumMicroOps = 2; 19206c3fb27SDimitry Andric} 19306c3fb27SDimitry Andric 19406c3fb27SDimitry Andricdef V2Write_4cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> { 19506c3fb27SDimitry Andric let Latency = 4; 19606c3fb27SDimitry Andric let NumMicroOps = 2; 19706c3fb27SDimitry Andric} 19806c3fb27SDimitry Andric 19906c3fb27SDimitry Andricdef V2Write_5cyc_1L_1F : SchedWriteRes<[V2UnitL, V2UnitF]> { 20006c3fb27SDimitry Andric let Latency = 5; 20106c3fb27SDimitry Andric let NumMicroOps = 2; 20206c3fb27SDimitry Andric} 20306c3fb27SDimitry Andric 20406c3fb27SDimitry Andricdef V2Write_6cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> { 20506c3fb27SDimitry Andric let Latency = 6; 20606c3fb27SDimitry Andric let NumMicroOps = 2; 20706c3fb27SDimitry Andric} 20806c3fb27SDimitry Andric 20906c3fb27SDimitry Andricdef V2Write_7cyc_1F_1L : SchedWriteRes<[V2UnitF, V2UnitL]> { 21006c3fb27SDimitry Andric let Latency = 7; 21106c3fb27SDimitry Andric let NumMicroOps = 2; 21206c3fb27SDimitry Andric} 21306c3fb27SDimitry Andric 21406c3fb27SDimitry Andricdef V2Write_7cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> { 21506c3fb27SDimitry Andric let Latency = 7; 21606c3fb27SDimitry Andric let NumMicroOps = 2; 21706c3fb27SDimitry Andric} 21806c3fb27SDimitry Andric 21906c3fb27SDimitry Andricdef V2Write_1cyc_1L01_1D : SchedWriteRes<[V2UnitL01, V2UnitD]> { 22006c3fb27SDimitry Andric let Latency = 1; 22106c3fb27SDimitry Andric let NumMicroOps = 2; 22206c3fb27SDimitry Andric} 22306c3fb27SDimitry Andric 22406c3fb27SDimitry Andricdef V2Write_5cyc_1M0_1V : SchedWriteRes<[V2UnitM0, V2UnitV]> { 22506c3fb27SDimitry Andric let Latency = 5; 22606c3fb27SDimitry Andric let NumMicroOps = 2; 22706c3fb27SDimitry Andric} 22806c3fb27SDimitry Andric 22906c3fb27SDimitry Andricdef V2Write_2cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> { 23006c3fb27SDimitry Andric let Latency = 2; 23106c3fb27SDimitry Andric let NumMicroOps = 2; 23206c3fb27SDimitry Andric} 23306c3fb27SDimitry Andric 23406c3fb27SDimitry Andricdef V2Write_2cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> { 23506c3fb27SDimitry Andric let Latency = 2; 23606c3fb27SDimitry Andric let NumMicroOps = 2; 23706c3fb27SDimitry Andric} 23806c3fb27SDimitry Andric 23906c3fb27SDimitry Andricdef V2Write_2cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> { 24006c3fb27SDimitry Andric let Latency = 2; 24106c3fb27SDimitry Andric let NumMicroOps = 2; 24206c3fb27SDimitry Andric} 24306c3fb27SDimitry Andric 24406c3fb27SDimitry Andricdef V2Write_4cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> { 24506c3fb27SDimitry Andric let Latency = 4; 24606c3fb27SDimitry Andric let NumMicroOps = 2; 24706c3fb27SDimitry Andric} 24806c3fb27SDimitry Andric 24906c3fb27SDimitry Andricdef V2Write_4cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> { 25006c3fb27SDimitry Andric let Latency = 4; 25106c3fb27SDimitry Andric let NumMicroOps = 2; 25206c3fb27SDimitry Andric} 25306c3fb27SDimitry Andric 25406c3fb27SDimitry Andricdef V2Write_4cyc_1V13_1V : SchedWriteRes<[V2UnitV13, V2UnitV]> { 25506c3fb27SDimitry Andric let Latency = 4; 25606c3fb27SDimitry Andric let NumMicroOps = 2; 25706c3fb27SDimitry Andric} 25806c3fb27SDimitry Andric 25906c3fb27SDimitry Andricdef V2Write_4cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> { 26006c3fb27SDimitry Andric let Latency = 4; 26106c3fb27SDimitry Andric let NumMicroOps = 2; 26206c3fb27SDimitry Andric} 26306c3fb27SDimitry Andric 26406c3fb27SDimitry Andricdef V2Write_4cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> { 26506c3fb27SDimitry Andric let Latency = 4; 26606c3fb27SDimitry Andric let NumMicroOps = 2; 26706c3fb27SDimitry Andric} 26806c3fb27SDimitry Andric 26906c3fb27SDimitry Andricdef V2Write_4cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> { 27006c3fb27SDimitry Andric let Latency = 4; 27106c3fb27SDimitry Andric let NumMicroOps = 2; 27206c3fb27SDimitry Andric} 27306c3fb27SDimitry Andric 27406c3fb27SDimitry Andricdef V2Write_6cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> { 27506c3fb27SDimitry Andric let Latency = 6; 27606c3fb27SDimitry Andric let NumMicroOps = 2; 27706c3fb27SDimitry Andric} 27806c3fb27SDimitry Andric 27906c3fb27SDimitry Andricdef V2Write_6cyc_2L : SchedWriteRes<[V2UnitL, V2UnitL]> { 28006c3fb27SDimitry Andric let Latency = 6; 28106c3fb27SDimitry Andric let NumMicroOps = 2; 28206c3fb27SDimitry Andric} 28306c3fb27SDimitry Andric 28406c3fb27SDimitry Andricdef V2Write_8cyc_1L_1V : SchedWriteRes<[V2UnitL, V2UnitV]> { 28506c3fb27SDimitry Andric let Latency = 8; 28606c3fb27SDimitry Andric let NumMicroOps = 2; 28706c3fb27SDimitry Andric} 28806c3fb27SDimitry Andric 28906c3fb27SDimitry Andricdef V2Write_4cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> { 29006c3fb27SDimitry Andric let Latency = 4; 29106c3fb27SDimitry Andric let NumMicroOps = 2; 29206c3fb27SDimitry Andric} 29306c3fb27SDimitry Andric 29406c3fb27SDimitry Andricdef V2Write_3cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { 29506c3fb27SDimitry Andric let Latency = 3; 29606c3fb27SDimitry Andric let NumMicroOps = 2; 29706c3fb27SDimitry Andric} 29806c3fb27SDimitry Andric 29906c3fb27SDimitry Andricdef V2Write_4cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { 30006c3fb27SDimitry Andric let Latency = 4; 30106c3fb27SDimitry Andric let NumMicroOps = 2; 30206c3fb27SDimitry Andric} 30306c3fb27SDimitry Andric 30406c3fb27SDimitry Andricdef V2Write_1cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { 30506c3fb27SDimitry Andric let Latency = 1; 30606c3fb27SDimitry Andric let NumMicroOps = 2; 30706c3fb27SDimitry Andric} 30806c3fb27SDimitry Andric 30906c3fb27SDimitry Andricdef V2Write_2cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> { 31006c3fb27SDimitry Andric let Latency = 2; 31106c3fb27SDimitry Andric let NumMicroOps = 2; 31206c3fb27SDimitry Andric} 31306c3fb27SDimitry Andric 31406c3fb27SDimitry Andricdef V2Write_6cyc_2V1 : SchedWriteRes<[V2UnitV1, V2UnitV1]> { 31506c3fb27SDimitry Andric let Latency = 6; 31606c3fb27SDimitry Andric let NumMicroOps = 2; 31706c3fb27SDimitry Andric} 31806c3fb27SDimitry Andric 31906c3fb27SDimitry Andricdef V2Write_4cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> { 32006c3fb27SDimitry Andric let Latency = 4; 32106c3fb27SDimitry Andric let NumMicroOps = 2; 32206c3fb27SDimitry Andric} 32306c3fb27SDimitry Andric 32406c3fb27SDimitry Andricdef V2Write_5cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> { 32506c3fb27SDimitry Andric let Latency = 5; 32606c3fb27SDimitry Andric let NumMicroOps = 2; 32706c3fb27SDimitry Andric} 32806c3fb27SDimitry Andric 32906c3fb27SDimitry Andricdef V2Write_5cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> { 33006c3fb27SDimitry Andric let Latency = 5; 33106c3fb27SDimitry Andric let NumMicroOps = 2; 33206c3fb27SDimitry Andric} 33306c3fb27SDimitry Andric 33406c3fb27SDimitry Andricdef V2Write_5cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> { 33506c3fb27SDimitry Andric let Latency = 5; 33606c3fb27SDimitry Andric let NumMicroOps = 2; 33706c3fb27SDimitry Andric} 33806c3fb27SDimitry Andric 33906c3fb27SDimitry Andricdef V2Write_6cyc_1V1_1M0 : SchedWriteRes<[V2UnitV1, V2UnitM0]> { 34006c3fb27SDimitry Andric let Latency = 6; 34106c3fb27SDimitry Andric let NumMicroOps = 2; 34206c3fb27SDimitry Andric} 34306c3fb27SDimitry Andric 34406c3fb27SDimitry Andricdef V2Write_7cyc_1M0_1V02 : SchedWriteRes<[V2UnitM0, V2UnitV02]> { 34506c3fb27SDimitry Andric let Latency = 7; 34606c3fb27SDimitry Andric let NumMicroOps = 2; 34706c3fb27SDimitry Andric} 34806c3fb27SDimitry Andric 34906c3fb27SDimitry Andricdef V2Write_2cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> { 35006c3fb27SDimitry Andric let Latency = 2; 35106c3fb27SDimitry Andric let NumMicroOps = 2; 35206c3fb27SDimitry Andric} 35306c3fb27SDimitry Andric 35406c3fb27SDimitry Andricdef V2Write_3cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> { 35506c3fb27SDimitry Andric let Latency = 3; 35606c3fb27SDimitry Andric let NumMicroOps = 2; 35706c3fb27SDimitry Andric} 35806c3fb27SDimitry Andric 35906c3fb27SDimitry Andricdef V2Write_6cyc_1V_1V13 : SchedWriteRes<[V2UnitV, V2UnitV13]> { 36006c3fb27SDimitry Andric let Latency = 6; 36106c3fb27SDimitry Andric let NumMicroOps = 2; 36206c3fb27SDimitry Andric} 36306c3fb27SDimitry Andric 36406c3fb27SDimitry Andricdef V2Write_6cyc_1L_1M : SchedWriteRes<[V2UnitL, V2UnitM]> { 36506c3fb27SDimitry Andric let Latency = 6; 36606c3fb27SDimitry Andric let NumMicroOps = 2; 36706c3fb27SDimitry Andric} 36806c3fb27SDimitry Andric 36906c3fb27SDimitry Andricdef V2Write_6cyc_1L_1S : SchedWriteRes<[V2UnitL, V2UnitS]> { 37006c3fb27SDimitry Andric let Latency = 6; 37106c3fb27SDimitry Andric let NumMicroOps = 2; 37206c3fb27SDimitry Andric} 37306c3fb27SDimitry Andric 37406c3fb27SDimitry Andricdef V2Write_4cyc_2V13 : SchedWriteRes<[V2UnitV13, V2UnitV13]> { 37506c3fb27SDimitry Andric let Latency = 4; 37606c3fb27SDimitry Andric let NumMicroOps = 2; 37706c3fb27SDimitry Andric} 37806c3fb27SDimitry Andric 37906c3fb27SDimitry Andricdef V2Write_8cyc_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> { 38006c3fb27SDimitry Andric let Latency = 8; 38106c3fb27SDimitry Andric let NumMicroOps = 2; 38206c3fb27SDimitry Andric} 38306c3fb27SDimitry Andric 38406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 38506c3fb27SDimitry Andric// Define generic 3 micro-op types 38606c3fb27SDimitry Andric 38706c3fb27SDimitry Andricdef V2Write_1cyc_1L01_1D_1I : SchedWriteRes<[V2UnitL01, V2UnitD, V2UnitI]> { 38806c3fb27SDimitry Andric let Latency = 1; 38906c3fb27SDimitry Andric let NumMicroOps = 3; 39006c3fb27SDimitry Andric} 39106c3fb27SDimitry Andric 39206c3fb27SDimitry Andricdef V2Write_2cyc_1L01_1V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitI]> { 39306c3fb27SDimitry Andric let Latency = 2; 39406c3fb27SDimitry Andric let NumMicroOps = 3; 39506c3fb27SDimitry Andric} 39606c3fb27SDimitry Andric 39706c3fb27SDimitry Andricdef V2Write_2cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> { 39806c3fb27SDimitry Andric let Latency = 2; 39906c3fb27SDimitry Andric let NumMicroOps = 3; 40006c3fb27SDimitry Andric} 40106c3fb27SDimitry Andric 40206c3fb27SDimitry Andricdef V2Write_4cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> { 40306c3fb27SDimitry Andric let Latency = 4; 40406c3fb27SDimitry Andric let NumMicroOps = 3; 40506c3fb27SDimitry Andric} 40606c3fb27SDimitry Andric 40706c3fb27SDimitry Andricdef V2Write_9cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> { 40806c3fb27SDimitry Andric let Latency = 9; 40906c3fb27SDimitry Andric let NumMicroOps = 3; 41006c3fb27SDimitry Andric} 41106c3fb27SDimitry Andric 41206c3fb27SDimitry Andricdef V2Write_4cyc_3V01 : SchedWriteRes<[V2UnitV01, V2UnitV01, V2UnitV01]> { 41306c3fb27SDimitry Andric let Latency = 4; 41406c3fb27SDimitry Andric let NumMicroOps = 3; 41506c3fb27SDimitry Andric} 41606c3fb27SDimitry Andric 41706c3fb27SDimitry Andricdef V2Write_7cyc_1M_1M0_1V : SchedWriteRes<[V2UnitM, V2UnitM0, V2UnitV]> { 41806c3fb27SDimitry Andric let Latency = 7; 41906c3fb27SDimitry Andric let NumMicroOps = 3; 42006c3fb27SDimitry Andric} 42106c3fb27SDimitry Andric 42206c3fb27SDimitry Andricdef V2Write_2cyc_1L01_1S_1V : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV]> { 42306c3fb27SDimitry Andric let Latency = 2; 42406c3fb27SDimitry Andric let NumMicroOps = 3; 42506c3fb27SDimitry Andric} 42606c3fb27SDimitry Andric 42706c3fb27SDimitry Andricdef V2Write_2cyc_1L01_1S_1V01 : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV01]> { 42806c3fb27SDimitry Andric let Latency = 2; 42906c3fb27SDimitry Andric let NumMicroOps = 3; 43006c3fb27SDimitry Andric} 43106c3fb27SDimitry Andric 43206c3fb27SDimitry Andricdef V2Write_6cyc_3L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL]> { 43306c3fb27SDimitry Andric let Latency = 6; 43406c3fb27SDimitry Andric let NumMicroOps = 3; 43506c3fb27SDimitry Andric} 43606c3fb27SDimitry Andric 43706c3fb27SDimitry Andricdef V2Write_6cyc_3V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV]> { 43806c3fb27SDimitry Andric let Latency = 6; 43906c3fb27SDimitry Andric let NumMicroOps = 3; 44006c3fb27SDimitry Andric} 44106c3fb27SDimitry Andric 44206c3fb27SDimitry Andricdef V2Write_8cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> { 44306c3fb27SDimitry Andric let Latency = 8; 44406c3fb27SDimitry Andric let NumMicroOps = 3; 44506c3fb27SDimitry Andric} 44606c3fb27SDimitry Andric 44706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 44806c3fb27SDimitry Andric// Define generic 4 micro-op types 44906c3fb27SDimitry Andric 45006c3fb27SDimitry Andricdef V2Write_2cyc_1L01_2V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, 45106c3fb27SDimitry Andric V2UnitI]> { 45206c3fb27SDimitry Andric let Latency = 2; 45306c3fb27SDimitry Andric let NumMicroOps = 4; 45406c3fb27SDimitry Andric} 45506c3fb27SDimitry Andric 45606c3fb27SDimitry Andricdef V2Write_2cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, 45706c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 45806c3fb27SDimitry Andric let Latency = 2; 45906c3fb27SDimitry Andric let NumMicroOps = 4; 46006c3fb27SDimitry Andric} 46106c3fb27SDimitry Andric 46206c3fb27SDimitry Andricdef V2Write_4cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, 46306c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 46406c3fb27SDimitry Andric let Latency = 4; 46506c3fb27SDimitry Andric let NumMicroOps = 4; 46606c3fb27SDimitry Andric} 46706c3fb27SDimitry Andric 46806c3fb27SDimitry Andricdef V2Write_5cyc_1I_3L : SchedWriteRes<[V2UnitI, V2UnitL, V2UnitL, V2UnitL]> { 46906c3fb27SDimitry Andric let Latency = 5; 47006c3fb27SDimitry Andric let NumMicroOps = 4; 47106c3fb27SDimitry Andric} 47206c3fb27SDimitry Andric 47306c3fb27SDimitry Andricdef V2Write_9cyc_2L_2V1 : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV1, 47406c3fb27SDimitry Andric V2UnitV1]> { 47506c3fb27SDimitry Andric let Latency = 9; 47606c3fb27SDimitry Andric let NumMicroOps = 4; 47706c3fb27SDimitry Andric} 47806c3fb27SDimitry Andric 47906c3fb27SDimitry Andricdef V2Write_6cyc_4V0 : SchedWriteRes<[V2UnitV0, V2UnitV0, V2UnitV0, V2UnitV0]> { 48006c3fb27SDimitry Andric let Latency = 6; 48106c3fb27SDimitry Andric let NumMicroOps = 4; 48206c3fb27SDimitry Andric} 48306c3fb27SDimitry Andric 48406c3fb27SDimitry Andricdef V2Write_8cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { 48506c3fb27SDimitry Andric let Latency = 8; 48606c3fb27SDimitry Andric let NumMicroOps = 4; 48706c3fb27SDimitry Andric} 48806c3fb27SDimitry Andric 48906c3fb27SDimitry Andricdef V2Write_6cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, 49006c3fb27SDimitry Andric V2UnitV13]> { 49106c3fb27SDimitry Andric let Latency = 6; 49206c3fb27SDimitry Andric let NumMicroOps = 4; 49306c3fb27SDimitry Andric} 49406c3fb27SDimitry Andric 49506c3fb27SDimitry Andricdef V2Write_8cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, 49606c3fb27SDimitry Andric V2UnitV13]> { 49706c3fb27SDimitry Andric let Latency = 8; 49806c3fb27SDimitry Andric let NumMicroOps = 4; 49906c3fb27SDimitry Andric} 50006c3fb27SDimitry Andric 50106c3fb27SDimitry Andricdef V2Write_6cyc_4V02 : SchedWriteRes<[V2UnitV02, V2UnitV02, V2UnitV02, 50206c3fb27SDimitry Andric V2UnitV02]> { 50306c3fb27SDimitry Andric let Latency = 6; 50406c3fb27SDimitry Andric let NumMicroOps = 4; 50506c3fb27SDimitry Andric} 50606c3fb27SDimitry Andric 50706c3fb27SDimitry Andricdef V2Write_6cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { 50806c3fb27SDimitry Andric let Latency = 6; 50906c3fb27SDimitry Andric let NumMicroOps = 4; 51006c3fb27SDimitry Andric} 51106c3fb27SDimitry Andric 51206c3fb27SDimitry Andricdef V2Write_8cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> { 51306c3fb27SDimitry Andric let Latency = 8; 51406c3fb27SDimitry Andric let NumMicroOps = 4; 51506c3fb27SDimitry Andric} 51606c3fb27SDimitry Andric 51706c3fb27SDimitry Andricdef V2Write_9cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> { 51806c3fb27SDimitry Andric let Latency = 9; 51906c3fb27SDimitry Andric let NumMicroOps = 4; 52006c3fb27SDimitry Andric} 52106c3fb27SDimitry Andric 52206c3fb27SDimitry Andricdef V2Write_2cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV, 52306c3fb27SDimitry Andric V2UnitV]> { 52406c3fb27SDimitry Andric let Latency = 2; 52506c3fb27SDimitry Andric let NumMicroOps = 4; 52606c3fb27SDimitry Andric} 52706c3fb27SDimitry Andric 52806c3fb27SDimitry Andricdef V2Write_4cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV, 52906c3fb27SDimitry Andric V2UnitV]> { 53006c3fb27SDimitry Andric let Latency = 4; 53106c3fb27SDimitry Andric let NumMicroOps = 4; 53206c3fb27SDimitry Andric} 53306c3fb27SDimitry Andric 53406c3fb27SDimitry Andricdef V2Write_8cyc_2M0_2V02 : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitV02, 53506c3fb27SDimitry Andric V2UnitV02]> { 53606c3fb27SDimitry Andric let Latency = 8; 53706c3fb27SDimitry Andric let NumMicroOps = 4; 53806c3fb27SDimitry Andric} 53906c3fb27SDimitry Andric 54006c3fb27SDimitry Andricdef V2Write_8cyc_2V_2V1 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV1, 54106c3fb27SDimitry Andric V2UnitV1]> { 54206c3fb27SDimitry Andric let Latency = 8; 54306c3fb27SDimitry Andric let NumMicroOps = 4; 54406c3fb27SDimitry Andric} 54506c3fb27SDimitry Andric 54606c3fb27SDimitry Andricdef V2Write_4cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM, 54706c3fb27SDimitry Andric V2UnitM]> { 54806c3fb27SDimitry Andric let Latency = 4; 54906c3fb27SDimitry Andric let NumMicroOps = 4; 55006c3fb27SDimitry Andric} 55106c3fb27SDimitry Andric 55206c3fb27SDimitry Andricdef V2Write_5cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM, 55306c3fb27SDimitry Andric V2UnitM]> { 55406c3fb27SDimitry Andric let Latency = 5; 55506c3fb27SDimitry Andric let NumMicroOps = 4; 55606c3fb27SDimitry Andric} 55706c3fb27SDimitry Andric 55806c3fb27SDimitry Andricdef V2Write_6cyc_2I_2L : SchedWriteRes<[V2UnitI, V2UnitI, V2UnitL, V2UnitL]> { 55906c3fb27SDimitry Andric let Latency = 6; 56006c3fb27SDimitry Andric let NumMicroOps = 4; 56106c3fb27SDimitry Andric} 56206c3fb27SDimitry Andric 56306c3fb27SDimitry Andricdef V2Write_7cyc_4L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL]> { 56406c3fb27SDimitry Andric let Latency = 7; 56506c3fb27SDimitry Andric let NumMicroOps = 4; 56606c3fb27SDimitry Andric} 56706c3fb27SDimitry Andric 56806c3fb27SDimitry Andricdef V2Write_6cyc_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, 56906c3fb27SDimitry Andric V2UnitV01]> { 57006c3fb27SDimitry Andric let Latency = 6; 57106c3fb27SDimitry Andric let NumMicroOps = 4; 57206c3fb27SDimitry Andric} 57306c3fb27SDimitry Andric 57406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 57506c3fb27SDimitry Andric// Define generic 5 micro-op types 57606c3fb27SDimitry Andric 57706c3fb27SDimitry Andricdef V2Write_2cyc_1L01_2V01_2I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01, 57806c3fb27SDimitry Andric V2UnitI, V2UnitI]> { 57906c3fb27SDimitry Andric let Latency = 2; 58006c3fb27SDimitry Andric let NumMicroOps = 5; 58106c3fb27SDimitry Andric} 58206c3fb27SDimitry Andric 58306c3fb27SDimitry Andricdef V2Write_8cyc_2L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV, 58406c3fb27SDimitry Andric V2UnitV]> { 58506c3fb27SDimitry Andric let Latency = 8; 58606c3fb27SDimitry Andric let NumMicroOps = 5; 58706c3fb27SDimitry Andric} 58806c3fb27SDimitry Andric 58906c3fb27SDimitry Andricdef V2Write_9cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, 59006c3fb27SDimitry Andric V2UnitV]> { 59106c3fb27SDimitry Andric let Latency = 9; 59206c3fb27SDimitry Andric let NumMicroOps = 5; 59306c3fb27SDimitry Andric} 59406c3fb27SDimitry Andric 59506c3fb27SDimitry Andricdef V2Write_10cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, 59606c3fb27SDimitry Andric V2UnitV]> { 59706c3fb27SDimitry Andric let Latency = 10; 59806c3fb27SDimitry Andric let NumMicroOps = 5; 59906c3fb27SDimitry Andric} 60006c3fb27SDimitry Andric 60106c3fb27SDimitry Andricdef V2Write_6cyc_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV, 60206c3fb27SDimitry Andric V2UnitV]> { 60306c3fb27SDimitry Andric let Latency = 6; 60406c3fb27SDimitry Andric let NumMicroOps = 5; 60506c3fb27SDimitry Andric} 60606c3fb27SDimitry Andric 60706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 60806c3fb27SDimitry Andric// Define generic 6 micro-op types 60906c3fb27SDimitry Andric 61006c3fb27SDimitry Andricdef V2Write_8cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 61106c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 61206c3fb27SDimitry Andric let Latency = 8; 61306c3fb27SDimitry Andric let NumMicroOps = 6; 61406c3fb27SDimitry Andric} 61506c3fb27SDimitry Andric 61606c3fb27SDimitry Andricdef V2Write_9cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 61706c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 61806c3fb27SDimitry Andric let Latency = 9; 61906c3fb27SDimitry Andric let NumMicroOps = 6; 62006c3fb27SDimitry Andric} 62106c3fb27SDimitry Andric 62206c3fb27SDimitry Andricdef V2Write_9cyc_2L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, 62306c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 62406c3fb27SDimitry Andric let Latency = 9; 62506c3fb27SDimitry Andric let NumMicroOps = 6; 62606c3fb27SDimitry Andric} 62706c3fb27SDimitry Andric 62806c3fb27SDimitry Andricdef V2Write_9cyc_2L_2V_2S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, 62906c3fb27SDimitry Andric V2UnitV, V2UnitS, V2UnitS]> { 63006c3fb27SDimitry Andric let Latency = 9; 63106c3fb27SDimitry Andric let NumMicroOps = 6; 63206c3fb27SDimitry Andric} 63306c3fb27SDimitry Andric 63406c3fb27SDimitry Andricdef V2Write_9cyc_2V_4V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13, 63506c3fb27SDimitry Andric V2UnitV13, V2UnitV13, V2UnitV13]> { 63606c3fb27SDimitry Andric let Latency = 9; 63706c3fb27SDimitry Andric let NumMicroOps = 6; 63806c3fb27SDimitry Andric} 63906c3fb27SDimitry Andric 64006c3fb27SDimitry Andricdef V2Write_2cyc_3L01_3V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 64106c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 64206c3fb27SDimitry Andric let Latency = 2; 64306c3fb27SDimitry Andric let NumMicroOps = 6; 64406c3fb27SDimitry Andric} 64506c3fb27SDimitry Andric 64606c3fb27SDimitry Andricdef V2Write_4cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, 64706c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 64806c3fb27SDimitry Andric let Latency = 4; 64906c3fb27SDimitry Andric let NumMicroOps = 6; 65006c3fb27SDimitry Andric} 65106c3fb27SDimitry Andric 65206c3fb27SDimitry Andricdef V2Write_5cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, 65306c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 65406c3fb27SDimitry Andric let Latency = 5; 65506c3fb27SDimitry Andric let NumMicroOps = 6; 65606c3fb27SDimitry Andric} 65706c3fb27SDimitry Andric 65806c3fb27SDimitry Andricdef V2Write_2cyc_3L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 65906c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 66006c3fb27SDimitry Andric let Latency = 2; 66106c3fb27SDimitry Andric let NumMicroOps = 6; 66206c3fb27SDimitry Andric} 66306c3fb27SDimitry Andric 66406c3fb27SDimitry Andricdef V2Write_4cyc_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS, 66506c3fb27SDimitry Andric V2UnitS, V2UnitV01, V2UnitV01]> { 66606c3fb27SDimitry Andric let Latency = 4; 66706c3fb27SDimitry Andric let NumMicroOps = 6; 66806c3fb27SDimitry Andric} 66906c3fb27SDimitry Andric 67006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 67106c3fb27SDimitry Andric// Define generic 7 micro-op types 67206c3fb27SDimitry Andric 67306c3fb27SDimitry Andricdef V2Write_8cyc_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 67406c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { 67506c3fb27SDimitry Andric let Latency = 8; 67606c3fb27SDimitry Andric let NumMicroOps = 7; 67706c3fb27SDimitry Andric} 67806c3fb27SDimitry Andric 67906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 68006c3fb27SDimitry Andric// Define generic 8 micro-op types 68106c3fb27SDimitry Andric 68206c3fb27SDimitry Andricdef V2Write_2cyc_4L01_4V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 68306c3fb27SDimitry Andric V2UnitL01, V2UnitV, V2UnitV, V2UnitV, 68406c3fb27SDimitry Andric V2UnitV]> { 68506c3fb27SDimitry Andric let Latency = 2; 68606c3fb27SDimitry Andric let NumMicroOps = 8; 68706c3fb27SDimitry Andric} 68806c3fb27SDimitry Andric 68906c3fb27SDimitry Andricdef V2Write_2cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 69006c3fb27SDimitry Andric V2UnitL01, V2UnitV01, V2UnitV01, 69106c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 69206c3fb27SDimitry Andric let Latency = 2; 69306c3fb27SDimitry Andric let NumMicroOps = 8; 69406c3fb27SDimitry Andric} 69506c3fb27SDimitry Andric 69606c3fb27SDimitry Andricdef V2Write_4cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 69706c3fb27SDimitry Andric V2UnitL01, V2UnitV01, V2UnitV01, 69806c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 69906c3fb27SDimitry Andric let Latency = 4; 70006c3fb27SDimitry Andric let NumMicroOps = 8; 70106c3fb27SDimitry Andric} 70206c3fb27SDimitry Andric 70306c3fb27SDimitry Andricdef V2Write_6cyc_2L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01, 70406c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 70506c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 70606c3fb27SDimitry Andric let Latency = 6; 70706c3fb27SDimitry Andric let NumMicroOps = 8; 70806c3fb27SDimitry Andric} 70906c3fb27SDimitry Andric 71006c3fb27SDimitry Andricdef V2Write_8cyc_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL, 71106c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, V2UnitV]> { 71206c3fb27SDimitry Andric let Latency = 8; 71306c3fb27SDimitry Andric let NumMicroOps = 8; 71406c3fb27SDimitry Andric} 71506c3fb27SDimitry Andric 71606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 71706c3fb27SDimitry Andric// Define generic 9 micro-op types 71806c3fb27SDimitry Andric 71906c3fb27SDimitry Andricdef V2Write_6cyc_3L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 72006c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 72106c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 72206c3fb27SDimitry Andric let Latency = 6; 72306c3fb27SDimitry Andric let NumMicroOps = 9; 72406c3fb27SDimitry Andric} 72506c3fb27SDimitry Andric 72606c3fb27SDimitry Andricdef V2Write_10cyc_1L_8V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV, 72706c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, V2UnitV, 72806c3fb27SDimitry Andric V2UnitV]> { 72906c3fb27SDimitry Andric let Latency = 10; 73006c3fb27SDimitry Andric let NumMicroOps = 9; 73106c3fb27SDimitry Andric} 73206c3fb27SDimitry Andric 73306c3fb27SDimitry Andricdef V2Write_10cyc_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, 73406c3fb27SDimitry Andric V2UnitL, V2UnitL, V2UnitL, 73506c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS]> { 73606c3fb27SDimitry Andric let Latency = 10; 73706c3fb27SDimitry Andric let NumMicroOps = 9; 73806c3fb27SDimitry Andric} 73906c3fb27SDimitry Andric 74006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 74106c3fb27SDimitry Andric// Define generic 10 micro-op types 74206c3fb27SDimitry Andric 74306c3fb27SDimitry Andricdef V2Write_9cyc_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL, 74406c3fb27SDimitry Andric V2UnitL, V2UnitL, V2UnitV, V2UnitV, 74506c3fb27SDimitry Andric V2UnitV, V2UnitV]> { 74606c3fb27SDimitry Andric let Latency = 9; 74706c3fb27SDimitry Andric let NumMicroOps = 10; 74806c3fb27SDimitry Andric} 74906c3fb27SDimitry Andric 75006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 75106c3fb27SDimitry Andric// Define generic 12 micro-op types 75206c3fb27SDimitry Andric 75306c3fb27SDimitry Andricdef V2Write_5cyc_4L01_8V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 75406c3fb27SDimitry Andric V2UnitL01, V2UnitV01, V2UnitV01, 75506c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 75606c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 75706c3fb27SDimitry Andric let Latency = 5; 75806c3fb27SDimitry Andric let NumMicroOps = 12; 75906c3fb27SDimitry Andric} 76006c3fb27SDimitry Andric 76106c3fb27SDimitry Andricdef V2Write_9cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 76206c3fb27SDimitry Andric V2UnitL, V2UnitV, V2UnitV, 76306c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, 76406c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 76506c3fb27SDimitry Andric let Latency = 9; 76606c3fb27SDimitry Andric let NumMicroOps = 12; 76706c3fb27SDimitry Andric} 76806c3fb27SDimitry Andric 76906c3fb27SDimitry Andricdef V2Write_10cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 77006c3fb27SDimitry Andric V2UnitL, V2UnitV, V2UnitV, 77106c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, 77206c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV]> { 77306c3fb27SDimitry Andric let Latency = 10; 77406c3fb27SDimitry Andric let NumMicroOps = 12; 77506c3fb27SDimitry Andric} 77606c3fb27SDimitry Andric 77706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 77806c3fb27SDimitry Andric// Define generic 16 micro-op types 77906c3fb27SDimitry Andric 78006c3fb27SDimitry Andricdef V2Write_7cyc_4L01_12V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 78106c3fb27SDimitry Andric V2UnitL01, V2UnitV01, V2UnitV01, 78206c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 78306c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 78406c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 78506c3fb27SDimitry Andric V2UnitV01]> { 78606c3fb27SDimitry Andric let Latency = 7; 78706c3fb27SDimitry Andric let NumMicroOps = 16; 78806c3fb27SDimitry Andric} 78906c3fb27SDimitry Andric 79006c3fb27SDimitry Andricdef V2Write_10cyc_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, 79106c3fb27SDimitry Andric V2UnitL, V2UnitV, V2UnitV, 79206c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, 79306c3fb27SDimitry Andric V2UnitV, V2UnitV, V2UnitV, 79406c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 79506c3fb27SDimitry Andric V2UnitS]> { 79606c3fb27SDimitry Andric let Latency = 10; 79706c3fb27SDimitry Andric let NumMicroOps = 16; 79806c3fb27SDimitry Andric} 79906c3fb27SDimitry Andric 80006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 80106c3fb27SDimitry Andric// Define generic 18 micro-op types 80206c3fb27SDimitry Andric 80306c3fb27SDimitry Andricdef V2Write_7cyc_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 80406c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 80506c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 80606c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 80706c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 80806c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01]> { 80906c3fb27SDimitry Andric let Latency = 7; 81006c3fb27SDimitry Andric let NumMicroOps = 18; 81106c3fb27SDimitry Andric} 81206c3fb27SDimitry Andric 81306c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 81406c3fb27SDimitry Andric// Define generic 27 micro-op types 81506c3fb27SDimitry Andric 81606c3fb27SDimitry Andricdef V2Write_7cyc_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 81706c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 81806c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 81906c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 82006c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 82106c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 82206c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 82306c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 82406c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 82506c3fb27SDimitry Andric V2UnitV01]> { 82606c3fb27SDimitry Andric let Latency = 7; 82706c3fb27SDimitry Andric let NumMicroOps = 27; 82806c3fb27SDimitry Andric} 82906c3fb27SDimitry Andric 83006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 83106c3fb27SDimitry Andric// Define generic 36 micro-op types 83206c3fb27SDimitry Andric 83306c3fb27SDimitry Andricdef V2Write_11cyc_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01, 83406c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 83506c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 83606c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 83706c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 83806c3fb27SDimitry Andric V2UnitL01, V2UnitL01, V2UnitL01, 83906c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 84006c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 84106c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 84206c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 84306c3fb27SDimitry Andric V2UnitV01, V2UnitV01, V2UnitV01, 84406c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 84506c3fb27SDimitry Andric V2UnitV01]> { 84606c3fb27SDimitry Andric let Latency = 11; 84706c3fb27SDimitry Andric let NumMicroOps = 36; 84806c3fb27SDimitry Andric} 84906c3fb27SDimitry Andric 85006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 85106c3fb27SDimitry Andric// Define generic 54 micro-op types 85206c3fb27SDimitry Andric 85306c3fb27SDimitry Andricdef V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, 85406c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 85506c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 85606c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 85706c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 85806c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 85906c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 86006c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 86106c3fb27SDimitry Andric V2UnitL01, V2UnitL01, 86206c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86306c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86406c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86506c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86606c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86706c3fb27SDimitry Andric V2UnitS, V2UnitS, V2UnitS, 86806c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 86906c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87006c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87106c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87206c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87306c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87406c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87506c3fb27SDimitry Andric V2UnitV01, V2UnitV01, 87606c3fb27SDimitry Andric V2UnitV01, V2UnitV01]> { 87706c3fb27SDimitry Andric let Latency = 11; 87806c3fb27SDimitry Andric let NumMicroOps = 54; 87906c3fb27SDimitry Andric} 88006c3fb27SDimitry Andric 88106c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 88206c3fb27SDimitry Andric// Define predicate-controlled types 88306c3fb27SDimitry Andric 88406c3fb27SDimitry Andricdef V2Write_ArithI : SchedWriteVariant<[ 88506c3fb27SDimitry Andric SchedVar<IsCheapLSL, [V2Write_1cyc_1I]>, 88606c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>; 88706c3fb27SDimitry Andric 88806c3fb27SDimitry Andricdef V2Write_ArithF : SchedWriteVariant<[ 88906c3fb27SDimitry Andric SchedVar<IsCheapLSL, [V2Write_1cyc_1F]>, 89006c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>; 89106c3fb27SDimitry Andric 89206c3fb27SDimitry Andricdef V2Write_Logical : SchedWriteVariant<[ 89306c3fb27SDimitry Andric SchedVar<NeoverseNoLSL, [V2Write_1cyc_1F]>, 89406c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>; 89506c3fb27SDimitry Andric 89606c3fb27SDimitry Andricdef V2Write_Extr : SchedWriteVariant<[ 89706c3fb27SDimitry Andric SchedVar<IsRORImmIdiomPred, [V2Write_1cyc_1I]>, 89806c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_3cyc_1I_1M]>]>; 89906c3fb27SDimitry Andric 90006c3fb27SDimitry Andricdef V2Write_LdrHQ : SchedWriteVariant<[ 90106c3fb27SDimitry Andric SchedVar<NeoverseHQForm, [V2Write_7cyc_1I_1L]>, 90206c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_6cyc_1L]>]>; 90306c3fb27SDimitry Andric 90406c3fb27SDimitry Andricdef V2Write_StrHQ : SchedWriteVariant<[ 90506c3fb27SDimitry Andric SchedVar<NeoverseHQForm, [V2Write_2cyc_1L01_1V01_1I]>, 90606c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1L01_1V01]>]>; 90706c3fb27SDimitry Andric 9085f757f3fSDimitry Andricdef V2Write_0or1cyc_1I : SchedWriteVariant<[ 9095f757f3fSDimitry Andric SchedVar<NeoverseZeroMove, [V2Write_0cyc]>, 9105f757f3fSDimitry Andric SchedVar<NoSchedPred, [V2Write_1cyc_1I]>]>; 9115f757f3fSDimitry Andric 9125f757f3fSDimitry Andricdef V2Write_0or2cyc_1V : SchedWriteVariant<[ 9135f757f3fSDimitry Andric SchedVar<NeoverseZeroMove, [V2Write_0cyc]>, 9145f757f3fSDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1V]>]>; 9155f757f3fSDimitry Andric 9165f757f3fSDimitry Andricdef V2Write_0or3cyc_1M0 : SchedWriteVariant<[ 9175f757f3fSDimitry Andric SchedVar<NeoverseZeroMove, [V2Write_0cyc]>, 9185f757f3fSDimitry Andric SchedVar<NoSchedPred, [V2Write_3cyc_1M0]>]>; 9195f757f3fSDimitry Andric 92006c3fb27SDimitry Andricdef V2Write_2or3cyc_1M : SchedWriteVariant<[ 92106c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_3cyc_1M]>, 92206c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>; 92306c3fb27SDimitry Andric 92406c3fb27SDimitry Andricdef V2Write_3or4cyc_2M : SchedWriteVariant<[ 92506c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_4cyc_2M]>, 92606c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_3cyc_2M]>]>; 92706c3fb27SDimitry Andric 92806c3fb27SDimitry Andricdef V2Write_1or2cyc_1M0 : SchedWriteVariant<[ 92906c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_2cyc_1M0]>, 93006c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_1cyc_1M0]>]>; 93106c3fb27SDimitry Andric 93206c3fb27SDimitry Andricdef V2Write_2or3cyc_1M0 : SchedWriteVariant<[ 93306c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_3cyc_1M0]>, 93406c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M0]>]>; 93506c3fb27SDimitry Andric 93606c3fb27SDimitry Andricdef V2Write_1or2cyc_1M0_1M : SchedWriteVariant<[ 93706c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_2cyc_1M0_1M]>, 93806c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_1cyc_1M0_1M]>]>; 93906c3fb27SDimitry Andric 94006c3fb27SDimitry Andricdef V2Write_3or4cyc_1M0_1M : SchedWriteVariant<[ 94106c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_4cyc_1M0_1M]>, 94206c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_3cyc_1M0_1M]>]>; 94306c3fb27SDimitry Andric 94406c3fb27SDimitry Andricdef V2Write_4or5cyc_2M0_2M : SchedWriteVariant<[ 94506c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_5cyc_2M0_2M]>, 94606c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_4cyc_2M0_2M]>]>; 94706c3fb27SDimitry Andric 94806c3fb27SDimitry Andricdef V2Write_4or5cyc_1V0_1M0 : SchedWriteVariant<[ 94906c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_5cyc_1V0_1M0]>, 95006c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_4cyc_1V0_1M0]>]>; 95106c3fb27SDimitry Andric 95206c3fb27SDimitry Andricdef V2Write_2or3cyc_1V0_1M : SchedWriteVariant<[ 95306c3fb27SDimitry Andric SchedVar<NeoversePdIsPg, [V2Write_3cyc_1V0_1M]>, 95406c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1V0_1M]>]>; 95506c3fb27SDimitry Andric 95606c3fb27SDimitry Andricdef V2Write_IncDec : SchedWriteVariant<[ 95706c3fb27SDimitry Andric SchedVar<NeoverseCheapIncDec, [V2Write_1cyc_1F]>, 95806c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>; 95906c3fb27SDimitry Andric 96006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 96106c3fb27SDimitry Andric// Define forwarded types 96206c3fb27SDimitry Andric 96306c3fb27SDimitry Andric// NOTE: SOG, p. 16, n. 2: Accumulator forwarding is not supported for 96406c3fb27SDimitry Andric// consumers of 64 bit multiply high operations? 96506c3fb27SDimitry Andricdef V2Wr_IM : SchedWriteRes<[V2UnitM]> { let Latency = 2; } 96606c3fb27SDimitry Andricdef V2Wr_IMA : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } 96706c3fb27SDimitry Andricdef V2Wr_IMUL : SchedWriteVariant<[ 96806c3fb27SDimitry Andric SchedVar<IsReg3ZeroPred, [V2Wr_IM]>, 96906c3fb27SDimitry Andric SchedVar<NoSchedPred, [V2Wr_IMA]>]>; 97006c3fb27SDimitry Andricdef V2Rd_IMA : SchedReadAdvance<1, [V2Wr_IMA]>; 97106c3fb27SDimitry Andric 97206c3fb27SDimitry Andricdef V2Wr_FMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 97306c3fb27SDimitry Andricdef V2Rd_FMA : SchedReadAdvance<2, [WriteFMul, V2Wr_FMA]>; 97406c3fb27SDimitry Andric 97506c3fb27SDimitry Andricdef V2Wr_VA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 97606c3fb27SDimitry Andricdef V2Rd_VA : SchedReadAdvance<3, [V2Wr_VA]>; 97706c3fb27SDimitry Andric 97806c3fb27SDimitry Andricdef V2Wr_VDOT : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 97906c3fb27SDimitry Andricdef V2Rd_VDOT : SchedReadAdvance<2, [V2Wr_VDOT]>; 98006c3fb27SDimitry Andric 98106c3fb27SDimitry Andricdef V2Wr_VMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 98206c3fb27SDimitry Andricdef V2Rd_VMMA : SchedReadAdvance<2, [V2Wr_VMMA]>; 98306c3fb27SDimitry Andric 98406c3fb27SDimitry Andricdef V2Wr_VMA : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 98506c3fb27SDimitry Andricdef V2Rd_VMA : SchedReadAdvance<3, [V2Wr_VMA]>; 98606c3fb27SDimitry Andric 98706c3fb27SDimitry Andricdef V2Wr_VMAH : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; } 98806c3fb27SDimitry Andricdef V2Rd_VMAH : SchedReadAdvance<2, [V2Wr_VMAH]>; 98906c3fb27SDimitry Andric 99006c3fb27SDimitry Andricdef V2Wr_VMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 99106c3fb27SDimitry Andricdef V2Rd_VMAL : SchedReadAdvance<3, [V2Wr_VMAL]>; 99206c3fb27SDimitry Andric 99306c3fb27SDimitry Andricdef V2Wr_VPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 99406c3fb27SDimitry Andricdef V2Rd_VPA : SchedReadAdvance<3, [V2Wr_VPA]>; 99506c3fb27SDimitry Andric 99606c3fb27SDimitry Andricdef V2Wr_VSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 99706c3fb27SDimitry Andricdef V2Rd_VSA : SchedReadAdvance<3, [V2Wr_VSA]>; 99806c3fb27SDimitry Andric 99906c3fb27SDimitry Andricdef V2Wr_VFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 100006c3fb27SDimitry Andricdef V2Rd_VFCMA : SchedReadAdvance<2, [V2Wr_VFCMA]>; 100106c3fb27SDimitry Andric 100206c3fb27SDimitry Andricdef V2Wr_VFM : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 100306c3fb27SDimitry Andricdef V2Wr_VFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 100406c3fb27SDimitry Andricdef V2Rd_VFMA : SchedReadAdvance<2, [V2Wr_VFM, V2Wr_VFMA]>; 100506c3fb27SDimitry Andric 100606c3fb27SDimitry Andricdef V2Wr_VFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 100706c3fb27SDimitry Andricdef V2Rd_VFMAL : SchedReadAdvance<2, [V2Wr_VFMAL]>; 100806c3fb27SDimitry Andric 100906c3fb27SDimitry Andricdef V2Wr_VBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 101006c3fb27SDimitry Andricdef V2Rd_VBFDOT : SchedReadAdvance<2, [V2Wr_VBFDOT]>; 101106c3fb27SDimitry Andricdef V2Wr_VBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; } 101206c3fb27SDimitry Andricdef V2Rd_VBFMMA : SchedReadAdvance<2, [V2Wr_VBFMMA]>; 101306c3fb27SDimitry Andricdef V2Wr_VBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 101406c3fb27SDimitry Andricdef V2Rd_VBFMAL : SchedReadAdvance<3, [V2Wr_VBFMAL]>; 101506c3fb27SDimitry Andric 101606c3fb27SDimitry Andricdef V2Wr_CRC : SchedWriteRes<[V2UnitM0]> { let Latency = 2; } 101706c3fb27SDimitry Andricdef V2Rd_CRC : SchedReadAdvance<1, [V2Wr_CRC]>; 101806c3fb27SDimitry Andric 101906c3fb27SDimitry Andricdef V2Wr_ZA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 102006c3fb27SDimitry Andricdef V2Rd_ZA : SchedReadAdvance<3, [V2Wr_ZA]>; 102106c3fb27SDimitry Andricdef V2Wr_ZPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 102206c3fb27SDimitry Andricdef V2Rd_ZPA : SchedReadAdvance<3, [V2Wr_ZPA]>; 102306c3fb27SDimitry Andricdef V2Wr_ZSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; } 102406c3fb27SDimitry Andricdef V2Rd_ZSA : SchedReadAdvance<3, [V2Wr_ZSA]>; 102506c3fb27SDimitry Andric 102606c3fb27SDimitry Andricdef V2Wr_ZDOTB : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 102706c3fb27SDimitry Andricdef V2Rd_ZDOTB : SchedReadAdvance<2, [V2Wr_ZDOTB]>; 102806c3fb27SDimitry Andricdef V2Wr_ZDOTH : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 102906c3fb27SDimitry Andricdef V2Rd_ZDOTH : SchedReadAdvance<3, [V2Wr_ZDOTH]>; 103006c3fb27SDimitry Andric 103106c3fb27SDimitry Andric// NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce 103206c3fb27SDimitry Andric// throughput to 1 in case of forwarding? 103306c3fb27SDimitry Andricdef V2Wr_ZCMABHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 103406c3fb27SDimitry Andricdef V2Rd_ZCMABHS : SchedReadAdvance<3, [V2Wr_ZCMABHS]>; 103506c3fb27SDimitry Andricdef V2Wr_ZCMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } 103606c3fb27SDimitry Andricdef V2Rd_ZCMAD : SchedReadAdvance<2, [V2Wr_ZCMAD]>; 103706c3fb27SDimitry Andric 103806c3fb27SDimitry Andricdef V2Wr_ZMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; } 103906c3fb27SDimitry Andricdef V2Rd_ZMMA : SchedReadAdvance<2, [V2Wr_ZMMA]>; 104006c3fb27SDimitry Andric 104106c3fb27SDimitry Andricdef V2Wr_ZMABHS : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; } 104206c3fb27SDimitry Andricdef V2Rd_ZMABHS : SchedReadAdvance<3, [V2Wr_ZMABHS]>; 104306c3fb27SDimitry Andricdef V2Wr_ZMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } 104406c3fb27SDimitry Andricdef V2Rd_ZMAD : SchedReadAdvance<2, [V2Wr_ZMAD]>; 104506c3fb27SDimitry Andric 104606c3fb27SDimitry Andricdef V2Wr_ZMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 104706c3fb27SDimitry Andricdef V2Rd_ZMAL : SchedReadAdvance<3, [V2Wr_ZMAL]>; 104806c3fb27SDimitry Andric 104906c3fb27SDimitry Andricdef V2Wr_ZMASQL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 105006c3fb27SDimitry Andricdef V2Wr_ZMASQBHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; } 105106c3fb27SDimitry Andricdef V2Wr_ZMASQD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; } 105206c3fb27SDimitry Andricdef V2Rd_ZMASQ : SchedReadAdvance<2, [V2Wr_ZMASQL, V2Wr_ZMASQBHS, 105306c3fb27SDimitry Andric V2Wr_ZMASQD]>; 105406c3fb27SDimitry Andric 105506c3fb27SDimitry Andricdef V2Wr_ZFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 105606c3fb27SDimitry Andricdef V2Rd_ZFCMA : SchedReadAdvance<3, [V2Wr_ZFCMA]>; 105706c3fb27SDimitry Andric 105806c3fb27SDimitry Andricdef V2Wr_ZFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 105906c3fb27SDimitry Andricdef V2Rd_ZFMA : SchedReadAdvance<2, [V2Wr_ZFMA]>; 106006c3fb27SDimitry Andric 106106c3fb27SDimitry Andricdef V2Wr_ZFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; } 106206c3fb27SDimitry Andricdef V2Rd_ZFMAL : SchedReadAdvance<2, [V2Wr_ZFMAL]>; 106306c3fb27SDimitry Andric 106406c3fb27SDimitry Andricdef V2Wr_ZBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 106506c3fb27SDimitry Andricdef V2Rd_ZBFDOT : SchedReadAdvance<2, [V2Wr_ZBFDOT]>; 106606c3fb27SDimitry Andricdef V2Wr_ZBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; } 106706c3fb27SDimitry Andricdef V2Rd_ZBFMMA : SchedReadAdvance<2, [V2Wr_ZBFMMA]>; 106806c3fb27SDimitry Andricdef V2Wr_ZBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; } 106906c3fb27SDimitry Andricdef V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>; 107006c3fb27SDimitry Andric 107106c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 107206c3fb27SDimitry Andric// Define types with long resource cycles (rc) 107306c3fb27SDimitry Andric 10745f757f3fSDimitry Andricdef V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; } 10755f757f3fSDimitry Andricdef V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; } 10765f757f3fSDimitry Andricdef V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; } 10775f757f3fSDimitry Andricdef V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; } 10785f757f3fSDimitry Andricdef V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; } 10795f757f3fSDimitry Andricdef V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ReleaseAtCycles = [ 9]; } 10805f757f3fSDimitry Andricdef V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; } 10815f757f3fSDimitry Andricdef V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ReleaseAtCycles = [12]; } 10825f757f3fSDimitry Andricdef V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; } 10835f757f3fSDimitry Andricdef V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; } 10845f757f3fSDimitry Andricdef V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; } 10855f757f3fSDimitry Andricdef V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; } 10865f757f3fSDimitry Andricdef V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ReleaseAtCycles = [14]; } 108706c3fb27SDimitry Andric 108806c3fb27SDimitry Andric// Miscellaneous 108906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 109006c3fb27SDimitry Andric 109106c3fb27SDimitry Andricdef : InstRW<[WriteI], (instrs COPY)>; 109206c3fb27SDimitry Andric 109306c3fb27SDimitry Andric// §3.3 Branch instructions 109406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 109506c3fb27SDimitry Andric 109606c3fb27SDimitry Andric// Branch, immed 109706c3fb27SDimitry Andric// Compare and branch 109806c3fb27SDimitry Andricdef : SchedAlias<WriteBr, V2Write_1cyc_1B>; 109906c3fb27SDimitry Andric 110006c3fb27SDimitry Andric// Branch, register 110106c3fb27SDimitry Andricdef : SchedAlias<WriteBrReg, V2Write_1cyc_1B>; 110206c3fb27SDimitry Andric 110306c3fb27SDimitry Andric// Branch and link, immed 110406c3fb27SDimitry Andric// Branch and link, register 110506c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>; 110606c3fb27SDimitry Andric 110706c3fb27SDimitry Andric// §3.4 Arithmetic and Logical Instructions 110806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 110906c3fb27SDimitry Andric 111006c3fb27SDimitry Andric// ALU, basic 111106c3fb27SDimitry Andric// ALU, basic, flagset 111206c3fb27SDimitry Andricdef : SchedAlias<WriteI, V2Write_1cyc_1I>; 11135f757f3fSDimitry Andricdef : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>; 11145f757f3fSDimitry Andricdef : InstRW<[V2Write_0or1cyc_1I], (instregex "^MOVZ[WX]i$")>; 111506c3fb27SDimitry Andric 111606c3fb27SDimitry Andric// ALU, extend and shift 111706c3fb27SDimitry Andricdef : SchedAlias<WriteIEReg, V2Write_2cyc_1M>; 111806c3fb27SDimitry Andric 111906c3fb27SDimitry Andric// Arithmetic, LSL shift, shift <= 4 112006c3fb27SDimitry Andric// Arithmetic, flagset, LSL shift, shift <= 4 112106c3fb27SDimitry Andric// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4 112206c3fb27SDimitry Andricdef : SchedAlias<WriteISReg, V2Write_ArithI>; 112306c3fb27SDimitry Andricdef : InstRW<[V2Write_ArithF], 112406c3fb27SDimitry Andric (instregex "^(ADD|SUB)S[WX]rs$")>; 112506c3fb27SDimitry Andric 112606c3fb27SDimitry Andric// Arithmetic, immediate to logical address tag 112706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instrs ADDG, SUBG)>; 112806c3fb27SDimitry Andric 112906c3fb27SDimitry Andric// Convert floating-point condition flags 113006c3fb27SDimitry Andric// Flag manipulation instructions 113106c3fb27SDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 113206c3fb27SDimitry Andric 113306c3fb27SDimitry Andric// Insert Random Tags 113406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instrs IRG, IRGstack)>; 113506c3fb27SDimitry Andric 113606c3fb27SDimitry Andric// Insert Tag Mask 113706c3fb27SDimitry Andric// Subtract Pointer 113806c3fb27SDimitry Andric// Subtract Pointer, flagset 113906c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1I], (instrs GMI, SUBP, SUBPS)>; 114006c3fb27SDimitry Andric 114106c3fb27SDimitry Andric// Logical, shift, no flagset 11425f757f3fSDimitry Andricdef : InstRW<[V2Write_1cyc_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>; 11435f757f3fSDimitry Andricdef : InstRW<[V2Write_0or1cyc_1I], (instregex "^ORR[WX]rs$")>; 114406c3fb27SDimitry Andric 114506c3fb27SDimitry Andric// Logical, shift, flagset 114606c3fb27SDimitry Andricdef : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>; 114706c3fb27SDimitry Andric 114806c3fb27SDimitry Andric// Move and shift instructions 114906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 115006c3fb27SDimitry Andric 115106c3fb27SDimitry Andricdef : SchedAlias<WriteImm, V2Write_1cyc_1I>; 115206c3fb27SDimitry Andric 115306c3fb27SDimitry Andric// §3.5 Divide and multiply instructions 115406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 115506c3fb27SDimitry Andric 115606c3fb27SDimitry Andric// SDIV, UDIV 115706c3fb27SDimitry Andricdef : SchedAlias<WriteID32, V2Write_12cyc_1M0>; 115806c3fb27SDimitry Andricdef : SchedAlias<WriteID64, V2Write_20cyc_1M0>; 115906c3fb27SDimitry Andric 116006c3fb27SDimitry Andricdef : SchedAlias<WriteIM32, V2Write_2cyc_1M>; 116106c3fb27SDimitry Andricdef : SchedAlias<WriteIM64, V2Write_2cyc_1M>; 116206c3fb27SDimitry Andric 116306c3fb27SDimitry Andric// Multiply 116406c3fb27SDimitry Andric// Multiply accumulate, W-form 116506c3fb27SDimitry Andric// Multiply accumulate, X-form 116606c3fb27SDimitry Andricdef : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA], 116706c3fb27SDimitry Andric (instregex "^M(ADD|SUB)[WX]rrr$")>; 116806c3fb27SDimitry Andric 116906c3fb27SDimitry Andric// Multiply accumulate long 117006c3fb27SDimitry Andric// Multiply long 117106c3fb27SDimitry Andricdef : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA], 117206c3fb27SDimitry Andric (instregex "^(S|U)M(ADD|SUB)Lrrr$")>; 117306c3fb27SDimitry Andric 117406c3fb27SDimitry Andric// Multiply high 117506c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>; 117606c3fb27SDimitry Andric 117706c3fb27SDimitry Andric// Pointer Authentication Instructions (v8.3 PAC) 117806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 117906c3fb27SDimitry Andric 118006c3fb27SDimitry Andric// Authenticate data address 118106c3fb27SDimitry Andric// Authenticate instruction address 118206c3fb27SDimitry Andric// Compute pointer authentication code for data address 118306c3fb27SDimitry Andric// Compute pointer authentication code, using generic key 118406c3fb27SDimitry Andric// Compute pointer authentication code for instruction address 118506c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1M0], (instregex "^AUT", "^PAC")>; 118606c3fb27SDimitry Andric 118706c3fb27SDimitry Andric// Branch and link, register, with pointer authentication 118806c3fb27SDimitry Andric// Branch, register, with pointer authentication 118906c3fb27SDimitry Andric// Branch, return, with pointer authentication 119006c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA, 119106c3fb27SDimitry Andric BRAAZ, BRAB, BRABZ, RETAA, RETAB, 119206c3fb27SDimitry Andric ERETAA, ERETAB)>; 119306c3fb27SDimitry Andric 119406c3fb27SDimitry Andric 119506c3fb27SDimitry Andric// Load register, with pointer authentication 119606c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>; 119706c3fb27SDimitry Andric 119806c3fb27SDimitry Andric// Strip pointer authentication code 119906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M0], (instrs XPACD, XPACI, XPACLRI)>; 120006c3fb27SDimitry Andric 120106c3fb27SDimitry Andric// Miscellaneous data-processing instructions 120206c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 120306c3fb27SDimitry Andric 120406c3fb27SDimitry Andric// Address generation 120506c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1F], (instrs ADR, ADRP)>; 120606c3fb27SDimitry Andric 120706c3fb27SDimitry Andric// Bitfield extract, one reg 120806c3fb27SDimitry Andric// Bitfield extract, two regs 120906c3fb27SDimitry Andricdef : SchedAlias<WriteExtr, V2Write_Extr>; 121006c3fb27SDimitry Andricdef : InstRW<[V2Write_Extr], (instrs EXTRWrri, EXTRXrri)>; 121106c3fb27SDimitry Andric 121206c3fb27SDimitry Andric// Bitfield move, basic 121306c3fb27SDimitry Andricdef : SchedAlias<WriteIS, V2Write_1cyc_1I>; 121406c3fb27SDimitry Andric 121506c3fb27SDimitry Andric// Bitfield move, insert 121606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^BFM[WX]ri$")>; 121706c3fb27SDimitry Andric 121806c3fb27SDimitry Andric// Load instructions 121906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 122006c3fb27SDimitry Andric 122106c3fb27SDimitry Andric// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3. 122206c3fb27SDimitry Andric 122306c3fb27SDimitry Andricdef : SchedAlias<WriteLD, V2Write_4cyc_1L>; 122406c3fb27SDimitry Andricdef : SchedAlias<WriteLDIdx, V2Write_4cyc_1L>; 122506c3fb27SDimitry Andric 122606c3fb27SDimitry Andric// Load register, literal 122706c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>; 122806c3fb27SDimitry Andric 122906c3fb27SDimitry Andric// Load pair, signed immed offset, signed words 123006c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi], (instrs LDPSWi)>; 123106c3fb27SDimitry Andric 123206c3fb27SDimitry Andric// Load pair, immed post-index or immed pre-index, signed words 12335f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_5cyc_1I_3L, WriteLDHi], 123406c3fb27SDimitry Andric (instregex "^LDPSW(post|pre)$")>; 123506c3fb27SDimitry Andric 123606c3fb27SDimitry Andric// Store instructions 123706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 123806c3fb27SDimitry Andric 123906c3fb27SDimitry Andric// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I. 124006c3fb27SDimitry Andric 124106c3fb27SDimitry Andricdef : SchedAlias<WriteST, V2Write_1cyc_1L01_1D>; 124206c3fb27SDimitry Andricdef : SchedAlias<WriteSTIdx, V2Write_1cyc_1L01_1D>; 124306c3fb27SDimitry Andricdef : SchedAlias<WriteSTP, V2Write_1cyc_1L01_1D>; 12445f757f3fSDimitry Andricdef : SchedAlias<WriteAdr, V2Write_1cyc_1I>; 124506c3fb27SDimitry Andric 124606c3fb27SDimitry Andric// Tag load instructions 124706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 124806c3fb27SDimitry Andric 124906c3fb27SDimitry Andric// Load allocation tag 125006c3fb27SDimitry Andric// Load multiple allocation tags 125106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L], (instrs LDG, LDGM)>; 125206c3fb27SDimitry Andric 125306c3fb27SDimitry Andric// Tag store instructions 125406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 125506c3fb27SDimitry Andric 125606c3fb27SDimitry Andric// Store allocation tags to one or two granules, post-index 125706c3fb27SDimitry Andric// Store allocation tags to one or two granules, pre-index 125806c3fb27SDimitry Andric// Store allocation tag to one or two granules, zeroing, post-index 125906c3fb27SDimitry Andric// Store Allocation Tag to one or two granules, zeroing, pre-index 126006c3fb27SDimitry Andric// Store allocation tag and reg pair to memory, post-Index 126106c3fb27SDimitry Andric// Store allocation tag and reg pair to memory, pre-Index 126206c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex, 126306c3fb27SDimitry Andric ST2GPreIndex, ST2GPostIndex, 126406c3fb27SDimitry Andric STZGPreIndex, STZGPostIndex, 126506c3fb27SDimitry Andric STZ2GPreIndex, STZ2GPostIndex, 126606c3fb27SDimitry Andric STGPpre, STGPpost)>; 126706c3fb27SDimitry Andric 126806c3fb27SDimitry Andric// Store allocation tags to one or two granules, signed offset 126906c3fb27SDimitry Andric// Store allocation tag to two granules, zeroing, signed offset 127006c3fb27SDimitry Andric// Store allocation tag and reg pair to memory, signed offset 127106c3fb27SDimitry Andric// Store multiple allocation tags 127206c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi, 127306c3fb27SDimitry Andric STZ2Gi, STGPi, STGM, STZGM)>; 127406c3fb27SDimitry Andric 127506c3fb27SDimitry Andric// FP data processing instructions 127606c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 127706c3fb27SDimitry Andric 127806c3fb27SDimitry Andric// FP absolute value 127906c3fb27SDimitry Andric// FP arithmetic 128006c3fb27SDimitry Andric// FP min/max 128106c3fb27SDimitry Andric// FP negate 128206c3fb27SDimitry Andric// FP select 128306c3fb27SDimitry Andricdef : SchedAlias<WriteF, V2Write_2cyc_1V>; 128406c3fb27SDimitry Andric 128506c3fb27SDimitry Andric// FP compare 128606c3fb27SDimitry Andricdef : SchedAlias<WriteFCmp, V2Write_2cyc_1V0>; 128706c3fb27SDimitry Andric 128806c3fb27SDimitry Andric// FP divide, square root 128906c3fb27SDimitry Andricdef : SchedAlias<WriteFDiv, V2Write_7cyc_1V02>; 129006c3fb27SDimitry Andric 129106c3fb27SDimitry Andric// FP divide, H-form 129206c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1V02], (instrs FDIVHrr)>; 129306c3fb27SDimitry Andric// FP divide, S-form 129406c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02], (instrs FDIVSrr)>; 129506c3fb27SDimitry Andric// FP divide, D-form 129606c3fb27SDimitry Andricdef : InstRW<[V2Write_15cyc_1V02], (instrs FDIVDrr)>; 129706c3fb27SDimitry Andric 129806c3fb27SDimitry Andric// FP square root, H-form 129906c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1V02], (instrs FSQRTHr)>; 130006c3fb27SDimitry Andric// FP square root, S-form 130106c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1V02], (instrs FSQRTSr)>; 130206c3fb27SDimitry Andric// FP square root, D-form 130306c3fb27SDimitry Andricdef : InstRW<[V2Write_16cyc_1V02], (instrs FSQRTDr)>; 130406c3fb27SDimitry Andric 130506c3fb27SDimitry Andric// FP multiply 130606c3fb27SDimitry Andricdef : WriteRes<WriteFMul, [V2UnitV]> { let Latency = 3; } 130706c3fb27SDimitry Andric 130806c3fb27SDimitry Andric// FP multiply accumulate 130906c3fb27SDimitry Andricdef : InstRW<[V2Wr_FMA, ReadDefault, ReadDefault, V2Rd_FMA], 131006c3fb27SDimitry Andric (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>; 131106c3fb27SDimitry Andric 131206c3fb27SDimitry Andric// FP round to integral 131306c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$", 131406c3fb27SDimitry Andric "^FRINT(32|64)[XZ][SD]r$")>; 131506c3fb27SDimitry Andric 131606c3fb27SDimitry Andric// FP miscellaneous instructions 131706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 131806c3fb27SDimitry Andric 131906c3fb27SDimitry Andric// FP convert, from gen to vec reg 132006c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>; 132106c3fb27SDimitry Andric 132206c3fb27SDimitry Andric// FP convert, from vec to gen reg 132306c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V01], 132406c3fb27SDimitry Andric (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>; 132506c3fb27SDimitry Andric 132606c3fb27SDimitry Andric// FP convert, Javascript from vec to gen reg 132706c3fb27SDimitry Andricdef : SchedAlias<WriteFCvt, V2Write_3cyc_1V0>; 132806c3fb27SDimitry Andric 132906c3fb27SDimitry Andric// FP convert, from vec to vec reg 133006c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr, 133106c3fb27SDimitry Andric FCVTHDr, FCVTSDr, FCVTXNv1i64)>; 133206c3fb27SDimitry Andric 133306c3fb27SDimitry Andric// FP move, immed 133406c3fb27SDimitry Andric// FP move, register 133506c3fb27SDimitry Andricdef : SchedAlias<WriteFImm, V2Write_2cyc_1V>; 133606c3fb27SDimitry Andric 133706c3fb27SDimitry Andric// FP transfer, from gen to low half of vec reg 13385f757f3fSDimitry Andricdef : InstRW<[V2Write_0or3cyc_1M0], 13395f757f3fSDimitry Andric (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; 134006c3fb27SDimitry Andric 134106c3fb27SDimitry Andric// FP transfer, from gen to high half of vec reg 134206c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1M0_1V], (instrs FMOVXDHighr)>; 134306c3fb27SDimitry Andric 134406c3fb27SDimitry Andric// FP transfer, from vec to gen reg 134506c3fb27SDimitry Andricdef : SchedAlias<WriteFCopy, V2Write_2cyc_2V01>; 134606c3fb27SDimitry Andric 134706c3fb27SDimitry Andric// FP load instructions 134806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 134906c3fb27SDimitry Andric 135006c3fb27SDimitry Andric// Load vector reg, literal, S/D/Q forms 135106c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1F_1L], (instregex "^LDR[SDQ]l$")>; 135206c3fb27SDimitry Andric 135306c3fb27SDimitry Andric// Load vector reg, unscaled immed 135406c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LDUR[BHSDQ]i$")>; 135506c3fb27SDimitry Andric 135606c3fb27SDimitry Andric// Load vector reg, immed post-index 135706c3fb27SDimitry Andric// Load vector reg, immed pre-index 13585f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_1I_1L], 135906c3fb27SDimitry Andric (instregex "^LDR[BHSDQ](pre|post)$")>; 136006c3fb27SDimitry Andric 136106c3fb27SDimitry Andric// Load vector reg, unsigned immed 136206c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>; 136306c3fb27SDimitry Andric 136406c3fb27SDimitry Andric// Load vector reg, register offset, basic 136506c3fb27SDimitry Andric// Load vector reg, register offset, scale, S/D-form 136606c3fb27SDimitry Andric// Load vector reg, register offset, scale, H/Q-form 136706c3fb27SDimitry Andric// Load vector reg, register offset, extend 136806c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, S/D-form 136906c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, H/Q-form 137006c3fb27SDimitry Andricdef : InstRW<[V2Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>; 137106c3fb27SDimitry Andric 137206c3fb27SDimitry Andric// Load vector pair, immed offset, S/D-form 137306c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>; 137406c3fb27SDimitry Andric 137506c3fb27SDimitry Andric// Load vector pair, immed offset, Q-form 137606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>; 137706c3fb27SDimitry Andric 137806c3fb27SDimitry Andric// Load vector pair, immed post-index, S/D-form 137906c3fb27SDimitry Andric// Load vector pair, immed pre-index, S/D-form 13805f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_1I_1L, WriteLDHi], 138106c3fb27SDimitry Andric (instregex "^LDP[SD](pre|post)$")>; 138206c3fb27SDimitry Andric 138306c3fb27SDimitry Andric// Load vector pair, immed post-index, Q-form 138406c3fb27SDimitry Andric// Load vector pair, immed pre-index, Q-form 13855f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost, 138606c3fb27SDimitry Andric LDPQpre)>; 138706c3fb27SDimitry Andric 138806c3fb27SDimitry Andric// FP store instructions 138906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 139006c3fb27SDimitry Andric 139106c3fb27SDimitry Andric// Store vector reg, unscaled immed, B/H/S/D-form 139206c3fb27SDimitry Andric// Store vector reg, unscaled immed, Q-form 139306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>; 139406c3fb27SDimitry Andric 139506c3fb27SDimitry Andric// Store vector reg, immed post-index, B/H/S/D-form 139606c3fb27SDimitry Andric// Store vector reg, immed post-index, Q-form 139706c3fb27SDimitry Andric// Store vector reg, immed pre-index, B/H/S/D-form 139806c3fb27SDimitry Andric// Store vector reg, immed pre-index, Q-form 139906c3fb27SDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I], 140006c3fb27SDimitry Andric (instregex "^STR[BHSDQ](pre|post)$")>; 140106c3fb27SDimitry Andric 140206c3fb27SDimitry Andric// Store vector reg, unsigned immed, B/H/S/D-form 140306c3fb27SDimitry Andric// Store vector reg, unsigned immed, Q-form 140406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>; 140506c3fb27SDimitry Andric 140606c3fb27SDimitry Andric// Store vector reg, register offset, basic, B/H/S/D-form 140706c3fb27SDimitry Andric// Store vector reg, register offset, basic, Q-form 140806c3fb27SDimitry Andric// Store vector reg, register offset, scale, H-form 140906c3fb27SDimitry Andric// Store vector reg, register offset, scale, S/D-form 141006c3fb27SDimitry Andric// Store vector reg, register offset, scale, Q-form 141106c3fb27SDimitry Andric// Store vector reg, register offset, extend, B/H/S/D-form 141206c3fb27SDimitry Andric// Store vector reg, register offset, extend, Q-form 141306c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, H-form 141406c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, S/D-form 141506c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, Q-form 141606c3fb27SDimitry Andricdef : InstRW<[V2Write_StrHQ, ReadAdrBase], 141706c3fb27SDimitry Andric (instregex "^STR[BHSDQ]ro[WX]$")>; 141806c3fb27SDimitry Andric 141906c3fb27SDimitry Andric// Store vector pair, immed offset, S-form 142006c3fb27SDimitry Andric// Store vector pair, immed offset, D-form 142106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STN?P[SD]i$")>; 142206c3fb27SDimitry Andric 142306c3fb27SDimitry Andric// Store vector pair, immed offset, Q-form 142406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_2V01], (instrs STPQi, STNPQi)>; 142506c3fb27SDimitry Andric 142606c3fb27SDimitry Andric// Store vector pair, immed post-index, S-form 142706c3fb27SDimitry Andric// Store vector pair, immed post-index, D-form 142806c3fb27SDimitry Andric// Store vector pair, immed pre-index, S-form 142906c3fb27SDimitry Andric// Store vector pair, immed pre-index, D-form 143006c3fb27SDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I], 143106c3fb27SDimitry Andric (instregex "^STP[SD](pre|post)$")>; 143206c3fb27SDimitry Andric 143306c3fb27SDimitry Andric// Store vector pair, immed post-index, Q-form 143406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_2V01_1I], (instrs STPQpost)>; 143506c3fb27SDimitry Andric 143606c3fb27SDimitry Andric// Store vector pair, immed pre-index, Q-form 143706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_2V01_2I], (instrs STPQpre)>; 143806c3fb27SDimitry Andric 143906c3fb27SDimitry Andric// ASIMD integer instructions 144006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 144106c3fb27SDimitry Andric 144206c3fb27SDimitry Andric// ASIMD absolute diff 144306c3fb27SDimitry Andric// ASIMD absolute diff long 144406c3fb27SDimitry Andric// ASIMD arith, basic 144506c3fb27SDimitry Andric// ASIMD arith, complex 144606c3fb27SDimitry Andric// ASIMD arith, pair-wise 144706c3fb27SDimitry Andric// ASIMD compare 144806c3fb27SDimitry Andric// ASIMD logical 144906c3fb27SDimitry Andric// ASIMD max/min, basic and pair-wise 145006c3fb27SDimitry Andricdef : SchedAlias<WriteVd, V2Write_2cyc_1V>; 145106c3fb27SDimitry Andricdef : SchedAlias<WriteVq, V2Write_2cyc_1V>; 145206c3fb27SDimitry Andric 145306c3fb27SDimitry Andric// ASIMD absolute diff accum 145406c3fb27SDimitry Andric// ASIMD absolute diff accum long 145506c3fb27SDimitry Andricdef : InstRW<[V2Wr_VA, V2Rd_VA], (instregex "^[SU]ABAL?v")>; 145606c3fb27SDimitry Andric 145706c3fb27SDimitry Andric// ASIMD arith, reduce, 4H/4S 145806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>; 145906c3fb27SDimitry Andric 146006c3fb27SDimitry Andric// ASIMD arith, reduce, 8B/8H 146106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13_1V], 146206c3fb27SDimitry Andric (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>; 146306c3fb27SDimitry Andric 146406c3fb27SDimitry Andric// ASIMD arith, reduce, 16B 146506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>; 146606c3fb27SDimitry Andric 146706c3fb27SDimitry Andric// ASIMD dot product 146806c3fb27SDimitry Andric// ASIMD dot product using signed and unsigned integers 146906c3fb27SDimitry Andricdef : InstRW<[V2Wr_VDOT, V2Rd_VDOT], 147006c3fb27SDimitry Andric (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>; 147106c3fb27SDimitry Andric 147206c3fb27SDimitry Andric// ASIMD matrix multiply-accumulate 147306c3fb27SDimitry Andricdef : InstRW<[V2Wr_VMMA, V2Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>; 147406c3fb27SDimitry Andric 147506c3fb27SDimitry Andric// ASIMD max/min, reduce, 4H/4S 147606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$", 147706c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv4i32v$")>; 147806c3fb27SDimitry Andric 147906c3fb27SDimitry Andric// ASIMD max/min, reduce, 8B/8H 148006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$", 148106c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv8i16v$")>; 148206c3fb27SDimitry Andric 148306c3fb27SDimitry Andric// ASIMD max/min, reduce, 16B 148406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>; 148506c3fb27SDimitry Andric 148606c3fb27SDimitry Andric// ASIMD multiply 148706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>; 148806c3fb27SDimitry Andric 148906c3fb27SDimitry Andric// ASIMD multiply accumulate 149006c3fb27SDimitry Andricdef : InstRW<[V2Wr_VMA, V2Rd_VMA], (instregex "^MLAv", "^MLSv")>; 149106c3fb27SDimitry Andric 149206c3fb27SDimitry Andric// ASIMD multiply accumulate high 149306c3fb27SDimitry Andricdef : InstRW<[V2Wr_VMAH, V2Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>; 149406c3fb27SDimitry Andric 149506c3fb27SDimitry Andric// ASIMD multiply accumulate long 149606c3fb27SDimitry Andricdef : InstRW<[V2Wr_VMAL, V2Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>; 149706c3fb27SDimitry Andric 149806c3fb27SDimitry Andric// ASIMD multiply accumulate saturating long 149906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDML[AS]L[iv]")>; 150006c3fb27SDimitry Andric 150106c3fb27SDimitry Andric// ASIMD multiply/multiply long (8x8) polynomial, D-form 150206c3fb27SDimitry Andric// ASIMD multiply/multiply long (8x8) polynomial, Q-form 150306c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>; 150406c3fb27SDimitry Andric 150506c3fb27SDimitry Andric// ASIMD multiply long 150606c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>; 150706c3fb27SDimitry Andric 150806c3fb27SDimitry Andric// ASIMD pairwise add and accumulate long 150906c3fb27SDimitry Andricdef : InstRW<[V2Wr_VPA, V2Rd_VPA], (instregex "^[SU]ADALPv")>; 151006c3fb27SDimitry Andric 151106c3fb27SDimitry Andric// ASIMD shift accumulate 151206c3fb27SDimitry Andricdef : InstRW<[V2Wr_VSA, V2Rd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>; 151306c3fb27SDimitry Andric 151406c3fb27SDimitry Andric// ASIMD shift by immed, basic 151506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv", 151606c3fb27SDimitry Andric "^SSHLLv", "^SSHR[dv]", "^USHLLv", 151706c3fb27SDimitry Andric "^USHR[dv]")>; 151806c3fb27SDimitry Andric 151906c3fb27SDimitry Andric// ASIMD shift by immed and insert, basic 152006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>; 152106c3fb27SDimitry Andric 152206c3fb27SDimitry Andric// ASIMD shift by immed, complex 152306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], 152406c3fb27SDimitry Andric (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$", 152506c3fb27SDimitry Andric "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$", 152606c3fb27SDimitry Andric "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]", 152706c3fb27SDimitry Andric "^UQSHRN[bhsv]", "^URSHR[dv]")>; 152806c3fb27SDimitry Andric 152906c3fb27SDimitry Andric// ASIMD shift by register, basic 153006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]SHLv")>; 153106c3fb27SDimitry Andric 153206c3fb27SDimitry Andric// ASIMD shift by register, complex 153306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], 153406c3fb27SDimitry Andric (instregex "^[SU]RSHLv", "^[SU]QRSHLv", 153506c3fb27SDimitry Andric "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>; 153606c3fb27SDimitry Andric 153706c3fb27SDimitry Andric// ASIMD floating-point instructions 153806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 153906c3fb27SDimitry Andric 154006c3fb27SDimitry Andric// ASIMD FP absolute value/difference 154106c3fb27SDimitry Andric// ASIMD FP arith, normal 154206c3fb27SDimitry Andric// ASIMD FP compare 154306c3fb27SDimitry Andric// ASIMD FP complex add 154406c3fb27SDimitry Andric// ASIMD FP max/min, normal 154506c3fb27SDimitry Andric// ASIMD FP max/min, pairwise 154606c3fb27SDimitry Andric// ASIMD FP negate 154706c3fb27SDimitry Andric// Handled by SchedAlias<WriteV[dq], ...> 154806c3fb27SDimitry Andric 154906c3fb27SDimitry Andric// ASIMD FP complex multiply add 155006c3fb27SDimitry Andricdef : InstRW<[V2Wr_VFCMA, V2Rd_VFCMA], (instregex "^FCMLAv")>; 155106c3fb27SDimitry Andric 155206c3fb27SDimitry Andric// ASIMD FP convert, long (F16 to F32) 155306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTL(v4|v8)i16")>; 155406c3fb27SDimitry Andric 155506c3fb27SDimitry Andric// ASIMD FP convert, long (F32 to F64) 155606c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTL(v2|v4)i32")>; 155706c3fb27SDimitry Andric 155806c3fb27SDimitry Andric// ASIMD FP convert, narrow (F32 to F16) 155906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTN(v4|v8)i16")>; 156006c3fb27SDimitry Andric 156106c3fb27SDimitry Andric// ASIMD FP convert, narrow (F64 to F32) 156206c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTN(v2|v4)i32", 156306c3fb27SDimitry Andric "^FCVTXN(v2|v4)f32")>; 156406c3fb27SDimitry Andric 156506c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F32 and Q-form F64 156606c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$", 156706c3fb27SDimitry Andric "^FCVT[AMNPZ][SU]v1i64$", 156806c3fb27SDimitry Andric "^FCVTZ[SU]d$", 156906c3fb27SDimitry Andric "^[SU]CVTFv2f(32|64)$", 157006c3fb27SDimitry Andric "^[SU]CVTFv1i64$", 157106c3fb27SDimitry Andric "^[SU]CVTFd$")>; 157206c3fb27SDimitry Andric 157306c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F16 and Q-form F32 157406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$", 157506c3fb27SDimitry Andric "^FCVT[AMNPZ][SU]v1i32$", 157606c3fb27SDimitry Andric "^FCVTZ[SU]s$", 157706c3fb27SDimitry Andric "^[SU]CVTFv4f(16|32)$", 157806c3fb27SDimitry Andric "^[SU]CVTFv1i32$", 157906c3fb27SDimitry Andric "^[SU]CVTFs$")>; 158006c3fb27SDimitry Andric 158106c3fb27SDimitry Andric// ASIMD FP convert, other, Q-form F16 158206c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$", 158306c3fb27SDimitry Andric "^FCVT[AMNPZ][SU]v1f16$", 158406c3fb27SDimitry Andric "^FCVTZ[SU]h$", 158506c3fb27SDimitry Andric "^[SU]CVTFv8f16$", 158606c3fb27SDimitry Andric "^[SU]CVTFv1i16$", 158706c3fb27SDimitry Andric "^[SU]CVTFh$")>; 158806c3fb27SDimitry Andric 158906c3fb27SDimitry Andric// ASIMD FP divide, D-form, F16 159006c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FDIVv4f16)>; 159106c3fb27SDimitry Andric 159206c3fb27SDimitry Andric// ASIMD FP divide, D-form, F32 159306c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FDIVv2f32)>; 159406c3fb27SDimitry Andric 159506c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F16 159606c3fb27SDimitry Andricdef : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FDIVv8f16)>; 159706c3fb27SDimitry Andric 159806c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F32 159906c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02_10rc], (instrs FDIVv4f32)>; 160006c3fb27SDimitry Andric 160106c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F64 160206c3fb27SDimitry Andricdef : InstRW<[V2Write_15cyc_1V02_14rc], (instrs FDIVv2f64)>; 160306c3fb27SDimitry Andric 160406c3fb27SDimitry Andric// ASIMD FP max/min, reduce, F32 and D-form F16 160506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>; 160606c3fb27SDimitry Andric 160706c3fb27SDimitry Andric// ASIMD FP max/min, reduce, Q-form F16 160806c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>; 160906c3fb27SDimitry Andric 161006c3fb27SDimitry Andric// ASIMD FP multiply 161106c3fb27SDimitry Andricdef : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>; 161206c3fb27SDimitry Andric 161306c3fb27SDimitry Andric// ASIMD FP multiply accumulate 161406c3fb27SDimitry Andricdef : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>; 161506c3fb27SDimitry Andric 161606c3fb27SDimitry Andric// ASIMD FP multiply accumulate long 161706c3fb27SDimitry Andricdef : InstRW<[V2Wr_VFMAL, V2Rd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>; 161806c3fb27SDimitry Andric 161906c3fb27SDimitry Andric// ASIMD FP round, D-form F32 and Q-form F64 162006c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], 162106c3fb27SDimitry Andric (instregex "^FRINT[AIMNPXZ]v2f(32|64)$", 162206c3fb27SDimitry Andric "^FRINT(32|64)[XZ]v2f(32|64)$")>; 162306c3fb27SDimitry Andric 162406c3fb27SDimitry Andric// ASIMD FP round, D-form F16 and Q-form F32 162506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], 162606c3fb27SDimitry Andric (instregex "^FRINT[AIMNPXZ]v4f(16|32)$", 162706c3fb27SDimitry Andric "^FRINT(32|64)[XZ]v4f32$")>; 162806c3fb27SDimitry Andric 162906c3fb27SDimitry Andric// ASIMD FP round, Q-form F16 163006c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>; 163106c3fb27SDimitry Andric 163206c3fb27SDimitry Andric// ASIMD FP square root, D-form, F16 163306c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FSQRTv4f16)>; 163406c3fb27SDimitry Andric 163506c3fb27SDimitry Andric// ASIMD FP square root, D-form, F32 163606c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FSQRTv2f32)>; 163706c3fb27SDimitry Andric 163806c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F16 163906c3fb27SDimitry Andricdef : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FSQRTv8f16)>; 164006c3fb27SDimitry Andric 164106c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F32 164206c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02_9rc], (instrs FSQRTv4f32)>; 164306c3fb27SDimitry Andric 164406c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F64 164506c3fb27SDimitry Andricdef : InstRW<[V2Write_16cyc_1V02_15rc], (instrs FSQRTv2f64)>; 164606c3fb27SDimitry Andric 164706c3fb27SDimitry Andric// ASIMD BFloat16 (BF16) instructions 164806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 164906c3fb27SDimitry Andric 165006c3fb27SDimitry Andric// ASIMD convert, F32 to BF16 165106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instrs BFCVTN, BFCVTN2)>; 165206c3fb27SDimitry Andric 165306c3fb27SDimitry Andric// ASIMD dot product 165406c3fb27SDimitry Andricdef : InstRW<[V2Wr_VBFDOT, V2Rd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>; 165506c3fb27SDimitry Andric 165606c3fb27SDimitry Andric// ASIMD matrix multiply accumulate 165706c3fb27SDimitry Andricdef : InstRW<[V2Wr_VBFMMA, V2Rd_VBFMMA], (instrs BFMMLA)>; 165806c3fb27SDimitry Andric 165906c3fb27SDimitry Andric// ASIMD multiply accumulate long 166006c3fb27SDimitry Andricdef : InstRW<[V2Wr_VBFMAL, V2Rd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT, 166106c3fb27SDimitry Andric BFMLALTIdx)>; 166206c3fb27SDimitry Andric 166306c3fb27SDimitry Andric// Scalar convert, F32 to BF16 166406c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instrs BFCVT)>; 166506c3fb27SDimitry Andric 166606c3fb27SDimitry Andric// ASIMD miscellaneous instructions 166706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 166806c3fb27SDimitry Andric 166906c3fb27SDimitry Andric// ASIMD bit reverse 167006c3fb27SDimitry Andric// ASIMD bitwise insert 167106c3fb27SDimitry Andric// ASIMD count 167206c3fb27SDimitry Andric// ASIMD duplicate, element 167306c3fb27SDimitry Andric// ASIMD extract 167406c3fb27SDimitry Andric// ASIMD extract narrow 167506c3fb27SDimitry Andric// ASIMD insert, element to element 167606c3fb27SDimitry Andric// ASIMD move, FP immed 167706c3fb27SDimitry Andric// ASIMD move, integer immed 167806c3fb27SDimitry Andric// ASIMD reverse 167906c3fb27SDimitry Andric// ASIMD table lookup extension, 1 table reg 168006c3fb27SDimitry Andric// ASIMD transpose 168106c3fb27SDimitry Andric// ASIMD unzip/zip 168206c3fb27SDimitry Andric// Handled by SchedAlias<WriteV[dq], ...> 16835f757f3fSDimitry Andricdef : InstRW<[V2Write_0or2cyc_1V], (instrs MOVID, MOVIv2d_ns)>; 168406c3fb27SDimitry Andric 168506c3fb27SDimitry Andric// ASIMD duplicate, gen reg 168606c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1M0], (instregex "^DUPv.+gpr")>; 168706c3fb27SDimitry Andric 168806c3fb27SDimitry Andric// ASIMD extract narrow, saturating 168906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>; 169006c3fb27SDimitry Andric 169106c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form U32 169206c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>; 169306c3fb27SDimitry Andric 169406c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form U32 169506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>; 169606c3fb27SDimitry Andric 169706c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms 169806c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instrs FRECPEv1f16, FRECPEv1i32, 169906c3fb27SDimitry Andric FRECPEv1i64, FRECPEv2f32, 170006c3fb27SDimitry Andric FRSQRTEv1f16, FRSQRTEv1i32, 170106c3fb27SDimitry Andric FRSQRTEv1i64, FRSQRTEv2f32)>; 170206c3fb27SDimitry Andric 170306c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 170406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instrs FRECPEv4f16, FRECPEv4f32, 170506c3fb27SDimitry Andric FRSQRTEv4f16, FRSQRTEv4f32)>; 170606c3fb27SDimitry Andric 170706c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form F16 170806c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>; 170906c3fb27SDimitry Andric 171006c3fb27SDimitry Andric// ASIMD reciprocal exponent 171106c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FRECPXv")>; 171206c3fb27SDimitry Andric 171306c3fb27SDimitry Andric// ASIMD reciprocal step 171406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V], (instregex "^FRECPS(32|64|v)", 171506c3fb27SDimitry Andric "^FRSQRTS(32|64|v)")>; 171606c3fb27SDimitry Andric 171706c3fb27SDimitry Andric// ASIMD table lookup, 1 or 2 table regs 171806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V01], (instrs TBLv8i8One, TBLv16i8One, 171906c3fb27SDimitry Andric TBLv8i8Two, TBLv16i8Two)>; 172006c3fb27SDimitry Andric 172106c3fb27SDimitry Andric// ASIMD table lookup, 3 table regs 172206c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V01], (instrs TBLv8i8Three, TBLv16i8Three)>; 172306c3fb27SDimitry Andric 172406c3fb27SDimitry Andric// ASIMD table lookup, 4 table regs 172506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>; 172606c3fb27SDimitry Andric 172706c3fb27SDimitry Andric// ASIMD table lookup extension, 2 table reg 172806c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V], (instrs TBXv8i8Two, TBXv16i8Two)>; 172906c3fb27SDimitry Andric 173006c3fb27SDimitry Andric// ASIMD table lookup extension, 3 table reg 173106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3V], (instrs TBXv8i8Three, TBXv16i8Three)>; 173206c3fb27SDimitry Andric 173306c3fb27SDimitry Andric// ASIMD table lookup extension, 4 table reg 173406c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_5V], (instrs TBXv8i8Four, TBXv16i8Four)>; 173506c3fb27SDimitry Andric 173606c3fb27SDimitry Andric// ASIMD transfer, element to gen reg 173706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2V01], (instregex "^[SU]MOVv")>; 173806c3fb27SDimitry Andric 173906c3fb27SDimitry Andric// ASIMD transfer, gen reg to element 174006c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>; 174106c3fb27SDimitry Andric 174206c3fb27SDimitry Andric// ASIMD load instructions 174306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 174406c3fb27SDimitry Andric 174506c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg, D-form 174606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>; 17475f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_1L], 174806c3fb27SDimitry Andric (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>; 174906c3fb27SDimitry Andric 175006c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg, Q-form 175106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>; 17525f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_1L], 175306c3fb27SDimitry Andric (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>; 175406c3fb27SDimitry Andric 175506c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg, D-form 175606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>; 17575f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_2L], 175806c3fb27SDimitry Andric (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>; 175906c3fb27SDimitry Andric 176006c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg, Q-form 176106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>; 17625f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_2L], 176306c3fb27SDimitry Andric (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>; 176406c3fb27SDimitry Andric 176506c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg, D-form 176606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>; 17675f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_3L], 176806c3fb27SDimitry Andric (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>; 176906c3fb27SDimitry Andric 177006c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg, Q-form 177106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>; 17725f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_3L], 177306c3fb27SDimitry Andric (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>; 177406c3fb27SDimitry Andric 177506c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, D-form 177606c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; 17775f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_7cyc_4L], 177806c3fb27SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; 177906c3fb27SDimitry Andric 178006c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, Q-form 178106c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; 17825f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_7cyc_4L], 178306c3fb27SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; 178406c3fb27SDimitry Andric 178506c3fb27SDimitry Andric// ASIMD load, 1 element, one lane, B/H/S 178606c3fb27SDimitry Andric// ASIMD load, 1 element, one lane, D 178706c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>; 17885f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>; 178906c3fb27SDimitry Andric 179006c3fb27SDimitry Andric// ASIMD load, 1 element, all lanes, D-form, B/H/S 179106c3fb27SDimitry Andric// ASIMD load, 1 element, all lanes, D-form, D 179206c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 17935f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 179406c3fb27SDimitry Andric 179506c3fb27SDimitry Andric// ASIMD load, 1 element, all lanes, Q-form 179606c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 17975f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 179806c3fb27SDimitry Andric 179906c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, D-form, B/H/S 180006c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>; 18015f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 180206c3fb27SDimitry Andric 180306c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, Q-form, B/H/S 180406c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, Q-form, D 180506c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 18065f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 180706c3fb27SDimitry Andric 180806c3fb27SDimitry Andric// ASIMD load, 2 element, one lane, B/H 180906c3fb27SDimitry Andric// ASIMD load, 2 element, one lane, S 181006c3fb27SDimitry Andric// ASIMD load, 2 element, one lane, D 181106c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>; 18125f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>; 181306c3fb27SDimitry Andric 181406c3fb27SDimitry Andric// ASIMD load, 2 element, all lanes, D-form, B/H/S 181506c3fb27SDimitry Andric// ASIMD load, 2 element, all lanes, D-form, D 181606c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 18175f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 181806c3fb27SDimitry Andric 181906c3fb27SDimitry Andric// ASIMD load, 2 element, all lanes, Q-form 182006c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 18215f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 182206c3fb27SDimitry Andric 182306c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, D-form, B/H/S 182406c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>; 18255f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 182606c3fb27SDimitry Andric 182706c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, Q-form, B/H/S 182806c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, Q-form, D 182906c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 18305f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 183106c3fb27SDimitry Andric 183206c3fb27SDimitry Andric// ASIMD load, 3 element, one lane, B/H 183306c3fb27SDimitry Andric// ASIMD load, 3 element, one lane, S 183406c3fb27SDimitry Andric// ASIMD load, 3 element, one lane, D 183506c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>; 18365f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>; 183706c3fb27SDimitry Andric 183806c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes, D-form, B/H/S 183906c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes, D-form, D 184006c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 18415f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 184206c3fb27SDimitry Andric 184306c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes, Q-form, B/H/S 184406c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes, Q-form, D 184506c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 18465f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 184706c3fb27SDimitry Andric 184806c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, D-form, B/H/S 184906c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>; 18505f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 185106c3fb27SDimitry Andric 185206c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, Q-form, B/H/S 185306c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, Q-form, D 185406c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 18555f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 185606c3fb27SDimitry Andric 185706c3fb27SDimitry Andric// ASIMD load, 4 element, one lane, B/H 185806c3fb27SDimitry Andric// ASIMD load, 4 element, one lane, S 185906c3fb27SDimitry Andric// ASIMD load, 4 element, one lane, D 186006c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>; 18615f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>; 186206c3fb27SDimitry Andric 186306c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes, D-form, B/H/S 186406c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes, D-form, D 186506c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 18665f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 186706c3fb27SDimitry Andric 186806c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes, Q-form, B/H/S 186906c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes, Q-form, D 187006c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 18715f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 187206c3fb27SDimitry Andric 187306c3fb27SDimitry Andric// ASIMD store instructions 187406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 187506c3fb27SDimitry Andric 187606c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg, D-form 187706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 18785f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 187906c3fb27SDimitry Andric 188006c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg, Q-form 188106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 18825f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 188306c3fb27SDimitry Andric 188406c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, D-form 188506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 18865f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 188706c3fb27SDimitry Andric 188806c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, Q-form 188906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 18905f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 189106c3fb27SDimitry Andric 189206c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, D-form 189306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 18945f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 189506c3fb27SDimitry Andric 189606c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, Q-form 189706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 18985f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 189906c3fb27SDimitry Andric 190006c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, D-form 190106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 19025f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 190306c3fb27SDimitry Andric 190406c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, Q-form 190506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 19065f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 190706c3fb27SDimitry Andric 190806c3fb27SDimitry Andric// ASIMD store, 1 element, one lane, B/H/S 190906c3fb27SDimitry Andric// ASIMD store, 1 element, one lane, D 191006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>; 19115f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)_POST$")>; 191206c3fb27SDimitry Andric 191306c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, D-form, B/H/S 191406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>; 19155f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 191606c3fb27SDimitry Andric 191706c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, Q-form, B/H/S 191806c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, Q-form, D 191906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 19205f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 192106c3fb27SDimitry Andric 192206c3fb27SDimitry Andric// ASIMD store, 2 element, one lane, B/H/S 192306c3fb27SDimitry Andric// ASIMD store, 2 element, one lane, D 192406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>; 19255f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)_POST$")>; 192606c3fb27SDimitry Andric 192706c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, D-form, B/H/S 192806c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>; 19295f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 193006c3fb27SDimitry Andric 193106c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, Q-form, B/H/S 193206c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, Q-form, D 193306c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 19345f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 193506c3fb27SDimitry Andric 193606c3fb27SDimitry Andric// ASIMD store, 3 element, one lane, B/H 193706c3fb27SDimitry Andric// ASIMD store, 3 element, one lane, S 193806c3fb27SDimitry Andric// ASIMD store, 3 element, one lane, D 193906c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>; 19405f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)_POST$")>; 194106c3fb27SDimitry Andric 194206c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, D-form, B/H/S 194306c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>; 19445f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 194506c3fb27SDimitry Andric 194606c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, B/H/S 194706c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>; 19485f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 194906c3fb27SDimitry Andric 195006c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, D 195106c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)$")>; 19525f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)_POST$")>; 195306c3fb27SDimitry Andric 195406c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, B/H/S 195506c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)$")>; 19565f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)_POST$")>; 195706c3fb27SDimitry Andric 195806c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, D 195906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)$")>; 19605f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)_POST$")>; 196106c3fb27SDimitry Andric 196206c3fb27SDimitry Andric// Cryptography extensions 196306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 196406c3fb27SDimitry Andric 196506c3fb27SDimitry Andric// Crypto AES ops 196606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>; 196706c3fb27SDimitry Andric 196806c3fb27SDimitry Andric// Crypto polynomial (64x64) multiply long 196906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instrs PMULLv1i64, PMULLv2i64)>; 197006c3fb27SDimitry Andric 197106c3fb27SDimitry Andric// Crypto SHA1 hash acceleration op 197206c3fb27SDimitry Andric// Crypto SHA1 schedule acceleration ops 197306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA1(H|SU0|SU1)")>; 197406c3fb27SDimitry Andric 197506c3fb27SDimitry Andric// Crypto SHA1 hash acceleration ops 197606c3fb27SDimitry Andric// Crypto SHA256 hash acceleration ops 197706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>; 197806c3fb27SDimitry Andric 197906c3fb27SDimitry Andric// Crypto SHA256 schedule acceleration ops 198006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA256SU[01]")>; 198106c3fb27SDimitry Andric 198206c3fb27SDimitry Andric// Crypto SHA512 hash acceleration ops 198306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>; 198406c3fb27SDimitry Andric 198506c3fb27SDimitry Andric// Crypto SHA3 ops 198606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instrs BCAX, EOR3, RAX1, XAR)>; 198706c3fb27SDimitry Andric 198806c3fb27SDimitry Andric// Crypto SM3 ops 198906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$", 199006c3fb27SDimitry Andric "^SM3TT[12][AB]$")>; 199106c3fb27SDimitry Andric 199206c3fb27SDimitry Andric// Crypto SM4 ops 199306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V0], (instrs SM4E, SM4ENCKEY)>; 199406c3fb27SDimitry Andric 199506c3fb27SDimitry Andric// CRC 199606c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 199706c3fb27SDimitry Andric 199806c3fb27SDimitry Andricdef : InstRW<[V2Wr_CRC, V2Rd_CRC], (instregex "^CRC32")>; 199906c3fb27SDimitry Andric 200006c3fb27SDimitry Andric// SVE Predicate instructions 200106c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 200206c3fb27SDimitry Andric 200306c3fb27SDimitry Andric// Loop control, based on predicate 200406c3fb27SDimitry Andricdef : InstRW<[V2Write_2or3cyc_1M], (instrs BRKA_PPmP, BRKA_PPzP, 200506c3fb27SDimitry Andric BRKB_PPmP, BRKB_PPzP)>; 200606c3fb27SDimitry Andric 200706c3fb27SDimitry Andric// Loop control, based on predicate and flag setting 200806c3fb27SDimitry Andricdef : InstRW<[V2Write_3or4cyc_2M], (instrs BRKAS_PPzP, BRKBS_PPzP)>; 200906c3fb27SDimitry Andric 201006c3fb27SDimitry Andric// Loop control, propagating 201106c3fb27SDimitry Andricdef : InstRW<[V2Write_2or3cyc_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, 201206c3fb27SDimitry Andric BRKPB_PPzPP)>; 201306c3fb27SDimitry Andric 201406c3fb27SDimitry Andric// Loop control, propagating and flag setting 201506c3fb27SDimitry Andricdef : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP, 201606c3fb27SDimitry Andric BRKPBS_PPzPP)>; 201706c3fb27SDimitry Andric 201806c3fb27SDimitry Andric// Loop control, based on GPR 201906c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_2M], 202006c3fb27SDimitry Andric (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>; 202106c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>; 202206c3fb27SDimitry Andric 202306c3fb27SDimitry Andric// Loop terminate 202406c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>; 202506c3fb27SDimitry Andric 202606c3fb27SDimitry Andric// Predicate counting scalar 202706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>; 202806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], 202906c3fb27SDimitry Andric (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI", 203006c3fb27SDimitry Andric "^SQ(DEC|INC)[BHWD]_XPiWdI", 203106c3fb27SDimitry Andric "^UQ(DEC|INC)[BHWD]_WPiI")>; 203206c3fb27SDimitry Andric 203306c3fb27SDimitry Andric// Predicate counting scalar, ALL, {1,2,4} 203406c3fb27SDimitry Andricdef : InstRW<[V2Write_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI")>; 203506c3fb27SDimitry Andric 203606c3fb27SDimitry Andric// Predicate counting scalar, active predicate 203706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], 203806c3fb27SDimitry Andric (instregex "^CNTP_XPP_[BHSD]", 203906c3fb27SDimitry Andric "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]", 204006c3fb27SDimitry Andric "^(UQDEC|UQINC)P_WP_[BHSD]", 204106c3fb27SDimitry Andric "^(SQDEC|SQINC)P_XPWd_[BHSD]")>; 204206c3fb27SDimitry Andric 204306c3fb27SDimitry Andric// Predicate counting vector, active predicate 204406c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1M_1M0_1V], 204506c3fb27SDimitry Andric (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>; 204606c3fb27SDimitry Andric 204706c3fb27SDimitry Andric// Predicate logical 204806c3fb27SDimitry Andricdef : InstRW<[V2Write_1or2cyc_1M0], 204906c3fb27SDimitry Andric (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>; 205006c3fb27SDimitry Andric 205106c3fb27SDimitry Andric// Predicate logical, flag setting 205206c3fb27SDimitry Andricdef : InstRW<[V2Write_1or2cyc_1M0_1M], 205306c3fb27SDimitry Andric (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>; 205406c3fb27SDimitry Andric 205506c3fb27SDimitry Andric// Predicate reverse 205606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^REV_PP_[BHSD]")>; 205706c3fb27SDimitry Andric 205806c3fb27SDimitry Andric// Predicate select 205906c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1M0], (instrs SEL_PPPP)>; 206006c3fb27SDimitry Andric 206106c3fb27SDimitry Andric// Predicate set 206206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>; 206306c3fb27SDimitry Andric 206406c3fb27SDimitry Andric// Predicate set/initialize, set flags 206506c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_2M], (instregex "^PTRUES_[BHSD]")>; 206606c3fb27SDimitry Andric 206706c3fb27SDimitry Andric// Predicate find first/next 206806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>; 206906c3fb27SDimitry Andric 207006c3fb27SDimitry Andric// Predicate test 207106c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1M], (instrs PTEST_PP)>; 207206c3fb27SDimitry Andric 207306c3fb27SDimitry Andric// Predicate transpose 207406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^TRN[12]_PPP_[BHSD]")>; 207506c3fb27SDimitry Andric 207606c3fb27SDimitry Andric// Predicate unpack and widen 207706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>; 207806c3fb27SDimitry Andric 207906c3fb27SDimitry Andric// Predicate zip/unzip 208006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>; 208106c3fb27SDimitry Andric 208206c3fb27SDimitry Andric// SVE integer instructions 208306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 208406c3fb27SDimitry Andric 208506c3fb27SDimitry Andric// Arithmetic, absolute diff 208606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]", 208706c3fb27SDimitry Andric "^[SU]ABD_ZPZZ_[BHSD]")>; 208806c3fb27SDimitry Andric 208906c3fb27SDimitry Andric// Arithmetic, absolute diff accum 209006c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>; 209106c3fb27SDimitry Andric 209206c3fb27SDimitry Andric// Arithmetic, absolute diff accum long 209306c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>; 209406c3fb27SDimitry Andric 209506c3fb27SDimitry Andric// Arithmetic, absolute diff long 209606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>; 209706c3fb27SDimitry Andric 209806c3fb27SDimitry Andric// Arithmetic, basic 209906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], 210006c3fb27SDimitry Andric (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]", 210106c3fb27SDimitry Andric "^(ADD|SUB)_ZZZ_[BHSD]", 210206c3fb27SDimitry Andric "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]", 210306c3fb27SDimitry Andric "^(ADD|SUB|SUBR)_ZI_[BHSD]", 210406c3fb27SDimitry Andric "^ADR_[SU]XTW_ZZZ_D_[0123]", 210506c3fb27SDimitry Andric "^ADR_LSL_ZZZ_[SD]_[0123]", 210606c3fb27SDimitry Andric "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]", 210706c3fb27SDimitry Andric "^SADDLBT_ZZZ_[HSD]", 210806c3fb27SDimitry Andric "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]", 210906c3fb27SDimitry Andric "^SSUBL(BT|TB)_ZZZ_[HSD]")>; 211006c3fb27SDimitry Andric 211106c3fb27SDimitry Andric// Arithmetic, complex 211206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], 211306c3fb27SDimitry Andric (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]", 211406c3fb27SDimitry Andric "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]", 211506c3fb27SDimitry Andric "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]", 211606c3fb27SDimitry Andric "^[SU]Q(ADD|SUB)_ZI_[BHSD]", 211706c3fb27SDimitry Andric "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]", 211806c3fb27SDimitry Andric "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>; 211906c3fb27SDimitry Andric 212006c3fb27SDimitry Andric// Arithmetic, large integer 212106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>; 212206c3fb27SDimitry Andric 212306c3fb27SDimitry Andric// Arithmetic, pairwise add 212406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>; 212506c3fb27SDimitry Andric 212606c3fb27SDimitry Andric// Arithmetic, pairwise add and accum long 212706c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA], 212806c3fb27SDimitry Andric (instregex "^[SU]ADALP_ZPmZ_[HSD]")>; 212906c3fb27SDimitry Andric 213006c3fb27SDimitry Andric// Arithmetic, shift 213106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], 213206c3fb27SDimitry Andric (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]", 213306c3fb27SDimitry Andric "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]", 213406c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPmI_[BHSD]", 213506c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPmZ_[BHSD]", 213606c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZZI_[BHSD]", 213706c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]", 213806c3fb27SDimitry Andric "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>; 213906c3fb27SDimitry Andric 214006c3fb27SDimitry Andric// Arithmetic, shift and accumulate 214106c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>; 214206c3fb27SDimitry Andric 214306c3fb27SDimitry Andric// Arithmetic, shift by immediate 214406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]", 214506c3fb27SDimitry Andric "^[SU]SHLL[BT]_ZZI_[HSD]")>; 214606c3fb27SDimitry Andric 214706c3fb27SDimitry Andric// Arithmetic, shift by immediate and insert 214806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>; 214906c3fb27SDimitry Andric 215006c3fb27SDimitry Andric// Arithmetic, shift complex 215106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], 215206c3fb27SDimitry Andric (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]", 215306c3fb27SDimitry Andric "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]", 215406c3fb27SDimitry Andric "^[SU]QR?SHL_ZPZZ_[BHSD]", 215506c3fb27SDimitry Andric "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]", 215606c3fb27SDimitry Andric "^SQSHRU?N[BT]_ZZI_[BHS]", 215706c3fb27SDimitry Andric "^UQR?SHRN[BT]_ZZI_[BHS]")>; 215806c3fb27SDimitry Andric 215906c3fb27SDimitry Andric// Arithmetic, shift right for divide 216006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>; 216106c3fb27SDimitry Andric 216206c3fb27SDimitry Andric// Arithmetic, shift rounding 216306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]", 216406c3fb27SDimitry Andric "^[SU]RSHL_ZPZZ_[BHSD]", 216506c3fb27SDimitry Andric "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>; 216606c3fb27SDimitry Andric 216706c3fb27SDimitry Andric// Bit manipulation 216806c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>; 216906c3fb27SDimitry Andric 217006c3fb27SDimitry Andric// Bitwise select 217106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>; 217206c3fb27SDimitry Andric 217306c3fb27SDimitry Andric// Count/reverse bits 217406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>; 217506c3fb27SDimitry Andric 217606c3fb27SDimitry Andric// Broadcast logical bitmask immediate to vector 217706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>; 217806c3fb27SDimitry Andric 217906c3fb27SDimitry Andric// Compare and set flags 218006c3fb27SDimitry Andricdef : InstRW<[V2Write_4or5cyc_1V0_1M0], 218106c3fb27SDimitry Andric (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]", 218206c3fb27SDimitry Andric "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>; 218306c3fb27SDimitry Andric 218406c3fb27SDimitry Andric// Complex add 218506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>; 218606c3fb27SDimitry Andric 218706c3fb27SDimitry Andric// Complex dot product 8-bit element 218806c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>; 218906c3fb27SDimitry Andric 219006c3fb27SDimitry Andric// Complex dot product 16-bit element 219106c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>; 219206c3fb27SDimitry Andric 219306c3fb27SDimitry Andric// Complex multiply-add B, H, S element size 219406c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZCMABHS, V2Rd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]", 219506c3fb27SDimitry Andric "^CMLA_ZZZI_[HS]")>; 219606c3fb27SDimitry Andric 219706c3fb27SDimitry Andric// Complex multiply-add D element size 219806c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZCMAD, V2Rd_ZCMAD], (instrs CMLA_ZZZ_D)>; 219906c3fb27SDimitry Andric 220006c3fb27SDimitry Andric// Conditional extract operations, scalar form 220106c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>; 220206c3fb27SDimitry Andric 220306c3fb27SDimitry Andric// Conditional extract operations, SIMD&FP scalar and vector forms 220406c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]", 220506c3fb27SDimitry Andric "^COMPACT_ZPZ_[SD]", 220606c3fb27SDimitry Andric "^SPLICE_ZPZZ?_[BHSD]")>; 220706c3fb27SDimitry Andric 220806c3fb27SDimitry Andric// Convert to floating point, 64b to float or convert to double 220906c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]", 221006c3fb27SDimitry Andric "^[SU]CVTF_ZPmZ_StoD")>; 221106c3fb27SDimitry Andric 221206c3fb27SDimitry Andric// Convert to floating point, 32b to single or half 221306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>; 221406c3fb27SDimitry Andric 221506c3fb27SDimitry Andric// Convert to floating point, 16b to half 221606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH")>; 221706c3fb27SDimitry Andric 221806c3fb27SDimitry Andric// Copy, scalar 221906c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>; 222006c3fb27SDimitry Andric 222106c3fb27SDimitry Andric// Copy, scalar SIMD&FP or imm 222206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]", 222306c3fb27SDimitry Andric "^CPY_ZPzI_[BHSD]")>; 222406c3fb27SDimitry Andric 222506c3fb27SDimitry Andric// Divides, 32 bit 222606c3fb27SDimitry Andricdef : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S", 222706c3fb27SDimitry Andric "^[SU]DIV_ZPZZ_S")>; 222806c3fb27SDimitry Andric 222906c3fb27SDimitry Andric// Divides, 64 bit 223006c3fb27SDimitry Andricdef : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D", 223106c3fb27SDimitry Andric "^[SU]DIV_ZPZZ_D")>; 223206c3fb27SDimitry Andric 223306c3fb27SDimitry Andric// Dot product, 8 bit 223406c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S")>; 223506c3fb27SDimitry Andric 223606c3fb27SDimitry Andric// Dot product, 8 bit, using signed and unsigned integers 223706c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>; 223806c3fb27SDimitry Andric 223906c3fb27SDimitry Andric// Dot product, 16 bit 224006c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_D")>; 224106c3fb27SDimitry Andric 224206c3fb27SDimitry Andric// Duplicate, immediate and indexed form 224306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^DUP_ZI_[BHSD]", 224406c3fb27SDimitry Andric "^DUP_ZZI_[BHSDQ]")>; 224506c3fb27SDimitry Andric 224606c3fb27SDimitry Andric// Duplicate, scalar form 224706c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1M0], (instregex "^DUP_ZR_[BHSD]")>; 224806c3fb27SDimitry Andric 224906c3fb27SDimitry Andric// Extend, sign or zero 225006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]XTB_ZPmZ_[HSD]", 225106c3fb27SDimitry Andric "^[SU]XTH_ZPmZ_[SD]", 225206c3fb27SDimitry Andric "^[SU]XTW_ZPmZ_[D]")>; 225306c3fb27SDimitry Andric 225406c3fb27SDimitry Andric// Extract 225506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instrs EXT_ZZI, EXT_ZZI_B)>; 225606c3fb27SDimitry Andric 225706c3fb27SDimitry Andric// Extract narrow saturating 225806c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]", 225906c3fb27SDimitry Andric "^SQXTUN[BT]_ZZ_[BHS]")>; 226006c3fb27SDimitry Andric 226106c3fb27SDimitry Andric// Extract/insert operation, SIMD and FP scalar form 226206c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]", 226306c3fb27SDimitry Andric "^INSR_ZV_[BHSD]")>; 226406c3fb27SDimitry Andric 226506c3fb27SDimitry Andric// Extract/insert operation, scalar 226606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]", 226706c3fb27SDimitry Andric "^INSR_ZR_[BHSD]")>; 226806c3fb27SDimitry Andric 226906c3fb27SDimitry Andric// Histogram operations 227006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^HISTCNT_ZPzZZ_[SD]", 227106c3fb27SDimitry Andric "^HISTSEG_ZZZ")>; 227206c3fb27SDimitry Andric 227306c3fb27SDimitry Andric// Horizontal operations, B, H, S form, immediate operands only 227406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^INDEX_II_[BHS]")>; 227506c3fb27SDimitry Andric 227606c3fb27SDimitry Andric// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar 227706c3fb27SDimitry Andric// operands only / immediate, scalar operands 227806c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>; 227906c3fb27SDimitry Andric 228006c3fb27SDimitry Andric// Horizontal operations, D form, immediate operands only 228106c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2V02], (instrs INDEX_II_D)>; 228206c3fb27SDimitry Andric 228306c3fb27SDimitry Andric// Horizontal operations, D form, scalar, immediate operands)/ scalar operands 228406c3fb27SDimitry Andric// only / immediate, scalar operands 228506c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D")>; 228606c3fb27SDimitry Andric 228706c3fb27SDimitry Andric// Logical 228806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], 228906c3fb27SDimitry Andric (instregex "^(AND|EOR|ORR)_ZI", 229006c3fb27SDimitry Andric "^(AND|BIC|EOR|ORR)_ZZZ", 229106c3fb27SDimitry Andric "^EOR(BT|TB)_ZZZ_[BHSD]", 229206c3fb27SDimitry Andric "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]", 229306c3fb27SDimitry Andric "^NOT_ZPmZ_[BHSD]")>; 229406c3fb27SDimitry Andric 229506c3fb27SDimitry Andric// Max/min, basic and pairwise 229606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]", 229706c3fb27SDimitry Andric "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]", 229806c3fb27SDimitry Andric "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>; 229906c3fb27SDimitry Andric 230006c3fb27SDimitry Andric// Matching operations 230106c3fb27SDimitry Andric// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the 230206c3fb27SDimitry Andric// latency for this instruction is 4 cycles. 230306c3fb27SDimitry Andricdef : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>; 230406c3fb27SDimitry Andric 230506c3fb27SDimitry Andric// Matrix multiply-accumulate 230606c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>; 230706c3fb27SDimitry Andric 230806c3fb27SDimitry Andric// Move prefix 230906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]", 231006c3fb27SDimitry Andric "^MOVPRFX_ZZ")>; 231106c3fb27SDimitry Andric 231206c3fb27SDimitry Andric// Multiply, B, H, S element size 231306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]", 231406c3fb27SDimitry Andric "^MUL_ZPZZ_[BHS]", 231506c3fb27SDimitry Andric "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]", 231606c3fb27SDimitry Andric "^[SU]MULH_ZPZZ_[BHS]")>; 231706c3fb27SDimitry Andric 231806c3fb27SDimitry Andric// Multiply, D element size 231906c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D", 232006c3fb27SDimitry Andric "^MUL_ZPZZ_D", 232106c3fb27SDimitry Andric "^[SU]MULH_(ZPmZ|ZZZ)_D", 232206c3fb27SDimitry Andric "^[SU]MULH_ZPZZ_D")>; 232306c3fb27SDimitry Andric 232406c3fb27SDimitry Andric// Multiply long 232506c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]", 232606c3fb27SDimitry Andric "^[SU]MULL[BT]_ZZZ_[HSD]")>; 232706c3fb27SDimitry Andric 232806c3fb27SDimitry Andric// Multiply accumulate, B, H, S element size 232906c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS], 233006c3fb27SDimitry Andric (instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>; 233106c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS], 233206c3fb27SDimitry Andric (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>; 233306c3fb27SDimitry Andric 233406c3fb27SDimitry Andric// Multiply accumulate, D element size 233506c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD], 233606c3fb27SDimitry Andric (instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>; 233706c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD], 233806c3fb27SDimitry Andric (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>; 233906c3fb27SDimitry Andric 234006c3fb27SDimitry Andric// Multiply accumulate long 234106c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMAL, V2Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]", 234206c3fb27SDimitry Andric "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>; 234306c3fb27SDimitry Andric 234406c3fb27SDimitry Andric// Multiply accumulate saturating doubling long regular 234506c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMASQL, V2Rd_ZMASQ], 234606c3fb27SDimitry Andric (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]", 234706c3fb27SDimitry Andric "^SQDML[AS]L[BT]_ZZZI_[SD]")>; 234806c3fb27SDimitry Andric 234906c3fb27SDimitry Andric// Multiply saturating doubling high, B, H, S element size 235006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULH_ZZZ_[BHS]", 235106c3fb27SDimitry Andric "^SQDMULH_ZZZI_[HS]")>; 235206c3fb27SDimitry Andric 235306c3fb27SDimitry Andric// Multiply saturating doubling high, D element size 235406c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>; 235506c3fb27SDimitry Andric 235606c3fb27SDimitry Andric// Multiply saturating doubling long 235706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]", 235806c3fb27SDimitry Andric "^SQDMULL[BT]_ZZZI_[SD]")>; 235906c3fb27SDimitry Andric 236006c3fb27SDimitry Andric// Multiply saturating rounding doubling regular/complex accumulate, B, H, S 236106c3fb27SDimitry Andric// element size 236206c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMASQBHS, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]", 236306c3fb27SDimitry Andric "^SQRDCMLAH_ZZZ_[BHS]", 236406c3fb27SDimitry Andric "^SQRDML[AS]H_ZZZI_[HS]", 236506c3fb27SDimitry Andric "^SQRDCMLAH_ZZZI_[HS]")>; 236606c3fb27SDimitry Andric 236706c3fb27SDimitry Andric// Multiply saturating rounding doubling regular/complex accumulate, D element 236806c3fb27SDimitry Andric// size 236906c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZMASQD, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D", 237006c3fb27SDimitry Andric "^SQRDCMLAH_ZZZ_D")>; 237106c3fb27SDimitry Andric 237206c3fb27SDimitry Andric// Multiply saturating rounding doubling regular/complex, B, H, S element size 237306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]", 237406c3fb27SDimitry Andric "^SQRDMULH_ZZZI_[HS]")>; 237506c3fb27SDimitry Andric 237606c3fb27SDimitry Andric// Multiply saturating rounding doubling regular/complex, D element size 237706c3fb27SDimitry Andricdef : InstRW<[V2Write_5cyc_2V02], (instregex "^SQRDMULH_ZZZI?_D")>; 237806c3fb27SDimitry Andric 237906c3fb27SDimitry Andric// Multiply/multiply long, (8x8) polynomial 238006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V23], (instregex "^PMUL_ZZZ_B", 238106c3fb27SDimitry Andric "^PMULL[BT]_ZZZ_[HDQ]")>; 238206c3fb27SDimitry Andric 238306c3fb27SDimitry Andric// Predicate counting vector 238406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>; 238506c3fb27SDimitry Andric 238606c3fb27SDimitry Andric// Reciprocal estimate 238706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>; 238806c3fb27SDimitry Andric 238906c3fb27SDimitry Andric// Reduction, arithmetic, B form 239006c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>; 239106c3fb27SDimitry Andric 239206c3fb27SDimitry Andric// Reduction, arithmetic, H form 239306c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>; 239406c3fb27SDimitry Andric 239506c3fb27SDimitry Andric// Reduction, arithmetic, S form 239606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>; 239706c3fb27SDimitry Andric 239806c3fb27SDimitry Andric// Reduction, arithmetic, D form 239906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>; 240006c3fb27SDimitry Andric 240106c3fb27SDimitry Andric// Reduction, logical 240206c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>; 240306c3fb27SDimitry Andric 240406c3fb27SDimitry Andric// Reverse, vector 240506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^REV_ZZ_[BHSD]", 240606c3fb27SDimitry Andric "^REVB_ZPmZ_[HSD]", 240706c3fb27SDimitry Andric "^REVH_ZPmZ_[SD]", 240806c3fb27SDimitry Andric "^REVW_ZPmZ_D")>; 240906c3fb27SDimitry Andric 241006c3fb27SDimitry Andric// Select, vector form 241106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^SEL_ZPZZ_[BHSD]")>; 241206c3fb27SDimitry Andric 241306c3fb27SDimitry Andric// Table lookup 241406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>; 241506c3fb27SDimitry Andric 241606c3fb27SDimitry Andric// Table lookup extension 241706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^TBX_ZZZ_[BHSD]")>; 241806c3fb27SDimitry Andric 241906c3fb27SDimitry Andric// Transpose, vector form 242006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>; 242106c3fb27SDimitry Andric 242206c3fb27SDimitry Andric// Unpack and extend 242306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>; 242406c3fb27SDimitry Andric 242506c3fb27SDimitry Andric// Zip/unzip 242606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>; 242706c3fb27SDimitry Andric 242806c3fb27SDimitry Andric// SVE floating-point instructions 242906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 243006c3fb27SDimitry Andric 243106c3fb27SDimitry Andric// Floating point absolute value/difference 243206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]", 243306c3fb27SDimitry Andric "^FABD_ZPZZ_[HSD]", 243406c3fb27SDimitry Andric "^FABS_ZPmZ_[HSD]")>; 243506c3fb27SDimitry Andric 243606c3fb27SDimitry Andric// Floating point arithmetic 243706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]", 243806c3fb27SDimitry Andric "^F(ADD|SUB)_ZPZ[IZ]_[HSD]", 243906c3fb27SDimitry Andric "^FADDP_ZPmZZ_[HSD]", 244006c3fb27SDimitry Andric "^FNEG_ZPmZ_[HSD]", 244106c3fb27SDimitry Andric "^FSUBR_ZPm[IZ]_[HSD]", 244206c3fb27SDimitry Andric "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>; 244306c3fb27SDimitry Andric 244406c3fb27SDimitry Andric// Floating point associative add, F16 244506c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>; 244606c3fb27SDimitry Andric 244706c3fb27SDimitry Andric// Floating point associative add, F32 244806c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1V1_5rc], (instrs FADDA_VPZ_S)>; 244906c3fb27SDimitry Andric 245006c3fb27SDimitry Andric// Floating point associative add, F64 245106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V], (instrs FADDA_VPZ_D)>; 245206c3fb27SDimitry Andric 245306c3fb27SDimitry Andric// Floating point compare 245406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]", 245506c3fb27SDimitry Andric "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]", 245606c3fb27SDimitry Andric "^FCM(LE|LT)_PPzZ0_[HSD]", 245706c3fb27SDimitry Andric "^FCMUO_PPzZZ_[HSD]")>; 245806c3fb27SDimitry Andric 245906c3fb27SDimitry Andric// Floating point complex add 246006c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V], (instregex "^FCADD_ZPmZ_[HSD]")>; 246106c3fb27SDimitry Andric 246206c3fb27SDimitry Andric// Floating point complex multiply add 246306c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZFCMA, ReadDefault, V2Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>; 246406c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZFCMA, V2Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>; 246506c3fb27SDimitry Andric 246606c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F32 or F32 to F16) 246706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)", 246806c3fb27SDimitry Andric "^FCVTLT_ZPmZ_HtoS", 246906c3fb27SDimitry Andric "^FCVTNT_ZPmZ_StoH")>; 247006c3fb27SDimitry Andric 247106c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 247206c3fb27SDimitry Andric// or F64 to F16) 247306c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)", 247406c3fb27SDimitry Andric "^FCVTLT_ZPmZ_StoD", 247506c3fb27SDimitry Andric "^FCVTNT_ZPmZ_DtoS")>; 247606c3fb27SDimitry Andric 247706c3fb27SDimitry Andric// Floating point convert, round to odd 247806c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>; 247906c3fb27SDimitry Andric 248006c3fb27SDimitry Andric// Floating point base2 log, F16 248106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>; 248206c3fb27SDimitry Andric 248306c3fb27SDimitry Andric// Floating point base2 log, F32 248406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>; 248506c3fb27SDimitry Andric 248606c3fb27SDimitry Andric// Floating point base2 log, F64 248706c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>; 248806c3fb27SDimitry Andric 248906c3fb27SDimitry Andric// Floating point convert to integer, F16 249006c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>; 249106c3fb27SDimitry Andric 249206c3fb27SDimitry Andric// Floating point convert to integer, F32 249306c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>; 249406c3fb27SDimitry Andric 249506c3fb27SDimitry Andric// Floating point convert to integer, F64 249606c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], 249706c3fb27SDimitry Andric (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>; 249806c3fb27SDimitry Andric 249906c3fb27SDimitry Andric// Floating point copy 250006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]", 250106c3fb27SDimitry Andric "^FDUP_ZI_[HSD]")>; 250206c3fb27SDimitry Andric 250306c3fb27SDimitry Andric// Floating point divide, F16 250406c3fb27SDimitry Andricdef : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>; 250506c3fb27SDimitry Andric 250606c3fb27SDimitry Andric// Floating point divide, F32 250706c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>; 250806c3fb27SDimitry Andric 250906c3fb27SDimitry Andric// Floating point divide, F64 251006c3fb27SDimitry Andricdef : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>; 251106c3fb27SDimitry Andric 251206c3fb27SDimitry Andric// Floating point min/max pairwise 251306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>; 251406c3fb27SDimitry Andric 251506c3fb27SDimitry Andric// Floating point min/max 251606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]", 251706c3fb27SDimitry Andric "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>; 251806c3fb27SDimitry Andric 251906c3fb27SDimitry Andric// Floating point multiply 252006c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]", 252106c3fb27SDimitry Andric "^FMULX_ZPZZ_[HSD]", 252206c3fb27SDimitry Andric "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]", 252306c3fb27SDimitry Andric "^FMUL_ZPZ[IZ]_[HSD]")>; 252406c3fb27SDimitry Andric 252506c3fb27SDimitry Andric// Floating point multiply accumulate 252606c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA], 252706c3fb27SDimitry Andric (instregex "^FN?ML[AS]_ZPmZZ_[HSD]", 252806c3fb27SDimitry Andric "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>; 252906c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA], 253006c3fb27SDimitry Andric (instregex "^FML[AS]_ZZZI_[HSD]", 253106c3fb27SDimitry Andric "^FN?ML[AS]_ZPZZZ_[HSD]")>; 253206c3fb27SDimitry Andric 253306c3fb27SDimitry Andric// Floating point multiply add/sub accumulate long 253406c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>; 253506c3fb27SDimitry Andric 253606c3fb27SDimitry Andric// Floating point reciprocal estimate, F16 253706c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>; 253806c3fb27SDimitry Andric 253906c3fb27SDimitry Andric// Floating point reciprocal estimate, F32 254006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>; 254106c3fb27SDimitry Andric 254206c3fb27SDimitry Andric// Floating point reciprocal estimate, F64 254306c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>; 254406c3fb27SDimitry Andric 254506c3fb27SDimitry Andric// Floating point reciprocal step 254606c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>; 254706c3fb27SDimitry Andric 254806c3fb27SDimitry Andric// Floating point reduction, F16 254906c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_4V], 255006c3fb27SDimitry Andric (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>; 255106c3fb27SDimitry Andric 255206c3fb27SDimitry Andric// Floating point reduction, F32 255306c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_3V], 255406c3fb27SDimitry Andric (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>; 255506c3fb27SDimitry Andric 255606c3fb27SDimitry Andric// Floating point reduction, F64 255706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V], 255806c3fb27SDimitry Andric (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>; 255906c3fb27SDimitry Andric 256006c3fb27SDimitry Andric// Floating point round to integral, F16 256106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>; 256206c3fb27SDimitry Andric 256306c3fb27SDimitry Andric// Floating point round to integral, F32 256406c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>; 256506c3fb27SDimitry Andric 256606c3fb27SDimitry Andric// Floating point round to integral, F64 256706c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>; 256806c3fb27SDimitry Andric 256906c3fb27SDimitry Andric// Floating point square root, F16 257006c3fb27SDimitry Andricdef : InstRW<[V2Write_13cyc_1V0_12rc], (instregex "^FSQRT_ZPmZ_H", "^FSQRT_ZPmZ_H")>; 257106c3fb27SDimitry Andric 257206c3fb27SDimitry Andric// Floating point square root, F32 257306c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1V0_9rc], (instregex "^FSQRT_ZPmZ_S", "^FSQRT_ZPmZ_S")>; 257406c3fb27SDimitry Andric 257506c3fb27SDimitry Andric// Floating point square root, F64 257606c3fb27SDimitry Andricdef : InstRW<[V2Write_16cyc_1V0_14rc], (instregex "^FSQRT_ZPmZ_D", "^FSQRT_ZPmZ_D")>; 257706c3fb27SDimitry Andric 257806c3fb27SDimitry Andric// Floating point trigonometric exponentiation 257906c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]")>; 258006c3fb27SDimitry Andric 258106c3fb27SDimitry Andric// Floating point trigonometric multiply add 258206c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]")>; 258306c3fb27SDimitry Andric 258406c3fb27SDimitry Andric// Floating point trigonometric, miscellaneous 258506c3fb27SDimitry Andricdef : InstRW<[V2Write_3cyc_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>; 258606c3fb27SDimitry Andric 258706c3fb27SDimitry Andric// SVE BFloat16 (BF16) instructions 258806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 258906c3fb27SDimitry Andric 259006c3fb27SDimitry Andric// Convert, F32 to BF16 259106c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>; 259206c3fb27SDimitry Andric 259306c3fb27SDimitry Andric// Dot product 259406c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZBFDOT, V2Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>; 259506c3fb27SDimitry Andric 259606c3fb27SDimitry Andric// Matrix multiply accumulate 259706c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZBFMMA, V2Rd_ZBFMMA], (instrs BFMMLA_ZZZ)>; 259806c3fb27SDimitry Andric 259906c3fb27SDimitry Andric// Multiply accumulate long 260006c3fb27SDimitry Andricdef : InstRW<[V2Wr_ZBFMAL, V2Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>; 260106c3fb27SDimitry Andric 260206c3fb27SDimitry Andric// SVE Load instructions 260306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 260406c3fb27SDimitry Andric 260506c3fb27SDimitry Andric// Load vector 260606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instrs LDR_ZXI)>; 260706c3fb27SDimitry Andric 260806c3fb27SDimitry Andric// Load predicate 260906c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L_1M], (instrs LDR_PXI)>; 261006c3fb27SDimitry Andric 261106c3fb27SDimitry Andric// Contiguous load, scalar + imm 26125f757f3fSDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$", 26135f757f3fSDimitry Andric "^LD1S?B_[HSD]_IMM$", 26145f757f3fSDimitry Andric "^LD1S?H_[SD]_IMM$", 26155f757f3fSDimitry Andric "^LD1S?W_D_IMM$" )>; 261606c3fb27SDimitry Andric// Contiguous load, scalar + scalar 261706c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]$", 261806c3fb27SDimitry Andric "^LD1S?B_[HSD]$", 261906c3fb27SDimitry Andric "^LD1S?H_[SD]$", 262006c3fb27SDimitry Andric "^LD1S?W_D$" )>; 262106c3fb27SDimitry Andric 262206c3fb27SDimitry Andric// Contiguous load broadcast, scalar + imm 262306c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1R[BHWD]_IMM$", 262406c3fb27SDimitry Andric "^LD1RS?B_[HSD]_IMM$", 262506c3fb27SDimitry Andric "^LD1RS?H_[SD]_IMM$", 262606c3fb27SDimitry Andric "^LD1RW_D_IMM$", 262706c3fb27SDimitry Andric "^LD1RSW_IMM$", 262806c3fb27SDimitry Andric "^LD1RQ_[BHWD]_IMM$")>; 262906c3fb27SDimitry Andric 263006c3fb27SDimitry Andric// Contiguous load broadcast, scalar + scalar 263106c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LD1RQ_[BHWD]$")>; 263206c3fb27SDimitry Andric 263306c3fb27SDimitry Andric// Non temporal load, scalar + imm 263406c3fb27SDimitry Andric// Non temporal load, scalar + scalar 263506c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>; 263606c3fb27SDimitry Andric 263706c3fb27SDimitry Andric// Non temporal gather load, vector + scalar 32-bit element size 263806c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S_REAL$", 263906c3fb27SDimitry Andric "^LDNT1S[BH]_ZZR_S_REAL$")>; 264006c3fb27SDimitry Andric 264106c3fb27SDimitry Andric// Non temporal gather load, vector + scalar 64-bit element size 264206c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D_REAL$")>; 264306c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_2L_2V1], (instrs LDNT1D_ZZR_D_REAL)>; 264406c3fb27SDimitry Andric 264506c3fb27SDimitry Andric// Contiguous first faulting load, scalar + scalar 264606c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L_1S], (instregex "^LDFF1[BHWD]_REAL$", 264706c3fb27SDimitry Andric "^LDFF1S?B_[HSD]_REAL$", 264806c3fb27SDimitry Andric "^LDFF1S?H_[SD]_REAL$", 264906c3fb27SDimitry Andric "^LDFF1S?W_D_REAL$")>; 265006c3fb27SDimitry Andric 265106c3fb27SDimitry Andric// Contiguous non faulting load, scalar + imm 265206c3fb27SDimitry Andricdef : InstRW<[V2Write_6cyc_1L], (instregex "^LDNF1[BHWD]_IMM_REAL$", 265306c3fb27SDimitry Andric "^LDNF1S?B_[HSD]_IMM_REAL$", 265406c3fb27SDimitry Andric "^LDNF1S?H_[SD]_IMM_REAL$", 265506c3fb27SDimitry Andric "^LDNF1S?W_D_IMM_REAL$")>; 265606c3fb27SDimitry Andric 265706c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + imm 265806c3fb27SDimitry Andricdef : InstRW<[V2Write_8cyc_2L_2V], (instregex "^LD2[BHWD]_IMM$")>; 265906c3fb27SDimitry Andric 266006c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + scalar 266106c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_2L_2V_2S], (instregex "^LD2[BHWD]$")>; 266206c3fb27SDimitry Andric 266306c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + imm 266406c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_3L_3V], (instregex "^LD3[BHWD]_IMM$")>; 266506c3fb27SDimitry Andric 266606c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + scalar 266706c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_3V_3L_3S], (instregex "^LD3[BHWD]$")>; 266806c3fb27SDimitry Andric 266906c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + imm 267006c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_4L_8V], (instregex "^LD4[BHWD]_IMM$")>; 267106c3fb27SDimitry Andric 267206c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + scalar 267306c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_4L_8V_4S], (instregex "^LD4[BHWD]$")>; 267406c3fb27SDimitry Andric 267506c3fb27SDimitry Andric// Gather load, vector + imm, 32-bit element size 267606c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM_REAL$", 267706c3fb27SDimitry Andric "^GLD(FF)?1W_IMM_REAL$")>; 267806c3fb27SDimitry Andric 267906c3fb27SDimitry Andric// Gather load, vector + imm, 64-bit element size 268006c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM_REAL$", 268106c3fb27SDimitry Andric "^GLD(FF)?1D_IMM_REAL$")>; 268206c3fb27SDimitry Andric 268306c3fb27SDimitry Andric// Gather load, 32-bit scaled offset 268406c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1L_8V], 268506c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED_REAL$", 268606c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_SCALED_REAL")>; 268706c3fb27SDimitry Andric 268806c3fb27SDimitry Andric// Gather load, 64-bit scaled offset 268906c3fb27SDimitry Andric// NOTE: These instructions are not specified in the SOG. 269006c3fb27SDimitry Andricdef : InstRW<[V2Write_10cyc_1L_4V], 269106c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED_REAL$", 269206c3fb27SDimitry Andric "^GLD(FF)?1D_([SU]XTW_)?SCALED_REAL$")>; 269306c3fb27SDimitry Andric 269406c3fb27SDimitry Andric// Gather load, 32-bit unpacked unscaled offset 269506c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW_REAL$", 269606c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_REAL$")>; 269706c3fb27SDimitry Andric 269806c3fb27SDimitry Andric// Gather load, 64-bit unpacked unscaled offset 269906c3fb27SDimitry Andric// NOTE: These instructions are not specified in the SOG. 270006c3fb27SDimitry Andricdef : InstRW<[V2Write_9cyc_1L_2V], 270106c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[BHW]_D_([SU]XTW_)?REAL$", 270206c3fb27SDimitry Andric "^GLD(FF)?1D_([SU]XTW_)?REAL$")>; 270306c3fb27SDimitry Andric 270406c3fb27SDimitry Andric// SVE Store instructions 270506c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 270606c3fb27SDimitry Andric 270706c3fb27SDimitry Andric// Store from predicate reg 270806c3fb27SDimitry Andricdef : InstRW<[V2Write_1cyc_1L01], (instrs STR_PXI)>; 270906c3fb27SDimitry Andric 271006c3fb27SDimitry Andric// Store from vector reg 271106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instrs STR_ZXI)>; 271206c3fb27SDimitry Andric 271306c3fb27SDimitry Andric// Contiguous store, scalar + imm 271406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BHWD]_IMM$", 271506c3fb27SDimitry Andric "^ST1B_[HSD]_IMM$", 271606c3fb27SDimitry Andric "^ST1H_[SD]_IMM$", 271706c3fb27SDimitry Andric "^ST1W_D_IMM$")>; 271806c3fb27SDimitry Andric 271906c3fb27SDimitry Andric// Contiguous store, scalar + scalar 272006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1S_1V01], (instregex "^ST1H(_[SD])?$")>; 272106c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BWD]$", 272206c3fb27SDimitry Andric "^ST1B_[HSD]$", 272306c3fb27SDimitry Andric "^ST1W_D$")>; 272406c3fb27SDimitry Andric 272506c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + imm 272606c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L01_1V01], (instregex "^ST2[BHWD]_IMM$")>; 272706c3fb27SDimitry Andric 272806c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + scalar 272906c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2L01_2S_2V01], (instrs ST2H)>; 273006c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_2L01_2V01], (instregex "^ST2[BWD]$")>; 273106c3fb27SDimitry Andric 273206c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + imm 273306c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_9L01_9V01], (instregex "^ST3[BHWD]_IMM$")>; 273406c3fb27SDimitry Andric 273506c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + scalar 273606c3fb27SDimitry Andricdef : InstRW<[V2Write_7cyc_9L01_9S_9V01], (instregex "^ST3[BHWD]$")>; 273706c3fb27SDimitry Andric 273806c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + imm 273906c3fb27SDimitry Andricdef : InstRW<[V2Write_11cyc_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>; 274006c3fb27SDimitry Andric 274106c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + scalar 274206c3fb27SDimitry Andricdef : InstRW<[V2Write_11cyc_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>; 274306c3fb27SDimitry Andric 274406c3fb27SDimitry Andric// Non temporal store, scalar + imm 274506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>; 274606c3fb27SDimitry Andric 274706c3fb27SDimitry Andric// Non temporal store, scalar + scalar 274806c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1S_1V], (instrs STNT1H_ZRR)>; 274906c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>; 275006c3fb27SDimitry Andric 275106c3fb27SDimitry Andric// Scatter non temporal store, vector + scalar 32-bit element size 275206c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>; 275306c3fb27SDimitry Andric 275406c3fb27SDimitry Andric// Scatter non temporal store, vector + scalar 64-bit element size 275506c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^STNT1[BHWD]_ZZR_D")>; 275606c3fb27SDimitry Andric 275706c3fb27SDimitry Andric// Scatter store vector + imm 32-bit element size 275806c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_IMM$", 275906c3fb27SDimitry Andric "^SST1W_IMM$")>; 276006c3fb27SDimitry Andric 276106c3fb27SDimitry Andric// Scatter store vector + imm 64-bit element size 276206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_IMM$", 276306c3fb27SDimitry Andric "^SST1D_IMM$")>; 276406c3fb27SDimitry Andric 276506c3fb27SDimitry Andric// Scatter store, 32-bit scaled offset 276606c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_4L01_4V01], 276706c3fb27SDimitry Andric (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>; 276806c3fb27SDimitry Andric 276906c3fb27SDimitry Andric// Scatter store, 32-bit unpacked unscaled offset 277006c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_[SU]XTW$", 277106c3fb27SDimitry Andric "^SST1D_[SU]XTW$")>; 277206c3fb27SDimitry Andric 277306c3fb27SDimitry Andric// Scatter store, 32-bit unpacked scaled offset 277406c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$", 277506c3fb27SDimitry Andric "^SST1D_[SU]XTW_SCALED$")>; 277606c3fb27SDimitry Andric 277706c3fb27SDimitry Andric// Scatter store, 32-bit unscaled offset 277806c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$", 277906c3fb27SDimitry Andric "^SST1W_[SU]XTW$")>; 278006c3fb27SDimitry Andric 278106c3fb27SDimitry Andric// Scatter store, 64-bit scaled offset 278206c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_SCALED$", 278306c3fb27SDimitry Andric "^SST1D_SCALED$")>; 278406c3fb27SDimitry Andric 278506c3fb27SDimitry Andric// Scatter store, 64-bit unscaled offset 278606c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D$", 278706c3fb27SDimitry Andric "^SST1D$")>; 278806c3fb27SDimitry Andric 278906c3fb27SDimitry Andric// SVE Miscellaneous instructions 279006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 279106c3fb27SDimitry Andric 279206c3fb27SDimitry Andric// Read first fault register, unpredicated 279306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M0], (instrs RDFFR_P_REAL)>; 279406c3fb27SDimitry Andric 279506c3fb27SDimitry Andric// Read first fault register, predicated 279606c3fb27SDimitry Andricdef : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs RDFFR_PPz_REAL)>; 279706c3fb27SDimitry Andric 279806c3fb27SDimitry Andric// Read first fault register and set flags 279906c3fb27SDimitry Andricdef : InstRW<[V2Write_4or5cyc_2M0_2M], (instrs RDFFRS_PPz)>; 280006c3fb27SDimitry Andric 280106c3fb27SDimitry Andric// Set first fault register 280206c3fb27SDimitry Andric// Write to first fault register 280306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1M0], (instrs SETFFR, WRFFR)>; 280406c3fb27SDimitry Andric 280506c3fb27SDimitry Andric// Prefetch 280606c3fb27SDimitry Andric// NOTE: This is not specified in the SOG. 280706c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1L], (instregex "^PRF[BHWD]")>; 280806c3fb27SDimitry Andric 280906c3fb27SDimitry Andric// SVE Cryptographic instructions 281006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 281106c3fb27SDimitry Andric 281206c3fb27SDimitry Andric// Crypto AES ops 281306c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]_ZZZ_B$", 281406c3fb27SDimitry Andric "^AESI?MC_ZZ_B$")>; 281506c3fb27SDimitry Andric 281606c3fb27SDimitry Andric// Crypto SHA3 ops 281706c3fb27SDimitry Andricdef : InstRW<[V2Write_2cyc_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$", 281806c3fb27SDimitry Andric "^RAX1_ZZZ_D$", 281906c3fb27SDimitry Andric "^XAR_ZZZI_[BHSD]$")>; 282006c3fb27SDimitry Andric 282106c3fb27SDimitry Andric// Crypto SM4 ops 282206c3fb27SDimitry Andricdef : InstRW<[V2Write_4cyc_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>; 282306c3fb27SDimitry Andric 282406c3fb27SDimitry Andric} 2825