10b57cec5SDimitry Andric//=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the scheduling model for Cavium ThunderX2T99 100b57cec5SDimitry Andric// processors. 110b57cec5SDimitry Andric// Based on Broadcom Vulcan. 120b57cec5SDimitry Andric// 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 160b57cec5SDimitry Andric// 2. Pipeline Description. 170b57cec5SDimitry Andric 180b57cec5SDimitry Andricdef ThunderX2T99Model : SchedMachineModel { 190b57cec5SDimitry Andric let IssueWidth = 4; // 4 micro-ops dispatched at a time. 200b57cec5SDimitry Andric let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer. 210b57cec5SDimitry Andric let LoadLatency = 4; // Optimistic load latency. 220b57cec5SDimitry Andric let MispredictPenalty = 12; // Extra cycles for mispredicted branch. 230b57cec5SDimitry Andric // Determined via a mix of micro-arch details and experimentation. 240b57cec5SDimitry Andric let LoopMicroOpBufferSize = 128; 250b57cec5SDimitry Andric let PostRAScheduler = 1; // Using PostRA sched. 260b57cec5SDimitry Andric let CompleteModel = 1; 270b57cec5SDimitry Andric 28e837bb5cSDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 29fe6060f1SDimitry Andric PAUnsupported.F, 30753f127fSDimitry Andric SMEUnsupported.F, 314c2d3b02SDimitry Andric [HasMTE, HasCSSC]); 320b57cec5SDimitry Andric // FIXME: Remove when all errors have been fixed. 330b57cec5SDimitry Andric let FullInstRWOverlapCheck = 0; 340b57cec5SDimitry Andric} 350b57cec5SDimitry Andric 360b57cec5SDimitry Andriclet SchedModel = ThunderX2T99Model in { 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric// Define the issue ports. 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric// Port 0: ALU, FP/SIMD. 410b57cec5SDimitry Andricdef THX2T99P0 : ProcResource<1>; 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric// Port 1: ALU, FP/SIMD, integer mul/div. 440b57cec5SDimitry Andricdef THX2T99P1 : ProcResource<1>; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric// Port 2: ALU, Branch. 470b57cec5SDimitry Andricdef THX2T99P2 : ProcResource<1>; 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric// Port 3: Store data. 500b57cec5SDimitry Andricdef THX2T99P3 : ProcResource<1>; 510b57cec5SDimitry Andric 520b57cec5SDimitry Andric// Port 4: Load/store. 530b57cec5SDimitry Andricdef THX2T99P4 : ProcResource<1>; 540b57cec5SDimitry Andric 550b57cec5SDimitry Andric// Port 5: Load/store. 560b57cec5SDimitry Andricdef THX2T99P5 : ProcResource<1>; 570b57cec5SDimitry Andric 580b57cec5SDimitry Andric// Define groups for the functional units on each issue port. Each group 590b57cec5SDimitry Andric// created will be used by a WriteRes later on. 600b57cec5SDimitry Andric// 610b57cec5SDimitry Andric// NOTE: Some groups only contain one member. This is a way to create names for 620b57cec5SDimitry Andric// the various functional units that share a single issue port. For example, 630b57cec5SDimitry Andric// "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1. 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric// Integer divide and multiply micro-ops only on port 1. 660b57cec5SDimitry Andricdef THX2T99I1 : ProcResGroup<[THX2T99P1]>; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric// Branch micro-ops only on port 2. 690b57cec5SDimitry Andricdef THX2T99I2 : ProcResGroup<[THX2T99P2]>; 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric// ALU micro-ops on ports 0, 1, and 2. 720b57cec5SDimitry Andricdef THX2T99I012 : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2]>; 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric// Crypto FP/SIMD micro-ops only on port 1. 750b57cec5SDimitry Andricdef THX2T99F1 : ProcResGroup<[THX2T99P1]>; 760b57cec5SDimitry Andric 770b57cec5SDimitry Andric// FP/SIMD micro-ops on ports 0 and 1. 780b57cec5SDimitry Andricdef THX2T99F01 : ProcResGroup<[THX2T99P0, THX2T99P1]>; 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric// Store data micro-ops only on port 3. 810b57cec5SDimitry Andricdef THX2T99SD : ProcResGroup<[THX2T99P3]>; 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric// Load/store micro-ops on ports 4 and 5. 840b57cec5SDimitry Andricdef THX2T99LS01 : ProcResGroup<[THX2T99P4, THX2T99P5]>; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric// 60 entry unified scheduler. 870b57cec5SDimitry Andricdef THX2T99Any : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2, 880b57cec5SDimitry Andric THX2T99P3, THX2T99P4, THX2T99P5]> { 890b57cec5SDimitry Andric let BufferSize = 60; 900b57cec5SDimitry Andric} 910b57cec5SDimitry Andric 920b57cec5SDimitry Andric// Define commonly used write types for InstRW specializations. 930b57cec5SDimitry Andric// All definitions follow the format: THX2T99Write_<NumCycles>Cyc_<Resources>. 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric// 3 cycles on I1. 960b57cec5SDimitry Andricdef THX2T99Write_3Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 970b57cec5SDimitry Andric let Latency = 3; 980b57cec5SDimitry Andric let NumMicroOps = 2; 990b57cec5SDimitry Andric} 1000b57cec5SDimitry Andric 1010b57cec5SDimitry Andric// 1 cycles on I2. 1020b57cec5SDimitry Andricdef THX2T99Write_1Cyc_I2 : SchedWriteRes<[THX2T99I2]> { 1030b57cec5SDimitry Andric let Latency = 1; 1040b57cec5SDimitry Andric let NumMicroOps = 2; 1050b57cec5SDimitry Andric} 1060b57cec5SDimitry Andric 1070b57cec5SDimitry Andric// 4 cycles on I1. 1080b57cec5SDimitry Andricdef THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 1090b57cec5SDimitry Andric let Latency = 4; 1100b57cec5SDimitry Andric let NumMicroOps = 2; 1110b57cec5SDimitry Andric} 1120b57cec5SDimitry Andric 1130b57cec5SDimitry Andric// 23 cycles on I1. 1140b57cec5SDimitry Andricdef THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 1150b57cec5SDimitry Andric let Latency = 23; 1165f757f3fSDimitry Andric let ReleaseAtCycles = [13, 23]; 1170b57cec5SDimitry Andric let NumMicroOps = 4; 1180b57cec5SDimitry Andric} 1190b57cec5SDimitry Andric 1200b57cec5SDimitry Andric// 39 cycles on I1. 1210b57cec5SDimitry Andricdef THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> { 1220b57cec5SDimitry Andric let Latency = 39; 1235f757f3fSDimitry Andric let ReleaseAtCycles = [13, 39]; 1240b57cec5SDimitry Andric let NumMicroOps = 4; 1250b57cec5SDimitry Andric} 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric// 1 cycle on I0, I1, or I2. 1280b57cec5SDimitry Andricdef THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 1290b57cec5SDimitry Andric let Latency = 1; 1300b57cec5SDimitry Andric let NumMicroOps = 2; 1310b57cec5SDimitry Andric} 1320b57cec5SDimitry Andric 1330b57cec5SDimitry Andric// 2 cycles on I0, I1, or I2. 1340b57cec5SDimitry Andricdef THX2T99Write_2Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 1350b57cec5SDimitry Andric let Latency = 2; 1360b57cec5SDimitry Andric let NumMicroOps = 2; 1370b57cec5SDimitry Andric} 1380b57cec5SDimitry Andric 1390b57cec5SDimitry Andric// 4 cycles on I0, I1, or I2. 1400b57cec5SDimitry Andricdef THX2T99Write_4Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 1410b57cec5SDimitry Andric let Latency = 2; 1420b57cec5SDimitry Andric let NumMicroOps = 3; 1430b57cec5SDimitry Andric} 1440b57cec5SDimitry Andric 1450b57cec5SDimitry Andric// 5 cycles on I0, I1, or I2. 1460b57cec5SDimitry Andricdef THX2T99Write_5Cyc_I012 : SchedWriteRes<[THX2T99I012]> { 1470b57cec5SDimitry Andric let Latency = 2; 1480b57cec5SDimitry Andric let NumMicroOps = 3; 1490b57cec5SDimitry Andric} 1500b57cec5SDimitry Andric 1510b57cec5SDimitry Andric// 5 cycles on F1. 1520b57cec5SDimitry Andricdef THX2T99Write_5Cyc_F1 : SchedWriteRes<[THX2T99F1]> { 1530b57cec5SDimitry Andric let Latency = 5; 1540b57cec5SDimitry Andric let NumMicroOps = 2; 1550b57cec5SDimitry Andric} 1560b57cec5SDimitry Andric 1570b57cec5SDimitry Andric// 7 cycles on F1. 1580b57cec5SDimitry Andricdef THX2T99Write_7Cyc_F1 : SchedWriteRes<[THX2T99F1]> { 1590b57cec5SDimitry Andric let Latency = 7; 1600b57cec5SDimitry Andric let NumMicroOps = 2; 1610b57cec5SDimitry Andric} 1620b57cec5SDimitry Andric 1630b57cec5SDimitry Andric// 4 cycles on F0 or F1. 1640b57cec5SDimitry Andricdef THX2T99Write_4Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1650b57cec5SDimitry Andric let Latency = 4; 1660b57cec5SDimitry Andric let NumMicroOps = 2; 1670b57cec5SDimitry Andric} 1680b57cec5SDimitry Andric 1690b57cec5SDimitry Andric// 5 cycles on F0 or F1. 1700b57cec5SDimitry Andricdef THX2T99Write_5Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1710b57cec5SDimitry Andric let Latency = 5; 1720b57cec5SDimitry Andric let NumMicroOps = 2; 1730b57cec5SDimitry Andric} 1740b57cec5SDimitry Andric 1750b57cec5SDimitry Andric// 6 cycles on F0 or F1. 1760b57cec5SDimitry Andricdef THX2T99Write_6Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1770b57cec5SDimitry Andric let Latency = 6; 1780b57cec5SDimitry Andric let NumMicroOps = 3; 1790b57cec5SDimitry Andric} 1800b57cec5SDimitry Andric 1810b57cec5SDimitry Andric// 7 cycles on F0 or F1. 1820b57cec5SDimitry Andricdef THX2T99Write_7Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1830b57cec5SDimitry Andric let Latency = 7; 1840b57cec5SDimitry Andric let NumMicroOps = 3; 1850b57cec5SDimitry Andric} 1860b57cec5SDimitry Andric 1870b57cec5SDimitry Andric// 8 cycles on F0 or F1. 1880b57cec5SDimitry Andricdef THX2T99Write_8Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1890b57cec5SDimitry Andric let Latency = 8; 1900b57cec5SDimitry Andric let NumMicroOps = 3; 1910b57cec5SDimitry Andric} 1920b57cec5SDimitry Andric 1930b57cec5SDimitry Andric// 10 cycles on F0 or F1. 1940b57cec5SDimitry Andricdef THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 1950b57cec5SDimitry Andric let Latency = 10; 1960b57cec5SDimitry Andric let NumMicroOps = 3; 1970b57cec5SDimitry Andric} 1980b57cec5SDimitry Andric 1990b57cec5SDimitry Andric// 16 cycles on F0 or F1. 2000b57cec5SDimitry Andricdef THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 2010b57cec5SDimitry Andric let Latency = 16; 2020b57cec5SDimitry Andric let NumMicroOps = 3; 2035f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2040b57cec5SDimitry Andric} 2050b57cec5SDimitry Andric 2060b57cec5SDimitry Andric// 23 cycles on F0 or F1. 2070b57cec5SDimitry Andricdef THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> { 2080b57cec5SDimitry Andric let Latency = 23; 2090b57cec5SDimitry Andric let NumMicroOps = 3; 2105f757f3fSDimitry Andric let ReleaseAtCycles = [11]; 2110b57cec5SDimitry Andric} 2120b57cec5SDimitry Andric 2130b57cec5SDimitry Andric// 1 cycles on LS0 or LS1. 2140b57cec5SDimitry Andricdef THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 2150b57cec5SDimitry Andric let Latency = 0; 2160b57cec5SDimitry Andric} 2170b57cec5SDimitry Andric 2180b57cec5SDimitry Andric// 1 cycles on LS0 or LS1 and I0, I1, or I2. 2190b57cec5SDimitry Andricdef THX2T99Write_1Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 2200b57cec5SDimitry Andric let Latency = 0; 2210b57cec5SDimitry Andric let NumMicroOps = 2; 2220b57cec5SDimitry Andric} 2230b57cec5SDimitry Andric 2240b57cec5SDimitry Andric// 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 2250b57cec5SDimitry Andricdef THX2T99Write_1Cyc_LS01_I012_I012 : 2260b57cec5SDimitry Andric SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 2270b57cec5SDimitry Andric let Latency = 0; 2280b57cec5SDimitry Andric let NumMicroOps = 3; 2290b57cec5SDimitry Andric} 2300b57cec5SDimitry Andric 2310b57cec5SDimitry Andric// 2 cycles on LS0 or LS1. 2320b57cec5SDimitry Andricdef THX2T99Write_2Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 2330b57cec5SDimitry Andric let Latency = 1; 2340b57cec5SDimitry Andric let NumMicroOps = 2; 2350b57cec5SDimitry Andric} 2360b57cec5SDimitry Andric 2370b57cec5SDimitry Andric// 4 cycles on LS0 or LS1. 2380b57cec5SDimitry Andricdef THX2T99Write_4Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 2390b57cec5SDimitry Andric let Latency = 4; 2400b57cec5SDimitry Andric let NumMicroOps = 4; 2410b57cec5SDimitry Andric} 2420b57cec5SDimitry Andric 2430b57cec5SDimitry Andric// 5 cycles on LS0 or LS1. 2440b57cec5SDimitry Andricdef THX2T99Write_5Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 2450b57cec5SDimitry Andric let Latency = 5; 2460b57cec5SDimitry Andric let NumMicroOps = 3; 2470b57cec5SDimitry Andric} 2480b57cec5SDimitry Andric 2490b57cec5SDimitry Andric// 6 cycles on LS0 or LS1. 2500b57cec5SDimitry Andricdef THX2T99Write_6Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { 2510b57cec5SDimitry Andric let Latency = 6; 2520b57cec5SDimitry Andric let NumMicroOps = 3; 2530b57cec5SDimitry Andric} 2540b57cec5SDimitry Andric 2550b57cec5SDimitry Andric// 4 cycles on LS0 or LS1 and I0, I1, or I2. 2560b57cec5SDimitry Andricdef THX2T99Write_4Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 2570b57cec5SDimitry Andric let Latency = 4; 2580b57cec5SDimitry Andric let NumMicroOps = 3; 2590b57cec5SDimitry Andric} 2600b57cec5SDimitry Andric 2610b57cec5SDimitry Andric// 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 2620b57cec5SDimitry Andricdef THX2T99Write_4Cyc_LS01_I012_I012 : 2630b57cec5SDimitry Andric SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 2640b57cec5SDimitry Andric let Latency = 4; 2650b57cec5SDimitry Andric let NumMicroOps = 3; 2660b57cec5SDimitry Andric} 2670b57cec5SDimitry Andric 2680b57cec5SDimitry Andric// 5 cycles on LS0 or LS1 and I0, I1, or I2. 2690b57cec5SDimitry Andricdef THX2T99Write_5Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 2700b57cec5SDimitry Andric let Latency = 5; 2710b57cec5SDimitry Andric let NumMicroOps = 3; 2720b57cec5SDimitry Andric} 2730b57cec5SDimitry Andric 2740b57cec5SDimitry Andric// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 2750b57cec5SDimitry Andricdef THX2T99Write_5Cyc_LS01_I012_I012 : 2760b57cec5SDimitry Andric SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 2770b57cec5SDimitry Andric let Latency = 5; 2780b57cec5SDimitry Andric let NumMicroOps = 3; 2790b57cec5SDimitry Andric} 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andric// 6 cycles on LS0 or LS1 and I0, I1, or I2. 2820b57cec5SDimitry Andricdef THX2T99Write_6Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 2830b57cec5SDimitry Andric let Latency = 6; 2840b57cec5SDimitry Andric let NumMicroOps = 4; 2850b57cec5SDimitry Andric} 2860b57cec5SDimitry Andric 2870b57cec5SDimitry Andric// 6 cycles on LS0 or LS1 and 2 of I0, I1, or I2. 2880b57cec5SDimitry Andricdef THX2T99Write_6Cyc_LS01_I012_I012 : 2890b57cec5SDimitry Andric SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { 2900b57cec5SDimitry Andric let Latency = 6; 2910b57cec5SDimitry Andric let NumMicroOps = 3; 2920b57cec5SDimitry Andric} 2930b57cec5SDimitry Andric 2940b57cec5SDimitry Andric// 1 cycles on LS0 or LS1 and F0 or F1. 2950b57cec5SDimitry Andricdef THX2T99Write_1Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 2960b57cec5SDimitry Andric let Latency = 1; 2970b57cec5SDimitry Andric let NumMicroOps = 2; 2980b57cec5SDimitry Andric} 2990b57cec5SDimitry Andric 3000b57cec5SDimitry Andric// 5 cycles on LS0 or LS1 and F0 or F1. 3010b57cec5SDimitry Andricdef THX2T99Write_5Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 3020b57cec5SDimitry Andric let Latency = 5; 3030b57cec5SDimitry Andric let NumMicroOps = 3; 3040b57cec5SDimitry Andric} 3050b57cec5SDimitry Andric 3060b57cec5SDimitry Andric// 6 cycles on LS0 or LS1 and F0 or F1. 3070b57cec5SDimitry Andricdef THX2T99Write_6Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 3080b57cec5SDimitry Andric let Latency = 6; 3090b57cec5SDimitry Andric let NumMicroOps = 3; 3100b57cec5SDimitry Andric} 3110b57cec5SDimitry Andric 3120b57cec5SDimitry Andric// 7 cycles on LS0 or LS1 and F0 or F1. 3130b57cec5SDimitry Andricdef THX2T99Write_7Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 3140b57cec5SDimitry Andric let Latency = 7; 3150b57cec5SDimitry Andric let NumMicroOps = 3; 3160b57cec5SDimitry Andric} 3170b57cec5SDimitry Andric 3180b57cec5SDimitry Andric// 8 cycles on LS0 or LS1 and F0 or F1. 3190b57cec5SDimitry Andricdef THX2T99Write_8Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { 3200b57cec5SDimitry Andric let Latency = 8; 3210b57cec5SDimitry Andric let NumMicroOps = 3; 3220b57cec5SDimitry Andric} 3230b57cec5SDimitry Andric 3240b57cec5SDimitry Andric// 8 cycles on LS0 or LS1 and I0, I1, or I2. 3250b57cec5SDimitry Andricdef THX2T99Write_8Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 3260b57cec5SDimitry Andric let Latency = 8; 3270b57cec5SDimitry Andric let NumMicroOps = 4; 3280b57cec5SDimitry Andric} 3290b57cec5SDimitry Andric 3300b57cec5SDimitry Andric// 12 cycles on LS0 or LS1 and I0, I1, or I2. 3310b57cec5SDimitry Andricdef THX2T99Write_12Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 3320b57cec5SDimitry Andric let Latency = 12; 3330b57cec5SDimitry Andric let NumMicroOps = 6; 3340b57cec5SDimitry Andric} 3350b57cec5SDimitry Andric 3360b57cec5SDimitry Andric// 16 cycles on LS0 or LS1 and I0, I1, or I2. 3370b57cec5SDimitry Andricdef THX2T99Write_16Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 3380b57cec5SDimitry Andric let Latency = 16; 3390b57cec5SDimitry Andric let NumMicroOps = 8; 3400b57cec5SDimitry Andric} 3410b57cec5SDimitry Andric 3420b57cec5SDimitry Andric// 24 cycles on LS0 or LS1 and I0, I1, or I2. 3430b57cec5SDimitry Andricdef THX2T99Write_24Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 3440b57cec5SDimitry Andric let Latency = 24; 3450b57cec5SDimitry Andric let NumMicroOps = 12; 3460b57cec5SDimitry Andric} 3470b57cec5SDimitry Andric 3480b57cec5SDimitry Andric// 32 cycles on LS0 or LS1 and I0, I1, or I2. 3490b57cec5SDimitry Andricdef THX2T99Write_32Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { 3500b57cec5SDimitry Andric let Latency = 32; 3510b57cec5SDimitry Andric let NumMicroOps = 16; 3520b57cec5SDimitry Andric} 3530b57cec5SDimitry Andric 3540b57cec5SDimitry Andric// Define commonly used read types. 3550b57cec5SDimitry Andric 3560b57cec5SDimitry Andric// No forwarding is provided for these types. 3570b57cec5SDimitry Andricdef : ReadAdvance<ReadI, 0>; 3580b57cec5SDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 3590b57cec5SDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 3600b57cec5SDimitry Andricdef : ReadAdvance<ReadIM, 0>; 3610b57cec5SDimitry Andricdef : ReadAdvance<ReadIMA, 0>; 3620b57cec5SDimitry Andricdef : ReadAdvance<ReadID, 0>; 3630b57cec5SDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 3640b57cec5SDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 3650b57cec5SDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 366349cc55cSDimitry Andricdef : ReadAdvance<ReadST, 0>; 3670b57cec5SDimitry Andric 3680b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3690b57cec5SDimitry Andric// 3. Instruction Tables. 3700b57cec5SDimitry Andric 3710b57cec5SDimitry Andric//--- 3720b57cec5SDimitry Andric// 3.1 Branch Instructions 3730b57cec5SDimitry Andric//--- 3740b57cec5SDimitry Andric 3750b57cec5SDimitry Andric// Branch, immed 3760b57cec5SDimitry Andric// Branch and link, immed 3770b57cec5SDimitry Andric// Compare and branch 3780b57cec5SDimitry Andricdef : WriteRes<WriteBr, [THX2T99I2]> { 3790b57cec5SDimitry Andric let Latency = 1; 3800b57cec5SDimitry Andric let NumMicroOps = 2; 3810b57cec5SDimitry Andric} 3820b57cec5SDimitry Andric 3830b57cec5SDimitry Andric// Branch, register 3840b57cec5SDimitry Andric// Branch and link, register != LR 3850b57cec5SDimitry Andric// Branch and link, register = LR 3860b57cec5SDimitry Andricdef : WriteRes<WriteBrReg, [THX2T99I2]> { 3870b57cec5SDimitry Andric let Latency = 1; 3880b57cec5SDimitry Andric let NumMicroOps = 2; 3890b57cec5SDimitry Andric} 3900b57cec5SDimitry Andric 3910b57cec5SDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 3920b57cec5SDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 3930b57cec5SDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 3940b57cec5SDimitry Andric 3950b57cec5SDimitry Andricdef : WriteRes<WriteAtomic, []> { 3960b57cec5SDimitry Andric let Latency = 4; 3970b57cec5SDimitry Andric let NumMicroOps = 2; 3980b57cec5SDimitry Andric} 3990b57cec5SDimitry Andric 4000b57cec5SDimitry Andric//--- 4010b57cec5SDimitry Andric// Branch 4020b57cec5SDimitry Andric//--- 4030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>; 4040b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>; 4050b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B..$")>; 4060b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I2], 4070b57cec5SDimitry Andric (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>; 4080b57cec5SDimitry Andric 4090b57cec5SDimitry Andric//--- 4100b57cec5SDimitry Andric// 3.2 Arithmetic and Logical Instructions 4110b57cec5SDimitry Andric// 3.3 Move and Shift Instructions 4120b57cec5SDimitry Andric//--- 4130b57cec5SDimitry Andric 4140b57cec5SDimitry Andric 4150b57cec5SDimitry Andric// ALU, basic 4160b57cec5SDimitry Andric// Conditional compare 4170b57cec5SDimitry Andric// Conditional select 4180b57cec5SDimitry Andric// Address generation 4190b57cec5SDimitry Andricdef : WriteRes<WriteI, [THX2T99I012]> { 4200b57cec5SDimitry Andric let Latency = 1; 4215f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 4220b57cec5SDimitry Andric let NumMicroOps = 2; 4230b57cec5SDimitry Andric} 4240b57cec5SDimitry Andric 4250b57cec5SDimitry Andricdef : InstRW<[WriteI], 4260b57cec5SDimitry Andric (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 4270b57cec5SDimitry Andric "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 4280b57cec5SDimitry Andric "ADC(W|X)r", 4290b57cec5SDimitry Andric "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 4300b57cec5SDimitry Andric "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 4310b57cec5SDimitry Andric "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 4320b57cec5SDimitry Andric "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 4330b57cec5SDimitry Andric "SBCS(W|X)r", "CCMN(W|X)(i|r)", 4340b57cec5SDimitry Andric "CCMP(W|X)(i|r)", "CSEL(W|X)r", 4350b57cec5SDimitry Andric "CSINC(W|X)r", "CSINV(W|X)r", 4360b57cec5SDimitry Andric "CSNEG(W|X)r")>; 4370b57cec5SDimitry Andric 4380b57cec5SDimitry Andricdef : InstRW<[WriteI], (instrs COPY)>; 4390b57cec5SDimitry Andric 4400b57cec5SDimitry Andric// ALU, extend and/or shift 4410b57cec5SDimitry Andricdef : WriteRes<WriteISReg, [THX2T99I012]> { 4420b57cec5SDimitry Andric let Latency = 2; 4435f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 4440b57cec5SDimitry Andric let NumMicroOps = 2; 4450b57cec5SDimitry Andric} 4460b57cec5SDimitry Andric 4470b57cec5SDimitry Andricdef : InstRW<[WriteISReg], 4480b57cec5SDimitry Andric (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 4490b57cec5SDimitry Andric "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 4500b57cec5SDimitry Andric "ADC(W|X)r", 4510b57cec5SDimitry Andric "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 4520b57cec5SDimitry Andric "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 4530b57cec5SDimitry Andric "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 4540b57cec5SDimitry Andric "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 4550b57cec5SDimitry Andric "SBCS(W|X)r", "CCMN(W|X)(i|r)", 4560b57cec5SDimitry Andric "CCMP(W|X)(i|r)", "CSEL(W|X)r", 4570b57cec5SDimitry Andric "CSINC(W|X)r", "CSINV(W|X)r", 4580b57cec5SDimitry Andric "CSNEG(W|X)r")>; 4590b57cec5SDimitry Andric 4600b57cec5SDimitry Andricdef : WriteRes<WriteIEReg, [THX2T99I012]> { 4610b57cec5SDimitry Andric let Latency = 1; 4625f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 4630b57cec5SDimitry Andric let NumMicroOps = 2; 4640b57cec5SDimitry Andric} 4650b57cec5SDimitry Andric 4660b57cec5SDimitry Andricdef : InstRW<[WriteIEReg], 4670b57cec5SDimitry Andric (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", 4680b57cec5SDimitry Andric "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", 4690b57cec5SDimitry Andric "ADC(W|X)r", 4700b57cec5SDimitry Andric "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", 4710b57cec5SDimitry Andric "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", 4720b57cec5SDimitry Andric "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", 4730b57cec5SDimitry Andric "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", 4740b57cec5SDimitry Andric "SBCS(W|X)r", "CCMN(W|X)(i|r)", 4750b57cec5SDimitry Andric "CCMP(W|X)(i|r)", "CSEL(W|X)r", 4760b57cec5SDimitry Andric "CSINC(W|X)r", "CSINV(W|X)r", 4770b57cec5SDimitry Andric "CSNEG(W|X)r")>; 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andric// Move immed 4800b57cec5SDimitry Andricdef : WriteRes<WriteImm, [THX2T99I012]> { 4810b57cec5SDimitry Andric let Latency = 1; 4820b57cec5SDimitry Andric let NumMicroOps = 2; 4830b57cec5SDimitry Andric} 4840b57cec5SDimitry Andric 4850b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], 4860b57cec5SDimitry Andric (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>; 4870b57cec5SDimitry Andric 4880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], 4890b57cec5SDimitry Andric (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>; 4900b57cec5SDimitry Andric 4910b57cec5SDimitry Andric// Variable shift 4920b57cec5SDimitry Andricdef : WriteRes<WriteIS, [THX2T99I012]> { 4930b57cec5SDimitry Andric let Latency = 1; 4940b57cec5SDimitry Andric let NumMicroOps = 2; 4950b57cec5SDimitry Andric} 4960b57cec5SDimitry Andric 4970b57cec5SDimitry Andric//--- 4980b57cec5SDimitry Andric// 3.4 Divide and Multiply Instructions 4990b57cec5SDimitry Andric//--- 5000b57cec5SDimitry Andric 5010b57cec5SDimitry Andric// Divide, W-form 5020b57cec5SDimitry Andric// Latency range of 13-23/13-39. 5030b57cec5SDimitry Andricdef : WriteRes<WriteID32, [THX2T99I1]> { 5040b57cec5SDimitry Andric let Latency = 39; 5055f757f3fSDimitry Andric let ReleaseAtCycles = [39]; 5060b57cec5SDimitry Andric let NumMicroOps = 4; 5070b57cec5SDimitry Andric} 5080b57cec5SDimitry Andric 5090b57cec5SDimitry Andric// Divide, X-form 5100b57cec5SDimitry Andricdef : WriteRes<WriteID64, [THX2T99I1]> { 5110b57cec5SDimitry Andric let Latency = 23; 5125f757f3fSDimitry Andric let ReleaseAtCycles = [23]; 5130b57cec5SDimitry Andric let NumMicroOps = 4; 5140b57cec5SDimitry Andric} 5150b57cec5SDimitry Andric 5160b57cec5SDimitry Andric// Multiply accumulate, W-form 5170b57cec5SDimitry Andricdef : WriteRes<WriteIM32, [THX2T99I012]> { 5180b57cec5SDimitry Andric let Latency = 5; 5190b57cec5SDimitry Andric let NumMicroOps = 3; 5200b57cec5SDimitry Andric} 5210b57cec5SDimitry Andric 5220b57cec5SDimitry Andric// Multiply accumulate, X-form 5230b57cec5SDimitry Andricdef : WriteRes<WriteIM64, [THX2T99I012]> { 5240b57cec5SDimitry Andric let Latency = 5; 5250b57cec5SDimitry Andric let NumMicroOps = 3; 5260b57cec5SDimitry Andric} 5270b57cec5SDimitry Andric 5280b57cec5SDimitry Andric//def : InstRW<[WriteIM32, ReadIM, ReadIM, ReadIMA, THX2T99Write_5Cyc_I012], 5290b57cec5SDimitry Andric// (instrs MADDWrrr, MSUBWrrr)>; 5300b57cec5SDimitry Andricdef : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>; 5310b57cec5SDimitry Andricdef : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>; 5320b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_I012], 5330b57cec5SDimitry Andric (instregex "(S|U)(MADDL|MSUBL)rrr")>; 5340b57cec5SDimitry Andric 5350b57cec5SDimitry Andricdef : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>; 5360b57cec5SDimitry Andricdef : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>; 5370b57cec5SDimitry Andric 5380b57cec5SDimitry Andric// Bitfield extract, two reg 5390b57cec5SDimitry Andricdef : WriteRes<WriteExtr, [THX2T99I012]> { 5400b57cec5SDimitry Andric let Latency = 1; 5410b57cec5SDimitry Andric let NumMicroOps = 2; 5420b57cec5SDimitry Andric} 5430b57cec5SDimitry Andric 5440b57cec5SDimitry Andric// Multiply high 5450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_I1], (instrs SMULHrr, UMULHrr)>; 5460b57cec5SDimitry Andric 5470b57cec5SDimitry Andric// Miscellaneous Data-Processing Instructions 5480b57cec5SDimitry Andric// Bitfield extract 5490b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], (instrs EXTRWrri, EXTRXrri)>; 5500b57cec5SDimitry Andric 5510b57cec5SDimitry Andric// Bitifield move - basic 5520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], 5530b57cec5SDimitry Andric (instrs SBFMWri, SBFMXri, UBFMWri, UBFMXri)>; 5540b57cec5SDimitry Andric 5550b57cec5SDimitry Andric// Bitfield move, insert 5560b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>; 5570b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>; 5580b57cec5SDimitry Andric 5590b57cec5SDimitry Andric// Count leading 5600b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$", 5610b57cec5SDimitry Andric "^CLZ(W|X)r$")>; 5620b57cec5SDimitry Andric 5630b57cec5SDimitry Andric// Reverse bits 5640b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_I012], (instrs RBITWr, RBITXr)>; 5650b57cec5SDimitry Andric 5660b57cec5SDimitry Andric// Cryptography Extensions 5670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AES[DE]")>; 5680b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AESI?MC")>; 5690b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL")>; 5700b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1SU0")>; 5710b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1(H|SU1)")>; 5720b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1[CMP]")>; 5730b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256SU0")>; 5740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256(H|H2|SU1)")>; 5750b57cec5SDimitry Andric 5760b57cec5SDimitry Andric// CRC Instructions 5770b57cec5SDimitry Andric// def : InstRW<[THX2T99Write_4Cyc_I1], (instregex "^CRC32", "^CRC32C")>; 5780b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_I1], 5790b57cec5SDimitry Andric (instrs CRC32Brr, CRC32Hrr, CRC32Wrr, CRC32Xrr)>; 5800b57cec5SDimitry Andric 5810b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_I1], 5820b57cec5SDimitry Andric (instrs CRC32CBrr, CRC32CHrr, CRC32CWrr, CRC32CXrr)>; 5830b57cec5SDimitry Andric 5840b57cec5SDimitry Andric// Reverse bits/bytes 5850b57cec5SDimitry Andric// NOTE: Handled by WriteI. 5860b57cec5SDimitry Andric 5870b57cec5SDimitry Andric//--- 5880b57cec5SDimitry Andric// 3.6 Load Instructions 5890b57cec5SDimitry Andric// 3.10 FP Load Instructions 5900b57cec5SDimitry Andric//--- 5910b57cec5SDimitry Andric 5920b57cec5SDimitry Andric// Load register, literal 5930b57cec5SDimitry Andric// Load register, unscaled immed 5940b57cec5SDimitry Andric// Load register, immed unprivileged 5950b57cec5SDimitry Andric// Load register, unsigned immed 5960b57cec5SDimitry Andricdef : WriteRes<WriteLD, [THX2T99LS01]> { 5970b57cec5SDimitry Andric let Latency = 4; 5980b57cec5SDimitry Andric let NumMicroOps = 4; 5990b57cec5SDimitry Andric} 6000b57cec5SDimitry Andric 6010b57cec5SDimitry Andric// Load register, immed post-index 6020b57cec5SDimitry Andric// NOTE: Handled by WriteLD, WriteI. 6030b57cec5SDimitry Andric// Load register, immed pre-index 6040b57cec5SDimitry Andric// NOTE: Handled by WriteLD, WriteAdr. 6050b57cec5SDimitry Andricdef : WriteRes<WriteAdr, [THX2T99I012]> { 6060b57cec5SDimitry Andric let Latency = 1; 6070b57cec5SDimitry Andric let NumMicroOps = 2; 6080b57cec5SDimitry Andric} 6090b57cec5SDimitry Andric 6100b57cec5SDimitry Andric// Load pair, immed offset, normal 6110b57cec5SDimitry Andric// Load pair, immed offset, signed words, base != SP 6120b57cec5SDimitry Andric// Load pair, immed offset signed words, base = SP 6130b57cec5SDimitry Andric// LDP only breaks into *one* LS micro-op. Thus 6140b57cec5SDimitry Andric// the resources are handled by WriteLD. 6150b57cec5SDimitry Andricdef : WriteRes<WriteLDHi, []> { 6160b57cec5SDimitry Andric let Latency = 5; 6170b57cec5SDimitry Andric let NumMicroOps = 5; 6180b57cec5SDimitry Andric} 6190b57cec5SDimitry Andric 6200b57cec5SDimitry Andric// Load register offset, basic 6210b57cec5SDimitry Andric// Load register, register offset, scale by 4/8 6220b57cec5SDimitry Andric// Load register, register offset, scale by 2 6230b57cec5SDimitry Andric// Load register offset, extend 6240b57cec5SDimitry Andric// Load register, register offset, extend, scale by 4/8 6250b57cec5SDimitry Andric// Load register, register offset, extend, scale by 2 6260b57cec5SDimitry Andricdef THX2T99WriteLDIdx : SchedWriteVariant<[ 6270b57cec5SDimitry Andric SchedVar<ScaledIdxPred, [THX2T99Write_6Cyc_LS01_I012_I012]>, 6280b57cec5SDimitry Andric SchedVar<NoSchedPred, [THX2T99Write_5Cyc_LS01_I012]>]>; 6290b57cec5SDimitry Andricdef : SchedAlias<WriteLDIdx, THX2T99WriteLDIdx>; 6300b57cec5SDimitry Andric 6310b57cec5SDimitry Andricdef THX2T99ReadAdrBase : SchedReadVariant<[ 6320b57cec5SDimitry Andric SchedVar<ScaledIdxPred, [ReadDefault]>, 6330b57cec5SDimitry Andric SchedVar<NoSchedPred, [ReadDefault]>]>; 6340b57cec5SDimitry Andricdef : SchedAlias<ReadAdrBase, THX2T99ReadAdrBase>; 6350b57cec5SDimitry Andric 6360b57cec5SDimitry Andric// Load pair, immed pre-index, normal 6370b57cec5SDimitry Andric// Load pair, immed pre-index, signed words 6380b57cec5SDimitry Andric// Load pair, immed post-index, normal 6390b57cec5SDimitry Andric// Load pair, immed post-index, signed words 6400b57cec5SDimitry Andric// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr. 6410b57cec5SDimitry Andric 6420b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPDi)>; 6430b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPQi)>; 6440b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPSi)>; 6450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPWi)>; 6460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPXi)>; 6470b57cec5SDimitry Andric 6480b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPDi)>; 6490b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPQi)>; 6500b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSi)>; 6510b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSWi)>; 6520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPWi)>; 6530b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPXi)>; 6540b57cec5SDimitry Andric 6550b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRBui)>; 6560b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDui)>; 6570b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRHui)>; 6580b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRQui)>; 6590b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRSui)>; 6600b57cec5SDimitry Andric 6610b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDl)>; 6620b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRQl)>; 6630b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRWl)>; 6640b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRXl)>; 6650b57cec5SDimitry Andric 6660b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRBi)>; 6670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRHi)>; 6680b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRWi)>; 6690b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRXi)>; 6700b57cec5SDimitry Andric 6710b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBWi)>; 6720b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBXi)>; 6730b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHWi)>; 6740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHXi)>; 6750b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSWi)>; 6760b57cec5SDimitry Andric 6770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 6780b57cec5SDimitry Andric (instrs LDPDpre)>; 6790b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 6800b57cec5SDimitry Andric (instrs LDPQpre)>; 6810b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 6820b57cec5SDimitry Andric (instrs LDPSpre)>; 6830b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 6840b57cec5SDimitry Andric (instrs LDPWpre)>; 6850b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 6860b57cec5SDimitry Andric (instrs LDPWpre)>; 6870b57cec5SDimitry Andric 6880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRBpre)>; 6890b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRDpre)>; 6900b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRHpre)>; 6910b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRQpre)>; 6920b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRSpre)>; 6930b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRWpre)>; 6940b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRXpre)>; 6950b57cec5SDimitry Andric 6960b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpre)>; 6970b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpre)>; 6980b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpost)>; 6990b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpost)>; 7000b57cec5SDimitry Andric 7010b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpre)>; 7020b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpre)>; 7030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpost)>; 7040b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpost)>; 7050b57cec5SDimitry Andric 7060b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpre)>; 7070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpost)>; 7080b57cec5SDimitry Andric 7090b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpre)>; 7100b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpost)>; 7110b57cec5SDimitry Andric 7120b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 7130b57cec5SDimitry Andric (instrs LDPDpost)>; 7140b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 7150b57cec5SDimitry Andric (instrs LDPQpost)>; 7160b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 7170b57cec5SDimitry Andric (instrs LDPSpost)>; 7180b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 7190b57cec5SDimitry Andric (instrs LDPWpost)>; 7200b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], 7210b57cec5SDimitry Andric (instrs LDPXpost)>; 7220b57cec5SDimitry Andric 7230b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>; 7240b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>; 7250b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>; 7260b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>; 7270b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>; 7280b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRWpost)>; 7290b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRXpost)>; 7300b57cec5SDimitry Andric 7310b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7320b57cec5SDimitry Andric (instrs LDPDpre)>; 7330b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7340b57cec5SDimitry Andric (instrs LDPQpre)>; 7350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7360b57cec5SDimitry Andric (instrs LDPSpre)>; 7370b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7380b57cec5SDimitry Andric (instrs LDPWpre)>; 7390b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7400b57cec5SDimitry Andric (instrs LDPXpre)>; 7410b57cec5SDimitry Andric 7420b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRBpre)>; 7430b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRDpre)>; 7440b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRHpre)>; 7450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRQpre)>; 7460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRSpre)>; 7470b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRWpre)>; 7480b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRXpre)>; 7490b57cec5SDimitry Andric 7500b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7510b57cec5SDimitry Andric (instrs LDPDpost)>; 7520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7530b57cec5SDimitry Andric (instrs LDPQpost)>; 7540b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7550b57cec5SDimitry Andric (instrs LDPSpost)>; 7560b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7570b57cec5SDimitry Andric (instrs LDPWpost)>; 7580b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], 7590b57cec5SDimitry Andric (instrs LDPXpost)>; 7600b57cec5SDimitry Andric 7610b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRBpost)>; 7620b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRDpost)>; 7630b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRHpost)>; 7640b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRQpost)>; 7650b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRSpost)>; 7660b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRWpost)>; 7670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRXpost)>; 7680b57cec5SDimitry Andric 7690b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroW)>; 7700b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroW)>; 7710b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroW)>; 7720b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroW)>; 7730b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroW)>; 7740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroW)>; 7750b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroW)>; 7760b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroW)>; 7770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroW)>; 7780b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroW)>; 7790b57cec5SDimitry Andric 7800b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroX)>; 7810b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroX)>; 7820b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroX)>; 7830b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroX)>; 7840b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroX)>; 7850b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroX)>; 7860b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroX)>; 7870b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroX)>; 7880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroX)>; 7890b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroX)>; 7900b57cec5SDimitry Andric 7910b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 7920b57cec5SDimitry Andric (instrs LDRBroW)>; 7930b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 7940b57cec5SDimitry Andric (instrs LDRBroW)>; 7950b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 7960b57cec5SDimitry Andric (instrs LDRDroW)>; 7970b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 7980b57cec5SDimitry Andric (instrs LDRHroW)>; 7990b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8000b57cec5SDimitry Andric (instrs LDRHHroW)>; 8010b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8020b57cec5SDimitry Andric (instrs LDRQroW)>; 8030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8040b57cec5SDimitry Andric (instrs LDRSroW)>; 8050b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8060b57cec5SDimitry Andric (instrs LDRSHWroW)>; 8070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8080b57cec5SDimitry Andric (instrs LDRSHXroW)>; 8090b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8100b57cec5SDimitry Andric (instrs LDRWroW)>; 8110b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8120b57cec5SDimitry Andric (instrs LDRXroW)>; 8130b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8140b57cec5SDimitry Andric (instrs LDRBroX)>; 8150b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8160b57cec5SDimitry Andric (instrs LDRDroX)>; 8170b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8180b57cec5SDimitry Andric (instrs LDRHroX)>; 8190b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8200b57cec5SDimitry Andric (instrs LDRHHroX)>; 8210b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8220b57cec5SDimitry Andric (instrs LDRQroX)>; 8230b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8240b57cec5SDimitry Andric (instrs LDRSroX)>; 8250b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8260b57cec5SDimitry Andric (instrs LDRSHWroX)>; 8270b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8280b57cec5SDimitry Andric (instrs LDRSHXroX)>; 8290b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8300b57cec5SDimitry Andric (instrs LDRWroX)>; 8310b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], 8320b57cec5SDimitry Andric (instrs LDRXroX)>; 8330b57cec5SDimitry Andric 8340b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBi)>; 8350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBBi)>; 8360b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURDi)>; 8370b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHi)>; 8380b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHHi)>; 8390b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURQi)>; 8400b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSi)>; 8410b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURXi)>; 8420b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBWi)>; 8430b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBXi)>; 8440b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHWi)>; 8450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHXi)>; 8460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSWi)>; 8470b57cec5SDimitry Andric 8480b57cec5SDimitry Andric//--- 8490b57cec5SDimitry Andric// Prefetch 8500b57cec5SDimitry Andric//--- 8510b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMl)>; 8520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFUMi)>; 8530b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMui)>; 8540b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroW)>; 8550b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroX)>; 8560b57cec5SDimitry Andric 8570b57cec5SDimitry Andric//-- 8580b57cec5SDimitry Andric// 3.7 Store Instructions 8590b57cec5SDimitry Andric// 3.11 FP Store Instructions 8600b57cec5SDimitry Andric//-- 8610b57cec5SDimitry Andric 8620b57cec5SDimitry Andric// Store register, unscaled immed 8630b57cec5SDimitry Andric// Store register, immed unprivileged 8640b57cec5SDimitry Andric// Store register, unsigned immed 8650b57cec5SDimitry Andricdef : WriteRes<WriteST, [THX2T99LS01, THX2T99SD]> { 8660b57cec5SDimitry Andric let Latency = 1; 8670b57cec5SDimitry Andric let NumMicroOps = 2; 8680b57cec5SDimitry Andric} 8690b57cec5SDimitry Andric 8700b57cec5SDimitry Andric// Store register, immed post-index 8710b57cec5SDimitry Andric// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase 8720b57cec5SDimitry Andric 8730b57cec5SDimitry Andric// Store register, immed pre-index 8740b57cec5SDimitry Andric// NOTE: Handled by WriteAdr, WriteST 8750b57cec5SDimitry Andric 8760b57cec5SDimitry Andric// Store register, register offset, basic 8770b57cec5SDimitry Andric// Store register, register offset, scaled by 4/8 8780b57cec5SDimitry Andric// Store register, register offset, scaled by 2 8790b57cec5SDimitry Andric// Store register, register offset, extend 8800b57cec5SDimitry Andric// Store register, register offset, extend, scale by 4/8 8810b57cec5SDimitry Andric// Store register, register offset, extend, scale by 1 8820b57cec5SDimitry Andricdef : WriteRes<WriteSTIdx, [THX2T99LS01, THX2T99SD, THX2T99I012]> { 8830b57cec5SDimitry Andric let Latency = 1; 8840b57cec5SDimitry Andric let NumMicroOps = 3; 8850b57cec5SDimitry Andric} 8860b57cec5SDimitry Andric 8870b57cec5SDimitry Andric// Store pair, immed offset, W-form 8880b57cec5SDimitry Andric// Store pair, immed offset, X-form 8890b57cec5SDimitry Andricdef : WriteRes<WriteSTP, [THX2T99LS01, THX2T99SD]> { 8900b57cec5SDimitry Andric let Latency = 1; 8910b57cec5SDimitry Andric let NumMicroOps = 2; 8920b57cec5SDimitry Andric} 8930b57cec5SDimitry Andric 8940b57cec5SDimitry Andric// Store pair, immed post-index, W-form 8950b57cec5SDimitry Andric// Store pair, immed post-index, X-form 8960b57cec5SDimitry Andric// Store pair, immed pre-index, W-form 8970b57cec5SDimitry Andric// Store pair, immed pre-index, X-form 8980b57cec5SDimitry Andric// NOTE: Handled by WriteAdr, WriteSTP. 8990b57cec5SDimitry Andric 9000b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBi)>; 9010b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBBi)>; 9020b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURDi)>; 9030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHi)>; 9040b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHHi)>; 9050b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURQi)>; 9060b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURSi)>; 9070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURWi)>; 9080b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURXi)>; 9090b57cec5SDimitry Andric 9100b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRBi)>; 9110b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRHi)>; 9120b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRWi)>; 9130b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRXi)>; 9140b57cec5SDimitry Andric 9150b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPDi)>; 9160b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPQi)>; 9170b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPXi)>; 9180b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPWi)>; 9190b57cec5SDimitry Andric 9200b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPDi)>; 9210b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPQi)>; 9220b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPXi)>; 9230b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPWi)>; 9240b57cec5SDimitry Andric 9250b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRBui)>; 9260b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRBui)>; 9270b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRDui)>; 9280b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRDui)>; 9290b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRHui)>; 9300b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRHui)>; 9310b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRQui)>; 9320b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRQui)>; 9330b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRXui)>; 9340b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRXui)>; 9350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRWui)>; 9360b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRWui)>; 9370b57cec5SDimitry Andric 9380b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9390b57cec5SDimitry Andric (instrs STPDpre, STPDpost)>; 9400b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9410b57cec5SDimitry Andric (instrs STPDpre, STPDpost)>; 9420b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9430b57cec5SDimitry Andric (instrs STPDpre, STPDpost)>; 9440b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9450b57cec5SDimitry Andric (instrs STPDpre, STPDpost)>; 9460b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9470b57cec5SDimitry Andric (instrs STPQpre, STPQpost)>; 9480b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9490b57cec5SDimitry Andric (instrs STPQpre, STPQpost)>; 9500b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9510b57cec5SDimitry Andric (instrs STPQpre, STPQpost)>; 9520b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9530b57cec5SDimitry Andric (instrs STPQpre, STPQpost)>; 9540b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9550b57cec5SDimitry Andric (instrs STPSpre, STPSpost)>; 9560b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9570b57cec5SDimitry Andric (instrs STPSpre, STPSpost)>; 9580b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9590b57cec5SDimitry Andric (instrs STPSpre, STPSpost)>; 9600b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9610b57cec5SDimitry Andric (instrs STPSpre, STPSpost)>; 9620b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9630b57cec5SDimitry Andric (instrs STPWpre, STPWpost)>; 9640b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9650b57cec5SDimitry Andric (instrs STPWpre, STPWpost)>; 9660b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9670b57cec5SDimitry Andric (instrs STPWpre, STPWpost)>; 9680b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9690b57cec5SDimitry Andric (instrs STPWpre, STPWpost)>; 9700b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9710b57cec5SDimitry Andric (instrs STPXpre, STPXpost)>; 9720b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9730b57cec5SDimitry Andric (instrs STPXpre, STPXpost)>; 9740b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9750b57cec5SDimitry Andric (instrs STPXpre, STPXpost)>; 9760b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9770b57cec5SDimitry Andric (instrs STPXpre, STPXpost)>; 9780b57cec5SDimitry Andric 9790b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9800b57cec5SDimitry Andric (instrs STRBpre, STRBpost)>; 9810b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9820b57cec5SDimitry Andric (instrs STRBpre, STRBpost)>; 9830b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9840b57cec5SDimitry Andric (instrs STRBpre, STRBpost)>; 9850b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9860b57cec5SDimitry Andric (instrs STRBpre, STRBpost)>; 9870b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9880b57cec5SDimitry Andric (instrs STRBBpre, STRBBpost)>; 9890b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9900b57cec5SDimitry Andric (instrs STRBBpre, STRBBpost)>; 9910b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 9920b57cec5SDimitry Andric (instrs STRBBpre, STRBBpost)>; 9930b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 9940b57cec5SDimitry Andric (instrs STRBBpre, STRBBpost)>; 9950b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 9960b57cec5SDimitry Andric (instrs STRDpre, STRDpost)>; 9970b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 9980b57cec5SDimitry Andric (instrs STRDpre, STRDpost)>; 9990b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10000b57cec5SDimitry Andric (instrs STRDpre, STRDpost)>; 10010b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10020b57cec5SDimitry Andric (instrs STRDpre, STRDpost)>; 10030b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10040b57cec5SDimitry Andric (instrs STRHpre, STRHpost)>; 10050b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10060b57cec5SDimitry Andric (instrs STRHpre, STRHpost)>; 10070b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10080b57cec5SDimitry Andric (instrs STRHpre, STRHpost)>; 10090b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10100b57cec5SDimitry Andric (instrs STRHpre, STRHpost)>; 10110b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10120b57cec5SDimitry Andric (instrs STRHHpre, STRHHpost)>; 10130b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10140b57cec5SDimitry Andric (instrs STRHHpre, STRHHpost)>; 10150b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10160b57cec5SDimitry Andric (instrs STRHHpre, STRHHpost)>; 10170b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10180b57cec5SDimitry Andric (instrs STRHHpre, STRHHpost)>; 10190b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10200b57cec5SDimitry Andric (instrs STRQpre, STRQpost)>; 10210b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10220b57cec5SDimitry Andric (instrs STRQpre, STRQpost)>; 10230b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10240b57cec5SDimitry Andric (instrs STRQpre, STRQpost)>; 10250b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10260b57cec5SDimitry Andric (instrs STRQpre, STRQpost)>; 10270b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10280b57cec5SDimitry Andric (instrs STRSpre, STRSpost)>; 10290b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10300b57cec5SDimitry Andric (instrs STRSpre, STRSpost)>; 10310b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10320b57cec5SDimitry Andric (instrs STRSpre, STRSpost)>; 10330b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10340b57cec5SDimitry Andric (instrs STRSpre, STRSpost)>; 10350b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10360b57cec5SDimitry Andric (instrs STRWpre, STRWpost)>; 10370b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10380b57cec5SDimitry Andric (instrs STRWpre, STRWpost)>; 10390b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10400b57cec5SDimitry Andric (instrs STRWpre, STRWpost)>; 10410b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10420b57cec5SDimitry Andric (instrs STRWpre, STRWpost)>; 10430b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], 10440b57cec5SDimitry Andric (instrs STRXpre, STRXpost)>; 10450b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10460b57cec5SDimitry Andric (instrs STRXpre, STRXpost)>; 10470b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], 10480b57cec5SDimitry Andric (instrs STRXpre, STRXpost)>; 10490b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10500b57cec5SDimitry Andric (instrs STRXpre, STRXpost)>; 10510b57cec5SDimitry Andric 10520b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10530b57cec5SDimitry Andric (instrs STRBroW, STRBroX)>; 10540b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10550b57cec5SDimitry Andric (instrs STRBroW, STRBroX)>; 10560b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10570b57cec5SDimitry Andric (instrs STRBBroW, STRBBroX)>; 10580b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10590b57cec5SDimitry Andric (instrs STRBBroW, STRBBroX)>; 10600b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10610b57cec5SDimitry Andric (instrs STRDroW, STRDroX)>; 10620b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10630b57cec5SDimitry Andric (instrs STRDroW, STRDroX)>; 10640b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10650b57cec5SDimitry Andric (instrs STRHroW, STRHroX)>; 10660b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10670b57cec5SDimitry Andric (instrs STRHroW, STRHroX)>; 10680b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10690b57cec5SDimitry Andric (instrs STRHHroW, STRHHroX)>; 10700b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10710b57cec5SDimitry Andric (instrs STRHHroW, STRHHroX)>; 10720b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10730b57cec5SDimitry Andric (instrs STRQroW, STRQroX)>; 10740b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10750b57cec5SDimitry Andric (instrs STRQroW, STRQroX)>; 10760b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10770b57cec5SDimitry Andric (instrs STRSroW, STRSroX)>; 10780b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10790b57cec5SDimitry Andric (instrs STRSroW, STRSroX)>; 10800b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10810b57cec5SDimitry Andric (instrs STRWroW, STRWroX)>; 10820b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10830b57cec5SDimitry Andric (instrs STRWroW, STRWroX)>; 10840b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], 10850b57cec5SDimitry Andric (instrs STRXroW, STRXroX)>; 10860b57cec5SDimitry Andricdef : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], 10870b57cec5SDimitry Andric (instrs STRXroW, STRXroX)>; 10880b57cec5SDimitry Andric 10890b57cec5SDimitry Andric//--- 10900b57cec5SDimitry Andric// 3.8 FP Data Processing Instructions 10910b57cec5SDimitry Andric//--- 10920b57cec5SDimitry Andric 10930b57cec5SDimitry Andric// FP absolute value 10940b57cec5SDimitry Andric// FP min/max 10950b57cec5SDimitry Andric// FP negate 10960b57cec5SDimitry Andricdef : WriteRes<WriteF, [THX2T99F01]> { 10970b57cec5SDimitry Andric let Latency = 5; 10980b57cec5SDimitry Andric let NumMicroOps = 2; 10990b57cec5SDimitry Andric} 11000b57cec5SDimitry Andric 11010b57cec5SDimitry Andric// FP arithmetic 11020b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADD", "^FSUB")>; 11030b57cec5SDimitry Andric 11040b57cec5SDimitry Andric// FP compare 11050b57cec5SDimitry Andricdef : WriteRes<WriteFCmp, [THX2T99F01]> { 11060b57cec5SDimitry Andric let Latency = 5; 11070b57cec5SDimitry Andric let NumMicroOps = 2; 11080b57cec5SDimitry Andric} 11090b57cec5SDimitry Andric 11100b57cec5SDimitry Andric// FP Mul, Div, Sqrt 11110b57cec5SDimitry Andricdef : WriteRes<WriteFDiv, [THX2T99F01]> { 11120b57cec5SDimitry Andric let Latency = 22; 11135f757f3fSDimitry Andric let ReleaseAtCycles = [19]; 11140b57cec5SDimitry Andric} 11150b57cec5SDimitry Andric 11160b57cec5SDimitry Andricdef THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> { 11170b57cec5SDimitry Andric let Latency = 16; 11185f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 11190b57cec5SDimitry Andric let NumMicroOps = 4; 11200b57cec5SDimitry Andric} 11210b57cec5SDimitry Andric 11220b57cec5SDimitry Andricdef THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> { 11230b57cec5SDimitry Andric let Latency = 16; 11245f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 11250b57cec5SDimitry Andric let NumMicroOps = 4; 11260b57cec5SDimitry Andric} 11270b57cec5SDimitry Andric 11280b57cec5SDimitry Andricdef THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> { 11290b57cec5SDimitry Andric let Latency = 23; 11305f757f3fSDimitry Andric let ReleaseAtCycles = [12]; 11310b57cec5SDimitry Andric let NumMicroOps = 4; 11320b57cec5SDimitry Andric} 11330b57cec5SDimitry Andric 11340b57cec5SDimitry Andricdef THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> { 11350b57cec5SDimitry Andric let Latency = 16; 11365f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 11370b57cec5SDimitry Andric let NumMicroOps = 4; 11380b57cec5SDimitry Andric} 11390b57cec5SDimitry Andric 11400b57cec5SDimitry Andricdef THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> { 11410b57cec5SDimitry Andric let Latency = 23; 11425f757f3fSDimitry Andric let ReleaseAtCycles = [12]; 11430b57cec5SDimitry Andric let NumMicroOps = 4; 11440b57cec5SDimitry Andric} 11450b57cec5SDimitry Andric 11460b57cec5SDimitry Andric// FP divide, S-form 11470b57cec5SDimitry Andric// FP square root, S-form 11480b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFDivSP], (instrs FDIVSrr)>; 11490b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>; 11500b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>; 11510b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; 11520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>; 11530b57cec5SDimitry Andric 11540b57cec5SDimitry Andric// FP divide, D-form 11550b57cec5SDimitry Andric// FP square root, D-form 11560b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFDivDP], (instrs FDIVDrr)>; 11570b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>; 11580b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>; 11590b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; 11600b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>; 11610b57cec5SDimitry Andric 11620b57cec5SDimitry Andric// FP multiply 11630b57cec5SDimitry Andric// FP multiply accumulate 11640b57cec5SDimitry Andricdef : WriteRes<WriteFMul, [THX2T99F01]> { 11650b57cec5SDimitry Andric let Latency = 6; 11665f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11670b57cec5SDimitry Andric let NumMicroOps = 3; 11680b57cec5SDimitry Andric} 11690b57cec5SDimitry Andric 11700b57cec5SDimitry Andricdef THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> { 11710b57cec5SDimitry Andric let Latency = 6; 11725f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11730b57cec5SDimitry Andric let NumMicroOps = 3; 11740b57cec5SDimitry Andric} 11750b57cec5SDimitry Andric 11760b57cec5SDimitry Andricdef THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> { 11770b57cec5SDimitry Andric let Latency = 6; 11785f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11790b57cec5SDimitry Andric let NumMicroOps = 3; 11800b57cec5SDimitry Andric} 11810b57cec5SDimitry Andric 11820b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFMul], (instregex "^FMUL", "^FNMUL")>; 11830b57cec5SDimitry Andricdef : InstRW<[THX2T99XWriteFMulAcc], 11840b57cec5SDimitry Andric (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>; 11850b57cec5SDimitry Andric 11860b57cec5SDimitry Andric// FP round to integral 11870b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 11880b57cec5SDimitry Andric (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>; 11890b57cec5SDimitry Andric 11900b57cec5SDimitry Andric// FP select 11910b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_F01], (instregex "^FCSEL")>; 11920b57cec5SDimitry Andric 11930b57cec5SDimitry Andric//--- 11940b57cec5SDimitry Andric// 3.9 FP Miscellaneous Instructions 11950b57cec5SDimitry Andric//--- 11960b57cec5SDimitry Andric 11970b57cec5SDimitry Andric// FP convert, from vec to vec reg 11980b57cec5SDimitry Andric// FP convert, from gen to vec reg 11990b57cec5SDimitry Andric// FP convert, from vec to gen reg 12000b57cec5SDimitry Andricdef : WriteRes<WriteFCvt, [THX2T99F01]> { 12010b57cec5SDimitry Andric let Latency = 7; 12020b57cec5SDimitry Andric let NumMicroOps = 3; 12030b57cec5SDimitry Andric} 12040b57cec5SDimitry Andric 12050b57cec5SDimitry Andric// FP move, immed 12060b57cec5SDimitry Andric// FP move, register 12070b57cec5SDimitry Andricdef : WriteRes<WriteFImm, [THX2T99F01]> { 12080b57cec5SDimitry Andric let Latency = 4; 12090b57cec5SDimitry Andric let NumMicroOps = 2; 12100b57cec5SDimitry Andric} 12110b57cec5SDimitry Andric 12120b57cec5SDimitry Andric// FP transfer, from gen to vec reg 12130b57cec5SDimitry Andric// FP transfer, from vec to gen reg 12140b57cec5SDimitry Andricdef : WriteRes<WriteFCopy, [THX2T99F01]> { 12150b57cec5SDimitry Andric let Latency = 4; 12160b57cec5SDimitry Andric let NumMicroOps = 2; 12170b57cec5SDimitry Andric} 12180b57cec5SDimitry Andric 12190b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>; 12200b57cec5SDimitry Andric 12210b57cec5SDimitry Andric//--- 12220b57cec5SDimitry Andric// 3.12 ASIMD Integer Instructions 12230b57cec5SDimitry Andric//--- 12240b57cec5SDimitry Andric 12250b57cec5SDimitry Andric// ASIMD absolute diff, D-form 12260b57cec5SDimitry Andric// ASIMD absolute diff, Q-form 12270b57cec5SDimitry Andric// ASIMD absolute diff accum, D-form 12280b57cec5SDimitry Andric// ASIMD absolute diff accum, Q-form 12290b57cec5SDimitry Andric// ASIMD absolute diff accum long 12300b57cec5SDimitry Andric// ASIMD absolute diff long 12310b57cec5SDimitry Andric// ASIMD arith, basic 12320b57cec5SDimitry Andric// ASIMD arith, complex 12330b57cec5SDimitry Andric// ASIMD compare 12340b57cec5SDimitry Andric// ASIMD logical (AND, BIC, EOR) 12350b57cec5SDimitry Andric// ASIMD max/min, basic 12360b57cec5SDimitry Andric// ASIMD max/min, reduce, 4H/4S 12370b57cec5SDimitry Andric// ASIMD max/min, reduce, 8B/8H 12380b57cec5SDimitry Andric// ASIMD max/min, reduce, 16B 12390b57cec5SDimitry Andric// ASIMD multiply, D-form 12400b57cec5SDimitry Andric// ASIMD multiply, Q-form 12410b57cec5SDimitry Andric// ASIMD multiply accumulate long 12420b57cec5SDimitry Andric// ASIMD multiply accumulate saturating long 12430b57cec5SDimitry Andric// ASIMD multiply long 12440b57cec5SDimitry Andric// ASIMD pairwise add and accumulate 12450b57cec5SDimitry Andric// ASIMD shift accumulate 12460b57cec5SDimitry Andric// ASIMD shift by immed, basic 12470b57cec5SDimitry Andric// ASIMD shift by immed and insert, basic, D-form 12480b57cec5SDimitry Andric// ASIMD shift by immed and insert, basic, Q-form 12490b57cec5SDimitry Andric// ASIMD shift by immed, complex 12500b57cec5SDimitry Andric// ASIMD shift by register, basic, D-form 12510b57cec5SDimitry Andric// ASIMD shift by register, basic, Q-form 12520b57cec5SDimitry Andric// ASIMD shift by register, complex, D-form 12530b57cec5SDimitry Andric// ASIMD shift by register, complex, Q-form 1254349cc55cSDimitry Andricdef : WriteRes<WriteVd, [THX2T99F01]> { 1255349cc55cSDimitry Andric let Latency = 7; 1256349cc55cSDimitry Andric let NumMicroOps = 4; 12575f757f3fSDimitry Andric let ReleaseAtCycles = [4]; 1258349cc55cSDimitry Andric} 1259349cc55cSDimitry Andricdef : WriteRes<WriteVq, [THX2T99F01]> { 12600b57cec5SDimitry Andric let Latency = 7; 12610b57cec5SDimitry Andric let NumMicroOps = 4; 12625f757f3fSDimitry Andric let ReleaseAtCycles = [4]; 12630b57cec5SDimitry Andric} 12640b57cec5SDimitry Andric 12650b57cec5SDimitry Andric// ASIMD arith, reduce, 4H/4S 12660b57cec5SDimitry Andric// ASIMD arith, reduce, 8B/8H 12670b57cec5SDimitry Andric// ASIMD arith, reduce, 16B 12680b57cec5SDimitry Andric 12690b57cec5SDimitry Andric// ASIMD logical (MVN (alias for NOT), ORN, ORR) 12700b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 12710b57cec5SDimitry Andric (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>; 12720b57cec5SDimitry Andric 12730b57cec5SDimitry Andric// ASIMD arith, reduce 12740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_10Cyc_F01], 12750b57cec5SDimitry Andric (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>; 12760b57cec5SDimitry Andric 12770b57cec5SDimitry Andric// ASIMD polynomial (8x8) multiply long 12780b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^(S|U|SQD)MULL")>; 12790b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 12800b57cec5SDimitry Andric (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>; 12810b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>; 12820b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>; 12830b57cec5SDimitry Andric 12840b57cec5SDimitry Andric// ASIMD absolute diff accum, D-form 12850b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 12860b57cec5SDimitry Andric (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 12870b57cec5SDimitry Andric// ASIMD absolute diff accum, Q-form 12880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 12890b57cec5SDimitry Andric (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 12900b57cec5SDimitry Andric// ASIMD absolute diff accum long 12910b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 12920b57cec5SDimitry Andric (instregex "^[SU]ABAL")>; 12930b57cec5SDimitry Andric// ASIMD arith, reduce, 4H/4S 12940b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 12950b57cec5SDimitry Andric (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 12960b57cec5SDimitry Andric// ASIMD arith, reduce, 8B 12970b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 12980b57cec5SDimitry Andric (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 12990b57cec5SDimitry Andric// ASIMD arith, reduce, 16B/16H 13000b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_10Cyc_F01], 13010b57cec5SDimitry Andric (instregex "^[SU]?ADDL?Vv16i8v$")>; 13020b57cec5SDimitry Andric// ASIMD max/min, reduce, 4H/4S 13030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_10Cyc_F01], 13040b57cec5SDimitry Andric (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 13050b57cec5SDimitry Andric// ASIMD max/min, reduce, 8B/8H 13060b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13070b57cec5SDimitry Andric (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 13080b57cec5SDimitry Andric// ASIMD max/min, reduce, 16B/16H 13090b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_10Cyc_F01], 13100b57cec5SDimitry Andric (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 13110b57cec5SDimitry Andric// ASIMD multiply, D-form 13120b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13130b57cec5SDimitry Andric (instregex "^(P?MUL|SQR?DMULH)" # 13140b57cec5SDimitry Andric "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # 13150b57cec5SDimitry Andric "(_indexed)?$")>; 13160b57cec5SDimitry Andric// ASIMD multiply, Q-form 13170b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13180b57cec5SDimitry Andric (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 13190b57cec5SDimitry Andric// ASIMD multiply accumulate, D-form 13200b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13210b57cec5SDimitry Andric (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 13220b57cec5SDimitry Andric// ASIMD multiply accumulate, Q-form 13230b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13240b57cec5SDimitry Andric (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 13250b57cec5SDimitry Andric// ASIMD shift accumulate 13260b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13270b57cec5SDimitry Andric (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>; 13280b57cec5SDimitry Andric 13290b57cec5SDimitry Andric// ASIMD shift by immed, basic 13300b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13310b57cec5SDimitry Andric (instregex "RSHRNv","SHRNv", "SQRSHRNv","SQRSHRUNv", 13320b57cec5SDimitry Andric "SQSHRNv","SQSHRUNv", "UQRSHRNv", 13330b57cec5SDimitry Andric "UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>; 13340b57cec5SDimitry Andric// ASIMD shift by immed, complex 13350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]?(Q|R){1,2}SHR")>; 13360b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQSHLU")>; 13370b57cec5SDimitry Andric// ASIMD shift by register, basic, Q-form 13380b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13390b57cec5SDimitry Andric (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 13400b57cec5SDimitry Andric// ASIMD shift by register, complex, D-form 13410b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13420b57cec5SDimitry Andric (instregex "^[SU][QR]{1,2}SHL" # 13430b57cec5SDimitry Andric "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 13440b57cec5SDimitry Andric// ASIMD shift by register, complex, Q-form 13450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13460b57cec5SDimitry Andric (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 13470b57cec5SDimitry Andric 13480b57cec5SDimitry Andric// ASIMD Arithmetic 13490b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13500b57cec5SDimitry Andric (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>; 13510b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13520b57cec5SDimitry Andric (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>; 13530b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(ADD|SUB)HNv.*")>; 13540b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(RADD|RSUB)HNv.*")>; 13550b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13560b57cec5SDimitry Andric (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD", 13570b57cec5SDimitry Andric "^SUQADD", "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; 13580b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13590b57cec5SDimitry Andric (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>; 13600b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 13610b57cec5SDimitry Andric (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" # 13620b57cec5SDimitry Andric "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>; 13630b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 13640b57cec5SDimitry Andric (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>; 13650b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADALP","^UADALP")>; 13660b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLPv","^UADDLPv")>; 13670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLV","^UADDLV")>; 13680b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13690b57cec5SDimitry Andric (instregex "^ADDVv","^SMAXVv","^UMAXVv","^SMINVv","^UMINVv")>; 13700b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13710b57cec5SDimitry Andric (instregex "^SABAv","^UABAv","^SABALv","^UABALv")>; 13720b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13730b57cec5SDimitry Andric (instregex "^SQADDv","^SQSUBv","^UQADDv","^UQSUBv")>; 13740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SUQADDv","^USQADDv")>; 13750b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13760b57cec5SDimitry Andric (instregex "^ADDHNv","^RADDHNv", "^RSUBHNv", 13770b57cec5SDimitry Andric "^SQABS", "^SQADD", "^SQNEG", "^SQSUB", 13780b57cec5SDimitry Andric "^SRHADD", "^SUBHNv", "^SUQADD", 13790b57cec5SDimitry Andric "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; 13800b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13810b57cec5SDimitry Andric (instregex "^CMEQv","^CMGEv","^CMGTv", 13820b57cec5SDimitry Andric "^CMLEv","^CMLTv", "^CMHIv","^CMHSv")>; 13830b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13840b57cec5SDimitry Andric (instregex "^SMAXv","^SMINv","^UMAXv","^UMINv", 13850b57cec5SDimitry Andric "^SMAXPv","^SMINPv","^UMAXPv","^UMINPv")>; 13860b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 13870b57cec5SDimitry Andric (instregex "^SABDv","^UABDv", "^SABDLv","^UABDLv")>; 13880b57cec5SDimitry Andric 13890b57cec5SDimitry Andric//--- 13900b57cec5SDimitry Andric// 3.13 ASIMD Floating-point Instructions 13910b57cec5SDimitry Andric//--- 13920b57cec5SDimitry Andric 13930b57cec5SDimitry Andric// ASIMD FP absolute value 13940b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FABSv")>; 13950b57cec5SDimitry Andric 13960b57cec5SDimitry Andric// ASIMD FP arith, normal, D-form 13970b57cec5SDimitry Andric// ASIMD FP arith, normal, Q-form 13980b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], 13990b57cec5SDimitry Andric (instregex "^FABDv", "^FADDv", "^FSUBv")>; 14000b57cec5SDimitry Andric 14010b57cec5SDimitry Andric// ASIMD FP arith,pairwise, D-form 14020b57cec5SDimitry Andric// ASIMD FP arith, pairwise, Q-form 14030b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADDPv")>; 14040b57cec5SDimitry Andric 14050b57cec5SDimitry Andric// ASIMD FP compare, D-form 14060b57cec5SDimitry Andric// ASIMD FP compare, Q-form 14070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>; 14080b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv", 14090b57cec5SDimitry Andric "^FCMGTv", "^FCMLEv", 14100b57cec5SDimitry Andric "^FCMLTv")>; 14110b57cec5SDimitry Andric 14120b57cec5SDimitry Andric// ASIMD FP round, D-form 14130b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 14140b57cec5SDimitry Andric (instregex "^FRINT[AIMNPXZ](v2f32)")>; 14150b57cec5SDimitry Andric// ASIMD FP round, Q-form 14160b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 14170b57cec5SDimitry Andric (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 14180b57cec5SDimitry Andric 14190b57cec5SDimitry Andric// ASIMD FP convert, long 14200b57cec5SDimitry Andric// ASIMD FP convert, narrow 14210b57cec5SDimitry Andric// ASIMD FP convert, other, D-form 14220b57cec5SDimitry Andric// ASIMD FP convert, other, Q-form 14230b57cec5SDimitry Andric// NOTE: Handled by WriteV. 14240b57cec5SDimitry Andric 14250b57cec5SDimitry Andric// ASIMD FP convert, long and narrow 14260b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FCVT(L|N|XN)v")>; 14270b57cec5SDimitry Andric// ASIMD FP convert, other, D-form 14280b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 14290b57cec5SDimitry Andric (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 14300b57cec5SDimitry Andric// ASIMD FP convert, other, Q-form 14310b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 14320b57cec5SDimitry Andric (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 14330b57cec5SDimitry Andric 14340b57cec5SDimitry Andric// ASIMD FP divide, D-form, F32 14350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv2f32)>; 14360b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv2f32")>; 14370b57cec5SDimitry Andric 14380b57cec5SDimitry Andric// ASIMD FP divide, Q-form, F32 14390b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv4f32)>; 14400b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv4f32")>; 14410b57cec5SDimitry Andric 14420b57cec5SDimitry Andric// ASIMD FP divide, Q-form, F64 14430b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_23Cyc_F01], (instrs FDIVv2f64)>; 14440b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_23Cyc_F01], (instregex "FDIVv2f64")>; 14450b57cec5SDimitry Andric 14460b57cec5SDimitry Andric// ASIMD FP max/min, normal, D-form 14470b57cec5SDimitry Andric// ASIMD FP max/min, normal, Q-form 14480b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv", 14490b57cec5SDimitry Andric "^FMINv", "^FMINNMv")>; 14500b57cec5SDimitry Andric 14510b57cec5SDimitry Andric// ASIMD FP max/min, pairwise, D-form 14520b57cec5SDimitry Andric// ASIMD FP max/min, pairwise, Q-form 14530b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv", 14540b57cec5SDimitry Andric "^FMINPv", "^FMINNMPv")>; 14550b57cec5SDimitry Andric 14560b57cec5SDimitry Andric// ASIMD FP max/min, reduce 14570b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv", 14580b57cec5SDimitry Andric "^FMINVv", "^FMINNMVv")>; 14590b57cec5SDimitry Andric 14600b57cec5SDimitry Andric// ASIMD FP multiply, D-form, FZ 14610b57cec5SDimitry Andric// ASIMD FP multiply, D-form, no FZ 14620b57cec5SDimitry Andric// ASIMD FP multiply, Q-form, FZ 14630b57cec5SDimitry Andric// ASIMD FP multiply, Q-form, no FZ 14640b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>; 14650b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], 14660b57cec5SDimitry Andric (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 14670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], 14680b57cec5SDimitry Andric (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 14690b57cec5SDimitry Andric 14700b57cec5SDimitry Andric// ASIMD FP multiply accumulate, Dform, FZ 14710b57cec5SDimitry Andric// ASIMD FP multiply accumulate, Dform, no FZ 14720b57cec5SDimitry Andric// ASIMD FP multiply accumulate, Qform, FZ 14730b57cec5SDimitry Andric// ASIMD FP multiply accumulate, Qform, no FZ 14740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>; 14750b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], 14760b57cec5SDimitry Andric (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 14770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], 14780b57cec5SDimitry Andric (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 14790b57cec5SDimitry Andric 14800b57cec5SDimitry Andric// ASIMD FP negate 14810b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FNEGv")>; 14820b57cec5SDimitry Andric 14830b57cec5SDimitry Andric//-- 14840b57cec5SDimitry Andric// 3.14 ASIMD Miscellaneous Instructions 14850b57cec5SDimitry Andric//-- 14860b57cec5SDimitry Andric 14870b57cec5SDimitry Andric// ASIMD bit reverse 14880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^RBITv")>; 14890b57cec5SDimitry Andric 14900b57cec5SDimitry Andric// ASIMD bitwise insert, D-form 14910b57cec5SDimitry Andric// ASIMD bitwise insert, Q-form 14920b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 14935ffd83dbSDimitry Andric (instregex "^BIFv", "^BITv", "^BSLv", "^BSPv")>; 14940b57cec5SDimitry Andric 14950b57cec5SDimitry Andric// ASIMD count, D-form 14960b57cec5SDimitry Andric// ASIMD count, Q-form 14970b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 14980b57cec5SDimitry Andric (instregex "^CLSv", "^CLZv", "^CNTv")>; 14990b57cec5SDimitry Andric 15000b57cec5SDimitry Andric// ASIMD duplicate, gen reg 15010b57cec5SDimitry Andric// ASIMD duplicate, element 15020b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv")>; 150304eeddc0SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUP(i8|i16|i32|i64)$")>; 15040b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv.+gpr")>; 15050b57cec5SDimitry Andric 15060b57cec5SDimitry Andric// ASIMD extract 15070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^EXTv")>; 15080b57cec5SDimitry Andric 15090b57cec5SDimitry Andric// ASIMD extract narrow 15100b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^XTNv")>; 15110b57cec5SDimitry Andric 15120b57cec5SDimitry Andric// ASIMD extract narrow, saturating 15130b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_F01], 15140b57cec5SDimitry Andric (instregex "^SQXTNv", "^SQXTUNv", "^UQXTNv")>; 15150b57cec5SDimitry Andric 15160b57cec5SDimitry Andric// ASIMD insert, element to element 15170b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; 15180b57cec5SDimitry Andric 15190b57cec5SDimitry Andric// ASIMD transfer, element to gen reg 15200b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; 15210b57cec5SDimitry Andric 15220b57cec5SDimitry Andric// ASIMD move, integer immed 15230b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>; 15240b57cec5SDimitry Andric 15250b57cec5SDimitry Andric// ASIMD move, FP immed 15260b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>; 15270b57cec5SDimitry Andric 15280b57cec5SDimitry Andric// ASIMD reciprocal estimate, D-form 15290b57cec5SDimitry Andric// ASIMD reciprocal estimate, Q-form 15300b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 15310b57cec5SDimitry Andric (instregex "^FRECPEv", "^FRECPXv", "^URECPEv", 15320b57cec5SDimitry Andric "^FRSQRTEv", "^URSQRTEv")>; 15330b57cec5SDimitry Andric 15340b57cec5SDimitry Andric// ASIMD reciprocal step, D-form, FZ 15350b57cec5SDimitry Andric// ASIMD reciprocal step, D-form, no FZ 15360b57cec5SDimitry Andric// ASIMD reciprocal step, Q-form, FZ 15370b57cec5SDimitry Andric// ASIMD reciprocal step, Q-form, no FZ 15380b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>; 15390b57cec5SDimitry Andric 15400b57cec5SDimitry Andric// ASIMD reverse 15410b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], 15420b57cec5SDimitry Andric (instregex "^REV16v", "^REV32v", "^REV64v")>; 15430b57cec5SDimitry Andric 15440b57cec5SDimitry Andric// ASIMD table lookup, D-form 15450b57cec5SDimitry Andric// ASIMD table lookup, Q-form 15460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_F01], (instregex "^TBLv", "^TBXv")>; 15470b57cec5SDimitry Andric 15480b57cec5SDimitry Andric// ASIMD transfer, element to word or word 15490b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; 15500b57cec5SDimitry Andric 15510b57cec5SDimitry Andric// ASIMD transfer, element to gen reg 15520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_F01], (instregex "(S|U)MOVv.*")>; 15530b57cec5SDimitry Andric 15540b57cec5SDimitry Andric// ASIMD transfer gen reg to element 15550b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; 15560b57cec5SDimitry Andric 15570b57cec5SDimitry Andric// ASIMD transpose 15580b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1v", "^TRN2v", 15590b57cec5SDimitry Andric "^UZP1v", "^UZP2v")>; 15600b57cec5SDimitry Andric 15610b57cec5SDimitry Andric// ASIMD unzip/zip 15620b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>; 15630b57cec5SDimitry Andric 15640b57cec5SDimitry Andric//-- 15650b57cec5SDimitry Andric// 3.15 ASIMD Load Instructions 15660b57cec5SDimitry Andric//-- 15670b57cec5SDimitry Andric 15680b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg, D-form 15690b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg, Q-form 15700b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], 15710b57cec5SDimitry Andric (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 15720b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], 15730b57cec5SDimitry Andric (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 15740b57cec5SDimitry Andric 15750b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg, D-form 15760b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg, Q-form 15770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01], 15780b57cec5SDimitry Andric (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 15790b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], 15800b57cec5SDimitry Andric (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 15810b57cec5SDimitry Andric 15820b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg, D-form 15830b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg, Q-form 15840b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01], 15850b57cec5SDimitry Andric (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 15860b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01, WriteAdr], 15870b57cec5SDimitry Andric (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 15880b57cec5SDimitry Andric 15890b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, D-form 15900b57cec5SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, Q-form 15910b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01], 15920b57cec5SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 15930b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01, WriteAdr], 15940b57cec5SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 15950b57cec5SDimitry Andric 15960b57cec5SDimitry Andric// ASIMD load, 1 element, one lane, B/H/S 15970b57cec5SDimitry Andric// ASIMD load, 1 element, one lane, D 15980b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD1i(8|16|32|64)$")>; 15990b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 16000b57cec5SDimitry Andric (instregex "^LD1i(8|16|32|64)_POST$")>; 16010b57cec5SDimitry Andric 16020b57cec5SDimitry Andric// ASIMD load, 1 element, all lanes, D-form, B/H/S 16030b57cec5SDimitry Andric// ASIMD load, 1 element, all lanes, D-form, D 16040b57cec5SDimitry Andric// ASIMD load, 1 element, all lanes, Q-form 16050b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 16060b57cec5SDimitry Andric (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 16080b57cec5SDimitry Andric (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16090b57cec5SDimitry Andric 16100b57cec5SDimitry Andric// ASIMD load, 2 element, multiple, D-form, B/H/S 16110b57cec5SDimitry Andric// ASIMD load, 2 element, multiple, Q-form, D 16120b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 16130b57cec5SDimitry Andric (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; 16140b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 16150b57cec5SDimitry Andric (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 16160b57cec5SDimitry Andric 16170b57cec5SDimitry Andric// ASIMD load, 2 element, one lane, B/H 16180b57cec5SDimitry Andric// ASIMD load, 2 element, one lane, S 16190b57cec5SDimitry Andric// ASIMD load, 2 element, one lane, D 16200b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD2i(8|16|32|64)$")>; 16210b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 16220b57cec5SDimitry Andric (instregex "^LD2i(8|16|32|64)_POST$")>; 16230b57cec5SDimitry Andric 16240b57cec5SDimitry Andric// ASIMD load, 2 element, all lanes, D-form, B/H/S 16250b57cec5SDimitry Andric// ASIMD load, 2 element, all lanes, D-form, D 16260b57cec5SDimitry Andric// ASIMD load, 2 element, all lanes, Q-form 16270b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01], 16280b57cec5SDimitry Andric (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16290b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], 16300b57cec5SDimitry Andric (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16310b57cec5SDimitry Andric 16320b57cec5SDimitry Andric// ASIMD load, 3 element, multiple, D-form, B/H/S 16330b57cec5SDimitry Andric// ASIMD load, 3 element, multiple, Q-form, B/H/S 16340b57cec5SDimitry Andric// ASIMD load, 3 element, multiple, Q-form, D 16350b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_LS01_F01], 16360b57cec5SDimitry Andric (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; 16370b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], 16380b57cec5SDimitry Andric (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 16390b57cec5SDimitry Andric 16400b57cec5SDimitry Andric// ASIMD load, 3 element, one lone, B/H 16410b57cec5SDimitry Andric// ASIMD load, 3 element, one lane, S 16420b57cec5SDimitry Andric// ASIMD load, 3 element, one lane, D 16430b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_LS01_F01], (instregex "^LD3i(8|16|32|64)$")>; 16440b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], 16450b57cec5SDimitry Andric (instregex "^LD3i(8|16|32|64)_POST$")>; 16460b57cec5SDimitry Andric 16470b57cec5SDimitry Andric// ASIMD load, 3 element, all lanes, D-form, B/H/S 16480b57cec5SDimitry Andric// ASIMD load, 3 element, all lanes, D-form, D 16490b57cec5SDimitry Andric// ASIMD load, 3 element, all lanes, Q-form, B/H/S 16500b57cec5SDimitry Andric// ASIMD load, 3 element, all lanes, Q-form, D 16510b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_LS01_F01], 16520b57cec5SDimitry Andric (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16530b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], 16540b57cec5SDimitry Andric (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16550b57cec5SDimitry Andric 16560b57cec5SDimitry Andric// ASIMD load, 4 element, multiple, D-form, B/H/S 16570b57cec5SDimitry Andric// ASIMD load, 4 element, multiple, Q-form, B/H/S 16580b57cec5SDimitry Andric// ASIMD load, 4 element, multiple, Q-form, D 16590b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_LS01_F01], 16600b57cec5SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; 16610b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], 16620b57cec5SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 16630b57cec5SDimitry Andric 16640b57cec5SDimitry Andric// ASIMD load, 4 element, one lane, B/H 16650b57cec5SDimitry Andric// ASIMD load, 4 element, one lane, S 16660b57cec5SDimitry Andric// ASIMD load, 4 element, one lane, D 16670b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_F01], (instregex "^LD4i(8|16|32|64)$")>; 16680b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], 16690b57cec5SDimitry Andric (instregex "^LD4i(8|16|32|64)_POST$")>; 16700b57cec5SDimitry Andric 16710b57cec5SDimitry Andric// ASIMD load, 4 element, all lanes, D-form, B/H/S 16720b57cec5SDimitry Andric// ASIMD load, 4 element, all lanes, D-form, D 16730b57cec5SDimitry Andric// ASIMD load, 4 element, all lanes, Q-form, B/H/S 16740b57cec5SDimitry Andric// ASIMD load, 4 element, all lanes, Q-form, D 16750b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_F01], 16760b57cec5SDimitry Andric (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], 16780b57cec5SDimitry Andric (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16790b57cec5SDimitry Andric 16800b57cec5SDimitry Andric//-- 16810b57cec5SDimitry Andric// 3.16 ASIMD Store Instructions 16820b57cec5SDimitry Andric//-- 16830b57cec5SDimitry Andric 16840b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg, D-form 16850b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg, Q-form 16860b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], 16870b57cec5SDimitry Andric (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16880b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 16890b57cec5SDimitry Andric (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16900b57cec5SDimitry Andric 16910b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, D-form 16920b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, Q-form 16930b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], 16940b57cec5SDimitry Andric (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 16950b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 16960b57cec5SDimitry Andric (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 16970b57cec5SDimitry Andric 16980b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, D-form 16990b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, Q-form 17000b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], 17010b57cec5SDimitry Andric (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 17020b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 17030b57cec5SDimitry Andric (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 17040b57cec5SDimitry Andric 17050b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, D-form 17060b57cec5SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, Q-form 17070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01], 17080b57cec5SDimitry Andric (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 17090b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], 17100b57cec5SDimitry Andric (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 17110b57cec5SDimitry Andric 17120b57cec5SDimitry Andric// ASIMD store, 1 element, one lane, B/H/S 17130b57cec5SDimitry Andric// ASIMD store, 1 element, one lane, D 17140b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 17150b57cec5SDimitry Andric (instregex "^ST1i(8|16|32|64)$")>; 17160b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17170b57cec5SDimitry Andric (instregex "^ST1i(8|16|32|64)_POST$")>; 17180b57cec5SDimitry Andric 17190b57cec5SDimitry Andric// ASIMD store, 2 element, multiple, D-form, B/H/S 17200b57cec5SDimitry Andric// ASIMD store, 2 element, multiple, Q-form, B/H/S 17210b57cec5SDimitry Andric// ASIMD store, 2 element, multiple, Q-form, D 17220b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 17230b57cec5SDimitry Andric (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; 17240b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17250b57cec5SDimitry Andric (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 17260b57cec5SDimitry Andric 17270b57cec5SDimitry Andric// ASIMD store, 2 element, one lane, B/H/S 17280b57cec5SDimitry Andric// ASIMD store, 2 element, one lane, D 17290b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 17300b57cec5SDimitry Andric (instregex "^ST2i(8|16|32|64)$")>; 17310b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17320b57cec5SDimitry Andric (instregex "^ST2i(8|16|32|64)_POST$")>; 17330b57cec5SDimitry Andric 17340b57cec5SDimitry Andric// ASIMD store, 3 element, multiple, D-form, B/H/S 17350b57cec5SDimitry Andric// ASIMD store, 3 element, multiple, Q-form, B/H/S 17360b57cec5SDimitry Andric// ASIMD store, 3 element, multiple, Q-form, D 17370b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 17380b57cec5SDimitry Andric (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; 17390b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17400b57cec5SDimitry Andric (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 17410b57cec5SDimitry Andric 17420b57cec5SDimitry Andric// ASIMD store, 3 element, one lane, B/H 17430b57cec5SDimitry Andric// ASIMD store, 3 element, one lane, S 17440b57cec5SDimitry Andric// ASIMD store, 3 element, one lane, D 17450b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST3i(8|16|32|64)$")>; 17460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17470b57cec5SDimitry Andric (instregex "^ST3i(8|16|32|64)_POST$")>; 17480b57cec5SDimitry Andric 17490b57cec5SDimitry Andric// ASIMD store, 4 element, multiple, D-form, B/H/S 17500b57cec5SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, B/H/S 17510b57cec5SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, D 17520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], 17530b57cec5SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; 17540b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17550b57cec5SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; 17560b57cec5SDimitry Andric 17570b57cec5SDimitry Andric// ASIMD store, 4 element, one lane, B/H 17580b57cec5SDimitry Andric// ASIMD store, 4 element, one lane, S 17590b57cec5SDimitry Andric// ASIMD store, 4 element, one lane, D 17600b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST4i(8|16|32|64)$")>; 17610b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], 17620b57cec5SDimitry Andric (instregex "^ST4i(8|16|32|64)_POST$")>; 17630b57cec5SDimitry Andric 17640b57cec5SDimitry Andric// V8.1a Atomics (LSE) 17650b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 17660b57cec5SDimitry Andric (instrs CASB, CASH, CASW, CASX)>; 17670b57cec5SDimitry Andric 17680b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17690b57cec5SDimitry Andric (instrs CASAB, CASAH, CASAW, CASAX)>; 17700b57cec5SDimitry Andric 17710b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17720b57cec5SDimitry Andric (instrs CASLB, CASLH, CASLW, CASLX)>; 17730b57cec5SDimitry Andric 17740b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 17750b57cec5SDimitry Andric (instrs CASALB, CASALH, CASALW, CASALX)>; 17760b57cec5SDimitry Andric 17770b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17780b57cec5SDimitry Andric (instrs LDLARB, LDLARH, LDLARW, LDLARX)>; 17790b57cec5SDimitry Andric 17800b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 17810b57cec5SDimitry Andric (instrs LDADDB, LDADDH, LDADDW, LDADDX)>; 17820b57cec5SDimitry Andric 17830b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17840b57cec5SDimitry Andric (instrs LDADDAB, LDADDAH, LDADDAW, LDADDAX)>; 17850b57cec5SDimitry Andric 17860b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17870b57cec5SDimitry Andric (instrs LDADDLB, LDADDLH, LDADDLW, LDADDLX)>; 17880b57cec5SDimitry Andric 17890b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 17900b57cec5SDimitry Andric (instrs LDADDALB, LDADDALH, LDADDALW, LDADDALX)>; 17910b57cec5SDimitry Andric 17920b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 17930b57cec5SDimitry Andric (instrs LDCLRB, LDCLRH, LDCLRW, LDCLRX)>; 17940b57cec5SDimitry Andric 17950b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17960b57cec5SDimitry Andric (instrs LDCLRAB, LDCLRAH, LDCLRAW, LDCLRAX)>; 17970b57cec5SDimitry Andric 17980b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 17990b57cec5SDimitry Andric (instrs LDCLRLB, LDCLRLH, LDCLRLW, LDCLRLX)>; 18000b57cec5SDimitry Andric 18010b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 18020b57cec5SDimitry Andric (instrs LDCLRALB, LDCLRALH, LDCLRALW, LDCLRALX)>; 18030b57cec5SDimitry Andric 18040b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18050b57cec5SDimitry Andric (instrs LDEORB, LDEORH, LDEORW, LDEORX)>; 18060b57cec5SDimitry Andric 18070b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18080b57cec5SDimitry Andric (instrs LDEORAB, LDEORAH, LDEORAW, LDEORAX)>; 18090b57cec5SDimitry Andric 18100b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18110b57cec5SDimitry Andric (instrs LDEORLB, LDEORLH, LDEORLW, LDEORLX)>; 18120b57cec5SDimitry Andric 18130b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 18140b57cec5SDimitry Andric (instrs LDEORALB, LDEORALH, LDEORALW, LDEORALX)>; 18150b57cec5SDimitry Andric 18160b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18170b57cec5SDimitry Andric (instrs LDSETB, LDSETH, LDSETW, LDSETX)>; 18180b57cec5SDimitry Andric 18190b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18200b57cec5SDimitry Andric (instrs LDSETAB, LDSETAH, LDSETAW, LDSETAX)>; 18210b57cec5SDimitry Andric 18220b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18230b57cec5SDimitry Andric (instrs LDSETLB, LDSETLH, LDSETLW, LDSETLX)>; 18240b57cec5SDimitry Andric 18250b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 18260b57cec5SDimitry Andric (instrs LDSETALB, LDSETALH, LDSETALW, LDSETALX)>; 18270b57cec5SDimitry Andric 18280b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18290b57cec5SDimitry Andric (instrs LDSMAXB, LDSMAXH, LDSMAXW, LDSMAXX, 18300b57cec5SDimitry Andric LDSMAXAB, LDSMAXAH, LDSMAXAW, LDSMAXAX, 18310b57cec5SDimitry Andric LDSMAXLB, LDSMAXLH, LDSMAXLW, LDSMAXLX, 18320b57cec5SDimitry Andric LDSMAXALB, LDSMAXALH, LDSMAXALW, LDSMAXALX)>; 18330b57cec5SDimitry Andric 18340b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18350b57cec5SDimitry Andric (instrs LDSMINB, LDSMINH, LDSMINW, LDSMINX, 18360b57cec5SDimitry Andric LDSMINAB, LDSMINAH, LDSMINAW, LDSMINAX, 18370b57cec5SDimitry Andric LDSMINLB, LDSMINLH, LDSMINLW, LDSMINLX, 18380b57cec5SDimitry Andric LDSMINALB, LDSMINALH, LDSMINALW, LDSMINALX)>; 18390b57cec5SDimitry Andric 18400b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18410b57cec5SDimitry Andric (instrs LDUMAXB, LDUMAXH, LDUMAXW, LDUMAXX, 18420b57cec5SDimitry Andric LDUMAXAB, LDUMAXAH, LDUMAXAW, LDUMAXAX, 18430b57cec5SDimitry Andric LDUMAXLB, LDUMAXLH, LDUMAXLW, LDUMAXLX, 18440b57cec5SDimitry Andric LDUMAXALB, LDUMAXALH, LDUMAXALW, LDUMAXALX)>; 18450b57cec5SDimitry Andric 18460b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18470b57cec5SDimitry Andric (instrs LDUMINB, LDUMINH, LDUMINW, LDUMINX, 18480b57cec5SDimitry Andric LDUMINAB, LDUMINAH, LDUMINAW, LDUMINAX, 18490b57cec5SDimitry Andric LDUMINLB, LDUMINLH, LDUMINLW, LDUMINLX, 18500b57cec5SDimitry Andric LDUMINALB, LDUMINALH, LDUMINALW, LDUMINALX)>; 18510b57cec5SDimitry Andric 18520b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18530b57cec5SDimitry Andric (instrs SWPB, SWPH, SWPW, SWPX)>; 18540b57cec5SDimitry Andric 18550b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18560b57cec5SDimitry Andric (instrs SWPAB, SWPAH, SWPAW, SWPAX)>; 18570b57cec5SDimitry Andric 18580b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], 18590b57cec5SDimitry Andric (instrs SWPLB, SWPLH, SWPLW, SWPLX)>; 18600b57cec5SDimitry Andric 18610b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], 18620b57cec5SDimitry Andric (instrs SWPALB, SWPALH, SWPALW, SWPALX)>; 18630b57cec5SDimitry Andric 18640b57cec5SDimitry Andricdef : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], 18650b57cec5SDimitry Andric (instrs STLLRB, STLLRH, STLLRW, STLLRX)>; 18660b57cec5SDimitry Andric 18670b57cec5SDimitry Andric} // SchedModel = ThunderX2T99Model 18680b57cec5SDimitry Andric 1869