1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node definitions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPUFPClassOp : SDTypeProfile<1, 2,
22  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
23>;
24
25def AMDGPUFPPackOp : SDTypeProfile<1, 2,
26  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
27>;
28
29def AMDGPUIntPackOp : SDTypeProfile<1, 2,
30  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
31>;
32
33def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
34  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
35>;
36
37// float, float, float, vcc
38def AMDGPUFmasOp : SDTypeProfile<1, 4,
39  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
40>;
41
42def ImmOp : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
43def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
44
45def AMDGPUIfOp : SDTypeProfile<1, 2,
46  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
47>;
48
49def AMDGPUElseOp : SDTypeProfile<1, 2,
50  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
51>;
52
53def AMDGPULoopOp : SDTypeProfile<0, 2,
54  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
55>;
56
57def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
58  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
59>;
60
61//===----------------------------------------------------------------------===//
62// AMDGPU DAG Nodes
63//
64
65def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
66def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
67def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
68
69def callseq_start : SDNode<"ISD::CALLSEQ_START",
70  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
71  [SDNPHasChain, SDNPOutGlue]
72>;
73
74def callseq_end : SDNode<"ISD::CALLSEQ_END",
75 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
76  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
77>;
78
79def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
80  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
81  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
82  SDNPVariadic]
83>;
84
85def AMDGPUTCReturnTP : SDTypeProfile<0, 3, [
86  SDTCisPtrTy<0>
87]>;
88
89def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN", AMDGPUTCReturnTP,
90[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
91>;
92
93def AMDGPUtc_return_gfx: SDNode<"AMDGPUISD::TC_RETURN_GFX", AMDGPUTCReturnTP,
94[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
95>;
96
97def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
98  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
99    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
100>;
101
102def AMDGPUconstdata_ptr : SDNode<
103  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
104                                                     SDTCisVT<0, iPTR>]>
105>;
106
107// This argument to this node is a dword address.
108def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
109
110def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
111def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
112// out = a - floor(a)
113def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
114
115// out = 1.0 / a
116def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
117
118// v_log_f32, which is log2
119def AMDGPUlog_impl : SDNode<"AMDGPUISD::LOG", SDTFPUnaryOp>;
120
121// v_exp_f32, which is exp2
122def AMDGPUexp_impl : SDNode<"AMDGPUISD::EXP", SDTFPUnaryOp>;
123
124// out = 1.0 / sqrt(a)
125def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
126
127def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
128
129def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
130
131// out = 1.0 / sqrt(a) result clamped to +/- max_float.
132def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
133
134def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
135def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
136def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
137def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
138def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
139def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
140
141
142def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
143
144// out = max(a, b) a and b are floats, where a nan comparison fails.
145// This is not commutative because this gives the second operand:
146//   x < nan ? x : nan -> nan
147//   nan < x ? nan : x -> x
148def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
149  []
150>;
151
152def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
153  [SDNPCommutative, SDNPAssociative]
154>;
155
156// out = min(a, b) a and b are floats, where a nan comparison fails.
157def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
158  []
159>;
160
161// FIXME: TableGen doesn't like commutative instructions with more
162// than 2 operands.
163// out = max(a, b, c) a, b and c are floats
164def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
165  [/*SDNPCommutative, SDNPAssociative*/]
166>;
167
168// out = max(a, b, c) a, b, and c are signed ints
169def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
170  [/*SDNPCommutative, SDNPAssociative*/]
171>;
172
173// out = max(a, b, c) a, b and c are unsigned ints
174def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
175  [/*SDNPCommutative, SDNPAssociative*/]
176>;
177
178// out = min(a, b, c) a, b and c are floats
179def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
180  [/*SDNPCommutative, SDNPAssociative*/]
181>;
182
183// out = min(a, b, c) a, b and c are signed ints
184def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
185  [/*SDNPCommutative, SDNPAssociative*/]
186>;
187
188// out = min(a, b) a and b are unsigned ints
189def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
190  [/*SDNPCommutative, SDNPAssociative*/]
191>;
192
193// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
194def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
195
196// out = (src1 > src0) ? 1 : 0
197def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
198
199def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
200  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
201]>;
202
203def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
204
205def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
206   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207
208def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
209  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
210
211def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
212  SDTIntToFPOp, []>;
213def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
214  SDTIntToFPOp, []>;
215def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
216  SDTIntToFPOp, []>;
217def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
218  SDTIntToFPOp, []>;
219
220def AMDGPUcvt_pk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32",
221  AMDGPUIntPackOp, []>;
222
223// urecip - This operation is a helper for integer division, it returns the
224// result of 1 / a as a fractional unsigned integer.
225// out = (2^32 / a) + e
226// e is rounding error
227def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
228
229// Special case divide preop and flags.
230def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
231
232//  Special case divide FMA with scale and flags (src0 = Quotient,
233//  src1 = Denominator, src2 = Numerator).
234def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
235                            [SDNPOptInGlue]>;
236
237// Single or double precision division fixup.
238// Special case divide fixup and flags(src0 = Quotient, src1 =
239// Denominator, src2 = Numerator).
240def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
241
242def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
243
244def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
245                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
246                          [SDNPHasChain, SDNPMayLoad]>;
247
248def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
249                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
250                           [SDNPHasChain, SDNPMayStore]>;
251
252// MSKOR instructions are atomic memory instructions used mainly for storing
253// 8-bit and 16-bit values.  The definition is:
254//
255// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
256//
257// src0: vec4(src, 0, 0, mask)
258// src1: dst - rat offset (aka pointer) in dwords
259def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
260                        SDTypeProfile<0, 2, []>,
261                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
262
263def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
264                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
265                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
266                             SDNPMemOperand]>;
267
268def AMDGPUround : SDNode<"ISD::FROUND",
269                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
270
271def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
272def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
273def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
274def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
275
276def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
277def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
278
279def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
280
281// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
282// when performing the multiply. The result is a 32-bit value.
283def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
284  [SDNPCommutative, SDNPAssociative]
285>;
286def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
287  [SDNPCommutative, SDNPAssociative]
288>;
289
290// mulhi24 yields the high-order 16 bits of the 48-bit result. Here's an example
291// that shows mulhi24 is not associative:
292//
293// Given a = 0x10002, b = c = 0xffffff:
294// mulhi24(mulhi24(a, b), c) = mulhi24(0x100, 0xffffff) = 0
295// Which is not equal to:
296// mulhi24(a, mulhi24(b, c)) = mulhi24(0x10002, 0xffff) = 1
297def AMDGPUmulhi_u24_impl : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
298  [SDNPCommutative]
299>;
300def AMDGPUmulhi_i24_impl : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
301  [SDNPCommutative]
302>;
303
304def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
305  []
306>;
307def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
308  []
309>;
310
311def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
312  []
313>;
314
315def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
316  []
317>;
318
319def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
320
321def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
322                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
323                                       SDTCisFP<0>, SDTCisVec<1>,
324                                       SDTCisInt<4>]>,
325                  []>;
326
327def AMDGPUperm_impl : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
328
329// SI+ export
330def AMDGPUExportOp : SDTypeProfile<0, 8, [
331  SDTCisInt<0>,       // i8 tgt
332  SDTCisInt<1>,       // i8 en
333                      // i32 or f32 src0
334  SDTCisSameAs<3, 2>, // f32 src1
335  SDTCisSameAs<4, 2>, // f32 src2
336  SDTCisSameAs<5, 2>, // f32 src3
337  SDTCisInt<6>,       // i1 compr
338  // skip done
339  SDTCisInt<1>        // i1 vm
340
341]>;
342
343
344//===----------------------------------------------------------------------===//
345// Flow Control Profile Types
346//===----------------------------------------------------------------------===//
347// Branch instruction where second and third are basic blocks
348def SDTIL_BRCond : SDTypeProfile<0, 2, [
349    SDTCisVT<0, OtherVT>
350    ]>;
351
352//===----------------------------------------------------------------------===//
353// Flow Control DAG Nodes
354//===----------------------------------------------------------------------===//
355def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
356
357//===----------------------------------------------------------------------===//
358// Call/Return DAG Nodes
359//===----------------------------------------------------------------------===//
360def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
361    [SDNPHasChain, SDNPOptInGlue]>;
362def AMDGPUendpgm_trap : SDNode<"AMDGPUISD::ENDPGM_TRAP", SDTNone,
363    [SDNPHasChain]>;
364
365def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
366    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
367
368def AMDGPUret_glue : SDNode<"AMDGPUISD::RET_GLUE", SDTNone,
369  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
370>;
371
372
373//===----------------------------------------------------------------------===//
374// Intrinsic/Custom node compatibility PatFrags
375//===----------------------------------------------------------------------===//
376
377def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
378                                           (AMDGPUrcp_impl node:$src)]>;
379def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
380                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
381
382def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
383                                           (AMDGPUrsq_impl node:$src)]>;
384
385def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
386                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
387
388def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
389                                           (AMDGPUsin_impl node:$src)]>;
390def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
391                                           (AMDGPUcos_impl node:$src)]>;
392def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
393                                             (AMDGPUfract_impl node:$src)]>;
394def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
395                                           (AMDGPUlog_impl node:$src)]>;
396def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),
397                                              (flog2 node:$src)]>;
398
399def AMDGPUexp : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
400                                           (AMDGPUexp_impl node:$src)]>;
401def AMDGPUexpf16 : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),
402                                              (fexp2 node:$src)]>;
403
404def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
405  [(int_amdgcn_class node:$src0, node:$src1),
406   (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
407
408def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
409  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
410   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
411
412def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
413  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
414   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
415
416def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
417  [(int_amdgcn_sffbh node:$src),
418   (AMDGPUffbh_i32_impl node:$src)]>;
419
420def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
421  [(ctlz_zero_undef node:$src),
422   (AMDGPUffbh_u32_impl node:$src)]>;
423
424def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
425  [(cttz_zero_undef node:$src),
426   (AMDGPUffbl_b32_impl node:$src)]>;
427
428def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
429  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
430  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
431
432def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
433  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
434  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
435
436def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
437  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
438  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
439
440def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
441  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
442  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
443
444def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
445  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
446  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
447
448def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
449  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
450   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
451
452def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
453  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
454   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
455
456def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
457  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
458   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
459
460def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
461  [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
462   (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
463
464def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
465  [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
466   (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
467
468def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
469  [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
470   (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
471
472def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
473  [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
474   (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
475
476def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
477  [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
478   (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
479
480def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
481  [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
482   (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
483
484def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
485  [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
486   (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
487
488def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
489  [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
490   (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;
491