1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32   const GCNSubtarget &ST;
33 
34 public:
35   AMDGPULegalizerInfo(const GCNSubtarget &ST,
36                       const GCNTargetMachine &TM);
37 
38   bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40   Register getSegmentAperture(unsigned AddrSpace,
41                               MachineRegisterInfo &MRI,
42                               MachineIRBuilder &B) const;
43 
44   bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45                              MachineIRBuilder &B) const;
46   bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47                      MachineIRBuilder &B) const;
48   bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49                      MachineIRBuilder &B) const;
50   bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
51                     MachineIRBuilder &B) const;
52   bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
53                               MachineIRBuilder &B) const;
54   bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
55                      MachineIRBuilder &B, bool Signed) const;
56   bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
57                      MachineIRBuilder &B, bool Signed) const;
58   bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
60                                 MachineIRBuilder &B) const;
61   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
62                                MachineIRBuilder &B) const;
63   bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
64                              MachineIRBuilder &B) const;
65 
66   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
67                       MachineIRBuilder &B) const;
68 
69   bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
70                                const GlobalValue *GV, int64_t Offset,
71                                unsigned GAFlags = SIInstrInfo::MO_NONE) const;
72 
73   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
74                            MachineIRBuilder &B) const;
75   bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
76 
77   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
78                     MachineIRBuilder &B) const;
79 
80   bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
81                              MachineIRBuilder &B) const;
82   bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
83                     double Log2BaseInverted) const;
84   bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
85   bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
86   bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
87                       MachineIRBuilder &B) const;
88 
89   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
90                            MachineIRBuilder &B) const;
91   bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI,
92                          MachineIRBuilder &B) const;
93 
94   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
95                       const ArgDescriptor *Arg,
96                       const TargetRegisterClass *ArgRC, LLT ArgTy) const;
97   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
98                       AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
99   bool legalizePreloadedArgIntrin(
100     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
101     AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
102 
103   bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
104                                MachineIRBuilder &B) const;
105 
106   void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg,
107                                      Register DstRemReg, Register Num,
108                                      Register Den) const;
109 
110   void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg,
111                                      Register DstRemReg, Register Num,
112                                      Register Den) const;
113 
114   bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
115                              MachineIRBuilder &B) const;
116 
117   bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
118                     MachineIRBuilder &B) const;
119   bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
120                       MachineIRBuilder &B) const;
121   bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
122                       MachineIRBuilder &B) const;
123   bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
124                       MachineIRBuilder &B) const;
125   bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
126                               MachineIRBuilder &B) const;
127   bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
128                                 MachineIRBuilder &B) const;
129   bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
130                               MachineIRBuilder &B) const;
131 
132   bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
133                                  MachineIRBuilder &B) const;
134 
135   bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
136                                    MachineInstr &MI, Intrinsic::ID IID) const;
137 
138   bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI,
139                          MachineIRBuilder &B) const;
140 
141   bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
142                               MachineIRBuilder &B) const;
143   bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
144                            MachineIRBuilder &B, unsigned AddrSpace) const;
145 
146   std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
147                                                    Register OrigOffset) const;
148   void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
149                        Register SOffset, unsigned ImmOffset, Register VIndex,
150                        MachineRegisterInfo &MRI) const;
151 
152   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
153                           Register Reg, bool ImageStore = false) const;
154   bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
155                               MachineIRBuilder &B, bool IsFormat) const;
156   bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
157                              MachineIRBuilder &B, bool IsFormat) const;
158   Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
159                               bool IsFormat) const;
160 
161   bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
162                            MachineIRBuilder &B, bool IsTyped,
163                            bool IsFormat) const;
164   bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
165                           MachineIRBuilder &B, bool IsFormat,
166                           bool IsTyped) const;
167   bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
168                             Intrinsic::ID IID) const;
169 
170   bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const;
171 
172   bool legalizeImageIntrinsic(
173       MachineInstr &MI, MachineIRBuilder &B,
174       GISelChangeObserver &Observer,
175       const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
176 
177   bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
178 
179   bool legalizeAtomicIncDec(MachineInstr &MI,  MachineIRBuilder &B,
180                             bool IsInc) const;
181 
182   bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
183                              MachineIRBuilder &B) const;
184   bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI,
185                           MachineIRBuilder &B) const;
186   bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI,
187                                MachineIRBuilder &B) const;
188   bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
189                        MachineIRBuilder &B) const;
190   bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
191                                   MachineIRBuilder &B) const;
192 
193   bool legalizeIntrinsic(LegalizerHelper &Helper,
194                          MachineInstr &MI) const override;
195 };
196 } // End llvm namespace.
197 #endif
198