1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 24 namespace llvm { 25 26 class LLT; 27 class GCNSubtarget; 28 class MachineIRBuilder; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class TargetRegisterInfo; 32 33 /// This class provides the information for the target register banks. 34 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 35 36 protected: 37 38 #define GET_TARGET_REGBANK_CLASS 39 #include "AMDGPUGenRegisterBank.inc" 40 }; 41 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 bool executeInWaterfallLoop(MachineIRBuilder &B, 63 MachineInstr &MI, 64 MachineRegisterInfo &MRI, 65 ArrayRef<unsigned> OpIndices) const; 66 bool executeInWaterfallLoop(MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 71 unsigned OpIdx) const; 72 bool applyMappingDynStackAlloc(MachineInstr &MI, 73 const OperandsMapper &OpdMapper, 74 MachineRegisterInfo &MRI) const; 75 bool applyMappingLoad(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool 79 applyMappingImage(MachineInstr &MI, 80 const OperandsMapper &OpdMapper, 81 MachineRegisterInfo &MRI, int RSrcIdx) const; 82 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 83 84 bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const; 85 86 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 87 Register Reg) const; 88 89 std::pair<Register, unsigned> 90 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 91 92 /// See RegisterBankInfo::applyMapping. 93 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 94 95 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 96 Register Ptr) const; 97 98 const RegisterBankInfo::InstructionMapping & 99 getInstrMappingForLoad(const MachineInstr &MI) const; 100 101 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 102 unsigned Default = AMDGPU::VGPRRegBankID) const; 103 104 // Return a value mapping for an operand that is required to be an SGPR. 105 const ValueMapping *getSGPROpMapping(Register Reg, 106 const MachineRegisterInfo &MRI, 107 const TargetRegisterInfo &TRI) const; 108 109 // Return a value mapping for an operand that is required to be a VGPR. 110 const ValueMapping *getVGPROpMapping(Register Reg, 111 const MachineRegisterInfo &MRI, 112 const TargetRegisterInfo &TRI) const; 113 114 // Return a value mapping for an operand that is required to be a AGPR. 115 const ValueMapping *getAGPROpMapping(Register Reg, 116 const MachineRegisterInfo &MRI, 117 const TargetRegisterInfo &TRI) const; 118 119 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 120 /// Regs. This appropriately sets the regbank of the new registers. 121 void split64BitValueForMapping(MachineIRBuilder &B, 122 SmallVector<Register, 2> &Regs, 123 LLT HalfTy, 124 Register Reg) const; 125 126 template <unsigned NumOps> 127 struct OpRegBankEntry { 128 int8_t RegBanks[NumOps]; 129 int16_t Cost; 130 }; 131 132 template <unsigned NumOps> 133 InstructionMappings 134 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 135 const std::array<unsigned, NumOps> RegSrcOpIdx, 136 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 137 138 RegisterBankInfo::InstructionMappings 139 getInstrAlternativeMappingsIntrinsic( 140 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 141 142 RegisterBankInfo::InstructionMappings 143 getInstrAlternativeMappingsIntrinsicWSideEffects( 144 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 145 146 unsigned getMappingType(const MachineRegisterInfo &MRI, 147 const MachineInstr &MI) const; 148 149 bool isSALUMapping(const MachineInstr &MI) const; 150 151 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 152 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 153 const InstructionMapping &getDefaultMappingAllVGPR( 154 const MachineInstr &MI) const; 155 156 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 157 const MachineInstr &MI, 158 int RsrcIdx) const; 159 160 public: 161 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 162 163 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 164 unsigned Size) const override; 165 166 unsigned getBreakDownCost(const ValueMapping &ValMapping, 167 const RegisterBank *CurBank = nullptr) const override; 168 169 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 170 LLT) const override; 171 172 InstructionMappings 173 getInstrAlternativeMappings(const MachineInstr &MI) const override; 174 175 const InstructionMapping & 176 getInstrMapping(const MachineInstr &MI) const override; 177 178 private: 179 180 bool foldExtractEltToCmpSelect(MachineInstr &MI, 181 MachineRegisterInfo &MRI, 182 const OperandsMapper &OpdMapper) const; 183 bool foldInsertEltToCmpSelect(MachineInstr &MI, 184 MachineRegisterInfo &MRI, 185 const OperandsMapper &OpdMapper) const; 186 }; 187 } // End llvm namespace. 188 #endif 189