1//===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9include "llvm/Target/Target.td"
10
11def R600InstrInfo : InstrInfo {
12  let guessInstructionProperties = 1;
13  let noNamedPositionallyEncodedOperands = 1;
14}
15
16def R600 : Target {
17  let InstructionSet = R600InstrInfo;
18  let AllowRegisterRenaming = 1;
19}
20
21let Namespace = "R600" in {
22
23foreach Index = 0-15 in {
24  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
25}
26
27include "R600RegisterInfo.td"
28
29}
30
31def NullALU : InstrItinClass;
32def ALU_NULL : FuncUnit;
33
34include "AMDGPUFeatures.td"
35include "R600Schedule.td"
36include "R600Processors.td"
37include "AMDGPUInstrInfo.td"
38include "AMDGPUInstructions.td"
39include "R600Instructions.td"
40include "R700Instructions.td"
41include "EvergreenInstructions.td"
42include "CaymanInstructions.td"
43
44// Calling convention for R600
45def CC_R600 : CallingConv<[
46  CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[
47    T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW,
48    T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW,
49    T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW,
50    T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW,
51    T30_XYZW, T31_XYZW, T32_XYZW
52  ]>>>
53]>;
54