1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 Machine Scheduler interface
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
16 
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include <vector>
19 
20 using namespace llvm;
21 
22 namespace llvm {
23 
24 class R600InstrInfo;
25 struct R600RegisterInfo;
26 
27 class R600SchedStrategy final : public MachineSchedStrategy {
28   const ScheduleDAGMILive *DAG = nullptr;
29   const R600InstrInfo *TII = nullptr;
30   const R600RegisterInfo *TRI = nullptr;
31   MachineRegisterInfo *MRI = nullptr;
32 
33   enum InstKind {
34     IDAlu,
35     IDFetch,
36     IDOther,
37     IDLast
38   };
39 
40   enum AluKind {
41     AluAny,
42     AluT_X,
43     AluT_Y,
44     AluT_Z,
45     AluT_W,
46     AluT_XYZW,
47     AluPredX,
48     AluTrans,
49     AluDiscarded, // LLVM Instructions that are going to be eliminated
50     AluLast
51   };
52 
53   std::vector<SUnit *> Available[IDLast], Pending[IDLast];
54   std::vector<SUnit *> AvailableAlus[AluLast];
55   std::vector<SUnit *> PhysicalRegCopy;
56 
57   InstKind CurInstKind;
58   int CurEmitted;
59   InstKind NextInstKind;
60 
61   unsigned AluInstCount;
62   unsigned FetchInstCount;
63 
64   int InstKindLimit[IDLast];
65 
66   int OccupiedSlotsMask;
67 
68 public:
69   R600SchedStrategy() = default;
70   ~R600SchedStrategy() override = default;
71 
72   void initialize(ScheduleDAGMI *dag) override;
73   SUnit *pickNode(bool &IsTopNode) override;
74   void schedNode(SUnit *SU, bool IsTopNode) override;
75   void releaseTopNode(SUnit *SU) override;
76   void releaseBottomNode(SUnit *SU) override;
77 
78 private:
79   std::vector<MachineInstr *> InstructionsGroupCandidate;
80   bool VLIW5;
81 
82   int getInstKind(SUnit *SU);
83   bool regBelongsToClass(Register Reg, const TargetRegisterClass *RC) const;
84   AluKind getAluKind(SUnit *SU) const;
85   void LoadAlu();
86   unsigned AvailablesAluCount() const;
87   SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
88   void PrepareNextSlot();
89   SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
90 
91   void AssignSlot(MachineInstr *MI, unsigned Slot);
92   SUnit* pickAlu();
93   SUnit* pickOther(int QID);
94   void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
95 };
96 
97 } // end namespace llvm
98 
99 #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
100