1 //===-- SIModeRegister.cpp - Mode Register --------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This pass inserts changes to the Mode register settings as required. 10 /// Note that currently it only deals with the Double Precision Floating Point 11 /// rounding mode setting, but is intended to be generic enough to be easily 12 /// expanded. 13 /// 14 //===----------------------------------------------------------------------===// 15 // 16 #include "AMDGPU.h" 17 #include "AMDGPUInstrInfo.h" 18 #include "AMDGPUSubtarget.h" 19 #include "SIInstrInfo.h" 20 #include "SIMachineFunctionInfo.h" 21 #include "llvm/ADT/Statistic.h" 22 #include "llvm/CodeGen/MachineFunctionPass.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/IR/Constants.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/IR/LLVMContext.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include <queue> 32 33 #define DEBUG_TYPE "si-mode-register" 34 35 STATISTIC(NumSetregInserted, "Number of setreg of mode register inserted."); 36 37 using namespace llvm; 38 39 struct Status { 40 // Mask is a bitmask where a '1' indicates the corresponding Mode bit has a 41 // known value 42 unsigned Mask; 43 unsigned Mode; 44 45 Status() : Mask(0), Mode(0){}; 46 47 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) { 48 Mode &= Mask; 49 }; 50 51 // merge two status values such that only values that don't conflict are 52 // preserved 53 Status merge(const Status &S) const { 54 return Status((Mask | S.Mask), ((Mode & ~S.Mask) | (S.Mode & S.Mask))); 55 } 56 57 // merge an unknown value by using the unknown value's mask to remove bits 58 // from the result 59 Status mergeUnknown(unsigned newMask) { 60 return Status(Mask & ~newMask, Mode & ~newMask); 61 } 62 63 // intersect two Status values to produce a mode and mask that is a subset 64 // of both values 65 Status intersect(const Status &S) const { 66 unsigned NewMask = (Mask & S.Mask) & (Mode ^ ~S.Mode); 67 unsigned NewMode = (Mode & NewMask); 68 return Status(NewMask, NewMode); 69 } 70 71 // produce the delta required to change the Mode to the required Mode 72 Status delta(const Status &S) const { 73 return Status((S.Mask & (Mode ^ S.Mode)) | (~Mask & S.Mask), S.Mode); 74 } 75 76 bool operator==(const Status &S) const { 77 return (Mask == S.Mask) && (Mode == S.Mode); 78 } 79 80 bool operator!=(const Status &S) const { return !(*this == S); } 81 82 bool isCompatible(Status &S) { 83 return ((Mask & S.Mask) == S.Mask) && ((Mode & S.Mask) == S.Mode); 84 } 85 86 bool isCombinable(Status &S) { 87 return !(Mask & S.Mask) || isCompatible(S); 88 } 89 }; 90 91 class BlockData { 92 public: 93 // The Status that represents the mode register settings required by the 94 // FirstInsertionPoint (if any) in this block. Calculated in Phase 1. 95 Status Require; 96 97 // The Status that represents the net changes to the Mode register made by 98 // this block, Calculated in Phase 1. 99 Status Change; 100 101 // The Status that represents the mode register settings on exit from this 102 // block. Calculated in Phase 2. 103 Status Exit; 104 105 // The Status that represents the intersection of exit Mode register settings 106 // from all predecessor blocks. Calculated in Phase 2, and used by Phase 3. 107 Status Pred; 108 109 // In Phase 1 we record the first instruction that has a mode requirement, 110 // which is used in Phase 3 if we need to insert a mode change. 111 MachineInstr *FirstInsertionPoint; 112 113 BlockData() : FirstInsertionPoint(nullptr) {}; 114 }; 115 116 namespace { 117 118 class SIModeRegister : public MachineFunctionPass { 119 public: 120 static char ID; 121 122 std::vector<std::unique_ptr<BlockData>> BlockInfo; 123 std::queue<MachineBasicBlock *> Phase2List; 124 125 // The default mode register setting currently only caters for the floating 126 // point double precision rounding mode. 127 // We currently assume the default rounding mode is Round to Nearest 128 // NOTE: this should come from a per function rounding mode setting once such 129 // a setting exists. 130 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; 131 Status DefaultStatus = 132 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode)); 133 134 public: 135 SIModeRegister() : MachineFunctionPass(ID) {} 136 137 bool runOnMachineFunction(MachineFunction &MF) override; 138 139 void getAnalysisUsage(AnalysisUsage &AU) const override { 140 AU.setPreservesCFG(); 141 MachineFunctionPass::getAnalysisUsage(AU); 142 } 143 144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII); 145 146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII); 147 148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII); 149 150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII); 151 152 void insertSetreg(MachineBasicBlock &MBB, MachineInstr *I, 153 const SIInstrInfo *TII, Status InstrMode); 154 }; 155 } // End anonymous namespace. 156 157 INITIALIZE_PASS(SIModeRegister, DEBUG_TYPE, 158 "Insert required mode register values", false, false) 159 160 char SIModeRegister::ID = 0; 161 162 char &llvm::SIModeRegisterID = SIModeRegister::ID; 163 164 FunctionPass *llvm::createSIModeRegisterPass() { return new SIModeRegister(); } 165 166 // Determine the Mode register setting required for this instruction. 167 // Instructions which don't use the Mode register return a null Status. 168 // Note this currently only deals with instructions that use the floating point 169 // double precision setting. 170 Status SIModeRegister::getInstructionMode(MachineInstr &MI, 171 const SIInstrInfo *TII) { 172 if (TII->usesFPDPRounding(MI)) { 173 switch (MI.getOpcode()) { 174 case AMDGPU::V_INTERP_P1LL_F16: 175 case AMDGPU::V_INTERP_P1LV_F16: 176 case AMDGPU::V_INTERP_P2_F16: 177 // f16 interpolation instructions need double precision round to zero 178 return Status(FP_ROUND_MODE_DP(3), 179 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_ZERO)); 180 default: 181 return DefaultStatus; 182 } 183 } 184 return Status(); 185 } 186 187 // Insert a setreg instruction to update the Mode register. 188 // It is possible (though unlikely) for an instruction to require a change to 189 // the value of disjoint parts of the Mode register when we don't know the 190 // value of the intervening bits. In that case we need to use more than one 191 // setreg instruction. 192 void SIModeRegister::insertSetreg(MachineBasicBlock &MBB, MachineInstr *MI, 193 const SIInstrInfo *TII, Status InstrMode) { 194 while (InstrMode.Mask) { 195 unsigned Offset = countTrailingZeros<unsigned>(InstrMode.Mask); 196 unsigned Width = countTrailingOnes<unsigned>(InstrMode.Mask >> Offset); 197 unsigned Value = (InstrMode.Mode >> Offset) & ((1 << Width) - 1); 198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) 199 .addImm(Value) 200 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) | 201 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) | 202 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_)); 203 ++NumSetregInserted; 204 InstrMode.Mask &= ~(((1 << Width) - 1) << Offset); 205 } 206 } 207 208 // In Phase 1 we iterate through the instructions of the block and for each 209 // instruction we get its mode usage. If the instruction uses the Mode register 210 // we: 211 // - update the Change status, which tracks the changes to the Mode register 212 // made by this block 213 // - if this instruction's requirements are compatible with the current setting 214 // of the Mode register we merge the modes 215 // - if it isn't compatible and an InsertionPoint isn't set, then we set the 216 // InsertionPoint to the current instruction, and we remember the current 217 // mode 218 // - if it isn't compatible and InsertionPoint is set we insert a seteg before 219 // that instruction (unless this instruction forms part of the block's 220 // entry requirements in which case the insertion is deferred until Phase 3 221 // when predecessor exit values are known), and move the insertion point to 222 // this instruction 223 // - if this is a setreg instruction we treat it as an incompatible instruction. 224 // This is sub-optimal but avoids some nasty corner cases, and is expected to 225 // occur very rarely. 226 // - on exit we have set the Require, Change, and initial Exit modes. 227 void SIModeRegister::processBlockPhase1(MachineBasicBlock &MBB, 228 const SIInstrInfo *TII) { 229 auto NewInfo = llvm::make_unique<BlockData>(); 230 MachineInstr *InsertionPoint = nullptr; 231 // RequirePending is used to indicate whether we are collecting the initial 232 // requirements for the block, and need to defer the first InsertionPoint to 233 // Phase 3. It is set to false once we have set FirstInsertionPoint, or when 234 // we discover an explict setreg that means this block doesn't have any 235 // initial requirements. 236 bool RequirePending = true; 237 Status IPChange; 238 for (MachineInstr &MI : MBB) { 239 Status InstrMode = getInstructionMode(MI, TII); 240 if ((MI.getOpcode() == AMDGPU::S_SETREG_B32) || 241 (MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32)) { 242 // We preserve any explicit mode register setreg instruction we encounter, 243 // as we assume it has been inserted by a higher authority (this is 244 // likely to be a very rare occurrence). 245 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); 246 if (((Dst & AMDGPU::Hwreg::ID_MASK_) >> AMDGPU::Hwreg::ID_SHIFT_) != 247 AMDGPU::Hwreg::ID_MODE) 248 continue; 249 250 unsigned Width = ((Dst & AMDGPU::Hwreg::WIDTH_M1_MASK_) >> 251 AMDGPU::Hwreg::WIDTH_M1_SHIFT_) + 252 1; 253 unsigned Offset = 254 (Dst & AMDGPU::Hwreg::OFFSET_MASK_) >> AMDGPU::Hwreg::OFFSET_SHIFT_; 255 unsigned Mask = ((1 << Width) - 1) << Offset; 256 257 // If an InsertionPoint is set we will insert a setreg there. 258 if (InsertionPoint) { 259 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); 260 InsertionPoint = nullptr; 261 } 262 // If this is an immediate then we know the value being set, but if it is 263 // not an immediate then we treat the modified bits of the mode register 264 // as unknown. 265 if (MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32) { 266 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); 267 unsigned Mode = (Val << Offset) & Mask; 268 Status Setreg = Status(Mask, Mode); 269 // If we haven't already set the initial requirements for the block we 270 // don't need to as the requirements start from this explicit setreg. 271 RequirePending = false; 272 NewInfo->Change = NewInfo->Change.merge(Setreg); 273 } else { 274 NewInfo->Change = NewInfo->Change.mergeUnknown(Mask); 275 } 276 } else if (!NewInfo->Change.isCompatible(InstrMode)) { 277 // This instruction uses the Mode register and its requirements aren't 278 // compatible with the current mode. 279 if (InsertionPoint) { 280 // If the required mode change cannot be included in the current 281 // InsertionPoint changes, we need a setreg and start a new 282 // InsertionPoint. 283 if (!IPChange.delta(NewInfo->Change).isCombinable(InstrMode)) { 284 if (RequirePending) { 285 // This is the first insertionPoint in the block so we will defer 286 // the insertion of the setreg to Phase 3 where we know whether or 287 // not it is actually needed. 288 NewInfo->FirstInsertionPoint = InsertionPoint; 289 NewInfo->Require = NewInfo->Change; 290 RequirePending = false; 291 } else { 292 insertSetreg(MBB, InsertionPoint, TII, 293 IPChange.delta(NewInfo->Change)); 294 IPChange = NewInfo->Change; 295 } 296 // Set the new InsertionPoint 297 InsertionPoint = &MI; 298 } 299 NewInfo->Change = NewInfo->Change.merge(InstrMode); 300 } else { 301 // No InsertionPoint is currently set - this is either the first in 302 // the block or we have previously seen an explicit setreg. 303 InsertionPoint = &MI; 304 IPChange = NewInfo->Change; 305 NewInfo->Change = NewInfo->Change.merge(InstrMode); 306 } 307 } 308 } 309 if (RequirePending) { 310 // If we haven't yet set the initial requirements for the block we set them 311 // now. 312 NewInfo->FirstInsertionPoint = InsertionPoint; 313 NewInfo->Require = NewInfo->Change; 314 } else if (InsertionPoint) { 315 // We need to insert a setreg at the InsertionPoint 316 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); 317 } 318 NewInfo->Exit = NewInfo->Change; 319 BlockInfo[MBB.getNumber()] = std::move(NewInfo); 320 } 321 322 // In Phase 2 we revisit each block and calculate the common Mode register 323 // value provided by all predecessor blocks. If the Exit value for the block 324 // is changed, then we add the successor blocks to the worklist so that the 325 // exit value is propagated. 326 void SIModeRegister::processBlockPhase2(MachineBasicBlock &MBB, 327 const SIInstrInfo *TII) { 328 // BlockData *BI = BlockInfo[MBB.getNumber()]; 329 unsigned ThisBlock = MBB.getNumber(); 330 if (MBB.pred_empty()) { 331 // There are no predecessors, so use the default starting status. 332 BlockInfo[ThisBlock]->Pred = DefaultStatus; 333 } else { 334 // Build a status that is common to all the predecessors by intersecting 335 // all the predecessor exit status values. 336 MachineBasicBlock::pred_iterator P = MBB.pred_begin(), E = MBB.pred_end(); 337 MachineBasicBlock &PB = *(*P); 338 BlockInfo[ThisBlock]->Pred = BlockInfo[PB.getNumber()]->Exit; 339 340 for (P = std::next(P); P != E; P = std::next(P)) { 341 MachineBasicBlock *Pred = *P; 342 BlockInfo[ThisBlock]->Pred = BlockInfo[ThisBlock]->Pred.intersect(BlockInfo[Pred->getNumber()]->Exit); 343 } 344 } 345 Status TmpStatus = BlockInfo[ThisBlock]->Pred.merge(BlockInfo[ThisBlock]->Change); 346 if (BlockInfo[ThisBlock]->Exit != TmpStatus) { 347 BlockInfo[ThisBlock]->Exit = TmpStatus; 348 // Add the successors to the work list so we can propagate the changed exit 349 // status. 350 for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(), 351 E = MBB.succ_end(); 352 S != E; S = std::next(S)) { 353 MachineBasicBlock &B = *(*S); 354 Phase2List.push(&B); 355 } 356 } 357 } 358 359 // In Phase 3 we revisit each block and if it has an insertion point defined we 360 // check whether the predecessor mode meets the block's entry requirements. If 361 // not we insert an appropriate setreg instruction to modify the Mode register. 362 void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB, 363 const SIInstrInfo *TII) { 364 // BlockData *BI = BlockInfo[MBB.getNumber()]; 365 unsigned ThisBlock = MBB.getNumber(); 366 if (!BlockInfo[ThisBlock]->Pred.isCompatible(BlockInfo[ThisBlock]->Require)) { 367 Status Delta = BlockInfo[ThisBlock]->Pred.delta(BlockInfo[ThisBlock]->Require); 368 if (BlockInfo[ThisBlock]->FirstInsertionPoint) 369 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta); 370 else 371 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); 372 } 373 } 374 375 bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) { 376 BlockInfo.resize(MF.getNumBlockIDs()); 377 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 378 const SIInstrInfo *TII = ST.getInstrInfo(); 379 380 // Processing is performed in a number of phases 381 382 // Phase 1 - determine the initial mode required by each block, and add setreg 383 // instructions for intra block requirements. 384 for (MachineBasicBlock &BB : MF) 385 processBlockPhase1(BB, TII); 386 387 // Phase 2 - determine the exit mode from each block. We add all blocks to the 388 // list here, but will also add any that need to be revisited during Phase 2 389 // processing. 390 for (MachineBasicBlock &BB : MF) 391 Phase2List.push(&BB); 392 while (!Phase2List.empty()) { 393 processBlockPhase2(*Phase2List.front(), TII); 394 Phase2List.pop(); 395 } 396 397 // Phase 3 - add an initial setreg to each block where the required entry mode 398 // is not satisfied by the exit mode of all its predecessors. 399 for (MachineBasicBlock &BB : MF) 400 processBlockPhase3(BB, TII); 401 402 BlockInfo.clear(); 403 404 return NumSetregInserted > 0; 405 } 406