1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 let mayLoad = 0; 37 let mayStore = 0; 38 let hasSideEffects = 0; 39 let UseNamedOperandTable = 1; 40 let VALU = 1; 41 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 42} 43 44class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 45 string asm, list<dag> pattern> : 46 InstSI <outs, ins, asm, pattern>, 47 VOP <opName>, 48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51 let UseNamedOperandTable = 1; 52 53 string Mnemonic = opName; 54 VOPProfile Pfl = P; 55 56 string AsmOperands; 57} 58 59class VOP3Common <dag outs, dag ins, string asm = "", 60 list<dag> pattern = [], bit HasMods = 0, 61 bit VOP3Only = 0> : 62 VOPAnyCommon <outs, ins, asm, pattern> { 63 64 // Using complex patterns gives VOP3 patterns a very high complexity rating, 65 // but standalone patterns are almost always preferred, so we need to adjust the 66 // priority lower. The goal is to use a high number to reduce complexity to 67 // zero (or less than zero). 68 let AddedComplexity = -1000; 69 70 let VOP3 = 1; 71 72 let AsmVariantName = AMDGPUAsmVariants.VOP3; 73 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 74 75 let isCodeGenOnly = 0; 76 77 int Size = 8; 78 79 // Because SGPRs may be allowed if there are multiple operands, we 80 // need a post-isel hook to insert copies in order to avoid 81 // violating constant bus requirements. 82 let hasPostISelHook = 1; 83} 84 85class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 86 bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> : 87 VOP_Pseudo <opName, "_e64", P, P.Outs64, 88 !if(isVop3OpSel, 89 P.InsVOP3OpSel, 90 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 91 "", pattern> { 92 93 let VOP3_OPSEL = isVop3OpSel; 94 let IsPacked = P.IsPacked; 95 let IsMAI = P.IsMAI; 96 97 let AsmOperands = !if(isVop3OpSel, 98 P.AsmVOP3OpSel, 99 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 100 101 let Size = 8; 102 let mayLoad = 0; 103 let mayStore = 0; 104 let hasSideEffects = 0; 105 106 // Because SGPRs may be allowed if there are multiple operands, we 107 // need a post-isel hook to insert copies in order to avoid 108 // violating constant bus requirements. 109 let hasPostISelHook = 1; 110 111 // Using complex patterns gives VOP3 patterns a very high complexity rating, 112 // but standalone patterns are almost always preferred, so we need to adjust the 113 // priority lower. The goal is to use a high number to reduce complexity to 114 // zero (or less than zero). 115 let AddedComplexity = -1000; 116 117 let VOP3 = 1; 118 let VALU = 1; 119 let FPClamp = P.HasFPClamp; 120 let IntClamp = P.HasIntClamp; 121 let ClampLo = P.HasClampLo; 122 let ClampHi = P.HasClampHi; 123 124 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 125 126 let mayRaiseFPException = ReadsModeReg; 127 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 128 129 let AsmVariantName = AMDGPUAsmVariants.VOP3; 130 let AsmMatchConverter = 131 !if(isVOP3P, 132 "cvtVOP3P", 133 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 134 "cvtVOP3", 135 "")); 136} 137 138class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 139 VOP3_Pseudo<opName, P, pattern, 1, 1> { 140 let VOP3P = 1; 141} 142 143class VOP_Real<VOP_Pseudo ps> { 144 Instruction Opcode = !cast<Instruction>(NAME); 145 bit IsSingle = ps.Pfl.IsSingle; 146} 147 148class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> : 149 VOP_Real <ps>, 150 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 151 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 152 153 let VALU = 1; 154 let VOP3 = 1; 155 let isPseudo = 0; 156 let isCodeGenOnly = 0; 157 let UseNamedOperandTable = 1; 158 159 let Constraints = ps.Constraints; 160 let DisableEncoding = ps.DisableEncoding; 161 162 // copy relevant pseudo op flags 163 let SubtargetPredicate = ps.SubtargetPredicate; 164 let OtherPredicates = ps.OtherPredicates; 165 let AsmMatchConverter = ps.AsmMatchConverter; 166 let AsmVariantName = ps.AsmVariantName; 167 let Constraints = ps.Constraints; 168 let DisableEncoding = ps.DisableEncoding; 169 let TSFlags = ps.TSFlags; 170 let UseNamedOperandTable = ps.UseNamedOperandTable; 171 let Uses = ps.Uses; 172 let Defs = ps.Defs; 173 let SchedRW = ps.SchedRW; 174 let mayLoad = ps.mayLoad; 175 let mayStore = ps.mayStore; 176 let TRANS = ps.TRANS; 177 178 VOPProfile Pfl = ps.Pfl; 179} 180 181// XXX - Is there any reason to distinguish this from regular VOP3 182// here? 183class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> : 184 VOP3_Real<ps, EncodingFamily>; 185 186class VOP3a<VOPProfile P> : Enc64 { 187 bits<4> src0_modifiers; 188 bits<9> src0; 189 bits<3> src1_modifiers; 190 bits<9> src1; 191 bits<3> src2_modifiers; 192 bits<9> src2; 193 bits<1> clamp; 194 bits<2> omod; 195 196 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 197 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 198 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 199 200 let Inst{31-26} = 0x34; //encoding 201 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 202 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 203 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 204 let Inst{60-59} = !if(P.HasOMod, omod, 0); 205 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 206 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 207 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 208} 209 210class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 211 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 212 let Inst{25-17} = op; 213} 214 215class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 216 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 217 let Inst{25-16} = op; 218 let Inst{31-26} = 0x35; 219} 220 221class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 222 let Inst{25-16} = op; 223 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 224} 225 226class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 227 bits<8> vdst; 228 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 229} 230 231class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 232 bits<8> vdst; 233 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 234} 235 236class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 237 bits<8> vdst; 238 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 239} 240 241class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 242 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 243 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 244 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 245 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 246} 247 248class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 249 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 250 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 251 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 252 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 253} 254 255// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 256class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 257 bits<2> attrchan; 258 bits<6> attr; 259 bits<1> high; 260 261 let Inst{8} = 0; // No modifiers for src0 262 let Inst{61} = 0; 263 264 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 265 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 266 267 let Inst{37-32} = attr; 268 let Inst{39-38} = attrchan; 269 let Inst{40} = !if(P.HasHigh, high, 0); 270 271 let Inst{49-41} = src0; 272} 273 274class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 275 bits<6> attr; 276 bits<2> attrchan; 277 bits<1> high; 278 279 let Inst{8} = 0; 280 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 281 let Inst{37-32} = attr; 282 let Inst{39-38} = attrchan; 283 let Inst{40} = !if(p.HasHigh, high, 0); 284 let Inst{49-41} = src0; 285 let Inst{61} = 0; 286 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 287} 288 289class VOP3be <VOPProfile P> : Enc64 { 290 bits<8> vdst; 291 bits<2> src0_modifiers; 292 bits<9> src0; 293 bits<2> src1_modifiers; 294 bits<9> src1; 295 bits<2> src2_modifiers; 296 bits<9> src2; 297 bits<7> sdst; 298 bits<2> omod; 299 300 let Inst{7-0} = vdst; 301 let Inst{14-8} = sdst; 302 let Inst{31-26} = 0x34; //encoding 303 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 304 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 305 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 306 let Inst{60-59} = !if(P.HasOMod, omod, 0); 307 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 308 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 309 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 310} 311 312class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 313 bits<8> vdst; 314 // neg, neg_hi, op_sel put in srcN_modifiers 315 bits<4> src0_modifiers; 316 bits<9> src0; 317 bits<4> src1_modifiers; 318 bits<9> src1; 319 bits<4> src2_modifiers; 320 bits<9> src2; 321 bits<1> clamp; 322 323 let Inst{7-0} = vdst; 324 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 325 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 326 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 327 328 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 329 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 330 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 331 332 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 333 334 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 335 336 let Inst{22-16} = op; 337 let Inst{31-23} = 0x1a7; //encoding 338 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 339 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 340 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 341 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 342 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 343 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 344 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 345 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 346} 347 348class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 349 bits<8> vdst; 350 bits<10> src0; 351 bits<10> src1; 352 bits<9> src2; 353 bits<3> blgp; 354 bits<3> cbsz; 355 bits<4> abid; 356 357 let Inst{7-0} = vdst; 358 359 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 360 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 361 362 let Inst{15} = acc_cd; 363 364 let Inst{22-16} = op; 365 let Inst{31-23} = 0x1a7; //encoding 366 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 367 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 368 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 369 370 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 371 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 372 373 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 374} 375 376 377class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 378 let Inst{31-23} = 0x198; //encoding 379} 380 381class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 382 let Inst{25-17} = op; 383} 384 385class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 386 bits<1> clamp; 387 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 388 let Inst{25-16} = op; 389 let Inst{31-26} = 0x35; 390} 391 392class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 393 bits<1> clamp; 394 let Inst{25-16} = op; 395 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 396} 397 398def SDWA { 399 // sdwa_sel 400 int BYTE_0 = 0; 401 int BYTE_1 = 1; 402 int BYTE_2 = 2; 403 int BYTE_3 = 3; 404 int WORD_0 = 4; 405 int WORD_1 = 5; 406 int DWORD = 6; 407 408 // dst_unused 409 int UNUSED_PAD = 0; 410 int UNUSED_SEXT = 1; 411 int UNUSED_PRESERVE = 2; 412} 413 414class VOP_SDWAe<VOPProfile P> : Enc64 { 415 bits<8> src0; 416 bits<3> src0_sel; 417 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 418 bits<3> src1_sel; 419 bits<2> src1_modifiers; 420 bits<3> dst_sel; 421 bits<2> dst_unused; 422 bits<1> clamp; 423 424 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 425 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 426 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 427 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 428 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 429 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 430 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 431 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 432 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 433 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 434} 435 436// GFX9 adds two features to SDWA: 437// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 438// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 439// than VGPRs (at most 1 can be an SGPR); 440// b. OMOD is the standard output modifier (result *2, *4, /2) 441// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 442// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 443// field. 444// a. When SD=1, the SDST is used as the destination for the compare result; 445// b. When SD=0, VCC is used. 446// 447// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 448 449// gfx9 SDWA basic encoding 450class VOP_SDWA9e<VOPProfile P> : Enc64 { 451 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 452 bits<3> src0_sel; 453 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 454 bits<3> src1_sel; 455 bits<2> src1_modifiers; 456 bits<1> src1_sgpr; 457 458 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 459 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 460 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 461 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 462 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 463 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 464 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 465 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 466 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 467} 468 469// gfx9 SDWA-A 470class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 471 bits<3> dst_sel; 472 bits<2> dst_unused; 473 bits<1> clamp; 474 bits<2> omod; 475 476 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 477 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 478 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 479 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 480} 481 482// gfx9 SDWA-B 483class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 484 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 485 486 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 487 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 488} 489 490class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 491 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 492 VOP <opName>, 493 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 494 495 let isPseudo = 1; 496 let isCodeGenOnly = 1; 497 let UseNamedOperandTable = 1; 498 499 string Mnemonic = opName; 500 string AsmOperands = P.AsmSDWA; 501 string AsmOperands9 = P.AsmSDWA9; 502 503 let Size = 8; 504 let mayLoad = 0; 505 let mayStore = 0; 506 let hasSideEffects = 0; 507 508 let VALU = 1; 509 let SDWA = 1; 510 511 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 512 513 let mayRaiseFPException = ReadsModeReg; 514 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 515 516 let SubtargetPredicate = HasSDWA; 517 let AssemblerPredicate = HasSDWA; 518 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 519 AMDGPUAsmVariants.Disable); 520 let DecoderNamespace = "SDWA"; 521 522 VOPProfile Pfl = P; 523} 524 525class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 526 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 527 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 528 529 let VALU = 1; 530 let SDWA = 1; 531 let isPseudo = 0; 532 let isCodeGenOnly = 0; 533 534 let Defs = ps.Defs; 535 let Uses = ps.Uses; 536 let hasSideEffects = ps.hasSideEffects; 537 538 let Constraints = ps.Constraints; 539 let DisableEncoding = ps.DisableEncoding; 540 541 // Copy relevant pseudo op flags 542 let SubtargetPredicate = ps.SubtargetPredicate; 543 let AssemblerPredicate = ps.AssemblerPredicate; 544 let AsmMatchConverter = ps.AsmMatchConverter; 545 let AsmVariantName = ps.AsmVariantName; 546 let UseNamedOperandTable = ps.UseNamedOperandTable; 547 let DecoderNamespace = ps.DecoderNamespace; 548 let Constraints = ps.Constraints; 549 let DisableEncoding = ps.DisableEncoding; 550 let TSFlags = ps.TSFlags; 551 let SchedRW = ps.SchedRW; 552 let mayLoad = ps.mayLoad; 553 let mayStore = ps.mayStore; 554 let TRANS = ps.TRANS; 555} 556 557class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 558 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 559 560 let VALU = 1; 561 let SDWA = 1; 562 let isPseudo = 0; 563 let isCodeGenOnly = 0; 564 565 let Defs = ps.Defs; 566 let Uses = ps.Uses; 567 let hasSideEffects = ps.hasSideEffects; 568 569 let Constraints = ps.Constraints; 570 let DisableEncoding = ps.DisableEncoding; 571 572 let SubtargetPredicate = HasSDWA9; 573 let AssemblerPredicate = HasSDWA9; 574 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 575 AMDGPUAsmVariants.Disable); 576 let DecoderNamespace = "SDWA9"; 577 578 // Copy relevant pseudo op flags 579 let AsmMatchConverter = ps.AsmMatchConverter; 580 let UseNamedOperandTable = ps.UseNamedOperandTable; 581 let Constraints = ps.Constraints; 582 let DisableEncoding = ps.DisableEncoding; 583 let TSFlags = ps.TSFlags; 584 let SchedRW = ps.SchedRW; 585 let mayLoad = ps.mayLoad; 586 let mayStore = ps.mayStore; 587 let TRANS = ps.TRANS; 588} 589 590class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 591 Base_VOP_SDWA9_Real <ps >, 592 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 593 594class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 595 let SubtargetPredicate = HasSDWA10; 596 let AssemblerPredicate = HasSDWA10; 597 let DecoderNamespace = "SDWA10"; 598} 599 600class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 601 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 602 603class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 604 bits<2> src0_modifiers; 605 bits<8> src0; 606 bits<2> src1_modifiers; 607 bits<9> dpp_ctrl; 608 bits<1> bound_ctrl; 609 bits<4> bank_mask; 610 bits<4> row_mask; 611 bit fi; 612 613 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 614 let Inst{48-40} = dpp_ctrl; 615 let Inst{50} = !if(IsDPP16, fi, ?); 616 let Inst{51} = bound_ctrl; 617 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 618 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 619 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 620 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 621 let Inst{59-56} = bank_mask; 622 let Inst{63-60} = row_mask; 623} 624 625class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 626 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>, 627 VOP <OpName>, 628 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 629 630 let isPseudo = 1; 631 let isCodeGenOnly = 1; 632 633 let mayLoad = 0; 634 let mayStore = 0; 635 let hasSideEffects = 0; 636 let UseNamedOperandTable = 1; 637 638 let VALU = 1; 639 let DPP = 1; 640 let Size = 8; 641 642 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 643 644 let mayRaiseFPException = ReadsModeReg; 645 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 646 let isConvergent = 1; 647 648 string Mnemonic = OpName; 649 string AsmOperands = P.AsmDPP; 650 651 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 652 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 653 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 654 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 655 AMDGPUAsmVariants.Disable); 656 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 657 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 658 let DecoderNamespace = "DPP"; 659 660 VOPProfile Pfl = P; 661} 662 663class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 664 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 665 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 666 667 let VALU = 1; 668 let DPP = 1; 669 let isPseudo = 0; 670 let isCodeGenOnly = 0; 671 672 let Defs = ps.Defs; 673 let Uses = ps.Uses; 674 let hasSideEffects = ps.hasSideEffects; 675 676 let Constraints = ps.Constraints; 677 let DisableEncoding = ps.DisableEncoding; 678 679 // Copy relevant pseudo op flags 680 let isConvergent = ps.isConvergent; 681 let SubtargetPredicate = ps.SubtargetPredicate; 682 let AssemblerPredicate = ps.AssemblerPredicate; 683 let AsmMatchConverter = ps.AsmMatchConverter; 684 let AsmVariantName = ps.AsmVariantName; 685 let UseNamedOperandTable = ps.UseNamedOperandTable; 686 let DecoderNamespace = ps.DecoderNamespace; 687 let Constraints = ps.Constraints; 688 let DisableEncoding = ps.DisableEncoding; 689 let TSFlags = ps.TSFlags; 690 let SchedRW = ps.SchedRW; 691 let mayLoad = ps.mayLoad; 692 let mayStore = ps.mayStore; 693 let TRANS = ps.TRANS; 694} 695 696class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 697 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 698 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 699 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>, 700 VOP_DPPe<P, IsDPP16> { 701 702 let mayLoad = 0; 703 let mayStore = 0; 704 let hasSideEffects = 0; 705 let UseNamedOperandTable = 1; 706 707 let VALU = 1; 708 let DPP = 1; 709 let Size = 8; 710 711 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 712 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 713 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 714 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 715 AMDGPUAsmVariants.Disable); 716 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 717 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 718 let DecoderNamespace = "DPP"; 719} 720 721class VOP_DPP8e<VOPProfile P> : Enc64 { 722 bits<8> src0; 723 bits<24> dpp8; 724 bits<9> fi; 725 726 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 727 let Inst{63-40} = dpp8{23-0}; 728} 729 730class VOP_DPP8<string OpName, VOPProfile P> : 731 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>, 732 VOP_DPP8e<P> { 733 734 let mayLoad = 0; 735 let mayStore = 0; 736 let hasSideEffects = 0; 737 let UseNamedOperandTable = 1; 738 739 let VALU = 1; 740 let DPP = 1; 741 let Size = 8; 742 743 let AsmMatchConverter = "cvtDPP8"; 744 let SubtargetPredicate = HasDPP8; 745 let AssemblerPredicate = HasDPP8; 746 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, 747 AMDGPUAsmVariants.Disable); 748 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 749 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 750} 751 752def DPP8Mode { 753 int FI_0 = 0xE9; 754 int FI_1 = 0xEA; 755} 756 757class getNumNodeArgs<SDPatternOperator Op> { 758 SDNode N = !cast<SDNode>(Op); 759 SDTypeProfile TP = N.TypeProfile; 760 int ret = TP.NumOperands; 761} 762 763 764class getDivergentFrag<SDPatternOperator Op> { 765 766 int NumSrcArgs = getNumNodeArgs<Op>.ret; 767 PatFrag ret = PatFrag < 768 !if(!eq(NumSrcArgs, 1), 769 (ops node:$src0), 770 !if(!eq(NumSrcArgs, 2), 771 (ops node:$src0, node:$src1), 772 (ops node:$src0, node:$src1, node:$src2))), 773 !if(!eq(NumSrcArgs, 1), 774 (Op $src0), 775 !if(!eq(NumSrcArgs, 2), 776 (Op $src0, $src1), 777 (Op $src0, $src1, $src2))), 778 [{ return N->isDivergent(); }] 779 >; 780} 781 782class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 783 784 PatFrag Operator = getDivergentFrag < Op >.ret; 785 786 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 787 !subst(P.Src0RC32, P.Src0VT, 788 !subst(P.Src1RC32, P.Src1VT, tmp)))); 789 790 791 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 792 !subst(P.DstRC, P.DstVT, tmp))); 793 794 list<dag> ret = [!con(Outs, (set Ins))]; 795} 796 797class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 798 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 799} 800 801class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 802 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 803 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 804} 805 806class getVSrcOp<ValueType vt> { 807 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 808} 809 810// Class for binary integer operations with the clamp bit set for saturation 811// TODO: Add sub with negated inline constant pattern. 812class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 813 GCNPat<(node vt:$src0, vt:$src1), 814 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 815 DSTCLAMP.ENABLE) 816>; 817 818 819include "VOPCInstructions.td" 820include "VOP1Instructions.td" 821include "VOP2Instructions.td" 822include "VOP3Instructions.td" 823include "VOP3PInstructions.td" 824 825 826class VOPInfoTable <string Format> : GenericTable { 827 let FilterClass = Format # "_Real"; 828 let CppTypeName = "VOPInfo"; 829 let Fields = ["Opcode", "IsSingle"]; 830 831 let PrimaryKey = ["Opcode"]; 832 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 833} 834 835def VOP1InfoTable : VOPInfoTable<"VOP1">; 836def VOP2InfoTable : VOPInfoTable<"VOP2">; 837def VOP3InfoTable : VOPInfoTable<"VOP3">; 838