1 //===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the ARC implementation of the MRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARCRegisterInfo.h" 14 #include "ARC.h" 15 #include "ARCInstrInfo.h" 16 #include "ARCMachineFunctionInfo.h" 17 #include "ARCSubtarget.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineModuleInfo.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/CodeGen/TargetFrameLowering.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include "llvm/Target/TargetOptions.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "arc-reg-info" 34 35 #define GET_REGINFO_TARGET_DESC 36 #include "ARCGenRegisterInfo.inc" 37 38 static void replaceFrameIndex(MachineBasicBlock::iterator II, 39 const ARCInstrInfo &TII, unsigned Reg, 40 unsigned FrameReg, int Offset, int StackSize, 41 int ObjSize, RegScavenger *RS, int SPAdj) { 42 assert(RS && "Need register scavenger."); 43 MachineInstr &MI = *II; 44 MachineBasicBlock &MBB = *MI.getParent(); 45 DebugLoc DL = MI.getDebugLoc(); 46 unsigned BaseReg = FrameReg; 47 unsigned KillState = 0; 48 if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) { 49 // Loads can always be reached with LD_rlimm. 50 BuildMI(MBB, II, DL, TII.get(ARC::LD_rlimm), Reg) 51 .addReg(BaseReg) 52 .addImm(Offset) 53 .addMemOperand(*MI.memoperands_begin()); 54 MBB.erase(II); 55 return; 56 } 57 58 if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) { 59 // We need to use a scratch register to reach the far-away frame indexes. 60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); 61 if (!BaseReg) { 62 // We can be sure that the scavenged-register slot is within the range 63 // of the load offset. 64 const TargetRegisterInfo *TRI = 65 MBB.getParent()->getSubtarget().getRegisterInfo(); 66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); 67 assert(BaseReg && "Register scavenging failed."); 68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) 69 << " for FrameReg=" << printReg(FrameReg, TRI) 70 << "+Offset=" << Offset << "\n"); 71 (void)TRI; 72 RS->setRegUsed(BaseReg); 73 } 74 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; 75 BuildMI(MBB, II, DL, TII.get(AddOpc)) 76 .addReg(BaseReg, RegState::Define) 77 .addReg(FrameReg) 78 .addImm(Offset); 79 Offset = 0; 80 KillState = RegState::Kill; 81 } 82 switch (MI.getOpcode()) { 83 case ARC::LD_rs9: 84 assert((Offset % 4 == 0) && "LD needs 4 byte alignment."); 85 [[fallthrough]]; 86 case ARC::LDH_rs9: 87 case ARC::LDH_X_rs9: 88 assert((Offset % 2 == 0) && "LDH needs 2 byte alignment."); 89 [[fallthrough]]; 90 case ARC::LDB_rs9: 91 case ARC::LDB_X_rs9: 92 LLVM_DEBUG(dbgs() << "Building LDFI\n"); 93 BuildMI(MBB, II, DL, TII.get(MI.getOpcode()), Reg) 94 .addReg(BaseReg, KillState) 95 .addImm(Offset) 96 .addMemOperand(*MI.memoperands_begin()); 97 break; 98 case ARC::ST_rs9: 99 assert((Offset % 4 == 0) && "ST needs 4 byte alignment."); 100 [[fallthrough]]; 101 case ARC::STH_rs9: 102 assert((Offset % 2 == 0) && "STH needs 2 byte alignment."); 103 [[fallthrough]]; 104 case ARC::STB_rs9: 105 LLVM_DEBUG(dbgs() << "Building STFI\n"); 106 BuildMI(MBB, II, DL, TII.get(MI.getOpcode())) 107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 108 .addReg(BaseReg, KillState) 109 .addImm(Offset) 110 .addMemOperand(*MI.memoperands_begin()); 111 break; 112 case ARC::GETFI: 113 LLVM_DEBUG(dbgs() << "Building GETFI\n"); 114 BuildMI(MBB, II, DL, 115 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm)) 116 .addReg(Reg, RegState::Define) 117 .addReg(FrameReg) 118 .addImm(Offset); 119 break; 120 default: 121 llvm_unreachable("Unhandled opcode."); 122 } 123 124 // Erase old instruction. 125 MBB.erase(II); 126 } 127 128 ARCRegisterInfo::ARCRegisterInfo(const ARCSubtarget &ST) 129 : ARCGenRegisterInfo(ARC::BLINK), ST(ST) {} 130 131 bool ARCRegisterInfo::needsFrameMoves(const MachineFunction &MF) { 132 return MF.needsFrameMoves(); 133 } 134 135 const MCPhysReg * 136 ARCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 137 return CSR_ARC_SaveList; 138 } 139 140 BitVector ARCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 141 BitVector Reserved(getNumRegs()); 142 143 Reserved.set(ARC::ILINK); 144 Reserved.set(ARC::SP); 145 Reserved.set(ARC::GP); 146 Reserved.set(ARC::R25); 147 Reserved.set(ARC::BLINK); 148 Reserved.set(ARC::FP); 149 150 return Reserved; 151 } 152 153 bool ARCRegisterInfo::requiresRegisterScavenging( 154 const MachineFunction &MF) const { 155 return true; 156 } 157 158 bool ARCRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 159 return true; 160 } 161 162 bool ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 163 int SPAdj, unsigned FIOperandNum, 164 RegScavenger *RS) const { 165 assert(SPAdj == 0 && "Unexpected"); 166 MachineInstr &MI = *II; 167 MachineOperand &FrameOp = MI.getOperand(FIOperandNum); 168 int FrameIndex = FrameOp.getIndex(); 169 170 MachineFunction &MF = *MI.getParent()->getParent(); 171 const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo(); 172 const ARCFrameLowering *TFI = getFrameLowering(MF); 173 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex); 174 int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex); 175 int StackSize = MF.getFrameInfo().getStackSize(); 176 int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize(); 177 178 LLVM_DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n"); 179 LLVM_DEBUG(dbgs() << "<--------->\n"); 180 LLVM_DEBUG(dbgs() << MI << "\n"); 181 LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n"); 182 LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n"); 183 LLVM_DEBUG(dbgs() << "FrameOffset : " << Offset << "\n"); 184 LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n"); 185 LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n"); 186 (void)LocalFrameSize; 187 188 // Special handling of DBG_VALUE instructions. 189 if (MI.isDebugValue()) { 190 Register FrameReg = getFrameRegister(MF); 191 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 192 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 193 return false; 194 } 195 196 // fold constant into offset. 197 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 198 199 // TODO: assert based on the load type: 200 // ldb needs no alignment, 201 // ldh needs 2 byte alignment 202 // ld needs 4 byte alignment 203 LLVM_DEBUG(dbgs() << "Offset : " << Offset << "\n" 204 << "<--------->\n"); 205 206 Register Reg = MI.getOperand(0).getReg(); 207 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); 208 209 if (!TFI->hasFP(MF)) { 210 Offset = StackSize + Offset; 211 if (FrameIndex >= 0) 212 assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds."); 213 } else { 214 if (FrameIndex >= 0) { 215 assert((Offset < 0 && -Offset <= StackSize) && 216 "FP Offset not in bounds."); 217 } 218 } 219 replaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize, 220 ObjSize, RS, SPAdj); 221 return true; 222 } 223 224 Register ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 225 const ARCFrameLowering *TFI = getFrameLowering(MF); 226 return TFI->hasFP(MF) ? ARC::FP : ARC::SP; 227 } 228 229 const uint32_t * 230 ARCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 231 CallingConv::ID CC) const { 232 return CSR_ARC_RegMask; 233 } 234