1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Base ARM implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/IR/IntrinsicInst.h" 25 #include "llvm/IR/IntrinsicsARM.h" 26 #include <array> 27 #include <cstdint> 28 29 #define GET_INSTRINFO_HEADER 30 #include "ARMGenInstrInfo.inc" 31 32 namespace llvm { 33 34 class ARMBaseRegisterInfo; 35 class ARMSubtarget; 36 37 class ARMBaseInstrInfo : public ARMGenInstrInfo { 38 const ARMSubtarget &Subtarget; 39 40 protected: 41 // Can be only subclassed. 42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 43 44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, 45 unsigned LoadImmOpc, unsigned LoadOpc) const; 46 47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 48 /// and \p DefIdx. 49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 50 /// the list is modeled as <Reg:SubReg, SubIdx>. 51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 52 /// two elements: 53 /// - %1:sub1, sub0 54 /// - %2<:0>, sub1 55 /// 56 /// \returns true if it is possible to build such an input sequence 57 /// with the pair \p MI, \p DefIdx. False otherwise. 58 /// 59 /// \pre MI.isRegSequenceLike(). 60 bool getRegSequenceLikeInputs( 61 const MachineInstr &MI, unsigned DefIdx, 62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override; 63 64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 65 /// and \p DefIdx. 66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 68 /// - %1:sub1, sub0 69 /// 70 /// \returns true if it is possible to build such an input sequence 71 /// with the pair \p MI, \p DefIdx. False otherwise. 72 /// 73 /// \pre MI.isExtractSubregLike(). 74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 75 RegSubRegPairAndIdx &InputReg) const override; 76 77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 78 /// and \p DefIdx. 79 /// \p [out] BaseReg and \p [out] InsertedReg contain 80 /// the equivalent inputs of INSERT_SUBREG. 81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 82 /// - BaseReg: %0:sub0 83 /// - InsertedReg: %1:sub1, sub3 84 /// 85 /// \returns true if it is possible to build such an input sequence 86 /// with the pair \p MI, \p DefIdx. False otherwise. 87 /// 88 /// \pre MI.isInsertSubregLike(). 89 bool 90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 91 RegSubRegPair &BaseReg, 92 RegSubRegPairAndIdx &InsertedReg) const override; 93 94 /// Commutes the operands in the given instruction. 95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 96 /// 97 /// Do not call this method for a non-commutable instruction or for 98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 99 /// Even though the instruction is commutable, the method may still 100 /// fail to commute the operands, null pointer is returned in such cases. 101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 102 unsigned OpIdx1, 103 unsigned OpIdx2) const override; 104 /// If the specific machine instruction is an instruction that moves/copies 105 /// value from one register to another register return destination and source 106 /// registers as machine operands. 107 Optional<DestSourcePair> 108 isCopyInstrImpl(const MachineInstr &MI) const override; 109 110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to 111 /// enhance debug entry value descriptions for ARM targets. 112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 113 Register Reg) const override; 114 115 public: 116 // Return whether the target has an explicit NOP encoding. 117 bool hasNOP() const; 118 119 // Return the non-pre/post incrementing version of 'Opc'. Return 0 120 // if there is not such an opcode. 121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0; 122 123 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 124 MachineInstr &MI, 125 LiveVariables *LV) const override; 126 127 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 128 const ARMSubtarget &getSubtarget() const { return Subtarget; } 129 130 ScheduleHazardRecognizer * 131 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 132 const ScheduleDAG *DAG) const override; 133 134 ScheduleHazardRecognizer * 135 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 136 const ScheduleDAG *DAG) const override; 137 138 // Branch analysis. 139 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 140 MachineBasicBlock *&FBB, 141 SmallVectorImpl<MachineOperand> &Cond, 142 bool AllowModify = false) const override; 143 unsigned removeBranch(MachineBasicBlock &MBB, 144 int *BytesRemoved = nullptr) const override; 145 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 146 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 147 const DebugLoc &DL, 148 int *BytesAdded = nullptr) const override; 149 150 bool 151 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 152 153 // Predication support. 154 bool isPredicated(const MachineInstr &MI) const override; 155 156 // MIR printer helper function to annotate Operands with a comment. 157 std::string 158 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 159 unsigned OpIdx, 160 const TargetRegisterInfo *TRI) const override; 161 162 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { 163 int PIdx = MI.findFirstPredOperandIdx(); 164 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() 165 : ARMCC::AL; 166 } 167 168 bool PredicateInstruction(MachineInstr &MI, 169 ArrayRef<MachineOperand> Pred) const override; 170 171 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 172 ArrayRef<MachineOperand> Pred2) const override; 173 174 bool DefinesPredicate(MachineInstr &MI, 175 std::vector<MachineOperand> &Pred) const override; 176 177 bool isPredicable(const MachineInstr &MI) const override; 178 179 // CPSR defined in instruction 180 static bool isCPSRDefined(const MachineInstr &MI); 181 bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const; 182 bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const; 183 184 // Load, scaled register offset 185 bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const; 186 // Load, scaled register offset, not plus LSL2 187 bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const; 188 // Minus reg for ldstso addr mode 189 bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const; 190 // Scaled register offset in address mode 2 191 bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const; 192 // Load multiple, base reg in list 193 bool isLDMBaseRegInList(const MachineInstr &MI) const; 194 // get LDM variable defs size 195 unsigned getLDMVariableDefsSize(const MachineInstr &MI) const; 196 197 /// GetInstSize - Returns the size of the specified MachineInstr. 198 /// 199 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 200 201 unsigned isLoadFromStackSlot(const MachineInstr &MI, 202 int &FrameIndex) const override; 203 unsigned isStoreToStackSlot(const MachineInstr &MI, 204 int &FrameIndex) const override; 205 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 206 int &FrameIndex) const override; 207 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 208 int &FrameIndex) const override; 209 210 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 211 unsigned SrcReg, bool KillSrc, 212 const ARMSubtarget &Subtarget) const; 213 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 214 unsigned DestReg, bool KillSrc, 215 const ARMSubtarget &Subtarget) const; 216 217 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 218 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 219 bool KillSrc) const override; 220 221 void storeRegToStackSlot(MachineBasicBlock &MBB, 222 MachineBasicBlock::iterator MBBI, 223 Register SrcReg, bool isKill, int FrameIndex, 224 const TargetRegisterClass *RC, 225 const TargetRegisterInfo *TRI) const override; 226 227 void loadRegFromStackSlot(MachineBasicBlock &MBB, 228 MachineBasicBlock::iterator MBBI, 229 Register DestReg, int FrameIndex, 230 const TargetRegisterClass *RC, 231 const TargetRegisterInfo *TRI) const override; 232 233 bool expandPostRAPseudo(MachineInstr &MI) const override; 234 235 bool shouldSink(const MachineInstr &MI) const override; 236 237 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 238 Register DestReg, unsigned SubIdx, 239 const MachineInstr &Orig, 240 const TargetRegisterInfo &TRI) const override; 241 242 MachineInstr & 243 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, 244 const MachineInstr &Orig) const override; 245 246 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 247 unsigned SubIdx, unsigned State, 248 const TargetRegisterInfo *TRI) const; 249 250 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, 251 const MachineRegisterInfo *MRI) const override; 252 253 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 254 /// determine if two loads are loading from the same base address. It should 255 /// only return true if the base pointers are the same and the only 256 /// differences between the two addresses is the offset. It also returns the 257 /// offsets by reference. 258 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 259 int64_t &Offset2) const override; 260 261 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 262 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 263 /// should be scheduled togther. On some targets if two loads are loading from 264 /// addresses in the same cache line, it's better if they are scheduled 265 /// together. This function takes two integers that represent the load offsets 266 /// from the common base address. It returns true if it decides it's desirable 267 /// to schedule the two loads together. "NumLoads" is the number of loads that 268 /// have already been scheduled after Load1. 269 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 270 int64_t Offset1, int64_t Offset2, 271 unsigned NumLoads) const override; 272 273 bool isSchedulingBoundary(const MachineInstr &MI, 274 const MachineBasicBlock *MBB, 275 const MachineFunction &MF) const override; 276 277 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 278 unsigned NumCycles, unsigned ExtraPredCycles, 279 BranchProbability Probability) const override; 280 281 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 282 unsigned ExtraT, MachineBasicBlock &FMBB, 283 unsigned NumF, unsigned ExtraF, 284 BranchProbability Probability) const override; 285 286 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 287 BranchProbability Probability) const override { 288 return NumCycles == 1; 289 } 290 291 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 292 unsigned NumInsts) const override; 293 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override; 294 295 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 296 MachineBasicBlock &FMBB) const override; 297 298 /// analyzeCompare - For a comparison instruction, return the source registers 299 /// in SrcReg and SrcReg2 if having two register operands, and the value it 300 /// compares against in CmpValue. Return true if the comparison instruction 301 /// can be analyzed. 302 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 303 Register &SrcReg2, int &CmpMask, 304 int &CmpValue) const override; 305 306 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 307 /// that we can remove a "comparison with zero"; Remove a redundant CMP 308 /// instruction if the flags can be updated in the same way by an earlier 309 /// instruction such as SUB. 310 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 311 Register SrcReg2, int CmpMask, int CmpValue, 312 const MachineRegisterInfo *MRI) const override; 313 314 bool analyzeSelect(const MachineInstr &MI, 315 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 316 unsigned &FalseOp, bool &Optimizable) const override; 317 318 MachineInstr *optimizeSelect(MachineInstr &MI, 319 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 320 bool) const override; 321 322 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 323 /// instruction, try to fold the immediate into the use instruction. 324 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 325 MachineRegisterInfo *MRI) const override; 326 327 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 328 const MachineInstr &MI) const override; 329 330 int getOperandLatency(const InstrItineraryData *ItinData, 331 const MachineInstr &DefMI, unsigned DefIdx, 332 const MachineInstr &UseMI, 333 unsigned UseIdx) const override; 334 int getOperandLatency(const InstrItineraryData *ItinData, 335 SDNode *DefNode, unsigned DefIdx, 336 SDNode *UseNode, unsigned UseIdx) const override; 337 338 /// VFP/NEON execution domains. 339 std::pair<uint16_t, uint16_t> 340 getExecutionDomain(const MachineInstr &MI) const override; 341 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 342 343 unsigned 344 getPartialRegUpdateClearance(const MachineInstr &, unsigned, 345 const TargetRegisterInfo *) const override; 346 void breakPartialRegDependency(MachineInstr &, unsigned, 347 const TargetRegisterInfo *TRI) const override; 348 349 /// Get the number of addresses by LDM or VLDM or zero for unknown. 350 unsigned getNumLDMAddresses(const MachineInstr &MI) const; 351 352 std::pair<unsigned, unsigned> 353 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 354 ArrayRef<std::pair<unsigned, const char *>> 355 getSerializableDirectMachineOperandTargetFlags() const override; 356 ArrayRef<std::pair<unsigned, const char *>> 357 getSerializableBitmaskMachineOperandTargetFlags() const override; 358 359 /// ARM supports the MachineOutliner. 360 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 361 bool OutlineFromLinkOnceODRs) const override; 362 outliner::OutlinedFunction getOutliningCandidateInfo( 363 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 364 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, 365 unsigned Flags) const override; 366 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 367 unsigned &Flags) const override; 368 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 369 const outliner::OutlinedFunction &OF) const override; 370 MachineBasicBlock::iterator 371 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 372 MachineBasicBlock::iterator &It, MachineFunction &MF, 373 const outliner::Candidate &C) const override; 374 375 private: 376 /// Returns an unused general-purpose register which can be used for 377 /// constructing an outlined call if one exists. Returns 0 otherwise. 378 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 379 380 unsigned getInstBundleLength(const MachineInstr &MI) const; 381 382 int getVLDMDefCycle(const InstrItineraryData *ItinData, 383 const MCInstrDesc &DefMCID, 384 unsigned DefClass, 385 unsigned DefIdx, unsigned DefAlign) const; 386 int getLDMDefCycle(const InstrItineraryData *ItinData, 387 const MCInstrDesc &DefMCID, 388 unsigned DefClass, 389 unsigned DefIdx, unsigned DefAlign) const; 390 int getVSTMUseCycle(const InstrItineraryData *ItinData, 391 const MCInstrDesc &UseMCID, 392 unsigned UseClass, 393 unsigned UseIdx, unsigned UseAlign) const; 394 int getSTMUseCycle(const InstrItineraryData *ItinData, 395 const MCInstrDesc &UseMCID, 396 unsigned UseClass, 397 unsigned UseIdx, unsigned UseAlign) const; 398 int getOperandLatency(const InstrItineraryData *ItinData, 399 const MCInstrDesc &DefMCID, 400 unsigned DefIdx, unsigned DefAlign, 401 const MCInstrDesc &UseMCID, 402 unsigned UseIdx, unsigned UseAlign) const; 403 404 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 405 const MachineInstr &DefMI, unsigned DefIdx, 406 const MCInstrDesc &DefMCID, unsigned DefAdj, 407 const MachineOperand &DefMO, unsigned Reg, 408 const MachineInstr &UseMI, unsigned UseIdx, 409 const MCInstrDesc &UseMCID, unsigned UseAdj) const; 410 411 unsigned getPredicationCost(const MachineInstr &MI) const override; 412 413 unsigned getInstrLatency(const InstrItineraryData *ItinData, 414 const MachineInstr &MI, 415 unsigned *PredCost = nullptr) const override; 416 417 int getInstrLatency(const InstrItineraryData *ItinData, 418 SDNode *Node) const override; 419 420 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 421 const MachineRegisterInfo *MRI, 422 const MachineInstr &DefMI, unsigned DefIdx, 423 const MachineInstr &UseMI, 424 unsigned UseIdx) const override; 425 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 426 const MachineInstr &DefMI, 427 unsigned DefIdx) const override; 428 429 /// verifyInstruction - Perform target specific instruction verification. 430 bool verifyInstruction(const MachineInstr &MI, 431 StringRef &ErrInfo) const override; 432 433 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0; 434 435 void expandMEMCPY(MachineBasicBlock::iterator) const; 436 437 /// Identify instructions that can be folded into a MOVCC instruction, and 438 /// return the defining instruction. 439 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, 440 const TargetInstrInfo *TII) const; 441 442 private: 443 /// Modeling special VFP / NEON fp MLA / MLS hazards. 444 445 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 446 /// MLx table. 447 DenseMap<unsigned, unsigned> MLxEntryMap; 448 449 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 450 /// stalls when scheduled together with fp MLA / MLS opcodes. 451 SmallSet<unsigned, 16> MLxHazardOpcodes; 452 453 public: 454 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 455 /// instruction. 456 bool isFpMLxInstruction(unsigned Opcode) const { 457 return MLxEntryMap.count(Opcode); 458 } 459 460 /// isFpMLxInstruction - This version also returns the multiply opcode and the 461 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 462 /// the MLX instructions with an extra lane operand. 463 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 464 unsigned &AddSubOpc, bool &NegAcc, 465 bool &HasLane) const; 466 467 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 468 /// will cause stalls when scheduled after (within 4-cycle window) a fp 469 /// MLA / MLS instruction. 470 bool canCauseFpMLxStall(unsigned Opcode) const { 471 return MLxHazardOpcodes.count(Opcode); 472 } 473 474 /// Returns true if the instruction has a shift by immediate that can be 475 /// executed in one cycle less. 476 bool isSwiftFastImmShift(const MachineInstr *MI) const; 477 478 /// Returns predicate register associated with the given frame instruction. 479 unsigned getFramePred(const MachineInstr &MI) const { 480 assert(isFrameInstr(MI)); 481 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP: 482 // - argument declared in the pattern: 483 // 0 - frame size 484 // 1 - arg of CALLSEQ_START/CALLSEQ_END 485 // 2 - predicate code (like ARMCC::AL) 486 // - added by predOps: 487 // 3 - predicate reg 488 return MI.getOperand(3).getReg(); 489 } 490 491 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 492 Register Reg) const override; 493 }; 494 495 /// Get the operands corresponding to the given \p Pred value. By default, the 496 /// predicate register is assumed to be 0 (no register), but you can pass in a 497 /// \p PredReg if that is not the case. 498 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, 499 unsigned PredReg = 0) { 500 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)), 501 MachineOperand::CreateReg(PredReg, false)}}; 502 } 503 504 /// Get the operand corresponding to the conditional code result. By default, 505 /// this is 0 (no register). 506 static inline MachineOperand condCodeOp(unsigned CCReg = 0) { 507 return MachineOperand::CreateReg(CCReg, false); 508 } 509 510 /// Get the operand corresponding to the conditional code result for Thumb1. 511 /// This operand will always refer to CPSR and it will have the Define flag set. 512 /// You can optionally set the Dead flag by means of \p isDead. 513 static inline MachineOperand t1CondCodeOp(bool isDead = false) { 514 return MachineOperand::CreateReg(ARM::CPSR, 515 /*Define*/ true, /*Implicit*/ false, 516 /*Kill*/ false, isDead); 517 } 518 519 static inline 520 bool isUncondBranchOpcode(int Opc) { 521 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 522 } 523 524 // This table shows the VPT instruction variants, i.e. the different 525 // mask field encodings, see also B5.6. Predication/conditional execution in 526 // the ArmARM. 527 static inline bool isVPTOpcode(int Opc) { 528 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || 529 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || 530 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || 531 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || 532 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || 533 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || 534 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || 535 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || 536 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r || 537 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r || 538 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r || 539 Opc == ARM::MVE_VPST; 540 } 541 542 static inline 543 unsigned VCMPOpcodeToVPT(unsigned Opcode) { 544 switch (Opcode) { 545 default: 546 return 0; 547 case ARM::MVE_VCMPf32: 548 return ARM::MVE_VPTv4f32; 549 case ARM::MVE_VCMPf16: 550 return ARM::MVE_VPTv8f16; 551 case ARM::MVE_VCMPi8: 552 return ARM::MVE_VPTv16i8; 553 case ARM::MVE_VCMPi16: 554 return ARM::MVE_VPTv8i16; 555 case ARM::MVE_VCMPi32: 556 return ARM::MVE_VPTv4i32; 557 case ARM::MVE_VCMPu8: 558 return ARM::MVE_VPTv16u8; 559 case ARM::MVE_VCMPu16: 560 return ARM::MVE_VPTv8u16; 561 case ARM::MVE_VCMPu32: 562 return ARM::MVE_VPTv4u32; 563 case ARM::MVE_VCMPs8: 564 return ARM::MVE_VPTv16s8; 565 case ARM::MVE_VCMPs16: 566 return ARM::MVE_VPTv8s16; 567 case ARM::MVE_VCMPs32: 568 return ARM::MVE_VPTv4s32; 569 570 case ARM::MVE_VCMPf32r: 571 return ARM::MVE_VPTv4f32r; 572 case ARM::MVE_VCMPf16r: 573 return ARM::MVE_VPTv8f16r; 574 case ARM::MVE_VCMPi8r: 575 return ARM::MVE_VPTv16i8r; 576 case ARM::MVE_VCMPi16r: 577 return ARM::MVE_VPTv8i16r; 578 case ARM::MVE_VCMPi32r: 579 return ARM::MVE_VPTv4i32r; 580 case ARM::MVE_VCMPu8r: 581 return ARM::MVE_VPTv16u8r; 582 case ARM::MVE_VCMPu16r: 583 return ARM::MVE_VPTv8u16r; 584 case ARM::MVE_VCMPu32r: 585 return ARM::MVE_VPTv4u32r; 586 case ARM::MVE_VCMPs8r: 587 return ARM::MVE_VPTv16s8r; 588 case ARM::MVE_VCMPs16r: 589 return ARM::MVE_VPTv8s16r; 590 case ARM::MVE_VCMPs32r: 591 return ARM::MVE_VPTv4s32r; 592 } 593 } 594 595 static inline 596 unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop) { 597 switch (Opcode) { 598 default: 599 llvm_unreachable("unhandled vctp opcode"); 600 break; 601 case ARM::MVE_VCTP8: 602 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; 603 case ARM::MVE_VCTP16: 604 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; 605 case ARM::MVE_VCTP32: 606 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; 607 case ARM::MVE_VCTP64: 608 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; 609 } 610 return 0; 611 } 612 613 static inline unsigned getTailPredVectorWidth(unsigned Opcode) { 614 switch (Opcode) { 615 default: 616 llvm_unreachable("unhandled vctp opcode"); 617 case ARM::MVE_VCTP8: return 16; 618 case ARM::MVE_VCTP16: return 8; 619 case ARM::MVE_VCTP32: return 4; 620 case ARM::MVE_VCTP64: return 2; 621 } 622 return 0; 623 } 624 625 static inline 626 bool isVCTP(MachineInstr *MI) { 627 switch (MI->getOpcode()) { 628 default: 629 break; 630 case ARM::MVE_VCTP8: 631 case ARM::MVE_VCTP16: 632 case ARM::MVE_VCTP32: 633 case ARM::MVE_VCTP64: 634 return true; 635 } 636 return false; 637 } 638 639 static inline 640 bool isLoopStart(MachineInstr &MI) { 641 return MI.getOpcode() == ARM::t2DoLoopStart || 642 MI.getOpcode() == ARM::t2WhileLoopStart; 643 } 644 645 static inline 646 bool isCondBranchOpcode(int Opc) { 647 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 648 } 649 650 static inline bool isJumpTableBranchOpcode(int Opc) { 651 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || 652 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || 653 Opc == ARM::t2BR_JT; 654 } 655 656 static inline 657 bool isIndirectBranchOpcode(int Opc) { 658 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 659 } 660 661 static inline bool isPopOpcode(int Opc) { 662 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 663 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 664 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 665 } 666 667 static inline bool isPushOpcode(int Opc) { 668 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 669 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 670 } 671 672 static inline bool isSubImmOpcode(int Opc) { 673 return Opc == ARM::SUBri || 674 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || 675 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || 676 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; 677 } 678 679 static inline bool isMovRegOpcode(int Opc) { 680 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr; 681 } 682 /// isValidCoprocessorNumber - decide whether an explicit coprocessor 683 /// number is legal in generic instructions like CDP. The answer can 684 /// vary with the subtarget. 685 static inline bool isValidCoprocessorNumber(unsigned Num, 686 const FeatureBitset& featureBits) { 687 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the 688 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is 689 // useful for code which is shared with older architectures which do not know 690 // the new VFP/NEON mnemonics. 691 692 // Armv8-A disallows everything *other* than 111x (CP14 and CP15). 693 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE) 694 return false; 695 696 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15) 697 // which clash with MVE. 698 if (featureBits[ARM::HasV8_1MMainlineOps] && 699 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) 700 return false; 701 702 return true; 703 } 704 705 /// getInstrPredicate - If instruction is predicated, returns its predicate 706 /// condition, otherwise returns AL. It also returns the condition code 707 /// register by reference. 708 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg); 709 710 unsigned getMatchingCondBranchOpcode(unsigned Opc); 711 712 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 713 /// the instruction is encoded with an 'S' bit is determined by the optional 714 /// CPSR def operand. 715 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 716 717 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 718 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 719 /// code. 720 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 721 MachineBasicBlock::iterator &MBBI, 722 const DebugLoc &dl, Register DestReg, 723 Register BaseReg, int NumBytes, 724 ARMCC::CondCodes Pred, Register PredReg, 725 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 726 727 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 728 MachineBasicBlock::iterator &MBBI, 729 const DebugLoc &dl, Register DestReg, 730 Register BaseReg, int NumBytes, 731 ARMCC::CondCodes Pred, Register PredReg, 732 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 733 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 734 MachineBasicBlock::iterator &MBBI, 735 const DebugLoc &dl, Register DestReg, 736 Register BaseReg, int NumBytes, 737 const TargetInstrInfo &TII, 738 const ARMBaseRegisterInfo &MRI, 739 unsigned MIFlags = 0); 740 741 /// Tries to add registers to the reglist of a given base-updating 742 /// push/pop instruction to adjust the stack by an additional 743 /// NumBytes. This can save a few bytes per function in code-size, but 744 /// obviously generates more memory traffic. As such, it only takes 745 /// effect in functions being optimised for size. 746 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 747 MachineFunction &MF, MachineInstr *MI, 748 unsigned NumBytes); 749 750 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 751 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 752 /// offset could not be handled directly in MI, and return the left-over 753 /// portion by reference. 754 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 755 Register FrameReg, int &Offset, 756 const ARMBaseInstrInfo &TII); 757 758 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 759 Register FrameReg, int &Offset, 760 const ARMBaseInstrInfo &TII, 761 const TargetRegisterInfo *TRI); 762 763 /// Return true if Reg is defd between From and To 764 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, 765 MachineBasicBlock::iterator To, 766 const TargetRegisterInfo *TRI); 767 768 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning 769 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found. 770 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, 771 const TargetRegisterInfo *TRI); 772 773 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); 774 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg); 775 776 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); 777 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, 778 unsigned Inactive); 779 780 /// Returns the number of instructions required to materialize the given 781 /// constant in a register, or 3 if a literal pool load is needed. 782 /// If ForCodesize is specified, an approximate cost in bytes is returned. 783 unsigned ConstantMaterializationCost(unsigned Val, 784 const ARMSubtarget *Subtarget, 785 bool ForCodesize = false); 786 787 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2. 788 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as 789 /// specified. If the scores are equal, return the comparison for !ForCodesize. 790 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, 791 const ARMSubtarget *Subtarget, 792 bool ForCodesize = false); 793 794 // Return the immediate if this is ADDri or SUBri, scaled as appropriate. 795 // Returns 0 for unknown instructions. 796 inline int getAddSubImmediate(MachineInstr &MI) { 797 int Scale = 1; 798 unsigned ImmOp; 799 switch (MI.getOpcode()) { 800 case ARM::t2ADDri: 801 ImmOp = 2; 802 break; 803 case ARM::t2SUBri: 804 case ARM::t2SUBri12: 805 ImmOp = 2; 806 Scale = -1; 807 break; 808 case ARM::tSUBi3: 809 case ARM::tSUBi8: 810 ImmOp = 3; 811 Scale = -1; 812 break; 813 default: 814 return 0; 815 } 816 return Scale * MI.getOperand(ImmOp).getImm(); 817 } 818 819 // Given a memory access Opcode, check that the give Imm would be a valid Offset 820 // for this instruction using its addressing mode. 821 inline bool isLegalAddressImm(unsigned Opcode, int Imm, 822 const TargetInstrInfo *TII) { 823 const MCInstrDesc &Desc = TII->get(Opcode); 824 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 825 switch (AddrMode) { 826 case ARMII::AddrModeT2_i7: 827 return std::abs(Imm) < (((1 << 7) * 1) - 1); 828 case ARMII::AddrModeT2_i7s2: 829 return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0; 830 case ARMII::AddrModeT2_i7s4: 831 return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0; 832 default: 833 llvm_unreachable("Unhandled Addressing mode"); 834 } 835 } 836 837 // Return true if the given intrinsic is a gather or scatter 838 inline bool isGatherScatter(IntrinsicInst *IntInst) { 839 if (IntInst == nullptr) 840 return false; 841 unsigned IntrinsicID = IntInst->getIntrinsicID(); 842 return (IntrinsicID == Intrinsic::masked_gather || 843 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base || 844 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated || 845 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb || 846 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated || 847 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset || 848 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated || 849 IntrinsicID == Intrinsic::masked_scatter || 850 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base || 851 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated || 852 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb || 853 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated || 854 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset || 855 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated); 856 } 857 858 } // end namespace llvm 859 860 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 861