1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the base ARM implementation of TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMBaseRegisterInfo.h" 14 #include "ARM.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMFrameLowering.h" 17 #include "ARMMachineFunctionInfo.h" 18 #include "ARMSubtarget.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "MCTargetDesc/ARMBaseInfo.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineFrameInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineInstr.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineOperand.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RegisterScavenging.h" 33 #include "llvm/CodeGen/TargetInstrInfo.h" 34 #include "llvm/CodeGen/TargetRegisterInfo.h" 35 #include "llvm/CodeGen/VirtRegMap.h" 36 #include "llvm/IR/Attributes.h" 37 #include "llvm/IR/Constants.h" 38 #include "llvm/IR/DebugLoc.h" 39 #include "llvm/IR/Function.h" 40 #include "llvm/IR/Type.h" 41 #include "llvm/MC/MCInstrDesc.h" 42 #include "llvm/Support/Debug.h" 43 #include "llvm/Support/ErrorHandling.h" 44 #include "llvm/Support/raw_ostream.h" 45 #include "llvm/Target/TargetMachine.h" 46 #include "llvm/Target/TargetOptions.h" 47 #include <cassert> 48 #include <utility> 49 50 #define DEBUG_TYPE "arm-register-info" 51 52 #define GET_REGINFO_TARGET_DESC 53 #include "ARMGenRegisterInfo.inc" 54 55 using namespace llvm; 56 57 ARMBaseRegisterInfo::ARMBaseRegisterInfo() 58 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {} 59 60 static unsigned getFramePointerReg(const ARMSubtarget &STI) { 61 return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11; 62 } 63 64 const MCPhysReg* 65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 66 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); 67 bool UseSplitPush = STI.splitFramePushPop(*MF); 68 const MCPhysReg *RegList = 69 STI.isTargetDarwin() 70 ? CSR_iOS_SaveList 71 : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList); 72 73 const Function &F = MF->getFunction(); 74 if (F.getCallingConv() == CallingConv::GHC) { 75 // GHC set of callee saved regs is empty as all those regs are 76 // used for passing STG regs around 77 return CSR_NoRegs_SaveList; 78 } else if (F.hasFnAttribute("interrupt")) { 79 if (STI.isMClass()) { 80 // M-class CPUs have hardware which saves the registers needed to allow a 81 // function conforming to the AAPCS to function as a handler. 82 return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList; 83 } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") { 84 // Fast interrupt mode gives the handler a private copy of R8-R14, so less 85 // need to be saved to restore user-mode state. 86 return CSR_FIQ_SaveList; 87 } else { 88 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 89 // exception handling. 90 return CSR_GenericInt_SaveList; 91 } 92 } 93 94 if (STI.getTargetLowering()->supportSwiftError() && 95 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) { 96 if (STI.isTargetDarwin()) 97 return CSR_iOS_SwiftError_SaveList; 98 99 return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : 100 CSR_AAPCS_SwiftError_SaveList; 101 } 102 103 if (STI.isTargetDarwin() && F.getCallingConv() == CallingConv::CXX_FAST_TLS) 104 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR() 105 ? CSR_iOS_CXX_TLS_PE_SaveList 106 : CSR_iOS_CXX_TLS_SaveList; 107 return RegList; 108 } 109 110 const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy( 111 const MachineFunction *MF) const { 112 assert(MF && "Invalid MachineFunction pointer."); 113 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 114 MF->getInfo<ARMFunctionInfo>()->isSplitCSR()) 115 return CSR_iOS_CXX_TLS_ViaCopy_SaveList; 116 return nullptr; 117 } 118 119 const uint32_t * 120 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 121 CallingConv::ID CC) const { 122 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 123 if (CC == CallingConv::GHC) 124 // This is academic because all GHC calls are (supposed to be) tail calls 125 return CSR_NoRegs_RegMask; 126 127 if (STI.getTargetLowering()->supportSwiftError() && 128 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 129 return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask 130 : CSR_AAPCS_SwiftError_RegMask; 131 132 if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS) 133 return CSR_iOS_CXX_TLS_RegMask; 134 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 135 } 136 137 const uint32_t* 138 ARMBaseRegisterInfo::getNoPreservedMask() const { 139 return CSR_NoRegs_RegMask; 140 } 141 142 const uint32_t * 143 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const { 144 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() && 145 "only know about special TLS call on Darwin"); 146 return CSR_iOS_TLSCall_RegMask; 147 } 148 149 const uint32_t * 150 ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const { 151 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 152 if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only()) 153 return CSR_NoRegs_RegMask; 154 else 155 return CSR_FPRegs_RegMask; 156 } 157 158 const uint32_t * 159 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 160 CallingConv::ID CC) const { 161 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 162 // This should return a register mask that is the same as that returned by 163 // getCallPreservedMask but that additionally preserves the register used for 164 // the first i32 argument (which must also be the register used to return a 165 // single i32 return value) 166 // 167 // In case that the calling convention does not use the same register for 168 // both or otherwise does not want to enable this optimization, the function 169 // should return NULL 170 if (CC == CallingConv::GHC) 171 // This is academic because all GHC calls are (supposed to be) tail calls 172 return nullptr; 173 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 174 : CSR_AAPCS_ThisReturn_RegMask; 175 } 176 177 BitVector ARMBaseRegisterInfo:: 178 getReservedRegs(const MachineFunction &MF) const { 179 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 180 const ARMFrameLowering *TFI = getFrameLowering(MF); 181 182 // FIXME: avoid re-calculating this every time. 183 BitVector Reserved(getNumRegs()); 184 markSuperRegs(Reserved, ARM::SP); 185 markSuperRegs(Reserved, ARM::PC); 186 markSuperRegs(Reserved, ARM::FPSCR); 187 markSuperRegs(Reserved, ARM::APSR_NZCV); 188 if (TFI->hasFP(MF)) 189 markSuperRegs(Reserved, getFramePointerReg(STI)); 190 if (hasBasePointer(MF)) 191 markSuperRegs(Reserved, BasePtr); 192 // Some targets reserve R9. 193 if (STI.isR9Reserved()) 194 markSuperRegs(Reserved, ARM::R9); 195 // Reserve D16-D31 if the subtarget doesn't support them. 196 if (!STI.hasD32()) { 197 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); 198 for (unsigned R = 0; R < 16; ++R) 199 markSuperRegs(Reserved, ARM::D16 + R); 200 } 201 const TargetRegisterClass &RC = ARM::GPRPairRegClass; 202 for (unsigned Reg : RC) 203 for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI) 204 if (Reserved.test(*SI)) 205 markSuperRegs(Reserved, Reg); 206 // For v8.1m architecture 207 markSuperRegs(Reserved, ARM::ZR); 208 209 assert(checkAllSuperRegsMarked(Reserved)); 210 return Reserved; 211 } 212 213 bool ARMBaseRegisterInfo:: 214 isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const { 215 return !getReservedRegs(MF).test(PhysReg); 216 } 217 218 const TargetRegisterClass * 219 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 220 const MachineFunction &) const { 221 const TargetRegisterClass *Super = RC; 222 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 223 do { 224 switch (Super->getID()) { 225 case ARM::GPRRegClassID: 226 case ARM::SPRRegClassID: 227 case ARM::DPRRegClassID: 228 case ARM::QPRRegClassID: 229 case ARM::QQPRRegClassID: 230 case ARM::QQQQPRRegClassID: 231 case ARM::GPRPairRegClassID: 232 return Super; 233 } 234 Super = *I++; 235 } while (Super); 236 return RC; 237 } 238 239 const TargetRegisterClass * 240 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 241 const { 242 return &ARM::GPRRegClass; 243 } 244 245 const TargetRegisterClass * 246 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 247 if (RC == &ARM::CCRRegClass) 248 return &ARM::rGPRRegClass; // Can't copy CCR registers. 249 return RC; 250 } 251 252 unsigned 253 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 254 MachineFunction &MF) const { 255 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 256 const ARMFrameLowering *TFI = getFrameLowering(MF); 257 258 switch (RC->getID()) { 259 default: 260 return 0; 261 case ARM::tGPRRegClassID: { 262 // hasFP ends up calling getMaxCallFrameComputed() which may not be 263 // available when getPressureLimit() is called as part of 264 // ScheduleDAGRRList. 265 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed() 266 ? TFI->hasFP(MF) : true; 267 return 5 - HasFP; 268 } 269 case ARM::GPRRegClassID: { 270 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed() 271 ? TFI->hasFP(MF) : true; 272 return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0); 273 } 274 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 275 case ARM::DPRRegClassID: 276 return 32 - 10; 277 } 278 } 279 280 // Get the other register in a GPRPair. 281 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 282 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 283 if (ARM::GPRPairRegClass.contains(*Supers)) 284 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 285 return 0; 286 } 287 288 // Resolve the RegPairEven / RegPairOdd register allocator hints. 289 bool 290 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 291 ArrayRef<MCPhysReg> Order, 292 SmallVectorImpl<MCPhysReg> &Hints, 293 const MachineFunction &MF, 294 const VirtRegMap *VRM, 295 const LiveRegMatrix *Matrix) const { 296 const MachineRegisterInfo &MRI = MF.getRegInfo(); 297 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 298 299 unsigned Odd; 300 switch (Hint.first) { 301 case ARMRI::RegPairEven: 302 Odd = 0; 303 break; 304 case ARMRI::RegPairOdd: 305 Odd = 1; 306 break; 307 default: 308 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 309 return false; 310 } 311 312 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 313 // Check if the other part of the pair has already been assigned, and provide 314 // the paired register as the first hint. 315 unsigned Paired = Hint.second; 316 if (Paired == 0) 317 return false; 318 319 unsigned PairedPhys = 0; 320 if (TargetRegisterInfo::isPhysicalRegister(Paired)) { 321 PairedPhys = Paired; 322 } else if (VRM && VRM->hasPhys(Paired)) { 323 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); 324 } 325 326 // First prefer the paired physreg. 327 if (PairedPhys && is_contained(Order, PairedPhys)) 328 Hints.push_back(PairedPhys); 329 330 // Then prefer even or odd registers. 331 for (unsigned Reg : Order) { 332 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 333 continue; 334 // Don't provide hints that are paired to a reserved register. 335 unsigned Paired = getPairedGPR(Reg, !Odd, this); 336 if (!Paired || MRI.isReserved(Paired)) 337 continue; 338 Hints.push_back(Reg); 339 } 340 return false; 341 } 342 343 void 344 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, 345 MachineFunction &MF) const { 346 MachineRegisterInfo *MRI = &MF.getRegInfo(); 347 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 348 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 349 Hint.first == (unsigned)ARMRI::RegPairEven) && 350 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 351 // If 'Reg' is one of the even / odd register pair and it's now changed 352 // (e.g. coalesced) into a different register. The other register of the 353 // pair allocation hint must be updated to reflect the relationship 354 // change. 355 unsigned OtherReg = Hint.second; 356 Hint = MRI->getRegAllocationHint(OtherReg); 357 // Make sure the pair has not already divorced. 358 if (Hint.second == Reg) { 359 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 360 if (TargetRegisterInfo::isVirtualRegister(NewReg)) 361 MRI->setRegAllocationHint(NewReg, 362 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven 363 : ARMRI::RegPairOdd, OtherReg); 364 } 365 } 366 } 367 368 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 369 const MachineFrameInfo &MFI = MF.getFrameInfo(); 370 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 371 const ARMFrameLowering *TFI = getFrameLowering(MF); 372 373 // If we have stack realignment and VLAs, we have no pointer to use to 374 // access the stack. If we have stack realignment, and a large call frame, 375 // we have no place to allocate the emergency spill slot. 376 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 377 return true; 378 379 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 380 // negative range for ldr/str (255), and thumb1 is positive offsets only. 381 // 382 // It's going to be better to use the SP or Base Pointer instead. When there 383 // are variable sized objects, we can't reference off of the SP, so we 384 // reserve a Base Pointer. 385 // 386 // For Thumb2, estimate whether a negative offset from the frame pointer 387 // will be sufficient to reach the whole stack frame. If a function has a 388 // smallish frame, it's less likely to have lots of spills and callee saved 389 // space, so it's all more likely to be within range of the frame pointer. 390 // If it's wrong, the scavenger will still enable access to work, it just 391 // won't be optimal. (We should always be able to reach the emergency 392 // spill slot from the frame pointer.) 393 if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() && 394 MFI.getLocalFrameSize() >= 128) 395 return true; 396 // For Thumb1, if sp moves, nothing is in range, so force a base pointer. 397 // This is necessary for correctness in cases where we need an emergency 398 // spill slot. (In Thumb1, we can't use a negative offset from the frame 399 // pointer.) 400 if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF)) 401 return true; 402 return false; 403 } 404 405 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 406 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 407 const ARMFrameLowering *TFI = getFrameLowering(MF); 408 // We can't realign the stack if: 409 // 1. Dynamic stack realignment is explicitly disabled, 410 // 2. There are VLAs in the function and the base pointer is disabled. 411 if (!TargetRegisterInfo::canRealignStack(MF)) 412 return false; 413 // Stack realignment requires a frame pointer. If we already started 414 // register allocation with frame pointer elimination, it is too late now. 415 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>()))) 416 return false; 417 // We may also need a base pointer if there are dynamic allocas or stack 418 // pointer adjustments around calls. 419 if (TFI->hasReservedCallFrame(MF)) 420 return true; 421 // A base pointer is required and allowed. Check that it isn't too late to 422 // reserve it. 423 return MRI->canReserveReg(BasePtr); 424 } 425 426 bool ARMBaseRegisterInfo:: 427 cannotEliminateFrame(const MachineFunction &MF) const { 428 const MachineFrameInfo &MFI = MF.getFrameInfo(); 429 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack()) 430 return true; 431 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() 432 || needsStackRealignment(MF); 433 } 434 435 Register 436 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 437 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 438 const ARMFrameLowering *TFI = getFrameLowering(MF); 439 440 if (TFI->hasFP(MF)) 441 return getFramePointerReg(STI); 442 return ARM::SP; 443 } 444 445 /// emitLoadConstPool - Emits a load from constpool to materialize the 446 /// specified immediate. 447 void ARMBaseRegisterInfo::emitLoadConstPool( 448 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 449 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, 450 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { 451 MachineFunction &MF = *MBB.getParent(); 452 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 453 MachineConstantPool *ConstantPool = MF.getConstantPool(); 454 const Constant *C = 455 ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val); 456 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 457 458 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 459 .addReg(DestReg, getDefRegState(true), SubIdx) 460 .addConstantPoolIndex(Idx) 461 .addImm(0) 462 .add(predOps(Pred, PredReg)) 463 .setMIFlags(MIFlags); 464 } 465 466 bool ARMBaseRegisterInfo:: 467 requiresRegisterScavenging(const MachineFunction &MF) const { 468 return true; 469 } 470 471 bool ARMBaseRegisterInfo:: 472 trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 473 return true; 474 } 475 476 bool ARMBaseRegisterInfo:: 477 requiresFrameIndexScavenging(const MachineFunction &MF) const { 478 return true; 479 } 480 481 bool ARMBaseRegisterInfo:: 482 requiresVirtualBaseRegisters(const MachineFunction &MF) const { 483 return true; 484 } 485 486 int64_t ARMBaseRegisterInfo:: 487 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 488 const MCInstrDesc &Desc = MI->getDesc(); 489 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 490 int64_t InstrOffs = 0; 491 int Scale = 1; 492 unsigned ImmIdx = 0; 493 switch (AddrMode) { 494 case ARMII::AddrModeT2_i8: 495 case ARMII::AddrModeT2_i12: 496 case ARMII::AddrMode_i12: 497 InstrOffs = MI->getOperand(Idx+1).getImm(); 498 Scale = 1; 499 break; 500 case ARMII::AddrMode5: { 501 // VFP address mode. 502 const MachineOperand &OffOp = MI->getOperand(Idx+1); 503 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 504 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 505 InstrOffs = -InstrOffs; 506 Scale = 4; 507 break; 508 } 509 case ARMII::AddrMode2: 510 ImmIdx = Idx+2; 511 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 512 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 513 InstrOffs = -InstrOffs; 514 break; 515 case ARMII::AddrMode3: 516 ImmIdx = Idx+2; 517 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 518 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 519 InstrOffs = -InstrOffs; 520 break; 521 case ARMII::AddrModeT1_s: 522 ImmIdx = Idx+1; 523 InstrOffs = MI->getOperand(ImmIdx).getImm(); 524 Scale = 4; 525 break; 526 default: 527 llvm_unreachable("Unsupported addressing mode!"); 528 } 529 530 return InstrOffs * Scale; 531 } 532 533 /// needsFrameBaseReg - Returns true if the instruction's frame index 534 /// reference would be better served by a base register other than FP 535 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 536 /// references it should create new base registers for. 537 bool ARMBaseRegisterInfo:: 538 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 539 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 540 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 541 } 542 543 // It's the load/store FI references that cause issues, as it can be difficult 544 // to materialize the offset if it won't fit in the literal field. Estimate 545 // based on the size of the local frame and some conservative assumptions 546 // about the rest of the stack frame (note, this is pre-regalloc, so 547 // we don't know everything for certain yet) whether this offset is likely 548 // to be out of range of the immediate. Return true if so. 549 550 // We only generate virtual base registers for loads and stores, so 551 // return false for everything else. 552 unsigned Opc = MI->getOpcode(); 553 switch (Opc) { 554 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 555 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 556 case ARM::t2LDRi12: case ARM::t2LDRi8: 557 case ARM::t2STRi12: case ARM::t2STRi8: 558 case ARM::VLDRS: case ARM::VLDRD: 559 case ARM::VSTRS: case ARM::VSTRD: 560 case ARM::tSTRspi: case ARM::tLDRspi: 561 break; 562 default: 563 return false; 564 } 565 566 // Without a virtual base register, if the function has variable sized 567 // objects, all fixed-size local references will be via the frame pointer, 568 // Approximate the offset and see if it's legal for the instruction. 569 // Note that the incoming offset is based on the SP value at function entry, 570 // so it'll be negative. 571 MachineFunction &MF = *MI->getParent()->getParent(); 572 const ARMFrameLowering *TFI = getFrameLowering(MF); 573 MachineFrameInfo &MFI = MF.getFrameInfo(); 574 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 575 576 // Estimate an offset from the frame pointer. 577 // Conservatively assume all callee-saved registers get pushed. R4-R6 578 // will be earlier than the FP, so we ignore those. 579 // R7, LR 580 int64_t FPOffset = Offset - 8; 581 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 582 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 583 FPOffset -= 80; 584 // Estimate an offset from the stack pointer. 585 // The incoming offset is relating to the SP at the start of the function, 586 // but when we access the local it'll be relative to the SP after local 587 // allocation, so adjust our SP-relative offset by that allocation size. 588 Offset += MFI.getLocalFrameSize(); 589 // Assume that we'll have at least some spill slots allocated. 590 // FIXME: This is a total SWAG number. We should run some statistics 591 // and pick a real one. 592 Offset += 128; // 128 bytes of spill slots 593 594 // If there's a frame pointer and the addressing mode allows it, try using it. 595 // The FP is only available if there is no dynamic realignment. We 596 // don't know for sure yet whether we'll need that, so we guess based 597 // on whether there are any local variables that would trigger it. 598 unsigned StackAlign = TFI->getStackAlignment(); 599 if (TFI->hasFP(MF) && 600 !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 601 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset)) 602 return false; 603 } 604 // If we can reference via the stack pointer, try that. 605 // FIXME: This (and the code that resolves the references) can be improved 606 // to only disallow SP relative references in the live range of 607 // the VLA(s). In practice, it's unclear how much difference that 608 // would make, but it may be worth doing. 609 if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset)) 610 return false; 611 612 // The offset likely isn't legal, we want to allocate a virtual base register. 613 return true; 614 } 615 616 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 617 /// be a pointer to FrameIdx at the beginning of the basic block. 618 void ARMBaseRegisterInfo:: 619 materializeFrameBaseRegister(MachineBasicBlock *MBB, 620 unsigned BaseReg, int FrameIdx, 621 int64_t Offset) const { 622 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 623 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 624 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 625 626 MachineBasicBlock::iterator Ins = MBB->begin(); 627 DebugLoc DL; // Defaults to "unknown" 628 if (Ins != MBB->end()) 629 DL = Ins->getDebugLoc(); 630 631 const MachineFunction &MF = *MBB->getParent(); 632 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 633 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 634 const MCInstrDesc &MCID = TII.get(ADDriOpc); 635 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 636 637 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 638 .addFrameIndex(FrameIdx).addImm(Offset); 639 640 if (!AFI->isThumb1OnlyFunction()) 641 MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); 642 } 643 644 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 645 int64_t Offset) const { 646 MachineBasicBlock &MBB = *MI.getParent(); 647 MachineFunction &MF = *MBB.getParent(); 648 const ARMBaseInstrInfo &TII = 649 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 650 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 651 int Off = Offset; // ARM doesn't need the general 64-bit offsets 652 unsigned i = 0; 653 654 assert(!AFI->isThumb1OnlyFunction() && 655 "This resolveFrameIndex does not support Thumb1!"); 656 657 while (!MI.getOperand(i).isFI()) { 658 ++i; 659 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 660 } 661 bool Done = false; 662 if (!AFI->isThumbFunction()) 663 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 664 else { 665 assert(AFI->isThumb2Function()); 666 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 667 } 668 assert(Done && "Unable to resolve frame index!"); 669 (void)Done; 670 } 671 672 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 673 int64_t Offset) const { 674 const MCInstrDesc &Desc = MI->getDesc(); 675 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 676 unsigned i = 0; 677 for (; !MI->getOperand(i).isFI(); ++i) 678 assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!"); 679 680 // AddrMode4 and AddrMode6 cannot handle any offset. 681 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 682 return Offset == 0; 683 684 unsigned NumBits = 0; 685 unsigned Scale = 1; 686 bool isSigned = true; 687 switch (AddrMode) { 688 case ARMII::AddrModeT2_i8: 689 case ARMII::AddrModeT2_i12: 690 // i8 supports only negative, and i12 supports only positive, so 691 // based on Offset sign, consider the appropriate instruction 692 Scale = 1; 693 if (Offset < 0) { 694 NumBits = 8; 695 Offset = -Offset; 696 } else { 697 NumBits = 12; 698 } 699 break; 700 case ARMII::AddrMode5: 701 // VFP address mode. 702 NumBits = 8; 703 Scale = 4; 704 break; 705 case ARMII::AddrMode_i12: 706 case ARMII::AddrMode2: 707 NumBits = 12; 708 break; 709 case ARMII::AddrMode3: 710 NumBits = 8; 711 break; 712 case ARMII::AddrModeT1_s: 713 NumBits = (BaseReg == ARM::SP ? 8 : 5); 714 Scale = 4; 715 isSigned = false; 716 break; 717 default: 718 llvm_unreachable("Unsupported addressing mode!"); 719 } 720 721 Offset += getFrameIndexInstrOffset(MI, i); 722 // Make sure the offset is encodable for instructions that scale the 723 // immediate. 724 if ((Offset & (Scale-1)) != 0) 725 return false; 726 727 if (isSigned && Offset < 0) 728 Offset = -Offset; 729 730 unsigned Mask = (1 << NumBits) - 1; 731 if ((unsigned)Offset <= Mask * Scale) 732 return true; 733 734 return false; 735 } 736 737 void 738 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 739 int SPAdj, unsigned FIOperandNum, 740 RegScavenger *RS) const { 741 MachineInstr &MI = *II; 742 MachineBasicBlock &MBB = *MI.getParent(); 743 MachineFunction &MF = *MBB.getParent(); 744 const ARMBaseInstrInfo &TII = 745 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 746 const ARMFrameLowering *TFI = getFrameLowering(MF); 747 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 748 assert(!AFI->isThumb1OnlyFunction() && 749 "This eliminateFrameIndex does not support Thumb1!"); 750 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 751 unsigned FrameReg; 752 753 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 754 755 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 756 // call frame setup/destroy instructions have already been eliminated. That 757 // means the stack pointer cannot be used to access the emergency spill slot 758 // when !hasReservedCallFrame(). 759 #ifndef NDEBUG 760 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 761 assert(TFI->hasReservedCallFrame(MF) && 762 "Cannot use SP to access the emergency spill slot in " 763 "functions without a reserved call frame"); 764 assert(!MF.getFrameInfo().hasVarSizedObjects() && 765 "Cannot use SP to access the emergency spill slot in " 766 "functions with variable sized frame objects"); 767 } 768 #endif // NDEBUG 769 770 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 771 772 // Modify MI as necessary to handle as much of 'Offset' as possible 773 bool Done = false; 774 if (!AFI->isThumbFunction()) 775 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 776 else { 777 assert(AFI->isThumb2Function()); 778 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 779 } 780 if (Done) 781 return; 782 783 // If we get here, the immediate doesn't fit into the instruction. We folded 784 // as much as possible above, handle the rest, providing a register that is 785 // SP+LargeImm. 786 assert((Offset || 787 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 788 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 789 "This code isn't needed if offset already handled!"); 790 791 unsigned ScratchReg = 0; 792 int PIdx = MI.findFirstPredOperandIdx(); 793 ARMCC::CondCodes Pred = (PIdx == -1) 794 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 795 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); 796 if (Offset == 0) 797 // Must be addrmode4/6. 798 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 799 else { 800 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 801 if (!AFI->isThumbFunction()) 802 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 803 Offset, Pred, PredReg, TII); 804 else { 805 assert(AFI->isThumb2Function()); 806 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 807 Offset, Pred, PredReg, TII); 808 } 809 // Update the original instruction to use the scratch register. 810 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 811 } 812 } 813 814 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 815 const TargetRegisterClass *SrcRC, 816 unsigned SubReg, 817 const TargetRegisterClass *DstRC, 818 unsigned DstSubReg, 819 const TargetRegisterClass *NewRC, 820 LiveIntervals &LIS) const { 821 auto MBB = MI->getParent(); 822 auto MF = MBB->getParent(); 823 const MachineRegisterInfo &MRI = MF->getRegInfo(); 824 // If not copying into a sub-register this should be ok because we shouldn't 825 // need to split the reg. 826 if (!DstSubReg) 827 return true; 828 // Small registers don't frequently cause a problem, so we can coalesce them. 829 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && 830 getRegSizeInBits(*SrcRC) < 256) 831 return true; 832 833 auto NewRCWeight = 834 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 835 auto SrcRCWeight = 836 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 837 auto DstRCWeight = 838 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 839 // If the source register class is more expensive than the destination, the 840 // coalescing is probably profitable. 841 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 842 return true; 843 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 844 return true; 845 846 // If the register allocator isn't constrained, we can always allow coalescing 847 // unfortunately we don't know yet if we will be constrained. 848 // The goal of this heuristic is to restrict how many expensive registers 849 // we allow to coalesce in a given basic block. 850 auto AFI = MF->getInfo<ARMFunctionInfo>(); 851 auto It = AFI->getCoalescedWeight(MBB); 852 853 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 854 << It->second << "\n"); 855 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 856 << NewRCWeight.RegWeight << "\n"); 857 858 // This number is the largest round number that which meets the criteria: 859 // (1) addresses PR18825 860 // (2) generates better code in some test cases (like vldm-shed-a9.ll) 861 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 862 // In practice the SizeMultiplier will only factor in for straight line code 863 // that uses a lot of NEON vectors, which isn't terribly common. 864 unsigned SizeMultiplier = MBB->size()/100; 865 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 866 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 867 It->second += NewRCWeight.RegWeight; 868 return true; 869 } 870 return false; 871 } 872