1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMFeatures.h" 10 #include "ARMBaseInstrInfo.h" 11 #include "Utils/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMBaseInfo.h" 14 #include "MCTargetDesc/ARMInstPrinter.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMMCTargetDesc.h" 17 #include "TargetInfo/ARMTargetInfo.h" 18 #include "llvm/ADT/APFloat.h" 19 #include "llvm/ADT/APInt.h" 20 #include "llvm/ADT/None.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/SmallSet.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/ADT/StringMap.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInst.h" 32 #include "llvm/MC/MCInstrDesc.h" 33 #include "llvm/MC/MCInstrInfo.h" 34 #include "llvm/MC/MCObjectFileInfo.h" 35 #include "llvm/MC/MCParser/MCAsmLexer.h" 36 #include "llvm/MC/MCParser/MCAsmParser.h" 37 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 38 #include "llvm/MC/MCParser/MCAsmParserUtils.h" 39 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 40 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 41 #include "llvm/MC/MCRegisterInfo.h" 42 #include "llvm/MC/MCSection.h" 43 #include "llvm/MC/MCStreamer.h" 44 #include "llvm/MC/MCSubtargetInfo.h" 45 #include "llvm/MC/MCSymbol.h" 46 #include "llvm/MC/SubtargetFeature.h" 47 #include "llvm/Support/ARMBuildAttributes.h" 48 #include "llvm/Support/ARMEHABI.h" 49 #include "llvm/Support/Casting.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/Compiler.h" 52 #include "llvm/Support/ErrorHandling.h" 53 #include "llvm/Support/MathExtras.h" 54 #include "llvm/Support/SMLoc.h" 55 #include "llvm/Support/TargetParser.h" 56 #include "llvm/Support/TargetRegistry.h" 57 #include "llvm/Support/raw_ostream.h" 58 #include <algorithm> 59 #include <cassert> 60 #include <cstddef> 61 #include <cstdint> 62 #include <iterator> 63 #include <limits> 64 #include <memory> 65 #include <string> 66 #include <utility> 67 #include <vector> 68 69 #define DEBUG_TYPE "asm-parser" 70 71 using namespace llvm; 72 73 namespace llvm { 74 extern const MCInstrDesc ARMInsts[]; 75 } // end namespace llvm 76 77 namespace { 78 79 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly }; 80 81 static cl::opt<ImplicitItModeTy> ImplicitItMode( 82 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), 83 cl::desc("Allow conditional instructions outdside of an IT block"), 84 cl::values(clEnumValN(ImplicitItModeTy::Always, "always", 85 "Accept in both ISAs, emit implicit ITs in Thumb"), 86 clEnumValN(ImplicitItModeTy::Never, "never", 87 "Warn in ARM, reject in Thumb"), 88 clEnumValN(ImplicitItModeTy::ARMOnly, "arm", 89 "Accept in ARM, reject in Thumb"), 90 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb", 91 "Warn in ARM, emit implicit ITs in Thumb"))); 92 93 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes", 94 cl::init(false)); 95 96 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 97 98 static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { 99 // Position==0 means we're not in an IT block at all. Position==1 100 // means we want the first state bit, which is always 0 (Then). 101 // Position==2 means we want the second state bit, stored at bit 3 102 // of Mask, and so on downwards. So (5 - Position) will shift the 103 // right bit down to bit 0, including the always-0 bit at bit 4 for 104 // the mandatory initial Then. 105 return (Mask >> (5 - Position) & 1); 106 } 107 108 class UnwindContext { 109 using Locs = SmallVector<SMLoc, 4>; 110 111 MCAsmParser &Parser; 112 Locs FnStartLocs; 113 Locs CantUnwindLocs; 114 Locs PersonalityLocs; 115 Locs PersonalityIndexLocs; 116 Locs HandlerDataLocs; 117 int FPReg; 118 119 public: 120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 121 122 bool hasFnStart() const { return !FnStartLocs.empty(); } 123 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 124 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 125 126 bool hasPersonality() const { 127 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 128 } 129 130 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 131 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 132 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 133 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 134 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 135 136 void saveFPReg(int Reg) { FPReg = Reg; } 137 int getFPReg() const { return FPReg; } 138 139 void emitFnStartLocNotes() const { 140 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 141 FI != FE; ++FI) 142 Parser.Note(*FI, ".fnstart was specified here"); 143 } 144 145 void emitCantUnwindLocNotes() const { 146 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 147 UE = CantUnwindLocs.end(); UI != UE; ++UI) 148 Parser.Note(*UI, ".cantunwind was specified here"); 149 } 150 151 void emitHandlerDataLocNotes() const { 152 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 153 HE = HandlerDataLocs.end(); HI != HE; ++HI) 154 Parser.Note(*HI, ".handlerdata was specified here"); 155 } 156 157 void emitPersonalityLocNotes() const { 158 for (Locs::const_iterator PI = PersonalityLocs.begin(), 159 PE = PersonalityLocs.end(), 160 PII = PersonalityIndexLocs.begin(), 161 PIE = PersonalityIndexLocs.end(); 162 PI != PE || PII != PIE;) { 163 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 164 Parser.Note(*PI++, ".personality was specified here"); 165 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 166 Parser.Note(*PII++, ".personalityindex was specified here"); 167 else 168 llvm_unreachable(".personality and .personalityindex cannot be " 169 "at the same location"); 170 } 171 } 172 173 void reset() { 174 FnStartLocs = Locs(); 175 CantUnwindLocs = Locs(); 176 PersonalityLocs = Locs(); 177 HandlerDataLocs = Locs(); 178 PersonalityIndexLocs = Locs(); 179 FPReg = ARM::SP; 180 } 181 }; 182 183 184 class ARMAsmParser : public MCTargetAsmParser { 185 const MCRegisterInfo *MRI; 186 UnwindContext UC; 187 188 ARMTargetStreamer &getTargetStreamer() { 189 assert(getParser().getStreamer().getTargetStreamer() && 190 "do not have a target streamer"); 191 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 192 return static_cast<ARMTargetStreamer &>(TS); 193 } 194 195 // Map of register aliases registers via the .req directive. 196 StringMap<unsigned> RegisterReqs; 197 198 bool NextSymbolIsThumb; 199 200 bool useImplicitITThumb() const { 201 return ImplicitItMode == ImplicitItModeTy::Always || 202 ImplicitItMode == ImplicitItModeTy::ThumbOnly; 203 } 204 205 bool useImplicitITARM() const { 206 return ImplicitItMode == ImplicitItModeTy::Always || 207 ImplicitItMode == ImplicitItModeTy::ARMOnly; 208 } 209 210 struct { 211 ARMCC::CondCodes Cond; // Condition for IT block. 212 unsigned Mask:4; // Condition mask for instructions. 213 // Starting at first 1 (from lsb). 214 // '1' condition as indicated in IT. 215 // '0' inverse of condition (else). 216 // Count of instructions in IT block is 217 // 4 - trailingzeroes(mask) 218 // Note that this does not have the same encoding 219 // as in the IT instruction, which also depends 220 // on the low bit of the condition code. 221 222 unsigned CurPosition; // Current position in parsing of IT 223 // block. In range [0,4], with 0 being the IT 224 // instruction itself. Initialized according to 225 // count of instructions in block. ~0U if no 226 // active IT block. 227 228 bool IsExplicit; // true - The IT instruction was present in the 229 // input, we should not modify it. 230 // false - The IT instruction was added 231 // implicitly, we can extend it if that 232 // would be legal. 233 } ITState; 234 235 SmallVector<MCInst, 4> PendingConditionalInsts; 236 237 void flushPendingInstructions(MCStreamer &Out) override { 238 if (!inImplicitITBlock()) { 239 assert(PendingConditionalInsts.size() == 0); 240 return; 241 } 242 243 // Emit the IT instruction 244 MCInst ITInst; 245 ITInst.setOpcode(ARM::t2IT); 246 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); 247 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); 248 Out.EmitInstruction(ITInst, getSTI()); 249 250 // Emit the conditonal instructions 251 assert(PendingConditionalInsts.size() <= 4); 252 for (const MCInst &Inst : PendingConditionalInsts) { 253 Out.EmitInstruction(Inst, getSTI()); 254 } 255 PendingConditionalInsts.clear(); 256 257 // Clear the IT state 258 ITState.Mask = 0; 259 ITState.CurPosition = ~0U; 260 } 261 262 bool inITBlock() { return ITState.CurPosition != ~0U; } 263 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; } 264 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; } 265 266 bool lastInITBlock() { 267 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); 268 } 269 270 void forwardITPosition() { 271 if (!inITBlock()) return; 272 // Move to the next instruction in the IT block, if there is one. If not, 273 // mark the block as done, except for implicit IT blocks, which we leave 274 // open until we find an instruction that can't be added to it. 275 unsigned TZ = countTrailingZeros(ITState.Mask); 276 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit) 277 ITState.CurPosition = ~0U; // Done with the IT block after this. 278 } 279 280 // Rewind the state of the current IT block, removing the last slot from it. 281 void rewindImplicitITPosition() { 282 assert(inImplicitITBlock()); 283 assert(ITState.CurPosition > 1); 284 ITState.CurPosition--; 285 unsigned TZ = countTrailingZeros(ITState.Mask); 286 unsigned NewMask = 0; 287 NewMask |= ITState.Mask & (0xC << TZ); 288 NewMask |= 0x2 << TZ; 289 ITState.Mask = NewMask; 290 } 291 292 // Rewind the state of the current IT block, removing the last slot from it. 293 // If we were at the first slot, this closes the IT block. 294 void discardImplicitITBlock() { 295 assert(inImplicitITBlock()); 296 assert(ITState.CurPosition == 1); 297 ITState.CurPosition = ~0U; 298 } 299 300 // Return the low-subreg of a given Q register. 301 unsigned getDRegFromQReg(unsigned QReg) const { 302 return MRI->getSubReg(QReg, ARM::dsub_0); 303 } 304 305 // Get the condition code corresponding to the current IT block slot. 306 ARMCC::CondCodes currentITCond() { 307 unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition); 308 return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond; 309 } 310 311 // Invert the condition of the current IT block slot without changing any 312 // other slots in the same block. 313 void invertCurrentITCondition() { 314 if (ITState.CurPosition == 1) { 315 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond); 316 } else { 317 ITState.Mask ^= 1 << (5 - ITState.CurPosition); 318 } 319 } 320 321 // Returns true if the current IT block is full (all 4 slots used). 322 bool isITBlockFull() { 323 return inITBlock() && (ITState.Mask & 1); 324 } 325 326 // Extend the current implicit IT block to have one more slot with the given 327 // condition code. 328 void extendImplicitITBlock(ARMCC::CondCodes Cond) { 329 assert(inImplicitITBlock()); 330 assert(!isITBlockFull()); 331 assert(Cond == ITState.Cond || 332 Cond == ARMCC::getOppositeCondition(ITState.Cond)); 333 unsigned TZ = countTrailingZeros(ITState.Mask); 334 unsigned NewMask = 0; 335 // Keep any existing condition bits. 336 NewMask |= ITState.Mask & (0xE << TZ); 337 // Insert the new condition bit. 338 NewMask |= (Cond != ITState.Cond) << TZ; 339 // Move the trailing 1 down one bit. 340 NewMask |= 1 << (TZ - 1); 341 ITState.Mask = NewMask; 342 } 343 344 // Create a new implicit IT block with a dummy condition code. 345 void startImplicitITBlock() { 346 assert(!inITBlock()); 347 ITState.Cond = ARMCC::AL; 348 ITState.Mask = 8; 349 ITState.CurPosition = 1; 350 ITState.IsExplicit = false; 351 } 352 353 // Create a new explicit IT block with the given condition and mask. 354 // The mask should be in the format used in ARMOperand and 355 // MCOperand, with a 1 implying 'e', regardless of the low bit of 356 // the condition. 357 void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) { 358 assert(!inITBlock()); 359 ITState.Cond = Cond; 360 ITState.Mask = Mask; 361 ITState.CurPosition = 0; 362 ITState.IsExplicit = true; 363 } 364 365 struct { 366 unsigned Mask : 4; 367 unsigned CurPosition; 368 } VPTState; 369 bool inVPTBlock() { return VPTState.CurPosition != ~0U; } 370 void forwardVPTPosition() { 371 if (!inVPTBlock()) return; 372 unsigned TZ = countTrailingZeros(VPTState.Mask); 373 if (++VPTState.CurPosition == 5 - TZ) 374 VPTState.CurPosition = ~0U; 375 } 376 377 void Note(SMLoc L, const Twine &Msg, SMRange Range = None) { 378 return getParser().Note(L, Msg, Range); 379 } 380 381 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) { 382 return getParser().Warning(L, Msg, Range); 383 } 384 385 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) { 386 return getParser().Error(L, Msg, Range); 387 } 388 389 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, 390 unsigned ListNo, bool IsARPop = false); 391 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, 392 unsigned ListNo); 393 394 int tryParseRegister(); 395 bool tryParseRegisterWithWriteBack(OperandVector &); 396 int tryParseShiftRegister(OperandVector &); 397 bool parseRegisterList(OperandVector &, bool EnforceOrder = true); 398 bool parseMemory(OperandVector &); 399 bool parseOperand(OperandVector &, StringRef Mnemonic); 400 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 401 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 402 unsigned &ShiftAmount); 403 bool parseLiteralValues(unsigned Size, SMLoc L); 404 bool parseDirectiveThumb(SMLoc L); 405 bool parseDirectiveARM(SMLoc L); 406 bool parseDirectiveThumbFunc(SMLoc L); 407 bool parseDirectiveCode(SMLoc L); 408 bool parseDirectiveSyntax(SMLoc L); 409 bool parseDirectiveReq(StringRef Name, SMLoc L); 410 bool parseDirectiveUnreq(SMLoc L); 411 bool parseDirectiveArch(SMLoc L); 412 bool parseDirectiveEabiAttr(SMLoc L); 413 bool parseDirectiveCPU(SMLoc L); 414 bool parseDirectiveFPU(SMLoc L); 415 bool parseDirectiveFnStart(SMLoc L); 416 bool parseDirectiveFnEnd(SMLoc L); 417 bool parseDirectiveCantUnwind(SMLoc L); 418 bool parseDirectivePersonality(SMLoc L); 419 bool parseDirectiveHandlerData(SMLoc L); 420 bool parseDirectiveSetFP(SMLoc L); 421 bool parseDirectivePad(SMLoc L); 422 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 423 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 424 bool parseDirectiveLtorg(SMLoc L); 425 bool parseDirectiveEven(SMLoc L); 426 bool parseDirectivePersonalityIndex(SMLoc L); 427 bool parseDirectiveUnwindRaw(SMLoc L); 428 bool parseDirectiveTLSDescSeq(SMLoc L); 429 bool parseDirectiveMovSP(SMLoc L); 430 bool parseDirectiveObjectArch(SMLoc L); 431 bool parseDirectiveArchExtension(SMLoc L); 432 bool parseDirectiveAlign(SMLoc L); 433 bool parseDirectiveThumbSet(SMLoc L); 434 435 bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken); 436 StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken, 437 unsigned &PredicationCode, 438 unsigned &VPTPredicationCode, bool &CarrySetting, 439 unsigned &ProcessorIMod, StringRef &ITMask); 440 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken, 441 StringRef FullInst, bool &CanAcceptCarrySet, 442 bool &CanAcceptPredicationCode, 443 bool &CanAcceptVPTPredicationCode); 444 445 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, 446 OperandVector &Operands); 447 bool isThumb() const { 448 // FIXME: Can tablegen auto-generate this? 449 return getSTI().getFeatureBits()[ARM::ModeThumb]; 450 } 451 452 bool isThumbOne() const { 453 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; 454 } 455 456 bool isThumbTwo() const { 457 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; 458 } 459 460 bool hasThumb() const { 461 return getSTI().getFeatureBits()[ARM::HasV4TOps]; 462 } 463 464 bool hasThumb2() const { 465 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; 466 } 467 468 bool hasV6Ops() const { 469 return getSTI().getFeatureBits()[ARM::HasV6Ops]; 470 } 471 472 bool hasV6T2Ops() const { 473 return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; 474 } 475 476 bool hasV6MOps() const { 477 return getSTI().getFeatureBits()[ARM::HasV6MOps]; 478 } 479 480 bool hasV7Ops() const { 481 return getSTI().getFeatureBits()[ARM::HasV7Ops]; 482 } 483 484 bool hasV8Ops() const { 485 return getSTI().getFeatureBits()[ARM::HasV8Ops]; 486 } 487 488 bool hasV8MBaseline() const { 489 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; 490 } 491 492 bool hasV8MMainline() const { 493 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; 494 } 495 bool hasV8_1MMainline() const { 496 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps]; 497 } 498 bool hasMVE() const { 499 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps]; 500 } 501 bool hasMVEFloat() const { 502 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps]; 503 } 504 bool has8MSecExt() const { 505 return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; 506 } 507 508 bool hasARM() const { 509 return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; 510 } 511 512 bool hasDSP() const { 513 return getSTI().getFeatureBits()[ARM::FeatureDSP]; 514 } 515 516 bool hasD32() const { 517 return getSTI().getFeatureBits()[ARM::FeatureD32]; 518 } 519 520 bool hasV8_1aOps() const { 521 return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; 522 } 523 524 bool hasRAS() const { 525 return getSTI().getFeatureBits()[ARM::FeatureRAS]; 526 } 527 528 void SwitchMode() { 529 MCSubtargetInfo &STI = copySTI(); 530 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 531 setAvailableFeatures(FB); 532 } 533 534 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc); 535 536 bool isMClass() const { 537 return getSTI().getFeatureBits()[ARM::FeatureMClass]; 538 } 539 540 /// @name Auto-generated Match Functions 541 /// { 542 543 #define GET_ASSEMBLER_HEADER 544 #include "ARMGenAsmMatcher.inc" 545 546 /// } 547 548 OperandMatchResultTy parseITCondCode(OperandVector &); 549 OperandMatchResultTy parseCoprocNumOperand(OperandVector &); 550 OperandMatchResultTy parseCoprocRegOperand(OperandVector &); 551 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); 552 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); 553 OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &); 554 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); 555 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); 556 OperandMatchResultTy parseMSRMaskOperand(OperandVector &); 557 OperandMatchResultTy parseBankedRegOperand(OperandVector &); 558 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, 559 int High); 560 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { 561 return parsePKHImm(O, "lsl", 0, 31); 562 } 563 OperandMatchResultTy parsePKHASRImm(OperandVector &O) { 564 return parsePKHImm(O, "asr", 1, 32); 565 } 566 OperandMatchResultTy parseSetEndImm(OperandVector &); 567 OperandMatchResultTy parseShifterImm(OperandVector &); 568 OperandMatchResultTy parseRotImm(OperandVector &); 569 OperandMatchResultTy parseModImm(OperandVector &); 570 OperandMatchResultTy parseBitfield(OperandVector &); 571 OperandMatchResultTy parsePostIdxReg(OperandVector &); 572 OperandMatchResultTy parseAM3Offset(OperandVector &); 573 OperandMatchResultTy parseFPImm(OperandVector &); 574 OperandMatchResultTy parseVectorList(OperandVector &); 575 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 576 SMLoc &EndLoc); 577 578 // Asm Match Converter Methods 579 void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 580 void cvtThumbBranches(MCInst &Inst, const OperandVector &); 581 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &); 582 583 bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 584 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); 585 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); 586 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 587 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 588 bool isITBlockTerminator(MCInst &Inst) const; 589 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands); 590 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, 591 bool Load, bool ARMMode, bool Writeback); 592 593 public: 594 enum ARMMatchResultTy { 595 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 596 Match_RequiresNotITBlock, 597 Match_RequiresV6, 598 Match_RequiresThumb2, 599 Match_RequiresV8, 600 Match_RequiresFlagSetting, 601 #define GET_OPERAND_DIAGNOSTIC_TYPES 602 #include "ARMGenAsmMatcher.inc" 603 604 }; 605 606 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, 607 const MCInstrInfo &MII, const MCTargetOptions &Options) 608 : MCTargetAsmParser(Options, STI, MII), UC(Parser) { 609 MCAsmParserExtension::Initialize(Parser); 610 611 // Cache the MCRegisterInfo. 612 MRI = getContext().getRegisterInfo(); 613 614 // Initialize the set of available features. 615 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 616 617 // Add build attributes based on the selected target. 618 if (AddBuildAttributes) 619 getTargetStreamer().emitTargetAttributes(STI); 620 621 // Not in an ITBlock to start with. 622 ITState.CurPosition = ~0U; 623 624 VPTState.CurPosition = ~0U; 625 626 NextSymbolIsThumb = false; 627 } 628 629 // Implementation of the MCTargetAsmParser interface: 630 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 631 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 632 SMLoc NameLoc, OperandVector &Operands) override; 633 bool ParseDirective(AsmToken DirectiveID) override; 634 635 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 636 unsigned Kind) override; 637 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 638 639 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 640 OperandVector &Operands, MCStreamer &Out, 641 uint64_t &ErrorInfo, 642 bool MatchingInlineAsm) override; 643 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst, 644 SmallVectorImpl<NearMissInfo> &NearMisses, 645 bool MatchingInlineAsm, bool &EmitInITBlock, 646 MCStreamer &Out); 647 648 struct NearMissMessage { 649 SMLoc Loc; 650 SmallString<128> Message; 651 }; 652 653 const char *getCustomOperandDiag(ARMMatchResultTy MatchError); 654 655 void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, 656 SmallVectorImpl<NearMissMessage> &NearMissesOut, 657 SMLoc IDLoc, OperandVector &Operands); 658 void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc, 659 OperandVector &Operands); 660 661 void doBeforeLabelEmit(MCSymbol *Symbol) override; 662 663 void onLabelParsed(MCSymbol *Symbol) override; 664 }; 665 666 /// ARMOperand - Instances of this class represent a parsed ARM machine 667 /// operand. 668 class ARMOperand : public MCParsedAsmOperand { 669 enum KindTy { 670 k_CondCode, 671 k_VPTPred, 672 k_CCOut, 673 k_ITCondMask, 674 k_CoprocNum, 675 k_CoprocReg, 676 k_CoprocOption, 677 k_Immediate, 678 k_MemBarrierOpt, 679 k_InstSyncBarrierOpt, 680 k_TraceSyncBarrierOpt, 681 k_Memory, 682 k_PostIndexRegister, 683 k_MSRMask, 684 k_BankedReg, 685 k_ProcIFlags, 686 k_VectorIndex, 687 k_Register, 688 k_RegisterList, 689 k_RegisterListWithAPSR, 690 k_DPRRegisterList, 691 k_SPRRegisterList, 692 k_FPSRegisterListWithVPR, 693 k_FPDRegisterListWithVPR, 694 k_VectorList, 695 k_VectorListAllLanes, 696 k_VectorListIndexed, 697 k_ShiftedRegister, 698 k_ShiftedImmediate, 699 k_ShifterImmediate, 700 k_RotateImmediate, 701 k_ModifiedImmediate, 702 k_ConstantPoolImmediate, 703 k_BitfieldDescriptor, 704 k_Token, 705 } Kind; 706 707 SMLoc StartLoc, EndLoc, AlignmentLoc; 708 SmallVector<unsigned, 8> Registers; 709 710 struct CCOp { 711 ARMCC::CondCodes Val; 712 }; 713 714 struct VCCOp { 715 ARMVCC::VPTCodes Val; 716 }; 717 718 struct CopOp { 719 unsigned Val; 720 }; 721 722 struct CoprocOptionOp { 723 unsigned Val; 724 }; 725 726 struct ITMaskOp { 727 unsigned Mask:4; 728 }; 729 730 struct MBOptOp { 731 ARM_MB::MemBOpt Val; 732 }; 733 734 struct ISBOptOp { 735 ARM_ISB::InstSyncBOpt Val; 736 }; 737 738 struct TSBOptOp { 739 ARM_TSB::TraceSyncBOpt Val; 740 }; 741 742 struct IFlagsOp { 743 ARM_PROC::IFlags Val; 744 }; 745 746 struct MMaskOp { 747 unsigned Val; 748 }; 749 750 struct BankedRegOp { 751 unsigned Val; 752 }; 753 754 struct TokOp { 755 const char *Data; 756 unsigned Length; 757 }; 758 759 struct RegOp { 760 unsigned RegNum; 761 }; 762 763 // A vector register list is a sequential list of 1 to 4 registers. 764 struct VectorListOp { 765 unsigned RegNum; 766 unsigned Count; 767 unsigned LaneIndex; 768 bool isDoubleSpaced; 769 }; 770 771 struct VectorIndexOp { 772 unsigned Val; 773 }; 774 775 struct ImmOp { 776 const MCExpr *Val; 777 }; 778 779 /// Combined record for all forms of ARM address expressions. 780 struct MemoryOp { 781 unsigned BaseRegNum; 782 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 783 // was specified. 784 const MCConstantExpr *OffsetImm; // Offset immediate value 785 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 786 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 787 unsigned ShiftImm; // shift for OffsetReg. 788 unsigned Alignment; // 0 = no alignment specified 789 // n = alignment in bytes (2, 4, 8, 16, or 32) 790 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 791 }; 792 793 struct PostIdxRegOp { 794 unsigned RegNum; 795 bool isAdd; 796 ARM_AM::ShiftOpc ShiftTy; 797 unsigned ShiftImm; 798 }; 799 800 struct ShifterImmOp { 801 bool isASR; 802 unsigned Imm; 803 }; 804 805 struct RegShiftedRegOp { 806 ARM_AM::ShiftOpc ShiftTy; 807 unsigned SrcReg; 808 unsigned ShiftReg; 809 unsigned ShiftImm; 810 }; 811 812 struct RegShiftedImmOp { 813 ARM_AM::ShiftOpc ShiftTy; 814 unsigned SrcReg; 815 unsigned ShiftImm; 816 }; 817 818 struct RotImmOp { 819 unsigned Imm; 820 }; 821 822 struct ModImmOp { 823 unsigned Bits; 824 unsigned Rot; 825 }; 826 827 struct BitfieldOp { 828 unsigned LSB; 829 unsigned Width; 830 }; 831 832 union { 833 struct CCOp CC; 834 struct VCCOp VCC; 835 struct CopOp Cop; 836 struct CoprocOptionOp CoprocOption; 837 struct MBOptOp MBOpt; 838 struct ISBOptOp ISBOpt; 839 struct TSBOptOp TSBOpt; 840 struct ITMaskOp ITMask; 841 struct IFlagsOp IFlags; 842 struct MMaskOp MMask; 843 struct BankedRegOp BankedReg; 844 struct TokOp Tok; 845 struct RegOp Reg; 846 struct VectorListOp VectorList; 847 struct VectorIndexOp VectorIndex; 848 struct ImmOp Imm; 849 struct MemoryOp Memory; 850 struct PostIdxRegOp PostIdxReg; 851 struct ShifterImmOp ShifterImm; 852 struct RegShiftedRegOp RegShiftedReg; 853 struct RegShiftedImmOp RegShiftedImm; 854 struct RotImmOp RotImm; 855 struct ModImmOp ModImm; 856 struct BitfieldOp Bitfield; 857 }; 858 859 public: 860 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 861 862 /// getStartLoc - Get the location of the first token of this operand. 863 SMLoc getStartLoc() const override { return StartLoc; } 864 865 /// getEndLoc - Get the location of the last token of this operand. 866 SMLoc getEndLoc() const override { return EndLoc; } 867 868 /// getLocRange - Get the range between the first and last token of this 869 /// operand. 870 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 871 872 /// getAlignmentLoc - Get the location of the Alignment token of this operand. 873 SMLoc getAlignmentLoc() const { 874 assert(Kind == k_Memory && "Invalid access!"); 875 return AlignmentLoc; 876 } 877 878 ARMCC::CondCodes getCondCode() const { 879 assert(Kind == k_CondCode && "Invalid access!"); 880 return CC.Val; 881 } 882 883 ARMVCC::VPTCodes getVPTPred() const { 884 assert(isVPTPred() && "Invalid access!"); 885 return VCC.Val; 886 } 887 888 unsigned getCoproc() const { 889 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 890 return Cop.Val; 891 } 892 893 StringRef getToken() const { 894 assert(Kind == k_Token && "Invalid access!"); 895 return StringRef(Tok.Data, Tok.Length); 896 } 897 898 unsigned getReg() const override { 899 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 900 return Reg.RegNum; 901 } 902 903 const SmallVectorImpl<unsigned> &getRegList() const { 904 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || 905 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || 906 Kind == k_FPSRegisterListWithVPR || 907 Kind == k_FPDRegisterListWithVPR) && 908 "Invalid access!"); 909 return Registers; 910 } 911 912 const MCExpr *getImm() const { 913 assert(isImm() && "Invalid access!"); 914 return Imm.Val; 915 } 916 917 const MCExpr *getConstantPoolImm() const { 918 assert(isConstantPoolImm() && "Invalid access!"); 919 return Imm.Val; 920 } 921 922 unsigned getVectorIndex() const { 923 assert(Kind == k_VectorIndex && "Invalid access!"); 924 return VectorIndex.Val; 925 } 926 927 ARM_MB::MemBOpt getMemBarrierOpt() const { 928 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 929 return MBOpt.Val; 930 } 931 932 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 933 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 934 return ISBOpt.Val; 935 } 936 937 ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const { 938 assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!"); 939 return TSBOpt.Val; 940 } 941 942 ARM_PROC::IFlags getProcIFlags() const { 943 assert(Kind == k_ProcIFlags && "Invalid access!"); 944 return IFlags.Val; 945 } 946 947 unsigned getMSRMask() const { 948 assert(Kind == k_MSRMask && "Invalid access!"); 949 return MMask.Val; 950 } 951 952 unsigned getBankedReg() const { 953 assert(Kind == k_BankedReg && "Invalid access!"); 954 return BankedReg.Val; 955 } 956 957 bool isCoprocNum() const { return Kind == k_CoprocNum; } 958 bool isCoprocReg() const { return Kind == k_CoprocReg; } 959 bool isCoprocOption() const { return Kind == k_CoprocOption; } 960 bool isCondCode() const { return Kind == k_CondCode; } 961 bool isVPTPred() const { return Kind == k_VPTPred; } 962 bool isCCOut() const { return Kind == k_CCOut; } 963 bool isITMask() const { return Kind == k_ITCondMask; } 964 bool isITCondCode() const { return Kind == k_CondCode; } 965 bool isImm() const override { 966 return Kind == k_Immediate; 967 } 968 969 bool isARMBranchTarget() const { 970 if (!isImm()) return false; 971 972 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) 973 return CE->getValue() % 4 == 0; 974 return true; 975 } 976 977 978 bool isThumbBranchTarget() const { 979 if (!isImm()) return false; 980 981 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) 982 return CE->getValue() % 2 == 0; 983 return true; 984 } 985 986 // checks whether this operand is an unsigned offset which fits is a field 987 // of specified width and scaled by a specific number of bits 988 template<unsigned width, unsigned scale> 989 bool isUnsignedOffset() const { 990 if (!isImm()) return false; 991 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 992 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 993 int64_t Val = CE->getValue(); 994 int64_t Align = 1LL << scale; 995 int64_t Max = Align * ((1LL << width) - 1); 996 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 997 } 998 return false; 999 } 1000 1001 // checks whether this operand is an signed offset which fits is a field 1002 // of specified width and scaled by a specific number of bits 1003 template<unsigned width, unsigned scale> 1004 bool isSignedOffset() const { 1005 if (!isImm()) return false; 1006 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 1007 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1008 int64_t Val = CE->getValue(); 1009 int64_t Align = 1LL << scale; 1010 int64_t Max = Align * ((1LL << (width-1)) - 1); 1011 int64_t Min = -Align * (1LL << (width-1)); 1012 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 1013 } 1014 return false; 1015 } 1016 1017 // checks whether this operand is an offset suitable for the LE / 1018 // LETP instructions in Arm v8.1M 1019 bool isLEOffset() const { 1020 if (!isImm()) return false; 1021 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 1022 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1023 int64_t Val = CE->getValue(); 1024 return Val < 0 && Val >= -4094 && (Val & 1) == 0; 1025 } 1026 return false; 1027 } 1028 1029 // checks whether this operand is a memory operand computed as an offset 1030 // applied to PC. the offset may have 8 bits of magnitude and is represented 1031 // with two bits of shift. textually it may be either [pc, #imm], #imm or 1032 // relocable expression... 1033 bool isThumbMemPC() const { 1034 int64_t Val = 0; 1035 if (isImm()) { 1036 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 1038 if (!CE) return false; 1039 Val = CE->getValue(); 1040 } 1041 else if (isGPRMem()) { 1042 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 1043 if(Memory.BaseRegNum != ARM::PC) return false; 1044 Val = Memory.OffsetImm->getValue(); 1045 } 1046 else return false; 1047 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 1048 } 1049 1050 bool isFPImm() const { 1051 if (!isImm()) return false; 1052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1053 if (!CE) return false; 1054 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1055 return Val != -1; 1056 } 1057 1058 template<int64_t N, int64_t M> 1059 bool isImmediate() const { 1060 if (!isImm()) return false; 1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1062 if (!CE) return false; 1063 int64_t Value = CE->getValue(); 1064 return Value >= N && Value <= M; 1065 } 1066 1067 template<int64_t N, int64_t M> 1068 bool isImmediateS4() const { 1069 if (!isImm()) return false; 1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1071 if (!CE) return false; 1072 int64_t Value = CE->getValue(); 1073 return ((Value & 3) == 0) && Value >= N && Value <= M; 1074 } 1075 template<int64_t N, int64_t M> 1076 bool isImmediateS2() const { 1077 if (!isImm()) return false; 1078 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1079 if (!CE) return false; 1080 int64_t Value = CE->getValue(); 1081 return ((Value & 1) == 0) && Value >= N && Value <= M; 1082 } 1083 bool isFBits16() const { 1084 return isImmediate<0, 17>(); 1085 } 1086 bool isFBits32() const { 1087 return isImmediate<1, 33>(); 1088 } 1089 bool isImm8s4() const { 1090 return isImmediateS4<-1020, 1020>(); 1091 } 1092 bool isImm7s4() const { 1093 return isImmediateS4<-508, 508>(); 1094 } 1095 bool isImm7Shift0() const { 1096 return isImmediate<-127, 127>(); 1097 } 1098 bool isImm7Shift1() const { 1099 return isImmediateS2<-255, 255>(); 1100 } 1101 bool isImm7Shift2() const { 1102 return isImmediateS4<-511, 511>(); 1103 } 1104 bool isImm7() const { 1105 return isImmediate<-127, 127>(); 1106 } 1107 bool isImm0_1020s4() const { 1108 return isImmediateS4<0, 1020>(); 1109 } 1110 bool isImm0_508s4() const { 1111 return isImmediateS4<0, 508>(); 1112 } 1113 bool isImm0_508s4Neg() const { 1114 if (!isImm()) return false; 1115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1116 if (!CE) return false; 1117 int64_t Value = -CE->getValue(); 1118 // explicitly exclude zero. we want that to use the normal 0_508 version. 1119 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 1120 } 1121 1122 bool isImm0_4095Neg() const { 1123 if (!isImm()) return false; 1124 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1125 if (!CE) return false; 1126 // isImm0_4095Neg is used with 32-bit immediates only. 1127 // 32-bit immediates are zero extended to 64-bit when parsed, 1128 // thus simple -CE->getValue() results in a big negative number, 1129 // not a small positive number as intended 1130 if ((CE->getValue() >> 32) > 0) return false; 1131 uint32_t Value = -static_cast<uint32_t>(CE->getValue()); 1132 return Value > 0 && Value < 4096; 1133 } 1134 1135 bool isImm0_7() const { 1136 return isImmediate<0, 7>(); 1137 } 1138 1139 bool isImm1_16() const { 1140 return isImmediate<1, 16>(); 1141 } 1142 1143 bool isImm1_32() const { 1144 return isImmediate<1, 32>(); 1145 } 1146 1147 bool isImm8_255() const { 1148 return isImmediate<8, 255>(); 1149 } 1150 1151 bool isImm256_65535Expr() const { 1152 if (!isImm()) return false; 1153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1154 // If it's not a constant expression, it'll generate a fixup and be 1155 // handled later. 1156 if (!CE) return true; 1157 int64_t Value = CE->getValue(); 1158 return Value >= 256 && Value < 65536; 1159 } 1160 1161 bool isImm0_65535Expr() const { 1162 if (!isImm()) return false; 1163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1164 // If it's not a constant expression, it'll generate a fixup and be 1165 // handled later. 1166 if (!CE) return true; 1167 int64_t Value = CE->getValue(); 1168 return Value >= 0 && Value < 65536; 1169 } 1170 1171 bool isImm24bit() const { 1172 return isImmediate<0, 0xffffff + 1>(); 1173 } 1174 1175 bool isImmThumbSR() const { 1176 return isImmediate<1, 33>(); 1177 } 1178 1179 template<int shift> 1180 bool isExpImmValue(uint64_t Value) const { 1181 uint64_t mask = (1 << shift) - 1; 1182 if ((Value & mask) != 0 || (Value >> shift) > 0xff) 1183 return false; 1184 return true; 1185 } 1186 1187 template<int shift> 1188 bool isExpImm() const { 1189 if (!isImm()) return false; 1190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1191 if (!CE) return false; 1192 1193 return isExpImmValue<shift>(CE->getValue()); 1194 } 1195 1196 template<int shift, int size> 1197 bool isInvertedExpImm() const { 1198 if (!isImm()) return false; 1199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1200 if (!CE) return false; 1201 1202 uint64_t OriginalValue = CE->getValue(); 1203 uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1); 1204 return isExpImmValue<shift>(InvertedValue); 1205 } 1206 1207 bool isPKHLSLImm() const { 1208 return isImmediate<0, 32>(); 1209 } 1210 1211 bool isPKHASRImm() const { 1212 return isImmediate<0, 33>(); 1213 } 1214 1215 bool isAdrLabel() const { 1216 // If we have an immediate that's not a constant, treat it as a label 1217 // reference needing a fixup. 1218 if (isImm() && !isa<MCConstantExpr>(getImm())) 1219 return true; 1220 1221 // If it is a constant, it must fit into a modified immediate encoding. 1222 if (!isImm()) return false; 1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1224 if (!CE) return false; 1225 int64_t Value = CE->getValue(); 1226 return (ARM_AM::getSOImmVal(Value) != -1 || 1227 ARM_AM::getSOImmVal(-Value) != -1); 1228 } 1229 1230 bool isT2SOImm() const { 1231 // If we have an immediate that's not a constant, treat it as an expression 1232 // needing a fixup. 1233 if (isImm() && !isa<MCConstantExpr>(getImm())) { 1234 // We want to avoid matching :upper16: and :lower16: as we want these 1235 // expressions to match in isImm0_65535Expr() 1236 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm()); 1237 return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && 1238 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)); 1239 } 1240 if (!isImm()) return false; 1241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1242 if (!CE) return false; 1243 int64_t Value = CE->getValue(); 1244 return ARM_AM::getT2SOImmVal(Value) != -1; 1245 } 1246 1247 bool isT2SOImmNot() const { 1248 if (!isImm()) return false; 1249 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1250 if (!CE) return false; 1251 int64_t Value = CE->getValue(); 1252 return ARM_AM::getT2SOImmVal(Value) == -1 && 1253 ARM_AM::getT2SOImmVal(~Value) != -1; 1254 } 1255 1256 bool isT2SOImmNeg() const { 1257 if (!isImm()) return false; 1258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1259 if (!CE) return false; 1260 int64_t Value = CE->getValue(); 1261 // Only use this when not representable as a plain so_imm. 1262 return ARM_AM::getT2SOImmVal(Value) == -1 && 1263 ARM_AM::getT2SOImmVal(-Value) != -1; 1264 } 1265 1266 bool isSetEndImm() const { 1267 if (!isImm()) return false; 1268 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1269 if (!CE) return false; 1270 int64_t Value = CE->getValue(); 1271 return Value == 1 || Value == 0; 1272 } 1273 1274 bool isReg() const override { return Kind == k_Register; } 1275 bool isRegList() const { return Kind == k_RegisterList; } 1276 bool isRegListWithAPSR() const { 1277 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList; 1278 } 1279 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1280 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1281 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; } 1282 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; } 1283 bool isToken() const override { return Kind == k_Token; } 1284 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1285 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1286 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; } 1287 bool isMem() const override { 1288 return isGPRMem() || isMVEMem(); 1289 } 1290 bool isMVEMem() const { 1291 if (Kind != k_Memory) 1292 return false; 1293 if (Memory.BaseRegNum && 1294 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && 1295 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) 1296 return false; 1297 if (Memory.OffsetRegNum && 1298 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( 1299 Memory.OffsetRegNum)) 1300 return false; 1301 return true; 1302 } 1303 bool isGPRMem() const { 1304 if (Kind != k_Memory) 1305 return false; 1306 if (Memory.BaseRegNum && 1307 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) 1308 return false; 1309 if (Memory.OffsetRegNum && 1310 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) 1311 return false; 1312 return true; 1313 } 1314 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1315 bool isRegShiftedReg() const { 1316 return Kind == k_ShiftedRegister && 1317 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( 1318 RegShiftedReg.SrcReg) && 1319 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( 1320 RegShiftedReg.ShiftReg); 1321 } 1322 bool isRegShiftedImm() const { 1323 return Kind == k_ShiftedImmediate && 1324 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( 1325 RegShiftedImm.SrcReg); 1326 } 1327 bool isRotImm() const { return Kind == k_RotateImmediate; } 1328 1329 template<unsigned Min, unsigned Max> 1330 bool isPowerTwoInRange() const { 1331 if (!isImm()) return false; 1332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1333 if (!CE) return false; 1334 int64_t Value = CE->getValue(); 1335 return Value > 0 && countPopulation((uint64_t)Value) == 1 && 1336 Value >= Min && Value <= Max; 1337 } 1338 bool isModImm() const { return Kind == k_ModifiedImmediate; } 1339 1340 bool isModImmNot() const { 1341 if (!isImm()) return false; 1342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1343 if (!CE) return false; 1344 int64_t Value = CE->getValue(); 1345 return ARM_AM::getSOImmVal(~Value) != -1; 1346 } 1347 1348 bool isModImmNeg() const { 1349 if (!isImm()) return false; 1350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1351 if (!CE) return false; 1352 int64_t Value = CE->getValue(); 1353 return ARM_AM::getSOImmVal(Value) == -1 && 1354 ARM_AM::getSOImmVal(-Value) != -1; 1355 } 1356 1357 bool isThumbModImmNeg1_7() const { 1358 if (!isImm()) return false; 1359 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1360 if (!CE) return false; 1361 int32_t Value = -(int32_t)CE->getValue(); 1362 return 0 < Value && Value < 8; 1363 } 1364 1365 bool isThumbModImmNeg8_255() const { 1366 if (!isImm()) return false; 1367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1368 if (!CE) return false; 1369 int32_t Value = -(int32_t)CE->getValue(); 1370 return 7 < Value && Value < 256; 1371 } 1372 1373 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; } 1374 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1375 bool isPostIdxRegShifted() const { 1376 return Kind == k_PostIndexRegister && 1377 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); 1378 } 1379 bool isPostIdxReg() const { 1380 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; 1381 } 1382 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1383 if (!isGPRMem()) 1384 return false; 1385 // No offset of any kind. 1386 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1387 (alignOK || Memory.Alignment == Alignment); 1388 } 1389 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const { 1390 if (!isGPRMem()) 1391 return false; 1392 1393 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( 1394 Memory.BaseRegNum)) 1395 return false; 1396 1397 // No offset of any kind. 1398 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1399 (alignOK || Memory.Alignment == Alignment); 1400 } 1401 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const { 1402 if (!isGPRMem()) 1403 return false; 1404 1405 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( 1406 Memory.BaseRegNum)) 1407 return false; 1408 1409 // No offset of any kind. 1410 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1411 (alignOK || Memory.Alignment == Alignment); 1412 } 1413 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const { 1414 if (!isGPRMem()) 1415 return false; 1416 1417 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( 1418 Memory.BaseRegNum)) 1419 return false; 1420 1421 // No offset of any kind. 1422 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1423 (alignOK || Memory.Alignment == Alignment); 1424 } 1425 bool isMemPCRelImm12() const { 1426 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1427 return false; 1428 // Base register must be PC. 1429 if (Memory.BaseRegNum != ARM::PC) 1430 return false; 1431 // Immediate offset in range [-4095, 4095]. 1432 if (!Memory.OffsetImm) return true; 1433 int64_t Val = Memory.OffsetImm->getValue(); 1434 return (Val > -4096 && Val < 4096) || 1435 (Val == std::numeric_limits<int32_t>::min()); 1436 } 1437 1438 bool isAlignedMemory() const { 1439 return isMemNoOffset(true); 1440 } 1441 1442 bool isAlignedMemoryNone() const { 1443 return isMemNoOffset(false, 0); 1444 } 1445 1446 bool isDupAlignedMemoryNone() const { 1447 return isMemNoOffset(false, 0); 1448 } 1449 1450 bool isAlignedMemory16() const { 1451 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1452 return true; 1453 return isMemNoOffset(false, 0); 1454 } 1455 1456 bool isDupAlignedMemory16() const { 1457 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1458 return true; 1459 return isMemNoOffset(false, 0); 1460 } 1461 1462 bool isAlignedMemory32() const { 1463 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1464 return true; 1465 return isMemNoOffset(false, 0); 1466 } 1467 1468 bool isDupAlignedMemory32() const { 1469 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1470 return true; 1471 return isMemNoOffset(false, 0); 1472 } 1473 1474 bool isAlignedMemory64() const { 1475 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1476 return true; 1477 return isMemNoOffset(false, 0); 1478 } 1479 1480 bool isDupAlignedMemory64() const { 1481 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1482 return true; 1483 return isMemNoOffset(false, 0); 1484 } 1485 1486 bool isAlignedMemory64or128() const { 1487 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1488 return true; 1489 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1490 return true; 1491 return isMemNoOffset(false, 0); 1492 } 1493 1494 bool isDupAlignedMemory64or128() const { 1495 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1496 return true; 1497 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1498 return true; 1499 return isMemNoOffset(false, 0); 1500 } 1501 1502 bool isAlignedMemory64or128or256() const { 1503 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1504 return true; 1505 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1506 return true; 1507 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. 1508 return true; 1509 return isMemNoOffset(false, 0); 1510 } 1511 1512 bool isAddrMode2() const { 1513 if (!isGPRMem() || Memory.Alignment != 0) return false; 1514 // Check for register offset. 1515 if (Memory.OffsetRegNum) return true; 1516 // Immediate offset in range [-4095, 4095]. 1517 if (!Memory.OffsetImm) return true; 1518 int64_t Val = Memory.OffsetImm->getValue(); 1519 return Val > -4096 && Val < 4096; 1520 } 1521 1522 bool isAM2OffsetImm() const { 1523 if (!isImm()) return false; 1524 // Immediate offset in range [-4095, 4095]. 1525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1526 if (!CE) return false; 1527 int64_t Val = CE->getValue(); 1528 return (Val == std::numeric_limits<int32_t>::min()) || 1529 (Val > -4096 && Val < 4096); 1530 } 1531 1532 bool isAddrMode3() const { 1533 // If we have an immediate that's not a constant, treat it as a label 1534 // reference needing a fixup. If it is a constant, it's something else 1535 // and we reject it. 1536 if (isImm() && !isa<MCConstantExpr>(getImm())) 1537 return true; 1538 if (!isGPRMem() || Memory.Alignment != 0) return false; 1539 // No shifts are legal for AM3. 1540 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1541 // Check for register offset. 1542 if (Memory.OffsetRegNum) return true; 1543 // Immediate offset in range [-255, 255]. 1544 if (!Memory.OffsetImm) return true; 1545 int64_t Val = Memory.OffsetImm->getValue(); 1546 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we 1547 // have to check for this too. 1548 return (Val > -256 && Val < 256) || 1549 Val == std::numeric_limits<int32_t>::min(); 1550 } 1551 1552 bool isAM3Offset() const { 1553 if (isPostIdxReg()) 1554 return true; 1555 if (!isImm()) 1556 return false; 1557 // Immediate offset in range [-255, 255]. 1558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1559 if (!CE) return false; 1560 int64_t Val = CE->getValue(); 1561 // Special case, #-0 is std::numeric_limits<int32_t>::min(). 1562 return (Val > -256 && Val < 256) || 1563 Val == std::numeric_limits<int32_t>::min(); 1564 } 1565 1566 bool isAddrMode5() const { 1567 // If we have an immediate that's not a constant, treat it as a label 1568 // reference needing a fixup. If it is a constant, it's something else 1569 // and we reject it. 1570 if (isImm() && !isa<MCConstantExpr>(getImm())) 1571 return true; 1572 if (!isGPRMem() || Memory.Alignment != 0) return false; 1573 // Check for register offset. 1574 if (Memory.OffsetRegNum) return false; 1575 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1576 if (!Memory.OffsetImm) return true; 1577 int64_t Val = Memory.OffsetImm->getValue(); 1578 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1579 Val == std::numeric_limits<int32_t>::min(); 1580 } 1581 1582 bool isAddrMode5FP16() const { 1583 // If we have an immediate that's not a constant, treat it as a label 1584 // reference needing a fixup. If it is a constant, it's something else 1585 // and we reject it. 1586 if (isImm() && !isa<MCConstantExpr>(getImm())) 1587 return true; 1588 if (!isGPRMem() || Memory.Alignment != 0) return false; 1589 // Check for register offset. 1590 if (Memory.OffsetRegNum) return false; 1591 // Immediate offset in range [-510, 510] and a multiple of 2. 1592 if (!Memory.OffsetImm) return true; 1593 int64_t Val = Memory.OffsetImm->getValue(); 1594 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || 1595 Val == std::numeric_limits<int32_t>::min(); 1596 } 1597 1598 bool isMemTBB() const { 1599 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || 1600 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1601 return false; 1602 return true; 1603 } 1604 1605 bool isMemTBH() const { 1606 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || 1607 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1608 Memory.Alignment != 0 ) 1609 return false; 1610 return true; 1611 } 1612 1613 bool isMemRegOffset() const { 1614 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1615 return false; 1616 return true; 1617 } 1618 1619 bool isT2MemRegOffset() const { 1620 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || 1621 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) 1622 return false; 1623 // Only lsl #{0, 1, 2, 3} allowed. 1624 if (Memory.ShiftType == ARM_AM::no_shift) 1625 return true; 1626 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1627 return false; 1628 return true; 1629 } 1630 1631 bool isMemThumbRR() const { 1632 // Thumb reg+reg addressing is simple. Just two registers, a base and 1633 // an offset. No shifts, negations or any other complicating factors. 1634 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || 1635 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1636 return false; 1637 return isARMLowRegister(Memory.BaseRegNum) && 1638 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1639 } 1640 1641 bool isMemThumbRIs4() const { 1642 if (!isGPRMem() || Memory.OffsetRegNum != 0 || 1643 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1644 return false; 1645 // Immediate offset, multiple of 4 in range [0, 124]. 1646 if (!Memory.OffsetImm) return true; 1647 int64_t Val = Memory.OffsetImm->getValue(); 1648 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1649 } 1650 1651 bool isMemThumbRIs2() const { 1652 if (!isGPRMem() || Memory.OffsetRegNum != 0 || 1653 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1654 return false; 1655 // Immediate offset, multiple of 4 in range [0, 62]. 1656 if (!Memory.OffsetImm) return true; 1657 int64_t Val = Memory.OffsetImm->getValue(); 1658 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1659 } 1660 1661 bool isMemThumbRIs1() const { 1662 if (!isGPRMem() || Memory.OffsetRegNum != 0 || 1663 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1664 return false; 1665 // Immediate offset in range [0, 31]. 1666 if (!Memory.OffsetImm) return true; 1667 int64_t Val = Memory.OffsetImm->getValue(); 1668 return Val >= 0 && Val <= 31; 1669 } 1670 1671 bool isMemThumbSPI() const { 1672 if (!isGPRMem() || Memory.OffsetRegNum != 0 || 1673 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1674 return false; 1675 // Immediate offset, multiple of 4 in range [0, 1020]. 1676 if (!Memory.OffsetImm) return true; 1677 int64_t Val = Memory.OffsetImm->getValue(); 1678 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1679 } 1680 1681 bool isMemImm8s4Offset() const { 1682 // If we have an immediate that's not a constant, treat it as a label 1683 // reference needing a fixup. If it is a constant, it's something else 1684 // and we reject it. 1685 if (isImm() && !isa<MCConstantExpr>(getImm())) 1686 return true; 1687 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1688 return false; 1689 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1690 if (!Memory.OffsetImm) return true; 1691 int64_t Val = Memory.OffsetImm->getValue(); 1692 // Special case, #-0 is std::numeric_limits<int32_t>::min(). 1693 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || 1694 Val == std::numeric_limits<int32_t>::min(); 1695 } 1696 bool isMemImm7s4Offset() const { 1697 // If we have an immediate that's not a constant, treat it as a label 1698 // reference needing a fixup. If it is a constant, it's something else 1699 // and we reject it. 1700 if (isImm() && !isa<MCConstantExpr>(getImm())) 1701 return true; 1702 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || 1703 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( 1704 Memory.BaseRegNum)) 1705 return false; 1706 // Immediate offset a multiple of 4 in range [-508, 508]. 1707 if (!Memory.OffsetImm) return true; 1708 int64_t Val = Memory.OffsetImm->getValue(); 1709 // Special case, #-0 is INT32_MIN. 1710 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN; 1711 } 1712 bool isMemImm0_1020s4Offset() const { 1713 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1714 return false; 1715 // Immediate offset a multiple of 4 in range [0, 1020]. 1716 if (!Memory.OffsetImm) return true; 1717 int64_t Val = Memory.OffsetImm->getValue(); 1718 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1719 } 1720 1721 bool isMemImm8Offset() const { 1722 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1723 return false; 1724 // Base reg of PC isn't allowed for these encodings. 1725 if (Memory.BaseRegNum == ARM::PC) return false; 1726 // Immediate offset in range [-255, 255]. 1727 if (!Memory.OffsetImm) return true; 1728 int64_t Val = Memory.OffsetImm->getValue(); 1729 return (Val == std::numeric_limits<int32_t>::min()) || 1730 (Val > -256 && Val < 256); 1731 } 1732 1733 template<unsigned Bits, unsigned RegClassID> 1734 bool isMemImm7ShiftedOffset() const { 1735 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || 1736 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) 1737 return false; 1738 1739 // Expect an immediate offset equal to an element of the range 1740 // [-127, 127], shifted left by Bits. 1741 1742 if (!Memory.OffsetImm) return true; 1743 int64_t Val = Memory.OffsetImm->getValue(); 1744 1745 // INT32_MIN is a special-case value (indicating the encoding with 1746 // zero offset and the subtract bit set) 1747 if (Val == INT32_MIN) 1748 return true; 1749 1750 unsigned Divisor = 1U << Bits; 1751 1752 // Check that the low bits are zero 1753 if (Val % Divisor != 0) 1754 return false; 1755 1756 // Check that the remaining offset is within range. 1757 Val /= Divisor; 1758 return (Val >= -127 && Val <= 127); 1759 } 1760 1761 template <int shift> bool isMemRegRQOffset() const { 1762 if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0) 1763 return false; 1764 1765 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( 1766 Memory.BaseRegNum)) 1767 return false; 1768 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( 1769 Memory.OffsetRegNum)) 1770 return false; 1771 1772 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) 1773 return false; 1774 1775 if (shift > 0 && 1776 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) 1777 return false; 1778 1779 return true; 1780 } 1781 1782 template <int shift> bool isMemRegQOffset() const { 1783 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1784 return false; 1785 1786 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( 1787 Memory.BaseRegNum)) 1788 return false; 1789 1790 if(!Memory.OffsetImm) return true; 1791 static_assert(shift < 56, 1792 "Such that we dont shift by a value higher than 62"); 1793 int64_t Val = Memory.OffsetImm->getValue(); 1794 1795 // The value must be a multiple of (1 << shift) 1796 if ((Val & ((1U << shift) - 1)) != 0) 1797 return false; 1798 1799 // And be in the right range, depending on the amount that it is shifted 1800 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set 1801 // separately. 1802 int64_t Range = (1U << (7+shift)) - 1; 1803 return (Val == INT32_MIN) || (Val > -Range && Val < Range); 1804 } 1805 1806 bool isMemPosImm8Offset() const { 1807 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1808 return false; 1809 // Immediate offset in range [0, 255]. 1810 if (!Memory.OffsetImm) return true; 1811 int64_t Val = Memory.OffsetImm->getValue(); 1812 return Val >= 0 && Val < 256; 1813 } 1814 1815 bool isMemNegImm8Offset() const { 1816 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1817 return false; 1818 // Base reg of PC isn't allowed for these encodings. 1819 if (Memory.BaseRegNum == ARM::PC) return false; 1820 // Immediate offset in range [-255, -1]. 1821 if (!Memory.OffsetImm) return false; 1822 int64_t Val = Memory.OffsetImm->getValue(); 1823 return (Val == std::numeric_limits<int32_t>::min()) || 1824 (Val > -256 && Val < 0); 1825 } 1826 1827 bool isMemUImm12Offset() const { 1828 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1829 return false; 1830 // Immediate offset in range [0, 4095]. 1831 if (!Memory.OffsetImm) return true; 1832 int64_t Val = Memory.OffsetImm->getValue(); 1833 return (Val >= 0 && Val < 4096); 1834 } 1835 1836 bool isMemImm12Offset() const { 1837 // If we have an immediate that's not a constant, treat it as a label 1838 // reference needing a fixup. If it is a constant, it's something else 1839 // and we reject it. 1840 1841 if (isImm() && !isa<MCConstantExpr>(getImm())) 1842 return true; 1843 1844 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1845 return false; 1846 // Immediate offset in range [-4095, 4095]. 1847 if (!Memory.OffsetImm) return true; 1848 int64_t Val = Memory.OffsetImm->getValue(); 1849 return (Val > -4096 && Val < 4096) || 1850 (Val == std::numeric_limits<int32_t>::min()); 1851 } 1852 1853 bool isConstPoolAsmImm() const { 1854 // Delay processing of Constant Pool Immediate, this will turn into 1855 // a constant. Match no other operand 1856 return (isConstantPoolImm()); 1857 } 1858 1859 bool isPostIdxImm8() const { 1860 if (!isImm()) return false; 1861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1862 if (!CE) return false; 1863 int64_t Val = CE->getValue(); 1864 return (Val > -256 && Val < 256) || 1865 (Val == std::numeric_limits<int32_t>::min()); 1866 } 1867 1868 bool isPostIdxImm8s4() const { 1869 if (!isImm()) return false; 1870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1871 if (!CE) return false; 1872 int64_t Val = CE->getValue(); 1873 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1874 (Val == std::numeric_limits<int32_t>::min()); 1875 } 1876 1877 bool isMSRMask() const { return Kind == k_MSRMask; } 1878 bool isBankedReg() const { return Kind == k_BankedReg; } 1879 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1880 1881 // NEON operands. 1882 bool isSingleSpacedVectorList() const { 1883 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1884 } 1885 1886 bool isDoubleSpacedVectorList() const { 1887 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1888 } 1889 1890 bool isVecListOneD() const { 1891 if (!isSingleSpacedVectorList()) return false; 1892 return VectorList.Count == 1; 1893 } 1894 1895 bool isVecListTwoMQ() const { 1896 return isSingleSpacedVectorList() && VectorList.Count == 2 && 1897 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( 1898 VectorList.RegNum); 1899 } 1900 1901 bool isVecListDPair() const { 1902 if (!isSingleSpacedVectorList()) return false; 1903 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1904 .contains(VectorList.RegNum)); 1905 } 1906 1907 bool isVecListThreeD() const { 1908 if (!isSingleSpacedVectorList()) return false; 1909 return VectorList.Count == 3; 1910 } 1911 1912 bool isVecListFourD() const { 1913 if (!isSingleSpacedVectorList()) return false; 1914 return VectorList.Count == 4; 1915 } 1916 1917 bool isVecListDPairSpaced() const { 1918 if (Kind != k_VectorList) return false; 1919 if (isSingleSpacedVectorList()) return false; 1920 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1921 .contains(VectorList.RegNum)); 1922 } 1923 1924 bool isVecListThreeQ() const { 1925 if (!isDoubleSpacedVectorList()) return false; 1926 return VectorList.Count == 3; 1927 } 1928 1929 bool isVecListFourQ() const { 1930 if (!isDoubleSpacedVectorList()) return false; 1931 return VectorList.Count == 4; 1932 } 1933 1934 bool isVecListFourMQ() const { 1935 return isSingleSpacedVectorList() && VectorList.Count == 4 && 1936 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( 1937 VectorList.RegNum); 1938 } 1939 1940 bool isSingleSpacedVectorAllLanes() const { 1941 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1942 } 1943 1944 bool isDoubleSpacedVectorAllLanes() const { 1945 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1946 } 1947 1948 bool isVecListOneDAllLanes() const { 1949 if (!isSingleSpacedVectorAllLanes()) return false; 1950 return VectorList.Count == 1; 1951 } 1952 1953 bool isVecListDPairAllLanes() const { 1954 if (!isSingleSpacedVectorAllLanes()) return false; 1955 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1956 .contains(VectorList.RegNum)); 1957 } 1958 1959 bool isVecListDPairSpacedAllLanes() const { 1960 if (!isDoubleSpacedVectorAllLanes()) return false; 1961 return VectorList.Count == 2; 1962 } 1963 1964 bool isVecListThreeDAllLanes() const { 1965 if (!isSingleSpacedVectorAllLanes()) return false; 1966 return VectorList.Count == 3; 1967 } 1968 1969 bool isVecListThreeQAllLanes() const { 1970 if (!isDoubleSpacedVectorAllLanes()) return false; 1971 return VectorList.Count == 3; 1972 } 1973 1974 bool isVecListFourDAllLanes() const { 1975 if (!isSingleSpacedVectorAllLanes()) return false; 1976 return VectorList.Count == 4; 1977 } 1978 1979 bool isVecListFourQAllLanes() const { 1980 if (!isDoubleSpacedVectorAllLanes()) return false; 1981 return VectorList.Count == 4; 1982 } 1983 1984 bool isSingleSpacedVectorIndexed() const { 1985 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1986 } 1987 1988 bool isDoubleSpacedVectorIndexed() const { 1989 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1990 } 1991 1992 bool isVecListOneDByteIndexed() const { 1993 if (!isSingleSpacedVectorIndexed()) return false; 1994 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1995 } 1996 1997 bool isVecListOneDHWordIndexed() const { 1998 if (!isSingleSpacedVectorIndexed()) return false; 1999 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 2000 } 2001 2002 bool isVecListOneDWordIndexed() const { 2003 if (!isSingleSpacedVectorIndexed()) return false; 2004 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 2005 } 2006 2007 bool isVecListTwoDByteIndexed() const { 2008 if (!isSingleSpacedVectorIndexed()) return false; 2009 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 2010 } 2011 2012 bool isVecListTwoDHWordIndexed() const { 2013 if (!isSingleSpacedVectorIndexed()) return false; 2014 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 2015 } 2016 2017 bool isVecListTwoQWordIndexed() const { 2018 if (!isDoubleSpacedVectorIndexed()) return false; 2019 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 2020 } 2021 2022 bool isVecListTwoQHWordIndexed() const { 2023 if (!isDoubleSpacedVectorIndexed()) return false; 2024 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 2025 } 2026 2027 bool isVecListTwoDWordIndexed() const { 2028 if (!isSingleSpacedVectorIndexed()) return false; 2029 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 2030 } 2031 2032 bool isVecListThreeDByteIndexed() const { 2033 if (!isSingleSpacedVectorIndexed()) return false; 2034 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 2035 } 2036 2037 bool isVecListThreeDHWordIndexed() const { 2038 if (!isSingleSpacedVectorIndexed()) return false; 2039 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 2040 } 2041 2042 bool isVecListThreeQWordIndexed() const { 2043 if (!isDoubleSpacedVectorIndexed()) return false; 2044 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 2045 } 2046 2047 bool isVecListThreeQHWordIndexed() const { 2048 if (!isDoubleSpacedVectorIndexed()) return false; 2049 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 2050 } 2051 2052 bool isVecListThreeDWordIndexed() const { 2053 if (!isSingleSpacedVectorIndexed()) return false; 2054 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 2055 } 2056 2057 bool isVecListFourDByteIndexed() const { 2058 if (!isSingleSpacedVectorIndexed()) return false; 2059 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 2060 } 2061 2062 bool isVecListFourDHWordIndexed() const { 2063 if (!isSingleSpacedVectorIndexed()) return false; 2064 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 2065 } 2066 2067 bool isVecListFourQWordIndexed() const { 2068 if (!isDoubleSpacedVectorIndexed()) return false; 2069 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 2070 } 2071 2072 bool isVecListFourQHWordIndexed() const { 2073 if (!isDoubleSpacedVectorIndexed()) return false; 2074 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 2075 } 2076 2077 bool isVecListFourDWordIndexed() const { 2078 if (!isSingleSpacedVectorIndexed()) return false; 2079 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 2080 } 2081 2082 bool isVectorIndex() const { return Kind == k_VectorIndex; } 2083 2084 template <unsigned NumLanes> 2085 bool isVectorIndexInRange() const { 2086 if (Kind != k_VectorIndex) return false; 2087 return VectorIndex.Val < NumLanes; 2088 } 2089 2090 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); } 2091 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); } 2092 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); } 2093 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); } 2094 2095 template<int PermittedValue, int OtherPermittedValue> 2096 bool isMVEPairVectorIndex() const { 2097 if (Kind != k_VectorIndex) return false; 2098 return VectorIndex.Val == PermittedValue || 2099 VectorIndex.Val == OtherPermittedValue; 2100 } 2101 2102 bool isNEONi8splat() const { 2103 if (!isImm()) return false; 2104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2105 // Must be a constant. 2106 if (!CE) return false; 2107 int64_t Value = CE->getValue(); 2108 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 2109 // value. 2110 return Value >= 0 && Value < 256; 2111 } 2112 2113 bool isNEONi16splat() const { 2114 if (isNEONByteReplicate(2)) 2115 return false; // Leave that for bytes replication and forbid by default. 2116 if (!isImm()) 2117 return false; 2118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2119 // Must be a constant. 2120 if (!CE) return false; 2121 unsigned Value = CE->getValue(); 2122 return ARM_AM::isNEONi16splat(Value); 2123 } 2124 2125 bool isNEONi16splatNot() const { 2126 if (!isImm()) 2127 return false; 2128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2129 // Must be a constant. 2130 if (!CE) return false; 2131 unsigned Value = CE->getValue(); 2132 return ARM_AM::isNEONi16splat(~Value & 0xffff); 2133 } 2134 2135 bool isNEONi32splat() const { 2136 if (isNEONByteReplicate(4)) 2137 return false; // Leave that for bytes replication and forbid by default. 2138 if (!isImm()) 2139 return false; 2140 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2141 // Must be a constant. 2142 if (!CE) return false; 2143 unsigned Value = CE->getValue(); 2144 return ARM_AM::isNEONi32splat(Value); 2145 } 2146 2147 bool isNEONi32splatNot() const { 2148 if (!isImm()) 2149 return false; 2150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2151 // Must be a constant. 2152 if (!CE) return false; 2153 unsigned Value = CE->getValue(); 2154 return ARM_AM::isNEONi32splat(~Value); 2155 } 2156 2157 static bool isValidNEONi32vmovImm(int64_t Value) { 2158 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 2159 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 2160 return ((Value & 0xffffffffffffff00) == 0) || 2161 ((Value & 0xffffffffffff00ff) == 0) || 2162 ((Value & 0xffffffffff00ffff) == 0) || 2163 ((Value & 0xffffffff00ffffff) == 0) || 2164 ((Value & 0xffffffffffff00ff) == 0xff) || 2165 ((Value & 0xffffffffff00ffff) == 0xffff); 2166 } 2167 2168 bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const { 2169 assert((Width == 8 || Width == 16 || Width == 32) && 2170 "Invalid element width"); 2171 assert(NumElems * Width <= 64 && "Invalid result width"); 2172 2173 if (!isImm()) 2174 return false; 2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2176 // Must be a constant. 2177 if (!CE) 2178 return false; 2179 int64_t Value = CE->getValue(); 2180 if (!Value) 2181 return false; // Don't bother with zero. 2182 if (Inv) 2183 Value = ~Value; 2184 2185 uint64_t Mask = (1ull << Width) - 1; 2186 uint64_t Elem = Value & Mask; 2187 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0) 2188 return false; 2189 if (Width == 32 && !isValidNEONi32vmovImm(Elem)) 2190 return false; 2191 2192 for (unsigned i = 1; i < NumElems; ++i) { 2193 Value >>= Width; 2194 if ((Value & Mask) != Elem) 2195 return false; 2196 } 2197 return true; 2198 } 2199 2200 bool isNEONByteReplicate(unsigned NumBytes) const { 2201 return isNEONReplicate(8, NumBytes, false); 2202 } 2203 2204 static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) { 2205 assert((FromW == 8 || FromW == 16 || FromW == 32) && 2206 "Invalid source width"); 2207 assert((ToW == 16 || ToW == 32 || ToW == 64) && 2208 "Invalid destination width"); 2209 assert(FromW < ToW && "ToW is not less than FromW"); 2210 } 2211 2212 template<unsigned FromW, unsigned ToW> 2213 bool isNEONmovReplicate() const { 2214 checkNeonReplicateArgs(FromW, ToW); 2215 if (ToW == 64 && isNEONi64splat()) 2216 return false; 2217 return isNEONReplicate(FromW, ToW / FromW, false); 2218 } 2219 2220 template<unsigned FromW, unsigned ToW> 2221 bool isNEONinvReplicate() const { 2222 checkNeonReplicateArgs(FromW, ToW); 2223 return isNEONReplicate(FromW, ToW / FromW, true); 2224 } 2225 2226 bool isNEONi32vmov() const { 2227 if (isNEONByteReplicate(4)) 2228 return false; // Let it to be classified as byte-replicate case. 2229 if (!isImm()) 2230 return false; 2231 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2232 // Must be a constant. 2233 if (!CE) 2234 return false; 2235 return isValidNEONi32vmovImm(CE->getValue()); 2236 } 2237 2238 bool isNEONi32vmovNeg() const { 2239 if (!isImm()) return false; 2240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2241 // Must be a constant. 2242 if (!CE) return false; 2243 return isValidNEONi32vmovImm(~CE->getValue()); 2244 } 2245 2246 bool isNEONi64splat() const { 2247 if (!isImm()) return false; 2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2249 // Must be a constant. 2250 if (!CE) return false; 2251 uint64_t Value = CE->getValue(); 2252 // i64 value with each byte being either 0 or 0xff. 2253 for (unsigned i = 0; i < 8; ++i, Value >>= 8) 2254 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 2255 return true; 2256 } 2257 2258 template<int64_t Angle, int64_t Remainder> 2259 bool isComplexRotation() const { 2260 if (!isImm()) return false; 2261 2262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2263 if (!CE) return false; 2264 uint64_t Value = CE->getValue(); 2265 2266 return (Value % Angle == Remainder && Value <= 270); 2267 } 2268 2269 bool isMVELongShift() const { 2270 if (!isImm()) return false; 2271 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2272 // Must be a constant. 2273 if (!CE) return false; 2274 uint64_t Value = CE->getValue(); 2275 return Value >= 1 && Value <= 32; 2276 } 2277 2278 bool isITCondCodeNoAL() const { 2279 if (!isITCondCode()) return false; 2280 ARMCC::CondCodes CC = getCondCode(); 2281 return CC != ARMCC::AL; 2282 } 2283 2284 bool isITCondCodeRestrictedI() const { 2285 if (!isITCondCode()) 2286 return false; 2287 ARMCC::CondCodes CC = getCondCode(); 2288 return CC == ARMCC::EQ || CC == ARMCC::NE; 2289 } 2290 2291 bool isITCondCodeRestrictedS() const { 2292 if (!isITCondCode()) 2293 return false; 2294 ARMCC::CondCodes CC = getCondCode(); 2295 return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE || 2296 CC == ARMCC::GE; 2297 } 2298 2299 bool isITCondCodeRestrictedU() const { 2300 if (!isITCondCode()) 2301 return false; 2302 ARMCC::CondCodes CC = getCondCode(); 2303 return CC == ARMCC::HS || CC == ARMCC::HI; 2304 } 2305 2306 bool isITCondCodeRestrictedFP() const { 2307 if (!isITCondCode()) 2308 return false; 2309 ARMCC::CondCodes CC = getCondCode(); 2310 return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT || 2311 CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE; 2312 } 2313 2314 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 2315 // Add as immediates when possible. Null MCExpr = 0. 2316 if (!Expr) 2317 Inst.addOperand(MCOperand::createImm(0)); 2318 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 2319 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2320 else 2321 Inst.addOperand(MCOperand::createExpr(Expr)); 2322 } 2323 2324 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const { 2325 assert(N == 1 && "Invalid number of operands!"); 2326 addExpr(Inst, getImm()); 2327 } 2328 2329 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const { 2330 assert(N == 1 && "Invalid number of operands!"); 2331 addExpr(Inst, getImm()); 2332 } 2333 2334 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 2335 assert(N == 2 && "Invalid number of operands!"); 2336 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 2337 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 2338 Inst.addOperand(MCOperand::createReg(RegNum)); 2339 } 2340 2341 void addVPTPredNOperands(MCInst &Inst, unsigned N) const { 2342 assert(N == 2 && "Invalid number of operands!"); 2343 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); 2344 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; 2345 Inst.addOperand(MCOperand::createReg(RegNum)); 2346 } 2347 2348 void addVPTPredROperands(MCInst &Inst, unsigned N) const { 2349 assert(N == 3 && "Invalid number of operands!"); 2350 addVPTPredNOperands(Inst, N-1); 2351 unsigned RegNum; 2352 if (getVPTPred() == ARMVCC::None) { 2353 RegNum = 0; 2354 } else { 2355 unsigned NextOpIndex = Inst.getNumOperands(); 2356 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()]; 2357 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); 2358 assert(TiedOp >= 0 && 2359 "Inactive register in vpred_r is not tied to an output!"); 2360 RegNum = Inst.getOperand(TiedOp).getReg(); 2361 } 2362 Inst.addOperand(MCOperand::createReg(RegNum)); 2363 } 2364 2365 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 2366 assert(N == 1 && "Invalid number of operands!"); 2367 Inst.addOperand(MCOperand::createImm(getCoproc())); 2368 } 2369 2370 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 2371 assert(N == 1 && "Invalid number of operands!"); 2372 Inst.addOperand(MCOperand::createImm(getCoproc())); 2373 } 2374 2375 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 2376 assert(N == 1 && "Invalid number of operands!"); 2377 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); 2378 } 2379 2380 void addITMaskOperands(MCInst &Inst, unsigned N) const { 2381 assert(N == 1 && "Invalid number of operands!"); 2382 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); 2383 } 2384 2385 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 2386 assert(N == 1 && "Invalid number of operands!"); 2387 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 2388 } 2389 2390 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const { 2391 assert(N == 1 && "Invalid number of operands!"); 2392 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); 2393 } 2394 2395 void addCCOutOperands(MCInst &Inst, unsigned N) const { 2396 assert(N == 1 && "Invalid number of operands!"); 2397 Inst.addOperand(MCOperand::createReg(getReg())); 2398 } 2399 2400 void addRegOperands(MCInst &Inst, unsigned N) const { 2401 assert(N == 1 && "Invalid number of operands!"); 2402 Inst.addOperand(MCOperand::createReg(getReg())); 2403 } 2404 2405 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 2406 assert(N == 3 && "Invalid number of operands!"); 2407 assert(isRegShiftedReg() && 2408 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 2409 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); 2410 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); 2411 Inst.addOperand(MCOperand::createImm( 2412 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 2413 } 2414 2415 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 2416 assert(N == 2 && "Invalid number of operands!"); 2417 assert(isRegShiftedImm() && 2418 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 2419 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); 2420 // Shift of #32 is encoded as 0 where permitted 2421 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 2422 Inst.addOperand(MCOperand::createImm( 2423 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 2424 } 2425 2426 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 2427 assert(N == 1 && "Invalid number of operands!"); 2428 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | 2429 ShifterImm.Imm)); 2430 } 2431 2432 void addRegListOperands(MCInst &Inst, unsigned N) const { 2433 assert(N == 1 && "Invalid number of operands!"); 2434 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2435 for (SmallVectorImpl<unsigned>::const_iterator 2436 I = RegList.begin(), E = RegList.end(); I != E; ++I) 2437 Inst.addOperand(MCOperand::createReg(*I)); 2438 } 2439 2440 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const { 2441 assert(N == 1 && "Invalid number of operands!"); 2442 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2443 for (SmallVectorImpl<unsigned>::const_iterator 2444 I = RegList.begin(), E = RegList.end(); I != E; ++I) 2445 Inst.addOperand(MCOperand::createReg(*I)); 2446 } 2447 2448 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 2449 addRegListOperands(Inst, N); 2450 } 2451 2452 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 2453 addRegListOperands(Inst, N); 2454 } 2455 2456 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const { 2457 addRegListOperands(Inst, N); 2458 } 2459 2460 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const { 2461 addRegListOperands(Inst, N); 2462 } 2463 2464 void addRotImmOperands(MCInst &Inst, unsigned N) const { 2465 assert(N == 1 && "Invalid number of operands!"); 2466 // Encoded as val>>3. The printer handles display as 8, 16, 24. 2467 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); 2468 } 2469 2470 void addModImmOperands(MCInst &Inst, unsigned N) const { 2471 assert(N == 1 && "Invalid number of operands!"); 2472 2473 // Support for fixups (MCFixup) 2474 if (isImm()) 2475 return addImmOperands(Inst, N); 2476 2477 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); 2478 } 2479 2480 void addModImmNotOperands(MCInst &Inst, unsigned N) const { 2481 assert(N == 1 && "Invalid number of operands!"); 2482 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2483 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); 2484 Inst.addOperand(MCOperand::createImm(Enc)); 2485 } 2486 2487 void addModImmNegOperands(MCInst &Inst, unsigned N) const { 2488 assert(N == 1 && "Invalid number of operands!"); 2489 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2490 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); 2491 Inst.addOperand(MCOperand::createImm(Enc)); 2492 } 2493 2494 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const { 2495 assert(N == 1 && "Invalid number of operands!"); 2496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2497 uint32_t Val = -CE->getValue(); 2498 Inst.addOperand(MCOperand::createImm(Val)); 2499 } 2500 2501 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const { 2502 assert(N == 1 && "Invalid number of operands!"); 2503 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2504 uint32_t Val = -CE->getValue(); 2505 Inst.addOperand(MCOperand::createImm(Val)); 2506 } 2507 2508 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 2509 assert(N == 1 && "Invalid number of operands!"); 2510 // Munge the lsb/width into a bitfield mask. 2511 unsigned lsb = Bitfield.LSB; 2512 unsigned width = Bitfield.Width; 2513 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 2514 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 2515 (32 - (lsb + width))); 2516 Inst.addOperand(MCOperand::createImm(Mask)); 2517 } 2518 2519 void addImmOperands(MCInst &Inst, unsigned N) const { 2520 assert(N == 1 && "Invalid number of operands!"); 2521 addExpr(Inst, getImm()); 2522 } 2523 2524 void addFBits16Operands(MCInst &Inst, unsigned N) const { 2525 assert(N == 1 && "Invalid number of operands!"); 2526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2527 Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); 2528 } 2529 2530 void addFBits32Operands(MCInst &Inst, unsigned N) const { 2531 assert(N == 1 && "Invalid number of operands!"); 2532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2533 Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); 2534 } 2535 2536 void addFPImmOperands(MCInst &Inst, unsigned N) const { 2537 assert(N == 1 && "Invalid number of operands!"); 2538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2539 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 2540 Inst.addOperand(MCOperand::createImm(Val)); 2541 } 2542 2543 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 2544 assert(N == 1 && "Invalid number of operands!"); 2545 // FIXME: We really want to scale the value here, but the LDRD/STRD 2546 // instruction don't encode operands that way yet. 2547 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2548 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2549 } 2550 2551 void addImm7s4Operands(MCInst &Inst, unsigned N) const { 2552 assert(N == 1 && "Invalid number of operands!"); 2553 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR 2554 // instruction don't encode operands that way yet. 2555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2556 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2557 } 2558 2559 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const { 2560 assert(N == 1 && "Invalid number of operands!"); 2561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2562 assert(CE != nullptr && "Invalid operand type!"); 2563 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2564 } 2565 2566 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const { 2567 assert(N == 1 && "Invalid number of operands!"); 2568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2569 assert(CE != nullptr && "Invalid operand type!"); 2570 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2571 } 2572 2573 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const { 2574 assert(N == 1 && "Invalid number of operands!"); 2575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2576 assert(CE != nullptr && "Invalid operand type!"); 2577 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2578 } 2579 2580 void addImm7Operands(MCInst &Inst, unsigned N) const { 2581 assert(N == 1 && "Invalid number of operands!"); 2582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2583 assert(CE != nullptr && "Invalid operand type!"); 2584 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2585 } 2586 2587 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 2588 assert(N == 1 && "Invalid number of operands!"); 2589 // The immediate is scaled by four in the encoding and is stored 2590 // in the MCInst as such. Lop off the low two bits here. 2591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2592 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 2593 } 2594 2595 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 2596 assert(N == 1 && "Invalid number of operands!"); 2597 // The immediate is scaled by four in the encoding and is stored 2598 // in the MCInst as such. Lop off the low two bits here. 2599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2600 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); 2601 } 2602 2603 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 2604 assert(N == 1 && "Invalid number of operands!"); 2605 // The immediate is scaled by four in the encoding and is stored 2606 // in the MCInst as such. Lop off the low two bits here. 2607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2608 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 2609 } 2610 2611 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 2612 assert(N == 1 && "Invalid number of operands!"); 2613 // The constant encodes as the immediate-1, and we store in the instruction 2614 // the bits as encoded, so subtract off one here. 2615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2616 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 2617 } 2618 2619 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 2620 assert(N == 1 && "Invalid number of operands!"); 2621 // The constant encodes as the immediate-1, and we store in the instruction 2622 // the bits as encoded, so subtract off one here. 2623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2624 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 2625 } 2626 2627 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 2628 assert(N == 1 && "Invalid number of operands!"); 2629 // The constant encodes as the immediate, except for 32, which encodes as 2630 // zero. 2631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2632 unsigned Imm = CE->getValue(); 2633 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); 2634 } 2635 2636 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 2637 assert(N == 1 && "Invalid number of operands!"); 2638 // An ASR value of 32 encodes as 0, so that's how we want to add it to 2639 // the instruction as well. 2640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2641 int Val = CE->getValue(); 2642 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); 2643 } 2644 2645 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 2646 assert(N == 1 && "Invalid number of operands!"); 2647 // The operand is actually a t2_so_imm, but we have its bitwise 2648 // negation in the assembly source, so twiddle it here. 2649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2650 Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue())); 2651 } 2652 2653 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 2654 assert(N == 1 && "Invalid number of operands!"); 2655 // The operand is actually a t2_so_imm, but we have its 2656 // negation in the assembly source, so twiddle it here. 2657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2658 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); 2659 } 2660 2661 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 2662 assert(N == 1 && "Invalid number of operands!"); 2663 // The operand is actually an imm0_4095, but we have its 2664 // negation in the assembly source, so twiddle it here. 2665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2666 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); 2667 } 2668 2669 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 2670 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 2671 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); 2672 return; 2673 } 2674 2675 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 2676 assert(SR && "Unknown value type!"); 2677 Inst.addOperand(MCOperand::createExpr(SR)); 2678 } 2679 2680 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 2681 assert(N == 1 && "Invalid number of operands!"); 2682 if (isImm()) { 2683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2684 if (CE) { 2685 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2686 return; 2687 } 2688 2689 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 2690 2691 assert(SR && "Unknown value type!"); 2692 Inst.addOperand(MCOperand::createExpr(SR)); 2693 return; 2694 } 2695 2696 assert(isGPRMem() && "Unknown value type!"); 2697 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 2698 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); 2699 } 2700 2701 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 2702 assert(N == 1 && "Invalid number of operands!"); 2703 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); 2704 } 2705 2706 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 2707 assert(N == 1 && "Invalid number of operands!"); 2708 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); 2709 } 2710 2711 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 2712 assert(N == 1 && "Invalid number of operands!"); 2713 Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt()))); 2714 } 2715 2716 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 2717 assert(N == 1 && "Invalid number of operands!"); 2718 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2719 } 2720 2721 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const { 2722 assert(N == 1 && "Invalid number of operands!"); 2723 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2724 } 2725 2726 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const { 2727 assert(N == 1 && "Invalid number of operands!"); 2728 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2729 } 2730 2731 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const { 2732 assert(N == 1 && "Invalid number of operands!"); 2733 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2734 } 2735 2736 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 2737 assert(N == 1 && "Invalid number of operands!"); 2738 int32_t Imm = Memory.OffsetImm->getValue(); 2739 Inst.addOperand(MCOperand::createImm(Imm)); 2740 } 2741 2742 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 2743 assert(N == 1 && "Invalid number of operands!"); 2744 assert(isImm() && "Not an immediate!"); 2745 2746 // If we have an immediate that's not a constant, treat it as a label 2747 // reference needing a fixup. 2748 if (!isa<MCConstantExpr>(getImm())) { 2749 Inst.addOperand(MCOperand::createExpr(getImm())); 2750 return; 2751 } 2752 2753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2754 int Val = CE->getValue(); 2755 Inst.addOperand(MCOperand::createImm(Val)); 2756 } 2757 2758 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 2759 assert(N == 2 && "Invalid number of operands!"); 2760 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2761 Inst.addOperand(MCOperand::createImm(Memory.Alignment)); 2762 } 2763 2764 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2765 addAlignedMemoryOperands(Inst, N); 2766 } 2767 2768 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2769 addAlignedMemoryOperands(Inst, N); 2770 } 2771 2772 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2773 addAlignedMemoryOperands(Inst, N); 2774 } 2775 2776 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2777 addAlignedMemoryOperands(Inst, N); 2778 } 2779 2780 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2781 addAlignedMemoryOperands(Inst, N); 2782 } 2783 2784 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2785 addAlignedMemoryOperands(Inst, N); 2786 } 2787 2788 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2789 addAlignedMemoryOperands(Inst, N); 2790 } 2791 2792 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2793 addAlignedMemoryOperands(Inst, N); 2794 } 2795 2796 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2797 addAlignedMemoryOperands(Inst, N); 2798 } 2799 2800 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2801 addAlignedMemoryOperands(Inst, N); 2802 } 2803 2804 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { 2805 addAlignedMemoryOperands(Inst, N); 2806 } 2807 2808 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 2809 assert(N == 3 && "Invalid number of operands!"); 2810 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2811 if (!Memory.OffsetRegNum) { 2812 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2813 // Special case for #-0 2814 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2815 if (Val < 0) Val = -Val; 2816 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2817 } else { 2818 // For register offset, we encode the shift type and negation flag 2819 // here. 2820 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2821 Memory.ShiftImm, Memory.ShiftType); 2822 } 2823 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2824 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2825 Inst.addOperand(MCOperand::createImm(Val)); 2826 } 2827 2828 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 2829 assert(N == 2 && "Invalid number of operands!"); 2830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2831 assert(CE && "non-constant AM2OffsetImm operand!"); 2832 int32_t Val = CE->getValue(); 2833 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2834 // Special case for #-0 2835 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2836 if (Val < 0) Val = -Val; 2837 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2838 Inst.addOperand(MCOperand::createReg(0)); 2839 Inst.addOperand(MCOperand::createImm(Val)); 2840 } 2841 2842 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 2843 assert(N == 3 && "Invalid number of operands!"); 2844 // If we have an immediate that's not a constant, treat it as a label 2845 // reference needing a fixup. If it is a constant, it's something else 2846 // and we reject it. 2847 if (isImm()) { 2848 Inst.addOperand(MCOperand::createExpr(getImm())); 2849 Inst.addOperand(MCOperand::createReg(0)); 2850 Inst.addOperand(MCOperand::createImm(0)); 2851 return; 2852 } 2853 2854 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2855 if (!Memory.OffsetRegNum) { 2856 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2857 // Special case for #-0 2858 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2859 if (Val < 0) Val = -Val; 2860 Val = ARM_AM::getAM3Opc(AddSub, Val); 2861 } else { 2862 // For register offset, we encode the shift type and negation flag 2863 // here. 2864 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2865 } 2866 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2867 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2868 Inst.addOperand(MCOperand::createImm(Val)); 2869 } 2870 2871 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 2872 assert(N == 2 && "Invalid number of operands!"); 2873 if (Kind == k_PostIndexRegister) { 2874 int32_t Val = 2875 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2876 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2877 Inst.addOperand(MCOperand::createImm(Val)); 2878 return; 2879 } 2880 2881 // Constant offset. 2882 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2883 int32_t Val = CE->getValue(); 2884 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2885 // Special case for #-0 2886 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2887 if (Val < 0) Val = -Val; 2888 Val = ARM_AM::getAM3Opc(AddSub, Val); 2889 Inst.addOperand(MCOperand::createReg(0)); 2890 Inst.addOperand(MCOperand::createImm(Val)); 2891 } 2892 2893 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2894 assert(N == 2 && "Invalid number of operands!"); 2895 // If we have an immediate that's not a constant, treat it as a label 2896 // reference needing a fixup. If it is a constant, it's something else 2897 // and we reject it. 2898 if (isImm()) { 2899 Inst.addOperand(MCOperand::createExpr(getImm())); 2900 Inst.addOperand(MCOperand::createImm(0)); 2901 return; 2902 } 2903 2904 // The lower two bits are always zero and as such are not encoded. 2905 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2906 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2907 // Special case for #-0 2908 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2909 if (Val < 0) Val = -Val; 2910 Val = ARM_AM::getAM5Opc(AddSub, Val); 2911 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2912 Inst.addOperand(MCOperand::createImm(Val)); 2913 } 2914 2915 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const { 2916 assert(N == 2 && "Invalid number of operands!"); 2917 // If we have an immediate that's not a constant, treat it as a label 2918 // reference needing a fixup. If it is a constant, it's something else 2919 // and we reject it. 2920 if (isImm()) { 2921 Inst.addOperand(MCOperand::createExpr(getImm())); 2922 Inst.addOperand(MCOperand::createImm(0)); 2923 return; 2924 } 2925 2926 // The lower bit is always zero and as such is not encoded. 2927 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0; 2928 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2929 // Special case for #-0 2930 if (Val == std::numeric_limits<int32_t>::min()) Val = 0; 2931 if (Val < 0) Val = -Val; 2932 Val = ARM_AM::getAM5FP16Opc(AddSub, Val); 2933 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2934 Inst.addOperand(MCOperand::createImm(Val)); 2935 } 2936 2937 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2938 assert(N == 2 && "Invalid number of operands!"); 2939 // If we have an immediate that's not a constant, treat it as a label 2940 // reference needing a fixup. If it is a constant, it's something else 2941 // and we reject it. 2942 if (isImm()) { 2943 Inst.addOperand(MCOperand::createExpr(getImm())); 2944 Inst.addOperand(MCOperand::createImm(0)); 2945 return; 2946 } 2947 2948 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2949 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2950 Inst.addOperand(MCOperand::createImm(Val)); 2951 } 2952 2953 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const { 2954 assert(N == 2 && "Invalid number of operands!"); 2955 // If we have an immediate that's not a constant, treat it as a label 2956 // reference needing a fixup. If it is a constant, it's something else 2957 // and we reject it. 2958 if (isImm()) { 2959 Inst.addOperand(MCOperand::createExpr(getImm())); 2960 Inst.addOperand(MCOperand::createImm(0)); 2961 return; 2962 } 2963 2964 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2965 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2966 Inst.addOperand(MCOperand::createImm(Val)); 2967 } 2968 2969 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2970 assert(N == 2 && "Invalid number of operands!"); 2971 // The lower two bits are always zero and as such are not encoded. 2972 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2973 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2974 Inst.addOperand(MCOperand::createImm(Val)); 2975 } 2976 2977 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const { 2978 assert(N == 2 && "Invalid number of operands!"); 2979 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2980 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2981 Inst.addOperand(MCOperand::createImm(Val)); 2982 } 2983 2984 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const { 2985 assert(N == 2 && "Invalid number of operands!"); 2986 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2987 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2988 } 2989 2990 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2991 assert(N == 2 && "Invalid number of operands!"); 2992 // If this is an immediate, it's a label reference. 2993 if (isImm()) { 2994 addExpr(Inst, getImm()); 2995 Inst.addOperand(MCOperand::createImm(0)); 2996 return; 2997 } 2998 2999 // Otherwise, it's a normal memory reg+offset. 3000 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 3001 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3002 Inst.addOperand(MCOperand::createImm(Val)); 3003 } 3004 3005 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 3006 assert(N == 2 && "Invalid number of operands!"); 3007 // If this is an immediate, it's a label reference. 3008 if (isImm()) { 3009 addExpr(Inst, getImm()); 3010 Inst.addOperand(MCOperand::createImm(0)); 3011 return; 3012 } 3013 3014 // Otherwise, it's a normal memory reg+offset. 3015 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 3016 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3017 Inst.addOperand(MCOperand::createImm(Val)); 3018 } 3019 3020 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const { 3021 assert(N == 1 && "Invalid number of operands!"); 3022 // This is container for the immediate that we will create the constant 3023 // pool from 3024 addExpr(Inst, getConstantPoolImm()); 3025 return; 3026 } 3027 3028 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 3029 assert(N == 2 && "Invalid number of operands!"); 3030 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3031 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 3032 } 3033 3034 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 3035 assert(N == 2 && "Invalid number of operands!"); 3036 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3037 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 3038 } 3039 3040 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 3041 assert(N == 3 && "Invalid number of operands!"); 3042 unsigned Val = 3043 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 3044 Memory.ShiftImm, Memory.ShiftType); 3045 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3046 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 3047 Inst.addOperand(MCOperand::createImm(Val)); 3048 } 3049 3050 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 3051 assert(N == 3 && "Invalid number of operands!"); 3052 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3053 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 3054 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); 3055 } 3056 3057 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 3058 assert(N == 2 && "Invalid number of operands!"); 3059 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3060 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 3061 } 3062 3063 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 3064 assert(N == 2 && "Invalid number of operands!"); 3065 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 3066 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3067 Inst.addOperand(MCOperand::createImm(Val)); 3068 } 3069 3070 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 3071 assert(N == 2 && "Invalid number of operands!"); 3072 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 3073 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3074 Inst.addOperand(MCOperand::createImm(Val)); 3075 } 3076 3077 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 3078 assert(N == 2 && "Invalid number of operands!"); 3079 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 3080 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3081 Inst.addOperand(MCOperand::createImm(Val)); 3082 } 3083 3084 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 3085 assert(N == 2 && "Invalid number of operands!"); 3086 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 3087 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 3088 Inst.addOperand(MCOperand::createImm(Val)); 3089 } 3090 3091 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 3092 assert(N == 1 && "Invalid number of operands!"); 3093 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3094 assert(CE && "non-constant post-idx-imm8 operand!"); 3095 int Imm = CE->getValue(); 3096 bool isAdd = Imm >= 0; 3097 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; 3098 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 3099 Inst.addOperand(MCOperand::createImm(Imm)); 3100 } 3101 3102 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 3103 assert(N == 1 && "Invalid number of operands!"); 3104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3105 assert(CE && "non-constant post-idx-imm8s4 operand!"); 3106 int Imm = CE->getValue(); 3107 bool isAdd = Imm >= 0; 3108 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0; 3109 // Immediate is scaled by 4. 3110 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 3111 Inst.addOperand(MCOperand::createImm(Imm)); 3112 } 3113 3114 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 3115 assert(N == 2 && "Invalid number of operands!"); 3116 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 3117 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); 3118 } 3119 3120 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 3121 assert(N == 2 && "Invalid number of operands!"); 3122 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 3123 // The sign, shift type, and shift amount are encoded in a single operand 3124 // using the AM2 encoding helpers. 3125 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 3126 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 3127 PostIdxReg.ShiftTy); 3128 Inst.addOperand(MCOperand::createImm(Imm)); 3129 } 3130 3131 void addPowerTwoOperands(MCInst &Inst, unsigned N) const { 3132 assert(N == 1 && "Invalid number of operands!"); 3133 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3134 Inst.addOperand(MCOperand::createImm(CE->getValue())); 3135 } 3136 3137 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 3138 assert(N == 1 && "Invalid number of operands!"); 3139 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); 3140 } 3141 3142 void addBankedRegOperands(MCInst &Inst, unsigned N) const { 3143 assert(N == 1 && "Invalid number of operands!"); 3144 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); 3145 } 3146 3147 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 3148 assert(N == 1 && "Invalid number of operands!"); 3149 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); 3150 } 3151 3152 void addVecListOperands(MCInst &Inst, unsigned N) const { 3153 assert(N == 1 && "Invalid number of operands!"); 3154 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 3155 } 3156 3157 void addMVEVecListOperands(MCInst &Inst, unsigned N) const { 3158 assert(N == 1 && "Invalid number of operands!"); 3159 3160 // When we come here, the VectorList field will identify a range 3161 // of q-registers by its base register and length, and it will 3162 // have already been error-checked to be the expected length of 3163 // range and contain only q-regs in the range q0-q7. So we can 3164 // count on the base register being in the range q0-q6 (for 2 3165 // regs) or q0-q4 (for 4) 3166 // 3167 // The MVE instructions taking a register range of this kind will 3168 // need an operand in the QQPR or QQQQPR class, representing the 3169 // entire range as a unit. So we must translate into that class, 3170 // by finding the index of the base register in the MQPR reg 3171 // class, and returning the super-register at the corresponding 3172 // index in the target class. 3173 3174 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; 3175 const MCRegisterClass *RC_out = (VectorList.Count == 2) ? 3176 &ARMMCRegisterClasses[ARM::QQPRRegClassID] : 3177 &ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; 3178 3179 unsigned I, E = RC_out->getNumRegs(); 3180 for (I = 0; I < E; I++) 3181 if (RC_in->getRegister(I) == VectorList.RegNum) 3182 break; 3183 assert(I < E && "Invalid vector list start register!"); 3184 3185 Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I))); 3186 } 3187 3188 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 3189 assert(N == 2 && "Invalid number of operands!"); 3190 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 3191 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); 3192 } 3193 3194 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 3195 assert(N == 1 && "Invalid number of operands!"); 3196 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3197 } 3198 3199 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 3200 assert(N == 1 && "Invalid number of operands!"); 3201 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3202 } 3203 3204 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 3205 assert(N == 1 && "Invalid number of operands!"); 3206 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3207 } 3208 3209 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const { 3210 assert(N == 1 && "Invalid number of operands!"); 3211 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3212 } 3213 3214 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const { 3215 assert(N == 1 && "Invalid number of operands!"); 3216 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3217 } 3218 3219 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const { 3220 assert(N == 1 && "Invalid number of operands!"); 3221 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 3222 } 3223 3224 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 3225 assert(N == 1 && "Invalid number of operands!"); 3226 // The immediate encodes the type of constant as well as the value. 3227 // Mask in that this is an i8 splat. 3228 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3229 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); 3230 } 3231 3232 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 3233 assert(N == 1 && "Invalid number of operands!"); 3234 // The immediate encodes the type of constant as well as the value. 3235 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3236 unsigned Value = CE->getValue(); 3237 Value = ARM_AM::encodeNEONi16splat(Value); 3238 Inst.addOperand(MCOperand::createImm(Value)); 3239 } 3240 3241 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { 3242 assert(N == 1 && "Invalid number of operands!"); 3243 // The immediate encodes the type of constant as well as the value. 3244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3245 unsigned Value = CE->getValue(); 3246 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); 3247 Inst.addOperand(MCOperand::createImm(Value)); 3248 } 3249 3250 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 3251 assert(N == 1 && "Invalid number of operands!"); 3252 // The immediate encodes the type of constant as well as the value. 3253 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3254 unsigned Value = CE->getValue(); 3255 Value = ARM_AM::encodeNEONi32splat(Value); 3256 Inst.addOperand(MCOperand::createImm(Value)); 3257 } 3258 3259 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { 3260 assert(N == 1 && "Invalid number of operands!"); 3261 // The immediate encodes the type of constant as well as the value. 3262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3263 unsigned Value = CE->getValue(); 3264 Value = ARM_AM::encodeNEONi32splat(~Value); 3265 Inst.addOperand(MCOperand::createImm(Value)); 3266 } 3267 3268 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const { 3269 // The immediate encodes the type of constant as well as the value. 3270 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3271 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 3272 Inst.getOpcode() == ARM::VMOVv16i8) && 3273 "All instructions that wants to replicate non-zero byte " 3274 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 3275 unsigned Value = CE->getValue(); 3276 if (Inv) 3277 Value = ~Value; 3278 unsigned B = Value & 0xff; 3279 B |= 0xe00; // cmode = 0b1110 3280 Inst.addOperand(MCOperand::createImm(B)); 3281 } 3282 3283 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const { 3284 assert(N == 1 && "Invalid number of operands!"); 3285 addNEONi8ReplicateOperands(Inst, true); 3286 } 3287 3288 static unsigned encodeNeonVMOVImmediate(unsigned Value) { 3289 if (Value >= 256 && Value <= 0xffff) 3290 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 3291 else if (Value > 0xffff && Value <= 0xffffff) 3292 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 3293 else if (Value > 0xffffff) 3294 Value = (Value >> 24) | 0x600; 3295 return Value; 3296 } 3297 3298 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 3299 assert(N == 1 && "Invalid number of operands!"); 3300 // The immediate encodes the type of constant as well as the value. 3301 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3302 unsigned Value = encodeNeonVMOVImmediate(CE->getValue()); 3303 Inst.addOperand(MCOperand::createImm(Value)); 3304 } 3305 3306 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const { 3307 assert(N == 1 && "Invalid number of operands!"); 3308 addNEONi8ReplicateOperands(Inst, false); 3309 } 3310 3311 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const { 3312 assert(N == 1 && "Invalid number of operands!"); 3313 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3314 assert((Inst.getOpcode() == ARM::VMOVv4i16 || 3315 Inst.getOpcode() == ARM::VMOVv8i16 || 3316 Inst.getOpcode() == ARM::VMVNv4i16 || 3317 Inst.getOpcode() == ARM::VMVNv8i16) && 3318 "All instructions that want to replicate non-zero half-word " 3319 "always must be replaced with V{MOV,MVN}v{4,8}i16."); 3320 uint64_t Value = CE->getValue(); 3321 unsigned Elem = Value & 0xffff; 3322 if (Elem >= 256) 3323 Elem = (Elem >> 8) | 0x200; 3324 Inst.addOperand(MCOperand::createImm(Elem)); 3325 } 3326 3327 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 3328 assert(N == 1 && "Invalid number of operands!"); 3329 // The immediate encodes the type of constant as well as the value. 3330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3331 unsigned Value = encodeNeonVMOVImmediate(~CE->getValue()); 3332 Inst.addOperand(MCOperand::createImm(Value)); 3333 } 3334 3335 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const { 3336 assert(N == 1 && "Invalid number of operands!"); 3337 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3338 assert((Inst.getOpcode() == ARM::VMOVv2i32 || 3339 Inst.getOpcode() == ARM::VMOVv4i32 || 3340 Inst.getOpcode() == ARM::VMVNv2i32 || 3341 Inst.getOpcode() == ARM::VMVNv4i32) && 3342 "All instructions that want to replicate non-zero word " 3343 "always must be replaced with V{MOV,MVN}v{2,4}i32."); 3344 uint64_t Value = CE->getValue(); 3345 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff); 3346 Inst.addOperand(MCOperand::createImm(Elem)); 3347 } 3348 3349 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 3350 assert(N == 1 && "Invalid number of operands!"); 3351 // The immediate encodes the type of constant as well as the value. 3352 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3353 uint64_t Value = CE->getValue(); 3354 unsigned Imm = 0; 3355 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 3356 Imm |= (Value & 1) << i; 3357 } 3358 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); 3359 } 3360 3361 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const { 3362 assert(N == 1 && "Invalid number of operands!"); 3363 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3364 Inst.addOperand(MCOperand::createImm(CE->getValue() / 90)); 3365 } 3366 3367 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const { 3368 assert(N == 1 && "Invalid number of operands!"); 3369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 3370 Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180)); 3371 } 3372 3373 void print(raw_ostream &OS) const override; 3374 3375 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { 3376 auto Op = make_unique<ARMOperand>(k_ITCondMask); 3377 Op->ITMask.Mask = Mask; 3378 Op->StartLoc = S; 3379 Op->EndLoc = S; 3380 return Op; 3381 } 3382 3383 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, 3384 SMLoc S) { 3385 auto Op = make_unique<ARMOperand>(k_CondCode); 3386 Op->CC.Val = CC; 3387 Op->StartLoc = S; 3388 Op->EndLoc = S; 3389 return Op; 3390 } 3391 3392 static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC, 3393 SMLoc S) { 3394 auto Op = make_unique<ARMOperand>(k_VPTPred); 3395 Op->VCC.Val = CC; 3396 Op->StartLoc = S; 3397 Op->EndLoc = S; 3398 return Op; 3399 } 3400 3401 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { 3402 auto Op = make_unique<ARMOperand>(k_CoprocNum); 3403 Op->Cop.Val = CopVal; 3404 Op->StartLoc = S; 3405 Op->EndLoc = S; 3406 return Op; 3407 } 3408 3409 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { 3410 auto Op = make_unique<ARMOperand>(k_CoprocReg); 3411 Op->Cop.Val = CopVal; 3412 Op->StartLoc = S; 3413 Op->EndLoc = S; 3414 return Op; 3415 } 3416 3417 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, 3418 SMLoc E) { 3419 auto Op = make_unique<ARMOperand>(k_CoprocOption); 3420 Op->Cop.Val = Val; 3421 Op->StartLoc = S; 3422 Op->EndLoc = E; 3423 return Op; 3424 } 3425 3426 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { 3427 auto Op = make_unique<ARMOperand>(k_CCOut); 3428 Op->Reg.RegNum = RegNum; 3429 Op->StartLoc = S; 3430 Op->EndLoc = S; 3431 return Op; 3432 } 3433 3434 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { 3435 auto Op = make_unique<ARMOperand>(k_Token); 3436 Op->Tok.Data = Str.data(); 3437 Op->Tok.Length = Str.size(); 3438 Op->StartLoc = S; 3439 Op->EndLoc = S; 3440 return Op; 3441 } 3442 3443 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, 3444 SMLoc E) { 3445 auto Op = make_unique<ARMOperand>(k_Register); 3446 Op->Reg.RegNum = RegNum; 3447 Op->StartLoc = S; 3448 Op->EndLoc = E; 3449 return Op; 3450 } 3451 3452 static std::unique_ptr<ARMOperand> 3453 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 3454 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, 3455 SMLoc E) { 3456 auto Op = make_unique<ARMOperand>(k_ShiftedRegister); 3457 Op->RegShiftedReg.ShiftTy = ShTy; 3458 Op->RegShiftedReg.SrcReg = SrcReg; 3459 Op->RegShiftedReg.ShiftReg = ShiftReg; 3460 Op->RegShiftedReg.ShiftImm = ShiftImm; 3461 Op->StartLoc = S; 3462 Op->EndLoc = E; 3463 return Op; 3464 } 3465 3466 static std::unique_ptr<ARMOperand> 3467 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 3468 unsigned ShiftImm, SMLoc S, SMLoc E) { 3469 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate); 3470 Op->RegShiftedImm.ShiftTy = ShTy; 3471 Op->RegShiftedImm.SrcReg = SrcReg; 3472 Op->RegShiftedImm.ShiftImm = ShiftImm; 3473 Op->StartLoc = S; 3474 Op->EndLoc = E; 3475 return Op; 3476 } 3477 3478 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, 3479 SMLoc S, SMLoc E) { 3480 auto Op = make_unique<ARMOperand>(k_ShifterImmediate); 3481 Op->ShifterImm.isASR = isASR; 3482 Op->ShifterImm.Imm = Imm; 3483 Op->StartLoc = S; 3484 Op->EndLoc = E; 3485 return Op; 3486 } 3487 3488 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, 3489 SMLoc E) { 3490 auto Op = make_unique<ARMOperand>(k_RotateImmediate); 3491 Op->RotImm.Imm = Imm; 3492 Op->StartLoc = S; 3493 Op->EndLoc = E; 3494 return Op; 3495 } 3496 3497 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, 3498 SMLoc S, SMLoc E) { 3499 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate); 3500 Op->ModImm.Bits = Bits; 3501 Op->ModImm.Rot = Rot; 3502 Op->StartLoc = S; 3503 Op->EndLoc = E; 3504 return Op; 3505 } 3506 3507 static std::unique_ptr<ARMOperand> 3508 CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) { 3509 auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate); 3510 Op->Imm.Val = Val; 3511 Op->StartLoc = S; 3512 Op->EndLoc = E; 3513 return Op; 3514 } 3515 3516 static std::unique_ptr<ARMOperand> 3517 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { 3518 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor); 3519 Op->Bitfield.LSB = LSB; 3520 Op->Bitfield.Width = Width; 3521 Op->StartLoc = S; 3522 Op->EndLoc = E; 3523 return Op; 3524 } 3525 3526 static std::unique_ptr<ARMOperand> 3527 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, 3528 SMLoc StartLoc, SMLoc EndLoc) { 3529 assert(Regs.size() > 0 && "RegList contains no registers?"); 3530 KindTy Kind = k_RegisterList; 3531 3532 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 3533 Regs.front().second)) { 3534 if (Regs.back().second == ARM::VPR) 3535 Kind = k_FPDRegisterListWithVPR; 3536 else 3537 Kind = k_DPRRegisterList; 3538 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( 3539 Regs.front().second)) { 3540 if (Regs.back().second == ARM::VPR) 3541 Kind = k_FPSRegisterListWithVPR; 3542 else 3543 Kind = k_SPRRegisterList; 3544 } 3545 3546 // Sort based on the register encoding values. 3547 array_pod_sort(Regs.begin(), Regs.end()); 3548 3549 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) 3550 Kind = k_RegisterListWithAPSR; 3551 3552 auto Op = make_unique<ARMOperand>(Kind); 3553 for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator 3554 I = Regs.begin(), E = Regs.end(); I != E; ++I) 3555 Op->Registers.push_back(I->second); 3556 3557 Op->StartLoc = StartLoc; 3558 Op->EndLoc = EndLoc; 3559 return Op; 3560 } 3561 3562 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, 3563 unsigned Count, 3564 bool isDoubleSpaced, 3565 SMLoc S, SMLoc E) { 3566 auto Op = make_unique<ARMOperand>(k_VectorList); 3567 Op->VectorList.RegNum = RegNum; 3568 Op->VectorList.Count = Count; 3569 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 3570 Op->StartLoc = S; 3571 Op->EndLoc = E; 3572 return Op; 3573 } 3574 3575 static std::unique_ptr<ARMOperand> 3576 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, 3577 SMLoc S, SMLoc E) { 3578 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes); 3579 Op->VectorList.RegNum = RegNum; 3580 Op->VectorList.Count = Count; 3581 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 3582 Op->StartLoc = S; 3583 Op->EndLoc = E; 3584 return Op; 3585 } 3586 3587 static std::unique_ptr<ARMOperand> 3588 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, 3589 bool isDoubleSpaced, SMLoc S, SMLoc E) { 3590 auto Op = make_unique<ARMOperand>(k_VectorListIndexed); 3591 Op->VectorList.RegNum = RegNum; 3592 Op->VectorList.Count = Count; 3593 Op->VectorList.LaneIndex = Index; 3594 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 3595 Op->StartLoc = S; 3596 Op->EndLoc = E; 3597 return Op; 3598 } 3599 3600 static std::unique_ptr<ARMOperand> 3601 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { 3602 auto Op = make_unique<ARMOperand>(k_VectorIndex); 3603 Op->VectorIndex.Val = Idx; 3604 Op->StartLoc = S; 3605 Op->EndLoc = E; 3606 return Op; 3607 } 3608 3609 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, 3610 SMLoc E) { 3611 auto Op = make_unique<ARMOperand>(k_Immediate); 3612 Op->Imm.Val = Val; 3613 Op->StartLoc = S; 3614 Op->EndLoc = E; 3615 return Op; 3616 } 3617 3618 static std::unique_ptr<ARMOperand> 3619 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, 3620 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, 3621 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, 3622 SMLoc E, SMLoc AlignmentLoc = SMLoc()) { 3623 auto Op = make_unique<ARMOperand>(k_Memory); 3624 Op->Memory.BaseRegNum = BaseRegNum; 3625 Op->Memory.OffsetImm = OffsetImm; 3626 Op->Memory.OffsetRegNum = OffsetRegNum; 3627 Op->Memory.ShiftType = ShiftType; 3628 Op->Memory.ShiftImm = ShiftImm; 3629 Op->Memory.Alignment = Alignment; 3630 Op->Memory.isNegative = isNegative; 3631 Op->StartLoc = S; 3632 Op->EndLoc = E; 3633 Op->AlignmentLoc = AlignmentLoc; 3634 return Op; 3635 } 3636 3637 static std::unique_ptr<ARMOperand> 3638 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, 3639 unsigned ShiftImm, SMLoc S, SMLoc E) { 3640 auto Op = make_unique<ARMOperand>(k_PostIndexRegister); 3641 Op->PostIdxReg.RegNum = RegNum; 3642 Op->PostIdxReg.isAdd = isAdd; 3643 Op->PostIdxReg.ShiftTy = ShiftTy; 3644 Op->PostIdxReg.ShiftImm = ShiftImm; 3645 Op->StartLoc = S; 3646 Op->EndLoc = E; 3647 return Op; 3648 } 3649 3650 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, 3651 SMLoc S) { 3652 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt); 3653 Op->MBOpt.Val = Opt; 3654 Op->StartLoc = S; 3655 Op->EndLoc = S; 3656 return Op; 3657 } 3658 3659 static std::unique_ptr<ARMOperand> 3660 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { 3661 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt); 3662 Op->ISBOpt.Val = Opt; 3663 Op->StartLoc = S; 3664 Op->EndLoc = S; 3665 return Op; 3666 } 3667 3668 static std::unique_ptr<ARMOperand> 3669 CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) { 3670 auto Op = make_unique<ARMOperand>(k_TraceSyncBarrierOpt); 3671 Op->TSBOpt.Val = Opt; 3672 Op->StartLoc = S; 3673 Op->EndLoc = S; 3674 return Op; 3675 } 3676 3677 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, 3678 SMLoc S) { 3679 auto Op = make_unique<ARMOperand>(k_ProcIFlags); 3680 Op->IFlags.Val = IFlags; 3681 Op->StartLoc = S; 3682 Op->EndLoc = S; 3683 return Op; 3684 } 3685 3686 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { 3687 auto Op = make_unique<ARMOperand>(k_MSRMask); 3688 Op->MMask.Val = MMask; 3689 Op->StartLoc = S; 3690 Op->EndLoc = S; 3691 return Op; 3692 } 3693 3694 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { 3695 auto Op = make_unique<ARMOperand>(k_BankedReg); 3696 Op->BankedReg.Val = Reg; 3697 Op->StartLoc = S; 3698 Op->EndLoc = S; 3699 return Op; 3700 } 3701 }; 3702 3703 } // end anonymous namespace. 3704 3705 void ARMOperand::print(raw_ostream &OS) const { 3706 auto RegName = [](unsigned Reg) { 3707 if (Reg) 3708 return ARMInstPrinter::getRegisterName(Reg); 3709 else 3710 return "noreg"; 3711 }; 3712 3713 switch (Kind) { 3714 case k_CondCode: 3715 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 3716 break; 3717 case k_VPTPred: 3718 OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">"; 3719 break; 3720 case k_CCOut: 3721 OS << "<ccout " << RegName(getReg()) << ">"; 3722 break; 3723 case k_ITCondMask: { 3724 static const char *const MaskStr[] = { 3725 "(invalid)", "(tttt)", "(ttt)", "(ttte)", 3726 "(tt)", "(ttet)", "(tte)", "(ttee)", 3727 "(t)", "(tett)", "(tet)", "(tete)", 3728 "(te)", "(teet)", "(tee)", "(teee)", 3729 }; 3730 assert((ITMask.Mask & 0xf) == ITMask.Mask); 3731 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 3732 break; 3733 } 3734 case k_CoprocNum: 3735 OS << "<coprocessor number: " << getCoproc() << ">"; 3736 break; 3737 case k_CoprocReg: 3738 OS << "<coprocessor register: " << getCoproc() << ">"; 3739 break; 3740 case k_CoprocOption: 3741 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 3742 break; 3743 case k_MSRMask: 3744 OS << "<mask: " << getMSRMask() << ">"; 3745 break; 3746 case k_BankedReg: 3747 OS << "<banked reg: " << getBankedReg() << ">"; 3748 break; 3749 case k_Immediate: 3750 OS << *getImm(); 3751 break; 3752 case k_MemBarrierOpt: 3753 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 3754 break; 3755 case k_InstSyncBarrierOpt: 3756 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 3757 break; 3758 case k_TraceSyncBarrierOpt: 3759 OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">"; 3760 break; 3761 case k_Memory: 3762 OS << "<memory"; 3763 if (Memory.BaseRegNum) 3764 OS << " base:" << RegName(Memory.BaseRegNum); 3765 if (Memory.OffsetImm) 3766 OS << " offset-imm:" << *Memory.OffsetImm; 3767 if (Memory.OffsetRegNum) 3768 OS << " offset-reg:" << (Memory.isNegative ? "-" : "") 3769 << RegName(Memory.OffsetRegNum); 3770 if (Memory.ShiftType != ARM_AM::no_shift) { 3771 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType); 3772 OS << " shift-imm:" << Memory.ShiftImm; 3773 } 3774 if (Memory.Alignment) 3775 OS << " alignment:" << Memory.Alignment; 3776 OS << ">"; 3777 break; 3778 case k_PostIndexRegister: 3779 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 3780 << RegName(PostIdxReg.RegNum); 3781 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 3782 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 3783 << PostIdxReg.ShiftImm; 3784 OS << ">"; 3785 break; 3786 case k_ProcIFlags: { 3787 OS << "<ARM_PROC::"; 3788 unsigned IFlags = getProcIFlags(); 3789 for (int i=2; i >= 0; --i) 3790 if (IFlags & (1 << i)) 3791 OS << ARM_PROC::IFlagsToString(1 << i); 3792 OS << ">"; 3793 break; 3794 } 3795 case k_Register: 3796 OS << "<register " << RegName(getReg()) << ">"; 3797 break; 3798 case k_ShifterImmediate: 3799 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 3800 << " #" << ShifterImm.Imm << ">"; 3801 break; 3802 case k_ShiftedRegister: 3803 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " " 3804 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " " 3805 << RegName(RegShiftedReg.ShiftReg) << ">"; 3806 break; 3807 case k_ShiftedImmediate: 3808 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " " 3809 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #" 3810 << RegShiftedImm.ShiftImm << ">"; 3811 break; 3812 case k_RotateImmediate: 3813 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 3814 break; 3815 case k_ModifiedImmediate: 3816 OS << "<mod_imm #" << ModImm.Bits << ", #" 3817 << ModImm.Rot << ")>"; 3818 break; 3819 case k_ConstantPoolImmediate: 3820 OS << "<constant_pool_imm #" << *getConstantPoolImm(); 3821 break; 3822 case k_BitfieldDescriptor: 3823 OS << "<bitfield " << "lsb: " << Bitfield.LSB 3824 << ", width: " << Bitfield.Width << ">"; 3825 break; 3826 case k_RegisterList: 3827 case k_RegisterListWithAPSR: 3828 case k_DPRRegisterList: 3829 case k_SPRRegisterList: 3830 case k_FPSRegisterListWithVPR: 3831 case k_FPDRegisterListWithVPR: { 3832 OS << "<register_list "; 3833 3834 const SmallVectorImpl<unsigned> &RegList = getRegList(); 3835 for (SmallVectorImpl<unsigned>::const_iterator 3836 I = RegList.begin(), E = RegList.end(); I != E; ) { 3837 OS << RegName(*I); 3838 if (++I < E) OS << ", "; 3839 } 3840 3841 OS << ">"; 3842 break; 3843 } 3844 case k_VectorList: 3845 OS << "<vector_list " << VectorList.Count << " * " 3846 << RegName(VectorList.RegNum) << ">"; 3847 break; 3848 case k_VectorListAllLanes: 3849 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 3850 << RegName(VectorList.RegNum) << ">"; 3851 break; 3852 case k_VectorListIndexed: 3853 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 3854 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">"; 3855 break; 3856 case k_Token: 3857 OS << "'" << getToken() << "'"; 3858 break; 3859 case k_VectorIndex: 3860 OS << "<vectorindex " << getVectorIndex() << ">"; 3861 break; 3862 } 3863 } 3864 3865 /// @name Auto-generated Match Functions 3866 /// { 3867 3868 static unsigned MatchRegisterName(StringRef Name); 3869 3870 /// } 3871 3872 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 3873 SMLoc &StartLoc, SMLoc &EndLoc) { 3874 const AsmToken &Tok = getParser().getTok(); 3875 StartLoc = Tok.getLoc(); 3876 EndLoc = Tok.getEndLoc(); 3877 RegNo = tryParseRegister(); 3878 3879 return (RegNo == (unsigned)-1); 3880 } 3881 3882 /// Try to parse a register name. The token must be an Identifier when called, 3883 /// and if it is a register name the token is eaten and the register number is 3884 /// returned. Otherwise return -1. 3885 int ARMAsmParser::tryParseRegister() { 3886 MCAsmParser &Parser = getParser(); 3887 const AsmToken &Tok = Parser.getTok(); 3888 if (Tok.isNot(AsmToken::Identifier)) return -1; 3889 3890 std::string lowerCase = Tok.getString().lower(); 3891 unsigned RegNum = MatchRegisterName(lowerCase); 3892 if (!RegNum) { 3893 RegNum = StringSwitch<unsigned>(lowerCase) 3894 .Case("r13", ARM::SP) 3895 .Case("r14", ARM::LR) 3896 .Case("r15", ARM::PC) 3897 .Case("ip", ARM::R12) 3898 // Additional register name aliases for 'gas' compatibility. 3899 .Case("a1", ARM::R0) 3900 .Case("a2", ARM::R1) 3901 .Case("a3", ARM::R2) 3902 .Case("a4", ARM::R3) 3903 .Case("v1", ARM::R4) 3904 .Case("v2", ARM::R5) 3905 .Case("v3", ARM::R6) 3906 .Case("v4", ARM::R7) 3907 .Case("v5", ARM::R8) 3908 .Case("v6", ARM::R9) 3909 .Case("v7", ARM::R10) 3910 .Case("v8", ARM::R11) 3911 .Case("sb", ARM::R9) 3912 .Case("sl", ARM::R10) 3913 .Case("fp", ARM::R11) 3914 .Default(0); 3915 } 3916 if (!RegNum) { 3917 // Check for aliases registered via .req. Canonicalize to lower case. 3918 // That's more consistent since register names are case insensitive, and 3919 // it's how the original entry was passed in from MC/MCParser/AsmParser. 3920 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 3921 // If no match, return failure. 3922 if (Entry == RegisterReqs.end()) 3923 return -1; 3924 Parser.Lex(); // Eat identifier token. 3925 return Entry->getValue(); 3926 } 3927 3928 // Some FPUs only have 16 D registers, so D16-D31 are invalid 3929 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) 3930 return -1; 3931 3932 Parser.Lex(); // Eat identifier token. 3933 3934 return RegNum; 3935 } 3936 3937 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 3938 // If a recoverable error occurs, return 1. If an irrecoverable error 3939 // occurs, return -1. An irrecoverable error is one where tokens have been 3940 // consumed in the process of trying to parse the shifter (i.e., when it is 3941 // indeed a shifter operand, but malformed). 3942 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { 3943 MCAsmParser &Parser = getParser(); 3944 SMLoc S = Parser.getTok().getLoc(); 3945 const AsmToken &Tok = Parser.getTok(); 3946 if (Tok.isNot(AsmToken::Identifier)) 3947 return -1; 3948 3949 std::string lowerCase = Tok.getString().lower(); 3950 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 3951 .Case("asl", ARM_AM::lsl) 3952 .Case("lsl", ARM_AM::lsl) 3953 .Case("lsr", ARM_AM::lsr) 3954 .Case("asr", ARM_AM::asr) 3955 .Case("ror", ARM_AM::ror) 3956 .Case("rrx", ARM_AM::rrx) 3957 .Default(ARM_AM::no_shift); 3958 3959 if (ShiftTy == ARM_AM::no_shift) 3960 return 1; 3961 3962 Parser.Lex(); // Eat the operator. 3963 3964 // The source register for the shift has already been added to the 3965 // operand list, so we need to pop it off and combine it into the shifted 3966 // register operand instead. 3967 std::unique_ptr<ARMOperand> PrevOp( 3968 (ARMOperand *)Operands.pop_back_val().release()); 3969 if (!PrevOp->isReg()) 3970 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 3971 int SrcReg = PrevOp->getReg(); 3972 3973 SMLoc EndLoc; 3974 int64_t Imm = 0; 3975 int ShiftReg = 0; 3976 if (ShiftTy == ARM_AM::rrx) { 3977 // RRX Doesn't have an explicit shift amount. The encoder expects 3978 // the shift register to be the same as the source register. Seems odd, 3979 // but OK. 3980 ShiftReg = SrcReg; 3981 } else { 3982 // Figure out if this is shifted by a constant or a register (for non-RRX). 3983 if (Parser.getTok().is(AsmToken::Hash) || 3984 Parser.getTok().is(AsmToken::Dollar)) { 3985 Parser.Lex(); // Eat hash. 3986 SMLoc ImmLoc = Parser.getTok().getLoc(); 3987 const MCExpr *ShiftExpr = nullptr; 3988 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 3989 Error(ImmLoc, "invalid immediate shift value"); 3990 return -1; 3991 } 3992 // The expression must be evaluatable as an immediate. 3993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 3994 if (!CE) { 3995 Error(ImmLoc, "invalid immediate shift value"); 3996 return -1; 3997 } 3998 // Range check the immediate. 3999 // lsl, ror: 0 <= imm <= 31 4000 // lsr, asr: 0 <= imm <= 32 4001 Imm = CE->getValue(); 4002 if (Imm < 0 || 4003 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 4004 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 4005 Error(ImmLoc, "immediate shift value out of range"); 4006 return -1; 4007 } 4008 // shift by zero is a nop. Always send it through as lsl. 4009 // ('as' compatibility) 4010 if (Imm == 0) 4011 ShiftTy = ARM_AM::lsl; 4012 } else if (Parser.getTok().is(AsmToken::Identifier)) { 4013 SMLoc L = Parser.getTok().getLoc(); 4014 EndLoc = Parser.getTok().getEndLoc(); 4015 ShiftReg = tryParseRegister(); 4016 if (ShiftReg == -1) { 4017 Error(L, "expected immediate or register in shift operand"); 4018 return -1; 4019 } 4020 } else { 4021 Error(Parser.getTok().getLoc(), 4022 "expected immediate or register in shift operand"); 4023 return -1; 4024 } 4025 } 4026 4027 if (ShiftReg && ShiftTy != ARM_AM::rrx) 4028 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 4029 ShiftReg, Imm, 4030 S, EndLoc)); 4031 else 4032 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 4033 S, EndLoc)); 4034 4035 return 0; 4036 } 4037 4038 /// Try to parse a register name. The token must be an Identifier when called. 4039 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 4040 /// if there is a "writeback". 'true' if it's not a register. 4041 /// 4042 /// TODO this is likely to change to allow different register types and or to 4043 /// parse for a specific register type. 4044 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { 4045 MCAsmParser &Parser = getParser(); 4046 SMLoc RegStartLoc = Parser.getTok().getLoc(); 4047 SMLoc RegEndLoc = Parser.getTok().getEndLoc(); 4048 int RegNo = tryParseRegister(); 4049 if (RegNo == -1) 4050 return true; 4051 4052 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); 4053 4054 const AsmToken &ExclaimTok = Parser.getTok(); 4055 if (ExclaimTok.is(AsmToken::Exclaim)) { 4056 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 4057 ExclaimTok.getLoc())); 4058 Parser.Lex(); // Eat exclaim token 4059 return false; 4060 } 4061 4062 // Also check for an index operand. This is only legal for vector registers, 4063 // but that'll get caught OK in operand matching, so we don't need to 4064 // explicitly filter everything else out here. 4065 if (Parser.getTok().is(AsmToken::LBrac)) { 4066 SMLoc SIdx = Parser.getTok().getLoc(); 4067 Parser.Lex(); // Eat left bracket token. 4068 4069 const MCExpr *ImmVal; 4070 if (getParser().parseExpression(ImmVal)) 4071 return true; 4072 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 4073 if (!MCE) 4074 return TokError("immediate value expected for vector index"); 4075 4076 if (Parser.getTok().isNot(AsmToken::RBrac)) 4077 return Error(Parser.getTok().getLoc(), "']' expected"); 4078 4079 SMLoc E = Parser.getTok().getEndLoc(); 4080 Parser.Lex(); // Eat right bracket token. 4081 4082 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 4083 SIdx, E, 4084 getContext())); 4085 } 4086 4087 return false; 4088 } 4089 4090 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 4091 /// instruction with a symbolic operand name. 4092 /// We accept "crN" syntax for GAS compatibility. 4093 /// <operand-name> ::= <prefix><number> 4094 /// If CoprocOp is 'c', then: 4095 /// <prefix> ::= c | cr 4096 /// If CoprocOp is 'p', then : 4097 /// <prefix> ::= p 4098 /// <number> ::= integer in range [0, 15] 4099 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 4100 // Use the same layout as the tablegen'erated register name matcher. Ugly, 4101 // but efficient. 4102 if (Name.size() < 2 || Name[0] != CoprocOp) 4103 return -1; 4104 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); 4105 4106 switch (Name.size()) { 4107 default: return -1; 4108 case 1: 4109 switch (Name[0]) { 4110 default: return -1; 4111 case '0': return 0; 4112 case '1': return 1; 4113 case '2': return 2; 4114 case '3': return 3; 4115 case '4': return 4; 4116 case '5': return 5; 4117 case '6': return 6; 4118 case '7': return 7; 4119 case '8': return 8; 4120 case '9': return 9; 4121 } 4122 case 2: 4123 if (Name[0] != '1') 4124 return -1; 4125 switch (Name[1]) { 4126 default: return -1; 4127 // CP10 and CP11 are VFP/NEON and so vector instructions should be used. 4128 // However, old cores (v5/v6) did use them in that way. 4129 case '0': return 10; 4130 case '1': return 11; 4131 case '2': return 12; 4132 case '3': return 13; 4133 case '4': return 14; 4134 case '5': return 15; 4135 } 4136 } 4137 } 4138 4139 /// parseITCondCode - Try to parse a condition code for an IT instruction. 4140 OperandMatchResultTy 4141 ARMAsmParser::parseITCondCode(OperandVector &Operands) { 4142 MCAsmParser &Parser = getParser(); 4143 SMLoc S = Parser.getTok().getLoc(); 4144 const AsmToken &Tok = Parser.getTok(); 4145 if (!Tok.is(AsmToken::Identifier)) 4146 return MatchOperand_NoMatch; 4147 unsigned CC = ARMCondCodeFromString(Tok.getString()); 4148 if (CC == ~0U) 4149 return MatchOperand_NoMatch; 4150 Parser.Lex(); // Eat the token. 4151 4152 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 4153 4154 return MatchOperand_Success; 4155 } 4156 4157 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 4158 /// token must be an Identifier when called, and if it is a coprocessor 4159 /// number, the token is eaten and the operand is added to the operand list. 4160 OperandMatchResultTy 4161 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { 4162 MCAsmParser &Parser = getParser(); 4163 SMLoc S = Parser.getTok().getLoc(); 4164 const AsmToken &Tok = Parser.getTok(); 4165 if (Tok.isNot(AsmToken::Identifier)) 4166 return MatchOperand_NoMatch; 4167 4168 int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p'); 4169 if (Num == -1) 4170 return MatchOperand_NoMatch; 4171 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits())) 4172 return MatchOperand_NoMatch; 4173 4174 Parser.Lex(); // Eat identifier token. 4175 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 4176 return MatchOperand_Success; 4177 } 4178 4179 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 4180 /// token must be an Identifier when called, and if it is a coprocessor 4181 /// number, the token is eaten and the operand is added to the operand list. 4182 OperandMatchResultTy 4183 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { 4184 MCAsmParser &Parser = getParser(); 4185 SMLoc S = Parser.getTok().getLoc(); 4186 const AsmToken &Tok = Parser.getTok(); 4187 if (Tok.isNot(AsmToken::Identifier)) 4188 return MatchOperand_NoMatch; 4189 4190 int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c'); 4191 if (Reg == -1) 4192 return MatchOperand_NoMatch; 4193 4194 Parser.Lex(); // Eat identifier token. 4195 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 4196 return MatchOperand_Success; 4197 } 4198 4199 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 4200 /// coproc_option : '{' imm0_255 '}' 4201 OperandMatchResultTy 4202 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { 4203 MCAsmParser &Parser = getParser(); 4204 SMLoc S = Parser.getTok().getLoc(); 4205 4206 // If this isn't a '{', this isn't a coprocessor immediate operand. 4207 if (Parser.getTok().isNot(AsmToken::LCurly)) 4208 return MatchOperand_NoMatch; 4209 Parser.Lex(); // Eat the '{' 4210 4211 const MCExpr *Expr; 4212 SMLoc Loc = Parser.getTok().getLoc(); 4213 if (getParser().parseExpression(Expr)) { 4214 Error(Loc, "illegal expression"); 4215 return MatchOperand_ParseFail; 4216 } 4217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4218 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 4219 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 4220 return MatchOperand_ParseFail; 4221 } 4222 int Val = CE->getValue(); 4223 4224 // Check for and consume the closing '}' 4225 if (Parser.getTok().isNot(AsmToken::RCurly)) 4226 return MatchOperand_ParseFail; 4227 SMLoc E = Parser.getTok().getEndLoc(); 4228 Parser.Lex(); // Eat the '}' 4229 4230 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 4231 return MatchOperand_Success; 4232 } 4233 4234 // For register list parsing, we need to map from raw GPR register numbering 4235 // to the enumeration values. The enumeration values aren't sorted by 4236 // register number due to our using "sp", "lr" and "pc" as canonical names. 4237 static unsigned getNextRegister(unsigned Reg) { 4238 // If this is a GPR, we need to do it manually, otherwise we can rely 4239 // on the sort ordering of the enumeration since the other reg-classes 4240 // are sane. 4241 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 4242 return Reg + 1; 4243 switch(Reg) { 4244 default: llvm_unreachable("Invalid GPR number!"); 4245 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 4246 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 4247 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 4248 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 4249 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 4250 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 4251 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 4252 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 4253 } 4254 } 4255 4256 /// Parse a register list. 4257 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, 4258 bool EnforceOrder) { 4259 MCAsmParser &Parser = getParser(); 4260 if (Parser.getTok().isNot(AsmToken::LCurly)) 4261 return TokError("Token is not a Left Curly Brace"); 4262 SMLoc S = Parser.getTok().getLoc(); 4263 Parser.Lex(); // Eat '{' token. 4264 SMLoc RegLoc = Parser.getTok().getLoc(); 4265 4266 // Check the first register in the list to see what register class 4267 // this is a list of. 4268 int Reg = tryParseRegister(); 4269 if (Reg == -1) 4270 return Error(RegLoc, "register expected"); 4271 4272 // The reglist instructions have at most 16 registers, so reserve 4273 // space for that many. 4274 int EReg = 0; 4275 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 4276 4277 // Allow Q regs and just interpret them as the two D sub-registers. 4278 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 4279 Reg = getDRegFromQReg(Reg); 4280 EReg = MRI->getEncodingValue(Reg); 4281 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4282 ++Reg; 4283 } 4284 const MCRegisterClass *RC; 4285 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 4286 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 4287 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 4288 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 4289 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 4290 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 4291 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) 4292 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; 4293 else 4294 return Error(RegLoc, "invalid register in register list"); 4295 4296 // Store the register. 4297 EReg = MRI->getEncodingValue(Reg); 4298 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4299 4300 // This starts immediately after the first register token in the list, 4301 // so we can see either a comma or a minus (range separator) as a legal 4302 // next token. 4303 while (Parser.getTok().is(AsmToken::Comma) || 4304 Parser.getTok().is(AsmToken::Minus)) { 4305 if (Parser.getTok().is(AsmToken::Minus)) { 4306 Parser.Lex(); // Eat the minus. 4307 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 4308 int EndReg = tryParseRegister(); 4309 if (EndReg == -1) 4310 return Error(AfterMinusLoc, "register expected"); 4311 // Allow Q regs and just interpret them as the two D sub-registers. 4312 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 4313 EndReg = getDRegFromQReg(EndReg) + 1; 4314 // If the register is the same as the start reg, there's nothing 4315 // more to do. 4316 if (Reg == EndReg) 4317 continue; 4318 // The register must be in the same register class as the first. 4319 if (!RC->contains(EndReg)) 4320 return Error(AfterMinusLoc, "invalid register in register list"); 4321 // Ranges must go from low to high. 4322 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 4323 return Error(AfterMinusLoc, "bad range in register list"); 4324 4325 // Add all the registers in the range to the register list. 4326 while (Reg != EndReg) { 4327 Reg = getNextRegister(Reg); 4328 EReg = MRI->getEncodingValue(Reg); 4329 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4330 } 4331 continue; 4332 } 4333 Parser.Lex(); // Eat the comma. 4334 RegLoc = Parser.getTok().getLoc(); 4335 int OldReg = Reg; 4336 const AsmToken RegTok = Parser.getTok(); 4337 Reg = tryParseRegister(); 4338 if (Reg == -1) 4339 return Error(RegLoc, "register expected"); 4340 // Allow Q regs and just interpret them as the two D sub-registers. 4341 bool isQReg = false; 4342 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 4343 Reg = getDRegFromQReg(Reg); 4344 isQReg = true; 4345 } 4346 if (!RC->contains(Reg) && 4347 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && 4348 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { 4349 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial 4350 // subset of GPRRegClassId except it contains APSR as well. 4351 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; 4352 } 4353 if (Reg == ARM::VPR && (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || 4354 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID])) { 4355 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; 4356 EReg = MRI->getEncodingValue(Reg); 4357 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4358 continue; 4359 } 4360 // The register must be in the same register class as the first. 4361 if (!RC->contains(Reg)) 4362 return Error(RegLoc, "invalid register in register list"); 4363 // In most cases, the list must be monotonically increasing. An 4364 // exception is CLRM, which is order-independent anyway, so 4365 // there's no potential for confusion if you write clrm {r2,r1} 4366 // instead of clrm {r1,r2}. 4367 if (EnforceOrder && 4368 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 4369 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 4370 Warning(RegLoc, "register list not in ascending order"); 4371 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) 4372 return Error(RegLoc, "register list not in ascending order"); 4373 } 4374 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 4375 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 4376 ") in register list"); 4377 continue; 4378 } 4379 // VFP register lists must also be contiguous. 4380 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 4381 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && 4382 Reg != OldReg + 1) 4383 return Error(RegLoc, "non-contiguous register range"); 4384 EReg = MRI->getEncodingValue(Reg); 4385 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4386 if (isQReg) { 4387 EReg = MRI->getEncodingValue(++Reg); 4388 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 4389 } 4390 } 4391 4392 if (Parser.getTok().isNot(AsmToken::RCurly)) 4393 return Error(Parser.getTok().getLoc(), "'}' expected"); 4394 SMLoc E = Parser.getTok().getEndLoc(); 4395 Parser.Lex(); // Eat '}' token. 4396 4397 // Push the register list operand. 4398 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 4399 4400 // The ARM system instruction variants for LDM/STM have a '^' token here. 4401 if (Parser.getTok().is(AsmToken::Caret)) { 4402 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 4403 Parser.Lex(); // Eat '^' token. 4404 } 4405 4406 return false; 4407 } 4408 4409 // Helper function to parse the lane index for vector lists. 4410 OperandMatchResultTy ARMAsmParser:: 4411 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 4412 MCAsmParser &Parser = getParser(); 4413 Index = 0; // Always return a defined index value. 4414 if (Parser.getTok().is(AsmToken::LBrac)) { 4415 Parser.Lex(); // Eat the '['. 4416 if (Parser.getTok().is(AsmToken::RBrac)) { 4417 // "Dn[]" is the 'all lanes' syntax. 4418 LaneKind = AllLanes; 4419 EndLoc = Parser.getTok().getEndLoc(); 4420 Parser.Lex(); // Eat the ']'. 4421 return MatchOperand_Success; 4422 } 4423 4424 // There's an optional '#' token here. Normally there wouldn't be, but 4425 // inline assemble puts one in, and it's friendly to accept that. 4426 if (Parser.getTok().is(AsmToken::Hash)) 4427 Parser.Lex(); // Eat '#' or '$'. 4428 4429 const MCExpr *LaneIndex; 4430 SMLoc Loc = Parser.getTok().getLoc(); 4431 if (getParser().parseExpression(LaneIndex)) { 4432 Error(Loc, "illegal expression"); 4433 return MatchOperand_ParseFail; 4434 } 4435 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 4436 if (!CE) { 4437 Error(Loc, "lane index must be empty or an integer"); 4438 return MatchOperand_ParseFail; 4439 } 4440 if (Parser.getTok().isNot(AsmToken::RBrac)) { 4441 Error(Parser.getTok().getLoc(), "']' expected"); 4442 return MatchOperand_ParseFail; 4443 } 4444 EndLoc = Parser.getTok().getEndLoc(); 4445 Parser.Lex(); // Eat the ']'. 4446 int64_t Val = CE->getValue(); 4447 4448 // FIXME: Make this range check context sensitive for .8, .16, .32. 4449 if (Val < 0 || Val > 7) { 4450 Error(Parser.getTok().getLoc(), "lane index out of range"); 4451 return MatchOperand_ParseFail; 4452 } 4453 Index = Val; 4454 LaneKind = IndexedLane; 4455 return MatchOperand_Success; 4456 } 4457 LaneKind = NoLanes; 4458 return MatchOperand_Success; 4459 } 4460 4461 // parse a vector register list 4462 OperandMatchResultTy 4463 ARMAsmParser::parseVectorList(OperandVector &Operands) { 4464 MCAsmParser &Parser = getParser(); 4465 VectorLaneTy LaneKind; 4466 unsigned LaneIndex; 4467 SMLoc S = Parser.getTok().getLoc(); 4468 // As an extension (to match gas), support a plain D register or Q register 4469 // (without encosing curly braces) as a single or double entry list, 4470 // respectively. 4471 if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) { 4472 SMLoc E = Parser.getTok().getEndLoc(); 4473 int Reg = tryParseRegister(); 4474 if (Reg == -1) 4475 return MatchOperand_NoMatch; 4476 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 4477 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 4478 if (Res != MatchOperand_Success) 4479 return Res; 4480 switch (LaneKind) { 4481 case NoLanes: 4482 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 4483 break; 4484 case AllLanes: 4485 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 4486 S, E)); 4487 break; 4488 case IndexedLane: 4489 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 4490 LaneIndex, 4491 false, S, E)); 4492 break; 4493 } 4494 return MatchOperand_Success; 4495 } 4496 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 4497 Reg = getDRegFromQReg(Reg); 4498 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 4499 if (Res != MatchOperand_Success) 4500 return Res; 4501 switch (LaneKind) { 4502 case NoLanes: 4503 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 4504 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 4505 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 4506 break; 4507 case AllLanes: 4508 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 4509 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 4510 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 4511 S, E)); 4512 break; 4513 case IndexedLane: 4514 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 4515 LaneIndex, 4516 false, S, E)); 4517 break; 4518 } 4519 return MatchOperand_Success; 4520 } 4521 Error(S, "vector register expected"); 4522 return MatchOperand_ParseFail; 4523 } 4524 4525 if (Parser.getTok().isNot(AsmToken::LCurly)) 4526 return MatchOperand_NoMatch; 4527 4528 Parser.Lex(); // Eat '{' token. 4529 SMLoc RegLoc = Parser.getTok().getLoc(); 4530 4531 int Reg = tryParseRegister(); 4532 if (Reg == -1) { 4533 Error(RegLoc, "register expected"); 4534 return MatchOperand_ParseFail; 4535 } 4536 unsigned Count = 1; 4537 int Spacing = 0; 4538 unsigned FirstReg = Reg; 4539 4540 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { 4541 Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected"); 4542 return MatchOperand_ParseFail; 4543 } 4544 // The list is of D registers, but we also allow Q regs and just interpret 4545 // them as the two D sub-registers. 4546 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 4547 FirstReg = Reg = getDRegFromQReg(Reg); 4548 Spacing = 1; // double-spacing requires explicit D registers, otherwise 4549 // it's ambiguous with four-register single spaced. 4550 ++Reg; 4551 ++Count; 4552 } 4553 4554 SMLoc E; 4555 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 4556 return MatchOperand_ParseFail; 4557 4558 while (Parser.getTok().is(AsmToken::Comma) || 4559 Parser.getTok().is(AsmToken::Minus)) { 4560 if (Parser.getTok().is(AsmToken::Minus)) { 4561 if (!Spacing) 4562 Spacing = 1; // Register range implies a single spaced list. 4563 else if (Spacing == 2) { 4564 Error(Parser.getTok().getLoc(), 4565 "sequential registers in double spaced list"); 4566 return MatchOperand_ParseFail; 4567 } 4568 Parser.Lex(); // Eat the minus. 4569 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 4570 int EndReg = tryParseRegister(); 4571 if (EndReg == -1) { 4572 Error(AfterMinusLoc, "register expected"); 4573 return MatchOperand_ParseFail; 4574 } 4575 // Allow Q regs and just interpret them as the two D sub-registers. 4576 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 4577 EndReg = getDRegFromQReg(EndReg) + 1; 4578 // If the register is the same as the start reg, there's nothing 4579 // more to do. 4580 if (Reg == EndReg) 4581 continue; 4582 // The register must be in the same register class as the first. 4583 if ((hasMVE() && 4584 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || 4585 (!hasMVE() && 4586 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { 4587 Error(AfterMinusLoc, "invalid register in register list"); 4588 return MatchOperand_ParseFail; 4589 } 4590 // Ranges must go from low to high. 4591 if (Reg > EndReg) { 4592 Error(AfterMinusLoc, "bad range in register list"); 4593 return MatchOperand_ParseFail; 4594 } 4595 // Parse the lane specifier if present. 4596 VectorLaneTy NextLaneKind; 4597 unsigned NextLaneIndex; 4598 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 4599 MatchOperand_Success) 4600 return MatchOperand_ParseFail; 4601 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 4602 Error(AfterMinusLoc, "mismatched lane index in register list"); 4603 return MatchOperand_ParseFail; 4604 } 4605 4606 // Add all the registers in the range to the register list. 4607 Count += EndReg - Reg; 4608 Reg = EndReg; 4609 continue; 4610 } 4611 Parser.Lex(); // Eat the comma. 4612 RegLoc = Parser.getTok().getLoc(); 4613 int OldReg = Reg; 4614 Reg = tryParseRegister(); 4615 if (Reg == -1) { 4616 Error(RegLoc, "register expected"); 4617 return MatchOperand_ParseFail; 4618 } 4619 4620 if (hasMVE()) { 4621 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { 4622 Error(RegLoc, "vector register in range Q0-Q7 expected"); 4623 return MatchOperand_ParseFail; 4624 } 4625 Spacing = 1; 4626 } 4627 // vector register lists must be contiguous. 4628 // It's OK to use the enumeration values directly here rather, as the 4629 // VFP register classes have the enum sorted properly. 4630 // 4631 // The list is of D registers, but we also allow Q regs and just interpret 4632 // them as the two D sub-registers. 4633 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 4634 if (!Spacing) 4635 Spacing = 1; // Register range implies a single spaced list. 4636 else if (Spacing == 2) { 4637 Error(RegLoc, 4638 "invalid register in double-spaced list (must be 'D' register')"); 4639 return MatchOperand_ParseFail; 4640 } 4641 Reg = getDRegFromQReg(Reg); 4642 if (Reg != OldReg + 1) { 4643 Error(RegLoc, "non-contiguous register range"); 4644 return MatchOperand_ParseFail; 4645 } 4646 ++Reg; 4647 Count += 2; 4648 // Parse the lane specifier if present. 4649 VectorLaneTy NextLaneKind; 4650 unsigned NextLaneIndex; 4651 SMLoc LaneLoc = Parser.getTok().getLoc(); 4652 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 4653 MatchOperand_Success) 4654 return MatchOperand_ParseFail; 4655 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 4656 Error(LaneLoc, "mismatched lane index in register list"); 4657 return MatchOperand_ParseFail; 4658 } 4659 continue; 4660 } 4661 // Normal D register. 4662 // Figure out the register spacing (single or double) of the list if 4663 // we don't know it already. 4664 if (!Spacing) 4665 Spacing = 1 + (Reg == OldReg + 2); 4666 4667 // Just check that it's contiguous and keep going. 4668 if (Reg != OldReg + Spacing) { 4669 Error(RegLoc, "non-contiguous register range"); 4670 return MatchOperand_ParseFail; 4671 } 4672 ++Count; 4673 // Parse the lane specifier if present. 4674 VectorLaneTy NextLaneKind; 4675 unsigned NextLaneIndex; 4676 SMLoc EndLoc = Parser.getTok().getLoc(); 4677 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 4678 return MatchOperand_ParseFail; 4679 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 4680 Error(EndLoc, "mismatched lane index in register list"); 4681 return MatchOperand_ParseFail; 4682 } 4683 } 4684 4685 if (Parser.getTok().isNot(AsmToken::RCurly)) { 4686 Error(Parser.getTok().getLoc(), "'}' expected"); 4687 return MatchOperand_ParseFail; 4688 } 4689 E = Parser.getTok().getEndLoc(); 4690 Parser.Lex(); // Eat '}' token. 4691 4692 switch (LaneKind) { 4693 case NoLanes: 4694 case AllLanes: { 4695 // Two-register operands have been converted to the 4696 // composite register classes. 4697 if (Count == 2 && !hasMVE()) { 4698 const MCRegisterClass *RC = (Spacing == 1) ? 4699 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 4700 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 4701 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 4702 } 4703 auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : 4704 ARMOperand::CreateVectorListAllLanes); 4705 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); 4706 break; 4707 } 4708 case IndexedLane: 4709 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 4710 LaneIndex, 4711 (Spacing == 2), 4712 S, E)); 4713 break; 4714 } 4715 return MatchOperand_Success; 4716 } 4717 4718 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 4719 OperandMatchResultTy 4720 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { 4721 MCAsmParser &Parser = getParser(); 4722 SMLoc S = Parser.getTok().getLoc(); 4723 const AsmToken &Tok = Parser.getTok(); 4724 unsigned Opt; 4725 4726 if (Tok.is(AsmToken::Identifier)) { 4727 StringRef OptStr = Tok.getString(); 4728 4729 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 4730 .Case("sy", ARM_MB::SY) 4731 .Case("st", ARM_MB::ST) 4732 .Case("ld", ARM_MB::LD) 4733 .Case("sh", ARM_MB::ISH) 4734 .Case("ish", ARM_MB::ISH) 4735 .Case("shst", ARM_MB::ISHST) 4736 .Case("ishst", ARM_MB::ISHST) 4737 .Case("ishld", ARM_MB::ISHLD) 4738 .Case("nsh", ARM_MB::NSH) 4739 .Case("un", ARM_MB::NSH) 4740 .Case("nshst", ARM_MB::NSHST) 4741 .Case("nshld", ARM_MB::NSHLD) 4742 .Case("unst", ARM_MB::NSHST) 4743 .Case("osh", ARM_MB::OSH) 4744 .Case("oshst", ARM_MB::OSHST) 4745 .Case("oshld", ARM_MB::OSHLD) 4746 .Default(~0U); 4747 4748 // ishld, oshld, nshld and ld are only available from ARMv8. 4749 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 4750 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 4751 Opt = ~0U; 4752 4753 if (Opt == ~0U) 4754 return MatchOperand_NoMatch; 4755 4756 Parser.Lex(); // Eat identifier token. 4757 } else if (Tok.is(AsmToken::Hash) || 4758 Tok.is(AsmToken::Dollar) || 4759 Tok.is(AsmToken::Integer)) { 4760 if (Parser.getTok().isNot(AsmToken::Integer)) 4761 Parser.Lex(); // Eat '#' or '$'. 4762 SMLoc Loc = Parser.getTok().getLoc(); 4763 4764 const MCExpr *MemBarrierID; 4765 if (getParser().parseExpression(MemBarrierID)) { 4766 Error(Loc, "illegal expression"); 4767 return MatchOperand_ParseFail; 4768 } 4769 4770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 4771 if (!CE) { 4772 Error(Loc, "constant expression expected"); 4773 return MatchOperand_ParseFail; 4774 } 4775 4776 int Val = CE->getValue(); 4777 if (Val & ~0xf) { 4778 Error(Loc, "immediate value out of range"); 4779 return MatchOperand_ParseFail; 4780 } 4781 4782 Opt = ARM_MB::RESERVED_0 + Val; 4783 } else 4784 return MatchOperand_ParseFail; 4785 4786 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 4787 return MatchOperand_Success; 4788 } 4789 4790 OperandMatchResultTy 4791 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { 4792 MCAsmParser &Parser = getParser(); 4793 SMLoc S = Parser.getTok().getLoc(); 4794 const AsmToken &Tok = Parser.getTok(); 4795 4796 if (Tok.isNot(AsmToken::Identifier)) 4797 return MatchOperand_NoMatch; 4798 4799 if (!Tok.getString().equals_lower("csync")) 4800 return MatchOperand_NoMatch; 4801 4802 Parser.Lex(); // Eat identifier token. 4803 4804 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); 4805 return MatchOperand_Success; 4806 } 4807 4808 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 4809 OperandMatchResultTy 4810 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { 4811 MCAsmParser &Parser = getParser(); 4812 SMLoc S = Parser.getTok().getLoc(); 4813 const AsmToken &Tok = Parser.getTok(); 4814 unsigned Opt; 4815 4816 if (Tok.is(AsmToken::Identifier)) { 4817 StringRef OptStr = Tok.getString(); 4818 4819 if (OptStr.equals_lower("sy")) 4820 Opt = ARM_ISB::SY; 4821 else 4822 return MatchOperand_NoMatch; 4823 4824 Parser.Lex(); // Eat identifier token. 4825 } else if (Tok.is(AsmToken::Hash) || 4826 Tok.is(AsmToken::Dollar) || 4827 Tok.is(AsmToken::Integer)) { 4828 if (Parser.getTok().isNot(AsmToken::Integer)) 4829 Parser.Lex(); // Eat '#' or '$'. 4830 SMLoc Loc = Parser.getTok().getLoc(); 4831 4832 const MCExpr *ISBarrierID; 4833 if (getParser().parseExpression(ISBarrierID)) { 4834 Error(Loc, "illegal expression"); 4835 return MatchOperand_ParseFail; 4836 } 4837 4838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 4839 if (!CE) { 4840 Error(Loc, "constant expression expected"); 4841 return MatchOperand_ParseFail; 4842 } 4843 4844 int Val = CE->getValue(); 4845 if (Val & ~0xf) { 4846 Error(Loc, "immediate value out of range"); 4847 return MatchOperand_ParseFail; 4848 } 4849 4850 Opt = ARM_ISB::RESERVED_0 + Val; 4851 } else 4852 return MatchOperand_ParseFail; 4853 4854 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 4855 (ARM_ISB::InstSyncBOpt)Opt, S)); 4856 return MatchOperand_Success; 4857 } 4858 4859 4860 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 4861 OperandMatchResultTy 4862 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { 4863 MCAsmParser &Parser = getParser(); 4864 SMLoc S = Parser.getTok().getLoc(); 4865 const AsmToken &Tok = Parser.getTok(); 4866 if (!Tok.is(AsmToken::Identifier)) 4867 return MatchOperand_NoMatch; 4868 StringRef IFlagsStr = Tok.getString(); 4869 4870 // An iflags string of "none" is interpreted to mean that none of the AIF 4871 // bits are set. Not a terribly useful instruction, but a valid encoding. 4872 unsigned IFlags = 0; 4873 if (IFlagsStr != "none") { 4874 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 4875 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower()) 4876 .Case("a", ARM_PROC::A) 4877 .Case("i", ARM_PROC::I) 4878 .Case("f", ARM_PROC::F) 4879 .Default(~0U); 4880 4881 // If some specific iflag is already set, it means that some letter is 4882 // present more than once, this is not acceptable. 4883 if (Flag == ~0U || (IFlags & Flag)) 4884 return MatchOperand_NoMatch; 4885 4886 IFlags |= Flag; 4887 } 4888 } 4889 4890 Parser.Lex(); // Eat identifier token. 4891 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 4892 return MatchOperand_Success; 4893 } 4894 4895 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 4896 OperandMatchResultTy 4897 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { 4898 MCAsmParser &Parser = getParser(); 4899 SMLoc S = Parser.getTok().getLoc(); 4900 const AsmToken &Tok = Parser.getTok(); 4901 4902 if (Tok.is(AsmToken::Integer)) { 4903 int64_t Val = Tok.getIntVal(); 4904 if (Val > 255 || Val < 0) { 4905 return MatchOperand_NoMatch; 4906 } 4907 unsigned SYSmvalue = Val & 0xFF; 4908 Parser.Lex(); 4909 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); 4910 return MatchOperand_Success; 4911 } 4912 4913 if (!Tok.is(AsmToken::Identifier)) 4914 return MatchOperand_NoMatch; 4915 StringRef Mask = Tok.getString(); 4916 4917 if (isMClass()) { 4918 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower()); 4919 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits())) 4920 return MatchOperand_NoMatch; 4921 4922 unsigned SYSmvalue = TheReg->Encoding & 0xFFF; 4923 4924 Parser.Lex(); // Eat identifier token. 4925 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); 4926 return MatchOperand_Success; 4927 } 4928 4929 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 4930 size_t Start = 0, Next = Mask.find('_'); 4931 StringRef Flags = ""; 4932 std::string SpecReg = Mask.slice(Start, Next).lower(); 4933 if (Next != StringRef::npos) 4934 Flags = Mask.slice(Next+1, Mask.size()); 4935 4936 // FlagsVal contains the complete mask: 4937 // 3-0: Mask 4938 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4939 unsigned FlagsVal = 0; 4940 4941 if (SpecReg == "apsr") { 4942 FlagsVal = StringSwitch<unsigned>(Flags) 4943 .Case("nzcvq", 0x8) // same as CPSR_f 4944 .Case("g", 0x4) // same as CPSR_s 4945 .Case("nzcvqg", 0xc) // same as CPSR_fs 4946 .Default(~0U); 4947 4948 if (FlagsVal == ~0U) { 4949 if (!Flags.empty()) 4950 return MatchOperand_NoMatch; 4951 else 4952 FlagsVal = 8; // No flag 4953 } 4954 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 4955 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 4956 if (Flags == "all" || Flags == "") 4957 Flags = "fc"; 4958 for (int i = 0, e = Flags.size(); i != e; ++i) { 4959 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 4960 .Case("c", 1) 4961 .Case("x", 2) 4962 .Case("s", 4) 4963 .Case("f", 8) 4964 .Default(~0U); 4965 4966 // If some specific flag is already set, it means that some letter is 4967 // present more than once, this is not acceptable. 4968 if (Flag == ~0U || (FlagsVal & Flag)) 4969 return MatchOperand_NoMatch; 4970 FlagsVal |= Flag; 4971 } 4972 } else // No match for special register. 4973 return MatchOperand_NoMatch; 4974 4975 // Special register without flags is NOT equivalent to "fc" flags. 4976 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 4977 // two lines would enable gas compatibility at the expense of breaking 4978 // round-tripping. 4979 // 4980 // if (!FlagsVal) 4981 // FlagsVal = 0x9; 4982 4983 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4984 if (SpecReg == "spsr") 4985 FlagsVal |= 16; 4986 4987 Parser.Lex(); // Eat identifier token. 4988 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4989 return MatchOperand_Success; 4990 } 4991 4992 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for 4993 /// use in the MRS/MSR instructions added to support virtualization. 4994 OperandMatchResultTy 4995 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { 4996 MCAsmParser &Parser = getParser(); 4997 SMLoc S = Parser.getTok().getLoc(); 4998 const AsmToken &Tok = Parser.getTok(); 4999 if (!Tok.is(AsmToken::Identifier)) 5000 return MatchOperand_NoMatch; 5001 StringRef RegName = Tok.getString(); 5002 5003 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower()); 5004 if (!TheReg) 5005 return MatchOperand_NoMatch; 5006 unsigned Encoding = TheReg->Encoding; 5007 5008 Parser.Lex(); // Eat identifier token. 5009 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); 5010 return MatchOperand_Success; 5011 } 5012 5013 OperandMatchResultTy 5014 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, 5015 int High) { 5016 MCAsmParser &Parser = getParser(); 5017 const AsmToken &Tok = Parser.getTok(); 5018 if (Tok.isNot(AsmToken::Identifier)) { 5019 Error(Parser.getTok().getLoc(), Op + " operand expected."); 5020 return MatchOperand_ParseFail; 5021 } 5022 StringRef ShiftName = Tok.getString(); 5023 std::string LowerOp = Op.lower(); 5024 std::string UpperOp = Op.upper(); 5025 if (ShiftName != LowerOp && ShiftName != UpperOp) { 5026 Error(Parser.getTok().getLoc(), Op + " operand expected."); 5027 return MatchOperand_ParseFail; 5028 } 5029 Parser.Lex(); // Eat shift type token. 5030 5031 // There must be a '#' and a shift amount. 5032 if (Parser.getTok().isNot(AsmToken::Hash) && 5033 Parser.getTok().isNot(AsmToken::Dollar)) { 5034 Error(Parser.getTok().getLoc(), "'#' expected"); 5035 return MatchOperand_ParseFail; 5036 } 5037 Parser.Lex(); // Eat hash token. 5038 5039 const MCExpr *ShiftAmount; 5040 SMLoc Loc = Parser.getTok().getLoc(); 5041 SMLoc EndLoc; 5042 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 5043 Error(Loc, "illegal expression"); 5044 return MatchOperand_ParseFail; 5045 } 5046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 5047 if (!CE) { 5048 Error(Loc, "constant expression expected"); 5049 return MatchOperand_ParseFail; 5050 } 5051 int Val = CE->getValue(); 5052 if (Val < Low || Val > High) { 5053 Error(Loc, "immediate value out of range"); 5054 return MatchOperand_ParseFail; 5055 } 5056 5057 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 5058 5059 return MatchOperand_Success; 5060 } 5061 5062 OperandMatchResultTy 5063 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { 5064 MCAsmParser &Parser = getParser(); 5065 const AsmToken &Tok = Parser.getTok(); 5066 SMLoc S = Tok.getLoc(); 5067 if (Tok.isNot(AsmToken::Identifier)) { 5068 Error(S, "'be' or 'le' operand expected"); 5069 return MatchOperand_ParseFail; 5070 } 5071 int Val = StringSwitch<int>(Tok.getString().lower()) 5072 .Case("be", 1) 5073 .Case("le", 0) 5074 .Default(-1); 5075 Parser.Lex(); // Eat the token. 5076 5077 if (Val == -1) { 5078 Error(S, "'be' or 'le' operand expected"); 5079 return MatchOperand_ParseFail; 5080 } 5081 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, 5082 getContext()), 5083 S, Tok.getEndLoc())); 5084 return MatchOperand_Success; 5085 } 5086 5087 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 5088 /// instructions. Legal values are: 5089 /// lsl #n 'n' in [0,31] 5090 /// asr #n 'n' in [1,32] 5091 /// n == 32 encoded as n == 0. 5092 OperandMatchResultTy 5093 ARMAsmParser::parseShifterImm(OperandVector &Operands) { 5094 MCAsmParser &Parser = getParser(); 5095 const AsmToken &Tok = Parser.getTok(); 5096 SMLoc S = Tok.getLoc(); 5097 if (Tok.isNot(AsmToken::Identifier)) { 5098 Error(S, "shift operator 'asr' or 'lsl' expected"); 5099 return MatchOperand_ParseFail; 5100 } 5101 StringRef ShiftName = Tok.getString(); 5102 bool isASR; 5103 if (ShiftName == "lsl" || ShiftName == "LSL") 5104 isASR = false; 5105 else if (ShiftName == "asr" || ShiftName == "ASR") 5106 isASR = true; 5107 else { 5108 Error(S, "shift operator 'asr' or 'lsl' expected"); 5109 return MatchOperand_ParseFail; 5110 } 5111 Parser.Lex(); // Eat the operator. 5112 5113 // A '#' and a shift amount. 5114 if (Parser.getTok().isNot(AsmToken::Hash) && 5115 Parser.getTok().isNot(AsmToken::Dollar)) { 5116 Error(Parser.getTok().getLoc(), "'#' expected"); 5117 return MatchOperand_ParseFail; 5118 } 5119 Parser.Lex(); // Eat hash token. 5120 SMLoc ExLoc = Parser.getTok().getLoc(); 5121 5122 const MCExpr *ShiftAmount; 5123 SMLoc EndLoc; 5124 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 5125 Error(ExLoc, "malformed shift expression"); 5126 return MatchOperand_ParseFail; 5127 } 5128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 5129 if (!CE) { 5130 Error(ExLoc, "shift amount must be an immediate"); 5131 return MatchOperand_ParseFail; 5132 } 5133 5134 int64_t Val = CE->getValue(); 5135 if (isASR) { 5136 // Shift amount must be in [1,32] 5137 if (Val < 1 || Val > 32) { 5138 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 5139 return MatchOperand_ParseFail; 5140 } 5141 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 5142 if (isThumb() && Val == 32) { 5143 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 5144 return MatchOperand_ParseFail; 5145 } 5146 if (Val == 32) Val = 0; 5147 } else { 5148 // Shift amount must be in [1,32] 5149 if (Val < 0 || Val > 31) { 5150 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 5151 return MatchOperand_ParseFail; 5152 } 5153 } 5154 5155 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 5156 5157 return MatchOperand_Success; 5158 } 5159 5160 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 5161 /// of instructions. Legal values are: 5162 /// ror #n 'n' in {0, 8, 16, 24} 5163 OperandMatchResultTy 5164 ARMAsmParser::parseRotImm(OperandVector &Operands) { 5165 MCAsmParser &Parser = getParser(); 5166 const AsmToken &Tok = Parser.getTok(); 5167 SMLoc S = Tok.getLoc(); 5168 if (Tok.isNot(AsmToken::Identifier)) 5169 return MatchOperand_NoMatch; 5170 StringRef ShiftName = Tok.getString(); 5171 if (ShiftName != "ror" && ShiftName != "ROR") 5172 return MatchOperand_NoMatch; 5173 Parser.Lex(); // Eat the operator. 5174 5175 // A '#' and a rotate amount. 5176 if (Parser.getTok().isNot(AsmToken::Hash) && 5177 Parser.getTok().isNot(AsmToken::Dollar)) { 5178 Error(Parser.getTok().getLoc(), "'#' expected"); 5179 return MatchOperand_ParseFail; 5180 } 5181 Parser.Lex(); // Eat hash token. 5182 SMLoc ExLoc = Parser.getTok().getLoc(); 5183 5184 const MCExpr *ShiftAmount; 5185 SMLoc EndLoc; 5186 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 5187 Error(ExLoc, "malformed rotate expression"); 5188 return MatchOperand_ParseFail; 5189 } 5190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 5191 if (!CE) { 5192 Error(ExLoc, "rotate amount must be an immediate"); 5193 return MatchOperand_ParseFail; 5194 } 5195 5196 int64_t Val = CE->getValue(); 5197 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 5198 // normally, zero is represented in asm by omitting the rotate operand 5199 // entirely. 5200 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 5201 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 5202 return MatchOperand_ParseFail; 5203 } 5204 5205 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 5206 5207 return MatchOperand_Success; 5208 } 5209 5210 OperandMatchResultTy 5211 ARMAsmParser::parseModImm(OperandVector &Operands) { 5212 MCAsmParser &Parser = getParser(); 5213 MCAsmLexer &Lexer = getLexer(); 5214 int64_t Imm1, Imm2; 5215 5216 SMLoc S = Parser.getTok().getLoc(); 5217 5218 // 1) A mod_imm operand can appear in the place of a register name: 5219 // add r0, #mod_imm 5220 // add r0, r0, #mod_imm 5221 // to correctly handle the latter, we bail out as soon as we see an 5222 // identifier. 5223 // 5224 // 2) Similarly, we do not want to parse into complex operands: 5225 // mov r0, #mod_imm 5226 // mov r0, :lower16:(_foo) 5227 if (Parser.getTok().is(AsmToken::Identifier) || 5228 Parser.getTok().is(AsmToken::Colon)) 5229 return MatchOperand_NoMatch; 5230 5231 // Hash (dollar) is optional as per the ARMARM 5232 if (Parser.getTok().is(AsmToken::Hash) || 5233 Parser.getTok().is(AsmToken::Dollar)) { 5234 // Avoid parsing into complex operands (#:) 5235 if (Lexer.peekTok().is(AsmToken::Colon)) 5236 return MatchOperand_NoMatch; 5237 5238 // Eat the hash (dollar) 5239 Parser.Lex(); 5240 } 5241 5242 SMLoc Sx1, Ex1; 5243 Sx1 = Parser.getTok().getLoc(); 5244 const MCExpr *Imm1Exp; 5245 if (getParser().parseExpression(Imm1Exp, Ex1)) { 5246 Error(Sx1, "malformed expression"); 5247 return MatchOperand_ParseFail; 5248 } 5249 5250 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp); 5251 5252 if (CE) { 5253 // Immediate must fit within 32-bits 5254 Imm1 = CE->getValue(); 5255 int Enc = ARM_AM::getSOImmVal(Imm1); 5256 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { 5257 // We have a match! 5258 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), 5259 (Enc & 0xF00) >> 7, 5260 Sx1, Ex1)); 5261 return MatchOperand_Success; 5262 } 5263 5264 // We have parsed an immediate which is not for us, fallback to a plain 5265 // immediate. This can happen for instruction aliases. For an example, 5266 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform 5267 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite 5268 // instruction with a mod_imm operand. The alias is defined such that the 5269 // parser method is shared, that's why we have to do this here. 5270 if (Parser.getTok().is(AsmToken::EndOfStatement)) { 5271 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 5272 return MatchOperand_Success; 5273 } 5274 } else { 5275 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an 5276 // MCFixup). Fallback to a plain immediate. 5277 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 5278 return MatchOperand_Success; 5279 } 5280 5281 // From this point onward, we expect the input to be a (#bits, #rot) pair 5282 if (Parser.getTok().isNot(AsmToken::Comma)) { 5283 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); 5284 return MatchOperand_ParseFail; 5285 } 5286 5287 if (Imm1 & ~0xFF) { 5288 Error(Sx1, "immediate operand must a number in the range [0, 255]"); 5289 return MatchOperand_ParseFail; 5290 } 5291 5292 // Eat the comma 5293 Parser.Lex(); 5294 5295 // Repeat for #rot 5296 SMLoc Sx2, Ex2; 5297 Sx2 = Parser.getTok().getLoc(); 5298 5299 // Eat the optional hash (dollar) 5300 if (Parser.getTok().is(AsmToken::Hash) || 5301 Parser.getTok().is(AsmToken::Dollar)) 5302 Parser.Lex(); 5303 5304 const MCExpr *Imm2Exp; 5305 if (getParser().parseExpression(Imm2Exp, Ex2)) { 5306 Error(Sx2, "malformed expression"); 5307 return MatchOperand_ParseFail; 5308 } 5309 5310 CE = dyn_cast<MCConstantExpr>(Imm2Exp); 5311 5312 if (CE) { 5313 Imm2 = CE->getValue(); 5314 if (!(Imm2 & ~0x1E)) { 5315 // We have a match! 5316 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); 5317 return MatchOperand_Success; 5318 } 5319 Error(Sx2, "immediate operand must an even number in the range [0, 30]"); 5320 return MatchOperand_ParseFail; 5321 } else { 5322 Error(Sx2, "constant expression expected"); 5323 return MatchOperand_ParseFail; 5324 } 5325 } 5326 5327 OperandMatchResultTy 5328 ARMAsmParser::parseBitfield(OperandVector &Operands) { 5329 MCAsmParser &Parser = getParser(); 5330 SMLoc S = Parser.getTok().getLoc(); 5331 // The bitfield descriptor is really two operands, the LSB and the width. 5332 if (Parser.getTok().isNot(AsmToken::Hash) && 5333 Parser.getTok().isNot(AsmToken::Dollar)) { 5334 Error(Parser.getTok().getLoc(), "'#' expected"); 5335 return MatchOperand_ParseFail; 5336 } 5337 Parser.Lex(); // Eat hash token. 5338 5339 const MCExpr *LSBExpr; 5340 SMLoc E = Parser.getTok().getLoc(); 5341 if (getParser().parseExpression(LSBExpr)) { 5342 Error(E, "malformed immediate expression"); 5343 return MatchOperand_ParseFail; 5344 } 5345 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 5346 if (!CE) { 5347 Error(E, "'lsb' operand must be an immediate"); 5348 return MatchOperand_ParseFail; 5349 } 5350 5351 int64_t LSB = CE->getValue(); 5352 // The LSB must be in the range [0,31] 5353 if (LSB < 0 || LSB > 31) { 5354 Error(E, "'lsb' operand must be in the range [0,31]"); 5355 return MatchOperand_ParseFail; 5356 } 5357 E = Parser.getTok().getLoc(); 5358 5359 // Expect another immediate operand. 5360 if (Parser.getTok().isNot(AsmToken::Comma)) { 5361 Error(Parser.getTok().getLoc(), "too few operands"); 5362 return MatchOperand_ParseFail; 5363 } 5364 Parser.Lex(); // Eat hash token. 5365 if (Parser.getTok().isNot(AsmToken::Hash) && 5366 Parser.getTok().isNot(AsmToken::Dollar)) { 5367 Error(Parser.getTok().getLoc(), "'#' expected"); 5368 return MatchOperand_ParseFail; 5369 } 5370 Parser.Lex(); // Eat hash token. 5371 5372 const MCExpr *WidthExpr; 5373 SMLoc EndLoc; 5374 if (getParser().parseExpression(WidthExpr, EndLoc)) { 5375 Error(E, "malformed immediate expression"); 5376 return MatchOperand_ParseFail; 5377 } 5378 CE = dyn_cast<MCConstantExpr>(WidthExpr); 5379 if (!CE) { 5380 Error(E, "'width' operand must be an immediate"); 5381 return MatchOperand_ParseFail; 5382 } 5383 5384 int64_t Width = CE->getValue(); 5385 // The LSB must be in the range [1,32-lsb] 5386 if (Width < 1 || Width > 32 - LSB) { 5387 Error(E, "'width' operand must be in the range [1,32-lsb]"); 5388 return MatchOperand_ParseFail; 5389 } 5390 5391 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 5392 5393 return MatchOperand_Success; 5394 } 5395 5396 OperandMatchResultTy 5397 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { 5398 // Check for a post-index addressing register operand. Specifically: 5399 // postidx_reg := '+' register {, shift} 5400 // | '-' register {, shift} 5401 // | register {, shift} 5402 5403 // This method must return MatchOperand_NoMatch without consuming any tokens 5404 // in the case where there is no match, as other alternatives take other 5405 // parse methods. 5406 MCAsmParser &Parser = getParser(); 5407 AsmToken Tok = Parser.getTok(); 5408 SMLoc S = Tok.getLoc(); 5409 bool haveEaten = false; 5410 bool isAdd = true; 5411 if (Tok.is(AsmToken::Plus)) { 5412 Parser.Lex(); // Eat the '+' token. 5413 haveEaten = true; 5414 } else if (Tok.is(AsmToken::Minus)) { 5415 Parser.Lex(); // Eat the '-' token. 5416 isAdd = false; 5417 haveEaten = true; 5418 } 5419 5420 SMLoc E = Parser.getTok().getEndLoc(); 5421 int Reg = tryParseRegister(); 5422 if (Reg == -1) { 5423 if (!haveEaten) 5424 return MatchOperand_NoMatch; 5425 Error(Parser.getTok().getLoc(), "register expected"); 5426 return MatchOperand_ParseFail; 5427 } 5428 5429 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 5430 unsigned ShiftImm = 0; 5431 if (Parser.getTok().is(AsmToken::Comma)) { 5432 Parser.Lex(); // Eat the ','. 5433 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 5434 return MatchOperand_ParseFail; 5435 5436 // FIXME: Only approximates end...may include intervening whitespace. 5437 E = Parser.getTok().getLoc(); 5438 } 5439 5440 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 5441 ShiftImm, S, E)); 5442 5443 return MatchOperand_Success; 5444 } 5445 5446 OperandMatchResultTy 5447 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { 5448 // Check for a post-index addressing register operand. Specifically: 5449 // am3offset := '+' register 5450 // | '-' register 5451 // | register 5452 // | # imm 5453 // | # + imm 5454 // | # - imm 5455 5456 // This method must return MatchOperand_NoMatch without consuming any tokens 5457 // in the case where there is no match, as other alternatives take other 5458 // parse methods. 5459 MCAsmParser &Parser = getParser(); 5460 AsmToken Tok = Parser.getTok(); 5461 SMLoc S = Tok.getLoc(); 5462 5463 // Do immediates first, as we always parse those if we have a '#'. 5464 if (Parser.getTok().is(AsmToken::Hash) || 5465 Parser.getTok().is(AsmToken::Dollar)) { 5466 Parser.Lex(); // Eat '#' or '$'. 5467 // Explicitly look for a '-', as we need to encode negative zero 5468 // differently. 5469 bool isNegative = Parser.getTok().is(AsmToken::Minus); 5470 const MCExpr *Offset; 5471 SMLoc E; 5472 if (getParser().parseExpression(Offset, E)) 5473 return MatchOperand_ParseFail; 5474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 5475 if (!CE) { 5476 Error(S, "constant expression expected"); 5477 return MatchOperand_ParseFail; 5478 } 5479 // Negative zero is encoded as the flag value 5480 // std::numeric_limits<int32_t>::min(). 5481 int32_t Val = CE->getValue(); 5482 if (isNegative && Val == 0) 5483 Val = std::numeric_limits<int32_t>::min(); 5484 5485 Operands.push_back( 5486 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E)); 5487 5488 return MatchOperand_Success; 5489 } 5490 5491 bool haveEaten = false; 5492 bool isAdd = true; 5493 if (Tok.is(AsmToken::Plus)) { 5494 Parser.Lex(); // Eat the '+' token. 5495 haveEaten = true; 5496 } else if (Tok.is(AsmToken::Minus)) { 5497 Parser.Lex(); // Eat the '-' token. 5498 isAdd = false; 5499 haveEaten = true; 5500 } 5501 5502 Tok = Parser.getTok(); 5503 int Reg = tryParseRegister(); 5504 if (Reg == -1) { 5505 if (!haveEaten) 5506 return MatchOperand_NoMatch; 5507 Error(Tok.getLoc(), "register expected"); 5508 return MatchOperand_ParseFail; 5509 } 5510 5511 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 5512 0, S, Tok.getEndLoc())); 5513 5514 return MatchOperand_Success; 5515 } 5516 5517 /// Convert parsed operands to MCInst. Needed here because this instruction 5518 /// only has two register operands, but multiplication is commutative so 5519 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 5520 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, 5521 const OperandVector &Operands) { 5522 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); 5523 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); 5524 // If we have a three-operand form, make sure to set Rn to be the operand 5525 // that isn't the same as Rd. 5526 unsigned RegOp = 4; 5527 if (Operands.size() == 6 && 5528 ((ARMOperand &)*Operands[4]).getReg() == 5529 ((ARMOperand &)*Operands[3]).getReg()) 5530 RegOp = 5; 5531 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); 5532 Inst.addOperand(Inst.getOperand(0)); 5533 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); 5534 } 5535 5536 void ARMAsmParser::cvtThumbBranches(MCInst &Inst, 5537 const OperandVector &Operands) { 5538 int CondOp = -1, ImmOp = -1; 5539 switch(Inst.getOpcode()) { 5540 case ARM::tB: 5541 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 5542 5543 case ARM::t2B: 5544 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 5545 5546 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 5547 } 5548 // first decide whether or not the branch should be conditional 5549 // by looking at it's location relative to an IT block 5550 if(inITBlock()) { 5551 // inside an IT block we cannot have any conditional branches. any 5552 // such instructions needs to be converted to unconditional form 5553 switch(Inst.getOpcode()) { 5554 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 5555 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 5556 } 5557 } else { 5558 // outside IT blocks we can only have unconditional branches with AL 5559 // condition code or conditional branches with non-AL condition code 5560 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); 5561 switch(Inst.getOpcode()) { 5562 case ARM::tB: 5563 case ARM::tBcc: 5564 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 5565 break; 5566 case ARM::t2B: 5567 case ARM::t2Bcc: 5568 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 5569 break; 5570 } 5571 } 5572 5573 // now decide on encoding size based on branch target range 5574 switch(Inst.getOpcode()) { 5575 // classify tB as either t2B or t1B based on range of immediate operand 5576 case ARM::tB: { 5577 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 5578 if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline()) 5579 Inst.setOpcode(ARM::t2B); 5580 break; 5581 } 5582 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 5583 case ARM::tBcc: { 5584 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 5585 if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline()) 5586 Inst.setOpcode(ARM::t2Bcc); 5587 break; 5588 } 5589 } 5590 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); 5591 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); 5592 } 5593 5594 void ARMAsmParser::cvtMVEVMOVQtoDReg( 5595 MCInst &Inst, const OperandVector &Operands) { 5596 5597 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2 5598 assert(Operands.size() == 8); 5599 5600 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt 5601 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 5602 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd 5603 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx 5604 // skip second copy of Qd in Operands[6] 5605 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 5606 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code 5607 } 5608 5609 /// Parse an ARM memory expression, return false if successful else return true 5610 /// or an error. The first token must be a '[' when called. 5611 bool ARMAsmParser::parseMemory(OperandVector &Operands) { 5612 MCAsmParser &Parser = getParser(); 5613 SMLoc S, E; 5614 if (Parser.getTok().isNot(AsmToken::LBrac)) 5615 return TokError("Token is not a Left Bracket"); 5616 S = Parser.getTok().getLoc(); 5617 Parser.Lex(); // Eat left bracket token. 5618 5619 const AsmToken &BaseRegTok = Parser.getTok(); 5620 int BaseRegNum = tryParseRegister(); 5621 if (BaseRegNum == -1) 5622 return Error(BaseRegTok.getLoc(), "register expected"); 5623 5624 // The next token must either be a comma, a colon or a closing bracket. 5625 const AsmToken &Tok = Parser.getTok(); 5626 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 5627 !Tok.is(AsmToken::RBrac)) 5628 return Error(Tok.getLoc(), "malformed memory operand"); 5629 5630 if (Tok.is(AsmToken::RBrac)) { 5631 E = Tok.getEndLoc(); 5632 Parser.Lex(); // Eat right bracket token. 5633 5634 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 5635 ARM_AM::no_shift, 0, 0, false, 5636 S, E)); 5637 5638 // If there's a pre-indexing writeback marker, '!', just add it as a token 5639 // operand. It's rather odd, but syntactically valid. 5640 if (Parser.getTok().is(AsmToken::Exclaim)) { 5641 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 5642 Parser.Lex(); // Eat the '!'. 5643 } 5644 5645 return false; 5646 } 5647 5648 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 5649 "Lost colon or comma in memory operand?!"); 5650 if (Tok.is(AsmToken::Comma)) { 5651 Parser.Lex(); // Eat the comma. 5652 } 5653 5654 // If we have a ':', it's an alignment specifier. 5655 if (Parser.getTok().is(AsmToken::Colon)) { 5656 Parser.Lex(); // Eat the ':'. 5657 E = Parser.getTok().getLoc(); 5658 SMLoc AlignmentLoc = Tok.getLoc(); 5659 5660 const MCExpr *Expr; 5661 if (getParser().parseExpression(Expr)) 5662 return true; 5663 5664 // The expression has to be a constant. Memory references with relocations 5665 // don't come through here, as they use the <label> forms of the relevant 5666 // instructions. 5667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 5668 if (!CE) 5669 return Error (E, "constant expression expected"); 5670 5671 unsigned Align = 0; 5672 switch (CE->getValue()) { 5673 default: 5674 return Error(E, 5675 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 5676 case 16: Align = 2; break; 5677 case 32: Align = 4; break; 5678 case 64: Align = 8; break; 5679 case 128: Align = 16; break; 5680 case 256: Align = 32; break; 5681 } 5682 5683 // Now we should have the closing ']' 5684 if (Parser.getTok().isNot(AsmToken::RBrac)) 5685 return Error(Parser.getTok().getLoc(), "']' expected"); 5686 E = Parser.getTok().getEndLoc(); 5687 Parser.Lex(); // Eat right bracket token. 5688 5689 // Don't worry about range checking the value here. That's handled by 5690 // the is*() predicates. 5691 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 5692 ARM_AM::no_shift, 0, Align, 5693 false, S, E, AlignmentLoc)); 5694 5695 // If there's a pre-indexing writeback marker, '!', just add it as a token 5696 // operand. 5697 if (Parser.getTok().is(AsmToken::Exclaim)) { 5698 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 5699 Parser.Lex(); // Eat the '!'. 5700 } 5701 5702 return false; 5703 } 5704 5705 // If we have a '#', it's an immediate offset, else assume it's a register 5706 // offset. Be friendly and also accept a plain integer (without a leading 5707 // hash) for gas compatibility. 5708 if (Parser.getTok().is(AsmToken::Hash) || 5709 Parser.getTok().is(AsmToken::Dollar) || 5710 Parser.getTok().is(AsmToken::Integer)) { 5711 if (Parser.getTok().isNot(AsmToken::Integer)) 5712 Parser.Lex(); // Eat '#' or '$'. 5713 E = Parser.getTok().getLoc(); 5714 5715 bool isNegative = getParser().getTok().is(AsmToken::Minus); 5716 const MCExpr *Offset; 5717 if (getParser().parseExpression(Offset)) 5718 return true; 5719 5720 // The expression has to be a constant. Memory references with relocations 5721 // don't come through here, as they use the <label> forms of the relevant 5722 // instructions. 5723 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 5724 if (!CE) 5725 return Error (E, "constant expression expected"); 5726 5727 // If the constant was #-0, represent it as 5728 // std::numeric_limits<int32_t>::min(). 5729 int32_t Val = CE->getValue(); 5730 if (isNegative && Val == 0) 5731 CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(), 5732 getContext()); 5733 5734 // Now we should have the closing ']' 5735 if (Parser.getTok().isNot(AsmToken::RBrac)) 5736 return Error(Parser.getTok().getLoc(), "']' expected"); 5737 E = Parser.getTok().getEndLoc(); 5738 Parser.Lex(); // Eat right bracket token. 5739 5740 // Don't worry about range checking the value here. That's handled by 5741 // the is*() predicates. 5742 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 5743 ARM_AM::no_shift, 0, 0, 5744 false, S, E)); 5745 5746 // If there's a pre-indexing writeback marker, '!', just add it as a token 5747 // operand. 5748 if (Parser.getTok().is(AsmToken::Exclaim)) { 5749 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 5750 Parser.Lex(); // Eat the '!'. 5751 } 5752 5753 return false; 5754 } 5755 5756 // The register offset is optionally preceded by a '+' or '-' 5757 bool isNegative = false; 5758 if (Parser.getTok().is(AsmToken::Minus)) { 5759 isNegative = true; 5760 Parser.Lex(); // Eat the '-'. 5761 } else if (Parser.getTok().is(AsmToken::Plus)) { 5762 // Nothing to do. 5763 Parser.Lex(); // Eat the '+'. 5764 } 5765 5766 E = Parser.getTok().getLoc(); 5767 int OffsetRegNum = tryParseRegister(); 5768 if (OffsetRegNum == -1) 5769 return Error(E, "register expected"); 5770 5771 // If there's a shift operator, handle it. 5772 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 5773 unsigned ShiftImm = 0; 5774 if (Parser.getTok().is(AsmToken::Comma)) { 5775 Parser.Lex(); // Eat the ','. 5776 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 5777 return true; 5778 } 5779 5780 // Now we should have the closing ']' 5781 if (Parser.getTok().isNot(AsmToken::RBrac)) 5782 return Error(Parser.getTok().getLoc(), "']' expected"); 5783 E = Parser.getTok().getEndLoc(); 5784 Parser.Lex(); // Eat right bracket token. 5785 5786 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, 5787 ShiftType, ShiftImm, 0, isNegative, 5788 S, E)); 5789 5790 // If there's a pre-indexing writeback marker, '!', just add it as a token 5791 // operand. 5792 if (Parser.getTok().is(AsmToken::Exclaim)) { 5793 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 5794 Parser.Lex(); // Eat the '!'. 5795 } 5796 5797 return false; 5798 } 5799 5800 /// parseMemRegOffsetShift - one of these two: 5801 /// ( lsl | lsr | asr | ror ) , # shift_amount 5802 /// rrx 5803 /// return true if it parses a shift otherwise it returns false. 5804 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 5805 unsigned &Amount) { 5806 MCAsmParser &Parser = getParser(); 5807 SMLoc Loc = Parser.getTok().getLoc(); 5808 const AsmToken &Tok = Parser.getTok(); 5809 if (Tok.isNot(AsmToken::Identifier)) 5810 return Error(Loc, "illegal shift operator"); 5811 StringRef ShiftName = Tok.getString(); 5812 if (ShiftName == "lsl" || ShiftName == "LSL" || 5813 ShiftName == "asl" || ShiftName == "ASL") 5814 St = ARM_AM::lsl; 5815 else if (ShiftName == "lsr" || ShiftName == "LSR") 5816 St = ARM_AM::lsr; 5817 else if (ShiftName == "asr" || ShiftName == "ASR") 5818 St = ARM_AM::asr; 5819 else if (ShiftName == "ror" || ShiftName == "ROR") 5820 St = ARM_AM::ror; 5821 else if (ShiftName == "rrx" || ShiftName == "RRX") 5822 St = ARM_AM::rrx; 5823 else if (ShiftName == "uxtw" || ShiftName == "UXTW") 5824 St = ARM_AM::uxtw; 5825 else 5826 return Error(Loc, "illegal shift operator"); 5827 Parser.Lex(); // Eat shift type token. 5828 5829 // rrx stands alone. 5830 Amount = 0; 5831 if (St != ARM_AM::rrx) { 5832 Loc = Parser.getTok().getLoc(); 5833 // A '#' and a shift amount. 5834 const AsmToken &HashTok = Parser.getTok(); 5835 if (HashTok.isNot(AsmToken::Hash) && 5836 HashTok.isNot(AsmToken::Dollar)) 5837 return Error(HashTok.getLoc(), "'#' expected"); 5838 Parser.Lex(); // Eat hash token. 5839 5840 const MCExpr *Expr; 5841 if (getParser().parseExpression(Expr)) 5842 return true; 5843 // Range check the immediate. 5844 // lsl, ror: 0 <= imm <= 31 5845 // lsr, asr: 0 <= imm <= 32 5846 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 5847 if (!CE) 5848 return Error(Loc, "shift amount must be an immediate"); 5849 int64_t Imm = CE->getValue(); 5850 if (Imm < 0 || 5851 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 5852 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 5853 return Error(Loc, "immediate shift value out of range"); 5854 // If <ShiftTy> #0, turn it into a no_shift. 5855 if (Imm == 0) 5856 St = ARM_AM::lsl; 5857 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 5858 if (Imm == 32) 5859 Imm = 0; 5860 Amount = Imm; 5861 } 5862 5863 return false; 5864 } 5865 5866 /// parseFPImm - A floating point immediate expression operand. 5867 OperandMatchResultTy 5868 ARMAsmParser::parseFPImm(OperandVector &Operands) { 5869 MCAsmParser &Parser = getParser(); 5870 // Anything that can accept a floating point constant as an operand 5871 // needs to go through here, as the regular parseExpression is 5872 // integer only. 5873 // 5874 // This routine still creates a generic Immediate operand, containing 5875 // a bitcast of the 64-bit floating point value. The various operands 5876 // that accept floats can check whether the value is valid for them 5877 // via the standard is*() predicates. 5878 5879 SMLoc S = Parser.getTok().getLoc(); 5880 5881 if (Parser.getTok().isNot(AsmToken::Hash) && 5882 Parser.getTok().isNot(AsmToken::Dollar)) 5883 return MatchOperand_NoMatch; 5884 5885 // Disambiguate the VMOV forms that can accept an FP immediate. 5886 // vmov.f32 <sreg>, #imm 5887 // vmov.f64 <dreg>, #imm 5888 // vmov.f32 <dreg>, #imm @ vector f32x2 5889 // vmov.f32 <qreg>, #imm @ vector f32x4 5890 // 5891 // There are also the NEON VMOV instructions which expect an 5892 // integer constant. Make sure we don't try to parse an FPImm 5893 // for these: 5894 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 5895 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); 5896 bool isVmovf = TyOp.isToken() && 5897 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" || 5898 TyOp.getToken() == ".f16"); 5899 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); 5900 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || 5901 Mnemonic.getToken() == "fconsts"); 5902 if (!(isVmovf || isFconst)) 5903 return MatchOperand_NoMatch; 5904 5905 Parser.Lex(); // Eat '#' or '$'. 5906 5907 // Handle negation, as that still comes through as a separate token. 5908 bool isNegative = false; 5909 if (Parser.getTok().is(AsmToken::Minus)) { 5910 isNegative = true; 5911 Parser.Lex(); 5912 } 5913 const AsmToken &Tok = Parser.getTok(); 5914 SMLoc Loc = Tok.getLoc(); 5915 if (Tok.is(AsmToken::Real) && isVmovf) { 5916 APFloat RealVal(APFloat::IEEEsingle(), Tok.getString()); 5917 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 5918 // If we had a '-' in front, toggle the sign bit. 5919 IntVal ^= (uint64_t)isNegative << 31; 5920 Parser.Lex(); // Eat the token. 5921 Operands.push_back(ARMOperand::CreateImm( 5922 MCConstantExpr::create(IntVal, getContext()), 5923 S, Parser.getTok().getLoc())); 5924 return MatchOperand_Success; 5925 } 5926 // Also handle plain integers. Instructions which allow floating point 5927 // immediates also allow a raw encoded 8-bit value. 5928 if (Tok.is(AsmToken::Integer) && isFconst) { 5929 int64_t Val = Tok.getIntVal(); 5930 Parser.Lex(); // Eat the token. 5931 if (Val > 255 || Val < 0) { 5932 Error(Loc, "encoded floating point value out of range"); 5933 return MatchOperand_ParseFail; 5934 } 5935 float RealVal = ARM_AM::getFPImmFloat(Val); 5936 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 5937 5938 Operands.push_back(ARMOperand::CreateImm( 5939 MCConstantExpr::create(Val, getContext()), S, 5940 Parser.getTok().getLoc())); 5941 return MatchOperand_Success; 5942 } 5943 5944 Error(Loc, "invalid floating point immediate"); 5945 return MatchOperand_ParseFail; 5946 } 5947 5948 /// Parse a arm instruction operand. For now this parses the operand regardless 5949 /// of the mnemonic. 5950 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { 5951 MCAsmParser &Parser = getParser(); 5952 SMLoc S, E; 5953 5954 // Check if the current operand has a custom associated parser, if so, try to 5955 // custom parse the operand, or fallback to the general approach. 5956 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 5957 if (ResTy == MatchOperand_Success) 5958 return false; 5959 // If there wasn't a custom match, try the generic matcher below. Otherwise, 5960 // there was a match, but an error occurred, in which case, just return that 5961 // the operand parsing failed. 5962 if (ResTy == MatchOperand_ParseFail) 5963 return true; 5964 5965 switch (getLexer().getKind()) { 5966 default: 5967 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5968 return true; 5969 case AsmToken::Identifier: { 5970 // If we've seen a branch mnemonic, the next operand must be a label. This 5971 // is true even if the label is a register name. So "br r1" means branch to 5972 // label "r1". 5973 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 5974 if (!ExpectLabel) { 5975 if (!tryParseRegisterWithWriteBack(Operands)) 5976 return false; 5977 int Res = tryParseShiftRegister(Operands); 5978 if (Res == 0) // success 5979 return false; 5980 else if (Res == -1) // irrecoverable error 5981 return true; 5982 // If this is VMRS, check for the apsr_nzcv operand. 5983 if (Mnemonic == "vmrs" && 5984 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 5985 S = Parser.getTok().getLoc(); 5986 Parser.Lex(); 5987 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 5988 return false; 5989 } 5990 } 5991 5992 // Fall though for the Identifier case that is not a register or a 5993 // special name. 5994 LLVM_FALLTHROUGH; 5995 } 5996 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 5997 case AsmToken::Integer: // things like 1f and 2b as a branch targets 5998 case AsmToken::String: // quoted label names. 5999 case AsmToken::Dot: { // . as a branch target 6000 // This was not a register so parse other operands that start with an 6001 // identifier (like labels) as expressions and create them as immediates. 6002 const MCExpr *IdVal; 6003 S = Parser.getTok().getLoc(); 6004 if (getParser().parseExpression(IdVal)) 6005 return true; 6006 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6007 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 6008 return false; 6009 } 6010 case AsmToken::LBrac: 6011 return parseMemory(Operands); 6012 case AsmToken::LCurly: 6013 return parseRegisterList(Operands, !Mnemonic.startswith("clr")); 6014 case AsmToken::Dollar: 6015 case AsmToken::Hash: 6016 // #42 -> immediate. 6017 S = Parser.getTok().getLoc(); 6018 Parser.Lex(); 6019 6020 if (Parser.getTok().isNot(AsmToken::Colon)) { 6021 bool isNegative = Parser.getTok().is(AsmToken::Minus); 6022 const MCExpr *ImmVal; 6023 if (getParser().parseExpression(ImmVal)) 6024 return true; 6025 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 6026 if (CE) { 6027 int32_t Val = CE->getValue(); 6028 if (isNegative && Val == 0) 6029 ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(), 6030 getContext()); 6031 } 6032 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6033 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 6034 6035 // There can be a trailing '!' on operands that we want as a separate 6036 // '!' Token operand. Handle that here. For example, the compatibility 6037 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 6038 if (Parser.getTok().is(AsmToken::Exclaim)) { 6039 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 6040 Parser.getTok().getLoc())); 6041 Parser.Lex(); // Eat exclaim token 6042 } 6043 return false; 6044 } 6045 // w/ a ':' after the '#', it's just like a plain ':'. 6046 LLVM_FALLTHROUGH; 6047 6048 case AsmToken::Colon: { 6049 S = Parser.getTok().getLoc(); 6050 // ":lower16:" and ":upper16:" expression prefixes 6051 // FIXME: Check it's an expression prefix, 6052 // e.g. (FOO - :lower16:BAR) isn't legal. 6053 ARMMCExpr::VariantKind RefKind; 6054 if (parsePrefix(RefKind)) 6055 return true; 6056 6057 const MCExpr *SubExprVal; 6058 if (getParser().parseExpression(SubExprVal)) 6059 return true; 6060 6061 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal, 6062 getContext()); 6063 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6064 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 6065 return false; 6066 } 6067 case AsmToken::Equal: { 6068 S = Parser.getTok().getLoc(); 6069 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 6070 return Error(S, "unexpected token in operand"); 6071 Parser.Lex(); // Eat '=' 6072 const MCExpr *SubExprVal; 6073 if (getParser().parseExpression(SubExprVal)) 6074 return true; 6075 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 6076 6077 // execute-only: we assume that assembly programmers know what they are 6078 // doing and allow literal pool creation here 6079 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); 6080 return false; 6081 } 6082 } 6083 } 6084 6085 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 6086 // :lower16: and :upper16:. 6087 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 6088 MCAsmParser &Parser = getParser(); 6089 RefKind = ARMMCExpr::VK_ARM_None; 6090 6091 // consume an optional '#' (GNU compatibility) 6092 if (getLexer().is(AsmToken::Hash)) 6093 Parser.Lex(); 6094 6095 // :lower16: and :upper16: modifiers 6096 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 6097 Parser.Lex(); // Eat ':' 6098 6099 if (getLexer().isNot(AsmToken::Identifier)) { 6100 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 6101 return true; 6102 } 6103 6104 enum { 6105 COFF = (1 << MCObjectFileInfo::IsCOFF), 6106 ELF = (1 << MCObjectFileInfo::IsELF), 6107 MACHO = (1 << MCObjectFileInfo::IsMachO), 6108 WASM = (1 << MCObjectFileInfo::IsWasm), 6109 }; 6110 static const struct PrefixEntry { 6111 const char *Spelling; 6112 ARMMCExpr::VariantKind VariantKind; 6113 uint8_t SupportedFormats; 6114 } PrefixEntries[] = { 6115 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO }, 6116 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO }, 6117 }; 6118 6119 StringRef IDVal = Parser.getTok().getIdentifier(); 6120 6121 const auto &Prefix = 6122 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries), 6123 [&IDVal](const PrefixEntry &PE) { 6124 return PE.Spelling == IDVal; 6125 }); 6126 if (Prefix == std::end(PrefixEntries)) { 6127 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 6128 return true; 6129 } 6130 6131 uint8_t CurrentFormat; 6132 switch (getContext().getObjectFileInfo()->getObjectFileType()) { 6133 case MCObjectFileInfo::IsMachO: 6134 CurrentFormat = MACHO; 6135 break; 6136 case MCObjectFileInfo::IsELF: 6137 CurrentFormat = ELF; 6138 break; 6139 case MCObjectFileInfo::IsCOFF: 6140 CurrentFormat = COFF; 6141 break; 6142 case MCObjectFileInfo::IsWasm: 6143 CurrentFormat = WASM; 6144 break; 6145 case MCObjectFileInfo::IsXCOFF: 6146 llvm_unreachable("unexpected object format"); 6147 break; 6148 } 6149 6150 if (~Prefix->SupportedFormats & CurrentFormat) { 6151 Error(Parser.getTok().getLoc(), 6152 "cannot represent relocation in the current file format"); 6153 return true; 6154 } 6155 6156 RefKind = Prefix->VariantKind; 6157 Parser.Lex(); 6158 6159 if (getLexer().isNot(AsmToken::Colon)) { 6160 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 6161 return true; 6162 } 6163 Parser.Lex(); // Eat the last ':' 6164 6165 return false; 6166 } 6167 6168 /// Given a mnemonic, split out possible predication code and carry 6169 /// setting letters to form a canonical mnemonic and flags. 6170 // 6171 // FIXME: Would be nice to autogen this. 6172 // FIXME: This is a bit of a maze of special cases. 6173 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 6174 StringRef ExtraToken, 6175 unsigned &PredicationCode, 6176 unsigned &VPTPredicationCode, 6177 bool &CarrySetting, 6178 unsigned &ProcessorIMod, 6179 StringRef &ITMask) { 6180 PredicationCode = ARMCC::AL; 6181 VPTPredicationCode = ARMVCC::None; 6182 CarrySetting = false; 6183 ProcessorIMod = 0; 6184 6185 // Ignore some mnemonics we know aren't predicated forms. 6186 // 6187 // FIXME: Would be nice to autogen this. 6188 if ((Mnemonic == "movs" && isThumb()) || 6189 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 6190 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 6191 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 6192 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 6193 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 6194 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 6195 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 6196 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 6197 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 6198 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 6199 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 6200 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" || 6201 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" || 6202 Mnemonic == "bxns" || Mnemonic == "blxns" || 6203 Mnemonic == "vudot" || Mnemonic == "vsdot" || 6204 Mnemonic == "vcmla" || Mnemonic == "vcadd" || 6205 Mnemonic == "vfmal" || Mnemonic == "vfmsl" || 6206 Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" || 6207 Mnemonic == "csel" || Mnemonic == "csinc" || 6208 Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" || 6209 Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" || 6210 Mnemonic == "csetm") 6211 return Mnemonic; 6212 6213 // First, split out any predication code. Ignore mnemonics we know aren't 6214 // predicated but do have a carry-set and so weren't caught above. 6215 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 6216 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 6217 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 6218 Mnemonic != "sbcs" && Mnemonic != "rscs" && 6219 !(hasMVE() && 6220 (Mnemonic == "vmine" || 6221 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" || 6222 Mnemonic == "vrshle" || Mnemonic == "vrshlt" || 6223 Mnemonic == "vmvne" || Mnemonic == "vorne" || 6224 Mnemonic == "vnege" || Mnemonic == "vnegt" || 6225 Mnemonic == "vmule" || Mnemonic == "vmult" || 6226 Mnemonic == "vrintne" || 6227 Mnemonic == "vcmult" || Mnemonic == "vcmule" || 6228 Mnemonic == "vpsele" || Mnemonic == "vpselt" || 6229 Mnemonic.startswith("vq")))) { 6230 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2)); 6231 if (CC != ~0U) { 6232 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 6233 PredicationCode = CC; 6234 } 6235 } 6236 6237 // Next, determine if we have a carry setting bit. We explicitly ignore all 6238 // the instructions we know end in 's'. 6239 if (Mnemonic.endswith("s") && 6240 !(Mnemonic == "cps" || Mnemonic == "mls" || 6241 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 6242 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 6243 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 6244 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 6245 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 6246 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 6247 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 6248 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 6249 Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" || 6250 Mnemonic == "vmlas" || 6251 (Mnemonic == "movs" && isThumb()))) { 6252 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 6253 CarrySetting = true; 6254 } 6255 6256 // The "cps" instruction can have a interrupt mode operand which is glued into 6257 // the mnemonic. Check if this is the case, split it and parse the imod op 6258 if (Mnemonic.startswith("cps")) { 6259 // Split out any imod code. 6260 unsigned IMod = 6261 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 6262 .Case("ie", ARM_PROC::IE) 6263 .Case("id", ARM_PROC::ID) 6264 .Default(~0U); 6265 if (IMod != ~0U) { 6266 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 6267 ProcessorIMod = IMod; 6268 } 6269 } 6270 6271 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" && 6272 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" && 6273 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" && 6274 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" && 6275 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" && 6276 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" && 6277 Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") { 6278 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1)); 6279 if (CC != ~0U) { 6280 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1); 6281 VPTPredicationCode = CC; 6282 } 6283 return Mnemonic; 6284 } 6285 6286 // The "it" instruction has the condition mask on the end of the mnemonic. 6287 if (Mnemonic.startswith("it")) { 6288 ITMask = Mnemonic.slice(2, Mnemonic.size()); 6289 Mnemonic = Mnemonic.slice(0, 2); 6290 } 6291 6292 if (Mnemonic.startswith("vpst")) { 6293 ITMask = Mnemonic.slice(4, Mnemonic.size()); 6294 Mnemonic = Mnemonic.slice(0, 4); 6295 } 6296 else if (Mnemonic.startswith("vpt")) { 6297 ITMask = Mnemonic.slice(3, Mnemonic.size()); 6298 Mnemonic = Mnemonic.slice(0, 3); 6299 } 6300 6301 return Mnemonic; 6302 } 6303 6304 /// Given a canonical mnemonic, determine if the instruction ever allows 6305 /// inclusion of carry set or predication code operands. 6306 // 6307 // FIXME: It would be nice to autogen this. 6308 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, 6309 StringRef ExtraToken, 6310 StringRef FullInst, 6311 bool &CanAcceptCarrySet, 6312 bool &CanAcceptPredicationCode, 6313 bool &CanAcceptVPTPredicationCode) { 6314 CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken); 6315 6316 CanAcceptCarrySet = 6317 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 6318 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 6319 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" || 6320 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" || 6321 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" || 6322 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" || 6323 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" || 6324 (!isThumb() && 6325 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" || 6326 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull")); 6327 6328 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 6329 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 6330 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || 6331 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || 6332 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || 6333 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || 6334 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || 6335 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" || 6336 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" || 6337 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 6338 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) || 6339 Mnemonic == "vmovx" || Mnemonic == "vins" || 6340 Mnemonic == "vudot" || Mnemonic == "vsdot" || 6341 Mnemonic == "vcmla" || Mnemonic == "vcadd" || 6342 Mnemonic == "vfmal" || Mnemonic == "vfmsl" || 6343 Mnemonic == "sb" || Mnemonic == "ssbb" || 6344 Mnemonic == "pssbb" || 6345 Mnemonic == "bfcsel" || Mnemonic == "wls" || 6346 Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" || 6347 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" || 6348 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" || 6349 Mnemonic == "cset" || Mnemonic == "csetm" || 6350 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") || 6351 (hasMVE() && 6352 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") || 6353 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") || 6354 Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") || 6355 Mnemonic.startswith("letp")))) { 6356 // These mnemonics are never predicable 6357 CanAcceptPredicationCode = false; 6358 } else if (!isThumb()) { 6359 // Some instructions are only predicable in Thumb mode 6360 CanAcceptPredicationCode = 6361 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 6362 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 6363 Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" && 6364 Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" && 6365 Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 6366 Mnemonic != "stc2" && Mnemonic != "stc2l" && 6367 Mnemonic != "tsb" && 6368 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 6369 } else if (isThumbOne()) { 6370 if (hasV6MOps()) 6371 CanAcceptPredicationCode = Mnemonic != "movs"; 6372 else 6373 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 6374 } else 6375 CanAcceptPredicationCode = true; 6376 } 6377 6378 // Some Thumb instructions have two operand forms that are not 6379 // available as three operand, convert to two operand form if possible. 6380 // 6381 // FIXME: We would really like to be able to tablegen'erate this. 6382 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic, 6383 bool CarrySetting, 6384 OperandVector &Operands) { 6385 if (Operands.size() != 6) 6386 return; 6387 6388 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); 6389 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); 6390 if (!Op3.isReg() || !Op4.isReg()) 6391 return; 6392 6393 auto Op3Reg = Op3.getReg(); 6394 auto Op4Reg = Op4.getReg(); 6395 6396 // For most Thumb2 cases we just generate the 3 operand form and reduce 6397 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr) 6398 // won't accept SP or PC so we do the transformation here taking care 6399 // with immediate range in the 'add sp, sp #imm' case. 6400 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); 6401 if (isThumbTwo()) { 6402 if (Mnemonic != "add") 6403 return; 6404 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || 6405 (Op5.isReg() && Op5.getReg() == ARM::PC); 6406 if (!TryTransform) { 6407 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || 6408 (Op5.isReg() && Op5.getReg() == ARM::SP)) && 6409 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && 6410 Op5.isImm() && !Op5.isImm0_508s4()); 6411 } 6412 if (!TryTransform) 6413 return; 6414 } else if (!isThumbOne()) 6415 return; 6416 6417 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" || 6418 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" || 6419 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" || 6420 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) 6421 return; 6422 6423 // If first 2 operands of a 3 operand instruction are the same 6424 // then transform to 2 operand version of the same instruction 6425 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' 6426 bool Transform = Op3Reg == Op4Reg; 6427 6428 // For communtative operations, we might be able to transform if we swap 6429 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially 6430 // as tADDrsp. 6431 const ARMOperand *LastOp = &Op5; 6432 bool Swap = false; 6433 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && 6434 ((Mnemonic == "add" && Op4Reg != ARM::SP) || 6435 Mnemonic == "and" || Mnemonic == "eor" || 6436 Mnemonic == "adc" || Mnemonic == "orr")) { 6437 Swap = true; 6438 LastOp = &Op4; 6439 Transform = true; 6440 } 6441 6442 // If both registers are the same then remove one of them from 6443 // the operand list, with certain exceptions. 6444 if (Transform) { 6445 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the 6446 // 2 operand forms don't exist. 6447 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") && 6448 LastOp->isReg()) 6449 Transform = false; 6450 6451 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into 6452 // 3-bits because the ARMARM says not to. 6453 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7()) 6454 Transform = false; 6455 } 6456 6457 if (Transform) { 6458 if (Swap) 6459 std::swap(Op4, Op5); 6460 Operands.erase(Operands.begin() + 3); 6461 } 6462 } 6463 6464 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 6465 OperandVector &Operands) { 6466 // FIXME: This is all horribly hacky. We really need a better way to deal 6467 // with optional operands like this in the matcher table. 6468 6469 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 6470 // another does not. Specifically, the MOVW instruction does not. So we 6471 // special case it here and remove the defaulted (non-setting) cc_out 6472 // operand if that's the instruction we're trying to match. 6473 // 6474 // We do this as post-processing of the explicit operands rather than just 6475 // conditionally adding the cc_out in the first place because we need 6476 // to check the type of the parsed immediate operand. 6477 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 6478 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && 6479 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && 6480 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6481 return true; 6482 6483 // Register-register 'add' for thumb does not have a cc_out operand 6484 // when there are only two register operands. 6485 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 6486 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6487 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6488 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 6489 return true; 6490 // Register-register 'add' for thumb does not have a cc_out operand 6491 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 6492 // have to check the immediate range here since Thumb2 has a variant 6493 // that can handle a different range and has a cc_out operand. 6494 if (((isThumb() && Mnemonic == "add") || 6495 (isThumbTwo() && Mnemonic == "sub")) && 6496 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6497 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6498 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 6499 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6500 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || 6501 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) 6502 return true; 6503 // For Thumb2, add/sub immediate does not have a cc_out operand for the 6504 // imm0_4095 variant. That's the least-preferred variant when 6505 // selecting via the generic "add" mnemonic, so to know that we 6506 // should remove the cc_out operand, we have to explicitly check that 6507 // it's not one of the other variants. Ugh. 6508 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 6509 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 6510 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6511 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 6512 // Nest conditions rather than one big 'if' statement for readability. 6513 // 6514 // If both registers are low, we're in an IT block, and the immediate is 6515 // in range, we should use encoding T1 instead, which has a cc_out. 6516 if (inITBlock() && 6517 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 6518 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 6519 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) 6520 return false; 6521 // Check against T3. If the second register is the PC, this is an 6522 // alternate form of ADR, which uses encoding T4, so check for that too. 6523 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 6524 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) 6525 return false; 6526 6527 // Otherwise, we use encoding T4, which does not have a cc_out 6528 // operand. 6529 return true; 6530 } 6531 6532 // The thumb2 multiply instruction doesn't have a CCOut register, so 6533 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 6534 // use the 16-bit encoding or not. 6535 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 6536 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6537 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6538 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6539 static_cast<ARMOperand &>(*Operands[5]).isReg() && 6540 // If the registers aren't low regs, the destination reg isn't the 6541 // same as one of the source regs, or the cc_out operand is zero 6542 // outside of an IT block, we have to use the 32-bit encoding, so 6543 // remove the cc_out operand. 6544 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6545 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6546 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 6547 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 6548 static_cast<ARMOperand &>(*Operands[5]).getReg() && 6549 static_cast<ARMOperand &>(*Operands[3]).getReg() != 6550 static_cast<ARMOperand &>(*Operands[4]).getReg()))) 6551 return true; 6552 6553 // Also check the 'mul' syntax variant that doesn't specify an explicit 6554 // destination register. 6555 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 6556 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6557 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6558 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6559 // If the registers aren't low regs or the cc_out operand is zero 6560 // outside of an IT block, we have to use the 32-bit encoding, so 6561 // remove the cc_out operand. 6562 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 6563 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 6564 !inITBlock())) 6565 return true; 6566 6567 // Register-register 'add/sub' for thumb does not have a cc_out operand 6568 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 6569 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 6570 // right, this will result in better diagnostics (which operand is off) 6571 // anyway. 6572 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 6573 (Operands.size() == 5 || Operands.size() == 6) && 6574 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6575 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 6576 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 6577 (static_cast<ARMOperand &>(*Operands[4]).isImm() || 6578 (Operands.size() == 6 && 6579 static_cast<ARMOperand &>(*Operands[5]).isImm()))) 6580 return true; 6581 6582 return false; 6583 } 6584 6585 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, 6586 OperandVector &Operands) { 6587 // VRINT{Z, X} have a predicate operand in VFP, but not in NEON 6588 unsigned RegIdx = 3; 6589 if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) || 6590 Mnemonic == "vrintr") && 6591 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || 6592 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { 6593 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && 6594 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || 6595 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) 6596 RegIdx = 4; 6597 6598 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 6599 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 6600 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 6601 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( 6602 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) 6603 return true; 6604 } 6605 return false; 6606 } 6607 6608 bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic, 6609 OperandVector &Operands) { 6610 if (!hasMVE() || Operands.size() < 3) 6611 return true; 6612 6613 if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") || 6614 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4")) 6615 return true; 6616 6617 if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot")) 6618 return false; 6619 6620 if (Mnemonic.startswith("vmov") && 6621 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") || 6622 Mnemonic.startswith("vmovx"))) { 6623 for (auto &Operand : Operands) { 6624 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() || 6625 ((*Operand).isReg() && 6626 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( 6627 (*Operand).getReg()) || 6628 ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 6629 (*Operand).getReg())))) { 6630 return true; 6631 } 6632 } 6633 return false; 6634 } else { 6635 for (auto &Operand : Operands) { 6636 // We check the larger class QPR instead of just the legal class 6637 // MQPR, to more accurately report errors when using Q registers 6638 // outside of the allowed range. 6639 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() || 6640 (Operand->isReg() && 6641 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains( 6642 Operand->getReg())))) 6643 return false; 6644 } 6645 return true; 6646 } 6647 } 6648 6649 static bool isDataTypeToken(StringRef Tok) { 6650 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 6651 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 6652 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 6653 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 6654 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 6655 Tok == ".f" || Tok == ".d"; 6656 } 6657 6658 // FIXME: This bit should probably be handled via an explicit match class 6659 // in the .td files that matches the suffix instead of having it be 6660 // a literal string token the way it is now. 6661 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 6662 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 6663 } 6664 6665 static void applyMnemonicAliases(StringRef &Mnemonic, 6666 const FeatureBitset &Features, 6667 unsigned VariantID); 6668 6669 // The GNU assembler has aliases of ldrd and strd with the second register 6670 // omitted. We don't have a way to do that in tablegen, so fix it up here. 6671 // 6672 // We have to be careful to not emit an invalid Rt2 here, because the rest of 6673 // the assmebly parser could then generate confusing diagnostics refering to 6674 // it. If we do find anything that prevents us from doing the transformation we 6675 // bail out, and let the assembly parser report an error on the instruction as 6676 // it is written. 6677 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic, 6678 OperandVector &Operands) { 6679 if (Mnemonic != "ldrd" && Mnemonic != "strd") 6680 return; 6681 if (Operands.size() < 4) 6682 return; 6683 6684 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); 6685 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 6686 6687 if (!Op2.isReg()) 6688 return; 6689 if (!Op3.isGPRMem()) 6690 return; 6691 6692 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); 6693 if (!GPR.contains(Op2.getReg())) 6694 return; 6695 6696 unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg()); 6697 if (!isThumb() && (RtEncoding & 1)) { 6698 // In ARM mode, the registers must be from an aligned pair, this 6699 // restriction does not apply in Thumb mode. 6700 return; 6701 } 6702 if (Op2.getReg() == ARM::PC) 6703 return; 6704 unsigned PairedReg = GPR.getRegister(RtEncoding + 1); 6705 if (!PairedReg || PairedReg == ARM::PC || 6706 (PairedReg == ARM::SP && !hasV8Ops())) 6707 return; 6708 6709 Operands.insert( 6710 Operands.begin() + 3, 6711 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); 6712 } 6713 6714 /// Parse an arm instruction mnemonic followed by its operands. 6715 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 6716 SMLoc NameLoc, OperandVector &Operands) { 6717 MCAsmParser &Parser = getParser(); 6718 6719 // Apply mnemonic aliases before doing anything else, as the destination 6720 // mnemonic may include suffices and we want to handle them normally. 6721 // The generic tblgen'erated code does this later, at the start of 6722 // MatchInstructionImpl(), but that's too late for aliases that include 6723 // any sort of suffix. 6724 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 6725 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 6726 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 6727 6728 // First check for the ARM-specific .req directive. 6729 if (Parser.getTok().is(AsmToken::Identifier) && 6730 Parser.getTok().getIdentifier() == ".req") { 6731 parseDirectiveReq(Name, NameLoc); 6732 // We always return 'error' for this, as we're done with this 6733 // statement and don't need to match the 'instruction." 6734 return true; 6735 } 6736 6737 // Create the leading tokens for the mnemonic, split by '.' characters. 6738 size_t Start = 0, Next = Name.find('.'); 6739 StringRef Mnemonic = Name.slice(Start, Next); 6740 StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1)); 6741 6742 // Split out the predication code and carry setting flag from the mnemonic. 6743 unsigned PredicationCode; 6744 unsigned VPTPredicationCode; 6745 unsigned ProcessorIMod; 6746 bool CarrySetting; 6747 StringRef ITMask; 6748 Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode, 6749 CarrySetting, ProcessorIMod, ITMask); 6750 6751 // In Thumb1, only the branch (B) instruction can be predicated. 6752 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 6753 return Error(NameLoc, "conditional execution not supported in Thumb1"); 6754 } 6755 6756 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 6757 6758 // Handle the mask for IT and VPT instructions. In ARMOperand and 6759 // MCOperand, this is stored in a format independent of the 6760 // condition code: the lowest set bit indicates the end of the 6761 // encoding, and above that, a 1 bit indicates 'else', and an 0 6762 // indicates 'then'. E.g. 6763 // IT -> 1000 6764 // ITx -> x100 (ITT -> 0100, ITE -> 1100) 6765 // ITxy -> xy10 (e.g. ITET -> 1010) 6766 // ITxyz -> xyz1 (e.g. ITEET -> 1101) 6767 if (Mnemonic == "it" || Mnemonic.startswith("vpt") || 6768 Mnemonic.startswith("vpst")) { 6769 SMLoc Loc = Mnemonic == "it" ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) : 6770 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) : 6771 SMLoc::getFromPointer(NameLoc.getPointer() + 4); 6772 if (ITMask.size() > 3) { 6773 if (Mnemonic == "it") 6774 return Error(Loc, "too many conditions on IT instruction"); 6775 return Error(Loc, "too many conditions on VPT instruction"); 6776 } 6777 unsigned Mask = 8; 6778 for (unsigned i = ITMask.size(); i != 0; --i) { 6779 char pos = ITMask[i - 1]; 6780 if (pos != 't' && pos != 'e') { 6781 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 6782 } 6783 Mask >>= 1; 6784 if (ITMask[i - 1] == 'e') 6785 Mask |= 8; 6786 } 6787 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 6788 } 6789 6790 // FIXME: This is all a pretty gross hack. We should automatically handle 6791 // optional operands like this via tblgen. 6792 6793 // Next, add the CCOut and ConditionCode operands, if needed. 6794 // 6795 // For mnemonics which can ever incorporate a carry setting bit or predication 6796 // code, our matching model involves us always generating CCOut and 6797 // ConditionCode operands to match the mnemonic "as written" and then we let 6798 // the matcher deal with finding the right instruction or generating an 6799 // appropriate error. 6800 bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode; 6801 getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet, 6802 CanAcceptPredicationCode, CanAcceptVPTPredicationCode); 6803 6804 // If we had a carry-set on an instruction that can't do that, issue an 6805 // error. 6806 if (!CanAcceptCarrySet && CarrySetting) { 6807 return Error(NameLoc, "instruction '" + Mnemonic + 6808 "' can not set flags, but 's' suffix specified"); 6809 } 6810 // If we had a predication code on an instruction that can't do that, issue an 6811 // error. 6812 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 6813 return Error(NameLoc, "instruction '" + Mnemonic + 6814 "' is not predicable, but condition code specified"); 6815 } 6816 6817 // If we had a VPT predication code on an instruction that can't do that, issue an 6818 // error. 6819 if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) { 6820 return Error(NameLoc, "instruction '" + Mnemonic + 6821 "' is not VPT predicable, but VPT code T/E is specified"); 6822 } 6823 6824 // Add the carry setting operand, if necessary. 6825 if (CanAcceptCarrySet) { 6826 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 6827 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 6828 Loc)); 6829 } 6830 6831 // Add the predication code operand, if necessary. 6832 if (CanAcceptPredicationCode) { 6833 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 6834 CarrySetting); 6835 Operands.push_back(ARMOperand::CreateCondCode( 6836 ARMCC::CondCodes(PredicationCode), Loc)); 6837 } 6838 6839 // Add the VPT predication code operand, if necessary. 6840 // FIXME: We don't add them for the instructions filtered below as these can 6841 // have custom operands which need special parsing. This parsing requires 6842 // the operand to be in the same place in the OperandVector as their 6843 // definition in tblgen. Since these instructions may also have the 6844 // scalar predication operand we do not add the vector one and leave until 6845 // now to fix it up. 6846 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" && 6847 !Mnemonic.startswith("vcmp") && 6848 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" && 6849 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) { 6850 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 6851 CarrySetting); 6852 Operands.push_back(ARMOperand::CreateVPTPred( 6853 ARMVCC::VPTCodes(VPTPredicationCode), Loc)); 6854 } 6855 6856 // Add the processor imod operand, if necessary. 6857 if (ProcessorIMod) { 6858 Operands.push_back(ARMOperand::CreateImm( 6859 MCConstantExpr::create(ProcessorIMod, getContext()), 6860 NameLoc, NameLoc)); 6861 } else if (Mnemonic == "cps" && isMClass()) { 6862 return Error(NameLoc, "instruction 'cps' requires effect for M-class"); 6863 } 6864 6865 // Add the remaining tokens in the mnemonic. 6866 while (Next != StringRef::npos) { 6867 Start = Next; 6868 Next = Name.find('.', Start + 1); 6869 ExtraToken = Name.slice(Start, Next); 6870 6871 // Some NEON instructions have an optional datatype suffix that is 6872 // completely ignored. Check for that. 6873 if (isDataTypeToken(ExtraToken) && 6874 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 6875 continue; 6876 6877 // For for ARM mode generate an error if the .n qualifier is used. 6878 if (ExtraToken == ".n" && !isThumb()) { 6879 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 6880 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 6881 "arm mode"); 6882 } 6883 6884 // The .n qualifier is always discarded as that is what the tables 6885 // and matcher expect. In ARM mode the .w qualifier has no effect, 6886 // so discard it to avoid errors that can be caused by the matcher. 6887 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 6888 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 6889 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 6890 } 6891 } 6892 6893 // Read the remaining operands. 6894 if (getLexer().isNot(AsmToken::EndOfStatement)) { 6895 // Read the first operand. 6896 if (parseOperand(Operands, Mnemonic)) { 6897 return true; 6898 } 6899 6900 while (parseOptionalToken(AsmToken::Comma)) { 6901 // Parse and remember the operand. 6902 if (parseOperand(Operands, Mnemonic)) { 6903 return true; 6904 } 6905 } 6906 } 6907 6908 if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list")) 6909 return true; 6910 6911 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); 6912 6913 // Some instructions, mostly Thumb, have forms for the same mnemonic that 6914 // do and don't have a cc_out optional-def operand. With some spot-checks 6915 // of the operand list, we can figure out which variant we're trying to 6916 // parse and adjust accordingly before actually matching. We shouldn't ever 6917 // try to remove a cc_out operand that was explicitly set on the 6918 // mnemonic, of course (CarrySetting == true). Reason number #317 the 6919 // table driven matcher doesn't fit well with the ARM instruction set. 6920 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) 6921 Operands.erase(Operands.begin() + 1); 6922 6923 // Some instructions have the same mnemonic, but don't always 6924 // have a predicate. Distinguish them here and delete the 6925 // appropriate predicate if needed. This could be either the scalar 6926 // predication code or the vector predication code. 6927 if (PredicationCode == ARMCC::AL && 6928 shouldOmitPredicateOperand(Mnemonic, Operands)) 6929 Operands.erase(Operands.begin() + 1); 6930 6931 6932 if (hasMVE()) { 6933 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) && 6934 Mnemonic == "vmov" && PredicationCode == ARMCC::LT) { 6935 // Very nasty hack to deal with the vector predicated variant of vmovlt 6936 // the scalar predicated vmov with condition 'lt'. We can not tell them 6937 // apart until we have parsed their operands. 6938 Operands.erase(Operands.begin() + 1); 6939 Operands.erase(Operands.begin()); 6940 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); 6941 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + 6942 Mnemonic.size() - 1 + CarrySetting); 6943 Operands.insert(Operands.begin(), 6944 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc)); 6945 Operands.insert(Operands.begin(), 6946 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc)); 6947 } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE && 6948 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { 6949 // Another nasty hack to deal with the ambiguity between vcvt with scalar 6950 // predication 'ne' and vcvtn with vector predication 'e'. As above we 6951 // can only distinguish between the two after we have parsed their 6952 // operands. 6953 Operands.erase(Operands.begin() + 1); 6954 Operands.erase(Operands.begin()); 6955 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); 6956 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + 6957 Mnemonic.size() - 1 + CarrySetting); 6958 Operands.insert(Operands.begin(), 6959 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc)); 6960 Operands.insert(Operands.begin(), 6961 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc)); 6962 } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT && 6963 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { 6964 // Another hack, this time to distinguish between scalar predicated vmul 6965 // with 'lt' predication code and the vector instruction vmullt with 6966 // vector predication code "none" 6967 Operands.erase(Operands.begin() + 1); 6968 Operands.erase(Operands.begin()); 6969 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); 6970 Operands.insert(Operands.begin(), 6971 ARMOperand::CreateToken(StringRef("vmullt"), MLoc)); 6972 } 6973 // For vmov and vcmp, as mentioned earlier, we did not add the vector 6974 // predication code, since these may contain operands that require 6975 // special parsing. So now we have to see if they require vector 6976 // predication and replace the scalar one with the vector predication 6977 // operand if that is the case. 6978 else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") || 6979 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") && 6980 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") && 6981 !Mnemonic.startswith("vcvtm"))) { 6982 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { 6983 // We could not split the vector predicate off vcvt because it might 6984 // have been the scalar vcvtt instruction. Now we know its a vector 6985 // instruction, we still need to check whether its the vector 6986 // predicated vcvt with 'Then' predication or the vector vcvtt. We can 6987 // distinguish the two based on the suffixes, if it is any of 6988 // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt. 6989 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) { 6990 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]); 6991 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]); 6992 if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") && 6993 Sz2.isToken() && Sz2.getToken().startswith(".f"))) { 6994 Operands.erase(Operands.begin()); 6995 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer()); 6996 VPTPredicationCode = ARMVCC::Then; 6997 6998 Mnemonic = Mnemonic.substr(0, 4); 6999 Operands.insert(Operands.begin(), 7000 ARMOperand::CreateToken(Mnemonic, MLoc)); 7001 } 7002 } 7003 Operands.erase(Operands.begin() + 1); 7004 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() + 7005 Mnemonic.size() + CarrySetting); 7006 Operands.insert(Operands.begin() + 1, 7007 ARMOperand::CreateVPTPred( 7008 ARMVCC::VPTCodes(VPTPredicationCode), PLoc)); 7009 } 7010 } else if (CanAcceptVPTPredicationCode) { 7011 // For all other instructions, make sure only one of the two 7012 // predication operands is left behind, depending on whether we should 7013 // use the vector predication. 7014 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { 7015 if (CanAcceptPredicationCode) 7016 Operands.erase(Operands.begin() + 2); 7017 else 7018 Operands.erase(Operands.begin() + 1); 7019 } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) { 7020 Operands.erase(Operands.begin() + 1); 7021 } 7022 } 7023 } 7024 7025 if (VPTPredicationCode != ARMVCC::None) { 7026 bool usedVPTPredicationCode = false; 7027 for (unsigned I = 1; I < Operands.size(); ++I) 7028 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) 7029 usedVPTPredicationCode = true; 7030 if (!usedVPTPredicationCode) { 7031 // If we have a VPT predication code and we haven't just turned it 7032 // into an operand, then it was a mistake for splitMnemonic to 7033 // separate it from the rest of the mnemonic in the first place, 7034 // and this may lead to wrong disassembly (e.g. scalar floating 7035 // point VCMPE is actually a different instruction from VCMP, so 7036 // we mustn't treat them the same). In that situation, glue it 7037 // back on. 7038 Mnemonic = Name.slice(0, Mnemonic.size() + 1); 7039 Operands.erase(Operands.begin()); 7040 Operands.insert(Operands.begin(), 7041 ARMOperand::CreateToken(Mnemonic, NameLoc)); 7042 } 7043 } 7044 7045 // ARM mode 'blx' need special handling, as the register operand version 7046 // is predicable, but the label operand version is not. So, we can't rely 7047 // on the Mnemonic based checking to correctly figure out when to put 7048 // a k_CondCode operand in the list. If we're trying to match the label 7049 // version, remove the k_CondCode operand here. 7050 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 7051 static_cast<ARMOperand &>(*Operands[2]).isImm()) 7052 Operands.erase(Operands.begin() + 1); 7053 7054 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 7055 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 7056 // a single GPRPair reg operand is used in the .td file to replace the two 7057 // GPRs. However, when parsing from asm, the two GRPs cannot be 7058 // automatically 7059 // expressed as a GPRPair, so we have to manually merge them. 7060 // FIXME: We would really like to be able to tablegen'erate this. 7061 if (!isThumb() && Operands.size() > 4 && 7062 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 7063 Mnemonic == "stlexd")) { 7064 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 7065 unsigned Idx = isLoad ? 2 : 3; 7066 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); 7067 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); 7068 7069 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); 7070 // Adjust only if Op1 and Op2 are GPRs. 7071 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 7072 MRC.contains(Op2.getReg())) { 7073 unsigned Reg1 = Op1.getReg(); 7074 unsigned Reg2 = Op2.getReg(); 7075 unsigned Rt = MRI->getEncodingValue(Reg1); 7076 unsigned Rt2 = MRI->getEncodingValue(Reg2); 7077 7078 // Rt2 must be Rt + 1 and Rt must be even. 7079 if (Rt + 1 != Rt2 || (Rt & 1)) { 7080 return Error(Op2.getStartLoc(), 7081 isLoad ? "destination operands must be sequential" 7082 : "source operands must be sequential"); 7083 } 7084 unsigned NewReg = MRI->getMatchingSuperReg( 7085 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); 7086 Operands[Idx] = 7087 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 7088 Operands.erase(Operands.begin() + Idx + 1); 7089 } 7090 } 7091 7092 // GNU Assembler extension (compatibility). 7093 fixupGNULDRDAlias(Mnemonic, Operands); 7094 7095 // FIXME: As said above, this is all a pretty gross hack. This instruction 7096 // does not fit with other "subs" and tblgen. 7097 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 7098 // so the Mnemonic is the original name "subs" and delete the predicate 7099 // operand so it will match the table entry. 7100 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 7101 static_cast<ARMOperand &>(*Operands[3]).isReg() && 7102 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && 7103 static_cast<ARMOperand &>(*Operands[4]).isReg() && 7104 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && 7105 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 7106 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); 7107 Operands.erase(Operands.begin() + 1); 7108 } 7109 return false; 7110 } 7111 7112 // Validate context-sensitive operand constraints. 7113 7114 // return 'true' if register list contains non-low GPR registers, 7115 // 'false' otherwise. If Reg is in the register list or is HiReg, set 7116 // 'containsReg' to true. 7117 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, 7118 unsigned Reg, unsigned HiReg, 7119 bool &containsReg) { 7120 containsReg = false; 7121 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 7122 unsigned OpReg = Inst.getOperand(i).getReg(); 7123 if (OpReg == Reg) 7124 containsReg = true; 7125 // Anything other than a low register isn't legal here. 7126 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 7127 return true; 7128 } 7129 return false; 7130 } 7131 7132 // Check if the specified regisgter is in the register list of the inst, 7133 // starting at the indicated operand number. 7134 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { 7135 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) { 7136 unsigned OpReg = Inst.getOperand(i).getReg(); 7137 if (OpReg == Reg) 7138 return true; 7139 } 7140 return false; 7141 } 7142 7143 // Return true if instruction has the interesting property of being 7144 // allowed in IT blocks, but not being predicable. 7145 static bool instIsBreakpoint(const MCInst &Inst) { 7146 return Inst.getOpcode() == ARM::tBKPT || 7147 Inst.getOpcode() == ARM::BKPT || 7148 Inst.getOpcode() == ARM::tHLT || 7149 Inst.getOpcode() == ARM::HLT; 7150 } 7151 7152 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, 7153 const OperandVector &Operands, 7154 unsigned ListNo, bool IsARPop) { 7155 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 7156 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 7157 7158 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 7159 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); 7160 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 7161 7162 if (!IsARPop && ListContainsSP) 7163 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 7164 "SP may not be in the register list"); 7165 else if (ListContainsPC && ListContainsLR) 7166 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 7167 "PC and LR may not be in the register list simultaneously"); 7168 return false; 7169 } 7170 7171 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, 7172 const OperandVector &Operands, 7173 unsigned ListNo) { 7174 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 7175 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 7176 7177 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 7178 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 7179 7180 if (ListContainsSP && ListContainsPC) 7181 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 7182 "SP and PC may not be in the register list"); 7183 else if (ListContainsSP) 7184 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 7185 "SP may not be in the register list"); 7186 else if (ListContainsPC) 7187 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 7188 "PC may not be in the register list"); 7189 return false; 7190 } 7191 7192 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, 7193 const OperandVector &Operands, 7194 bool Load, bool ARMMode, bool Writeback) { 7195 unsigned RtIndex = Load || !Writeback ? 0 : 1; 7196 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); 7197 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); 7198 7199 if (ARMMode) { 7200 // Rt can't be R14. 7201 if (Rt == 14) 7202 return Error(Operands[3]->getStartLoc(), 7203 "Rt can't be R14"); 7204 7205 // Rt must be even-numbered. 7206 if ((Rt & 1) == 1) 7207 return Error(Operands[3]->getStartLoc(), 7208 "Rt must be even-numbered"); 7209 7210 // Rt2 must be Rt + 1. 7211 if (Rt2 != Rt + 1) { 7212 if (Load) 7213 return Error(Operands[3]->getStartLoc(), 7214 "destination operands must be sequential"); 7215 else 7216 return Error(Operands[3]->getStartLoc(), 7217 "source operands must be sequential"); 7218 } 7219 7220 // FIXME: Diagnose m == 15 7221 // FIXME: Diagnose ldrd with m == t || m == t2. 7222 } 7223 7224 if (!ARMMode && Load) { 7225 if (Rt2 == Rt) 7226 return Error(Operands[3]->getStartLoc(), 7227 "destination operands can't be identical"); 7228 } 7229 7230 if (Writeback) { 7231 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 7232 7233 if (Rn == Rt || Rn == Rt2) { 7234 if (Load) 7235 return Error(Operands[3]->getStartLoc(), 7236 "base register needs to be different from destination " 7237 "registers"); 7238 else 7239 return Error(Operands[3]->getStartLoc(), 7240 "source register and base register can't be identical"); 7241 } 7242 7243 // FIXME: Diagnose ldrd/strd with writeback and n == 15. 7244 // (Except the immediate form of ldrd?) 7245 } 7246 7247 return false; 7248 } 7249 7250 static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) { 7251 for (unsigned i = 0; i < MCID.NumOperands; ++i) { 7252 if (ARM::isVpred(MCID.OpInfo[i].OperandType)) 7253 return i; 7254 } 7255 return -1; 7256 } 7257 7258 static bool isVectorPredicable(const MCInstrDesc &MCID) { 7259 return findFirstVectorPredOperandIdx(MCID) != -1; 7260 } 7261 7262 // FIXME: We would really like to be able to tablegen'erate this. 7263 bool ARMAsmParser::validateInstruction(MCInst &Inst, 7264 const OperandVector &Operands) { 7265 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 7266 SMLoc Loc = Operands[0]->getStartLoc(); 7267 7268 // Check the IT block state first. 7269 // NOTE: BKPT and HLT instructions have the interesting property of being 7270 // allowed in IT blocks, but not being predicable. They just always execute. 7271 if (inITBlock() && !instIsBreakpoint(Inst)) { 7272 // The instruction must be predicable. 7273 if (!MCID.isPredicable()) 7274 return Error(Loc, "instructions in IT block must be predicable"); 7275 ARMCC::CondCodes Cond = ARMCC::CondCodes( 7276 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm()); 7277 if (Cond != currentITCond()) { 7278 // Find the condition code Operand to get its SMLoc information. 7279 SMLoc CondLoc; 7280 for (unsigned I = 1; I < Operands.size(); ++I) 7281 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) 7282 CondLoc = Operands[I]->getStartLoc(); 7283 return Error(CondLoc, "incorrect condition in IT block; got '" + 7284 StringRef(ARMCondCodeToString(Cond)) + 7285 "', but expected '" + 7286 ARMCondCodeToString(currentITCond()) + "'"); 7287 } 7288 // Check for non-'al' condition codes outside of the IT block. 7289 } else if (isThumbTwo() && MCID.isPredicable() && 7290 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 7291 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 7292 Inst.getOpcode() != ARM::t2Bcc && 7293 Inst.getOpcode() != ARM::t2BFic) { 7294 return Error(Loc, "predicated instructions must be in IT block"); 7295 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() && 7296 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 7297 ARMCC::AL) { 7298 return Warning(Loc, "predicated instructions should be in IT block"); 7299 } else if (!MCID.isPredicable()) { 7300 // Check the instruction doesn't have a predicate operand anyway 7301 // that it's not allowed to use. Sometimes this happens in order 7302 // to keep instructions the same shape even though one cannot 7303 // legally be predicated, e.g. vmul.f16 vs vmul.f32. 7304 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 7305 if (MCID.OpInfo[i].isPredicate()) { 7306 if (Inst.getOperand(i).getImm() != ARMCC::AL) 7307 return Error(Loc, "instruction is not predicable"); 7308 break; 7309 } 7310 } 7311 } 7312 7313 // PC-setting instructions in an IT block, but not the last instruction of 7314 // the block, are UNPREDICTABLE. 7315 if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) { 7316 return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block"); 7317 } 7318 7319 if (inVPTBlock() && !instIsBreakpoint(Inst)) { 7320 unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition); 7321 if (!isVectorPredicable(MCID)) 7322 return Error(Loc, "instruction in VPT block must be predicable"); 7323 unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm(); 7324 unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then; 7325 if (Pred != VPTPred) { 7326 SMLoc PredLoc; 7327 for (unsigned I = 1; I < Operands.size(); ++I) 7328 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) 7329 PredLoc = Operands[I]->getStartLoc(); 7330 return Error(PredLoc, "incorrect predication in VPT block; got '" + 7331 StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) + 7332 "', but expected '" + 7333 ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'"); 7334 } 7335 } 7336 else if (isVectorPredicable(MCID) && 7337 Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() != 7338 ARMVCC::None) 7339 return Error(Loc, "VPT predicated instructions must be in VPT block"); 7340 7341 const unsigned Opcode = Inst.getOpcode(); 7342 switch (Opcode) { 7343 case ARM::t2IT: { 7344 // Encoding is unpredictable if it ever results in a notional 'NV' 7345 // predicate. Since we don't parse 'NV' directly this means an 'AL' 7346 // predicate with an "else" mask bit. 7347 unsigned Cond = Inst.getOperand(0).getImm(); 7348 unsigned Mask = Inst.getOperand(1).getImm(); 7349 7350 // Conditions only allowing a 't' are those with no set bit except 7351 // the lowest-order one that indicates the end of the sequence. In 7352 // other words, powers of 2. 7353 if (Cond == ARMCC::AL && countPopulation(Mask) != 1) 7354 return Error(Loc, "unpredictable IT predicate sequence"); 7355 break; 7356 } 7357 case ARM::LDRD: 7358 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, 7359 /*Writeback*/false)) 7360 return true; 7361 break; 7362 case ARM::LDRD_PRE: 7363 case ARM::LDRD_POST: 7364 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, 7365 /*Writeback*/true)) 7366 return true; 7367 break; 7368 case ARM::t2LDRDi8: 7369 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, 7370 /*Writeback*/false)) 7371 return true; 7372 break; 7373 case ARM::t2LDRD_PRE: 7374 case ARM::t2LDRD_POST: 7375 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, 7376 /*Writeback*/true)) 7377 return true; 7378 break; 7379 case ARM::t2BXJ: { 7380 const unsigned RmReg = Inst.getOperand(0).getReg(); 7381 // Rm = SP is no longer unpredictable in v8-A 7382 if (RmReg == ARM::SP && !hasV8Ops()) 7383 return Error(Operands[2]->getStartLoc(), 7384 "r13 (SP) is an unpredictable operand to BXJ"); 7385 return false; 7386 } 7387 case ARM::STRD: 7388 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, 7389 /*Writeback*/false)) 7390 return true; 7391 break; 7392 case ARM::STRD_PRE: 7393 case ARM::STRD_POST: 7394 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, 7395 /*Writeback*/true)) 7396 return true; 7397 break; 7398 case ARM::t2STRD_PRE: 7399 case ARM::t2STRD_POST: 7400 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, 7401 /*Writeback*/true)) 7402 return true; 7403 break; 7404 case ARM::STR_PRE_IMM: 7405 case ARM::STR_PRE_REG: 7406 case ARM::t2STR_PRE: 7407 case ARM::STR_POST_IMM: 7408 case ARM::STR_POST_REG: 7409 case ARM::t2STR_POST: 7410 case ARM::STRH_PRE: 7411 case ARM::t2STRH_PRE: 7412 case ARM::STRH_POST: 7413 case ARM::t2STRH_POST: 7414 case ARM::STRB_PRE_IMM: 7415 case ARM::STRB_PRE_REG: 7416 case ARM::t2STRB_PRE: 7417 case ARM::STRB_POST_IMM: 7418 case ARM::STRB_POST_REG: 7419 case ARM::t2STRB_POST: { 7420 // Rt must be different from Rn. 7421 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 7422 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7423 7424 if (Rt == Rn) 7425 return Error(Operands[3]->getStartLoc(), 7426 "source register and base register can't be identical"); 7427 return false; 7428 } 7429 case ARM::LDR_PRE_IMM: 7430 case ARM::LDR_PRE_REG: 7431 case ARM::t2LDR_PRE: 7432 case ARM::LDR_POST_IMM: 7433 case ARM::LDR_POST_REG: 7434 case ARM::t2LDR_POST: 7435 case ARM::LDRH_PRE: 7436 case ARM::t2LDRH_PRE: 7437 case ARM::LDRH_POST: 7438 case ARM::t2LDRH_POST: 7439 case ARM::LDRSH_PRE: 7440 case ARM::t2LDRSH_PRE: 7441 case ARM::LDRSH_POST: 7442 case ARM::t2LDRSH_POST: 7443 case ARM::LDRB_PRE_IMM: 7444 case ARM::LDRB_PRE_REG: 7445 case ARM::t2LDRB_PRE: 7446 case ARM::LDRB_POST_IMM: 7447 case ARM::LDRB_POST_REG: 7448 case ARM::t2LDRB_POST: 7449 case ARM::LDRSB_PRE: 7450 case ARM::t2LDRSB_PRE: 7451 case ARM::LDRSB_POST: 7452 case ARM::t2LDRSB_POST: { 7453 // Rt must be different from Rn. 7454 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 7455 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7456 7457 if (Rt == Rn) 7458 return Error(Operands[3]->getStartLoc(), 7459 "destination register and base register can't be identical"); 7460 return false; 7461 } 7462 7463 case ARM::MVE_VLDRBU8_rq: 7464 case ARM::MVE_VLDRBU16_rq: 7465 case ARM::MVE_VLDRBS16_rq: 7466 case ARM::MVE_VLDRBU32_rq: 7467 case ARM::MVE_VLDRBS32_rq: 7468 case ARM::MVE_VLDRHU16_rq: 7469 case ARM::MVE_VLDRHU16_rq_u: 7470 case ARM::MVE_VLDRHU32_rq: 7471 case ARM::MVE_VLDRHU32_rq_u: 7472 case ARM::MVE_VLDRHS32_rq: 7473 case ARM::MVE_VLDRHS32_rq_u: 7474 case ARM::MVE_VLDRWU32_rq: 7475 case ARM::MVE_VLDRWU32_rq_u: 7476 case ARM::MVE_VLDRDU64_rq: 7477 case ARM::MVE_VLDRDU64_rq_u: 7478 case ARM::MVE_VLDRWU32_qi: 7479 case ARM::MVE_VLDRWU32_qi_pre: 7480 case ARM::MVE_VLDRDU64_qi: 7481 case ARM::MVE_VLDRDU64_qi_pre: { 7482 // Qd must be different from Qm. 7483 unsigned QdIdx = 0, QmIdx = 2; 7484 bool QmIsPointer = false; 7485 switch (Opcode) { 7486 case ARM::MVE_VLDRWU32_qi: 7487 case ARM::MVE_VLDRDU64_qi: 7488 QmIdx = 1; 7489 QmIsPointer = true; 7490 break; 7491 case ARM::MVE_VLDRWU32_qi_pre: 7492 case ARM::MVE_VLDRDU64_qi_pre: 7493 QdIdx = 1; 7494 QmIsPointer = true; 7495 break; 7496 } 7497 7498 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); 7499 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); 7500 7501 if (Qd == Qm) { 7502 return Error(Operands[3]->getStartLoc(), 7503 Twine("destination vector register and vector ") + 7504 (QmIsPointer ? "pointer" : "offset") + 7505 " register can't be identical"); 7506 } 7507 return false; 7508 } 7509 7510 case ARM::SBFX: 7511 case ARM::t2SBFX: 7512 case ARM::UBFX: 7513 case ARM::t2UBFX: { 7514 // Width must be in range [1, 32-lsb]. 7515 unsigned LSB = Inst.getOperand(2).getImm(); 7516 unsigned Widthm1 = Inst.getOperand(3).getImm(); 7517 if (Widthm1 >= 32 - LSB) 7518 return Error(Operands[5]->getStartLoc(), 7519 "bitfield width must be in range [1,32-lsb]"); 7520 return false; 7521 } 7522 // Notionally handles ARM::tLDMIA_UPD too. 7523 case ARM::tLDMIA: { 7524 // If we're parsing Thumb2, the .w variant is available and handles 7525 // most cases that are normally illegal for a Thumb1 LDM instruction. 7526 // We'll make the transformation in processInstruction() if necessary. 7527 // 7528 // Thumb LDM instructions are writeback iff the base register is not 7529 // in the register list. 7530 unsigned Rn = Inst.getOperand(0).getReg(); 7531 bool HasWritebackToken = 7532 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 7533 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 7534 bool ListContainsBase; 7535 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 7536 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 7537 "registers must be in range r0-r7"); 7538 // If we should have writeback, then there should be a '!' token. 7539 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 7540 return Error(Operands[2]->getStartLoc(), 7541 "writeback operator '!' expected"); 7542 // If we should not have writeback, there must not be a '!'. This is 7543 // true even for the 32-bit wide encodings. 7544 if (ListContainsBase && HasWritebackToken) 7545 return Error(Operands[3]->getStartLoc(), 7546 "writeback operator '!' not allowed when base register " 7547 "in register list"); 7548 7549 if (validatetLDMRegList(Inst, Operands, 3)) 7550 return true; 7551 break; 7552 } 7553 case ARM::LDMIA_UPD: 7554 case ARM::LDMDB_UPD: 7555 case ARM::LDMIB_UPD: 7556 case ARM::LDMDA_UPD: 7557 // ARM variants loading and updating the same register are only officially 7558 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 7559 if (!hasV7Ops()) 7560 break; 7561 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 7562 return Error(Operands.back()->getStartLoc(), 7563 "writeback register not allowed in register list"); 7564 break; 7565 case ARM::t2LDMIA: 7566 case ARM::t2LDMDB: 7567 if (validatetLDMRegList(Inst, Operands, 3)) 7568 return true; 7569 break; 7570 case ARM::t2STMIA: 7571 case ARM::t2STMDB: 7572 if (validatetSTMRegList(Inst, Operands, 3)) 7573 return true; 7574 break; 7575 case ARM::t2LDMIA_UPD: 7576 case ARM::t2LDMDB_UPD: 7577 case ARM::t2STMIA_UPD: 7578 case ARM::t2STMDB_UPD: 7579 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 7580 return Error(Operands.back()->getStartLoc(), 7581 "writeback register not allowed in register list"); 7582 7583 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { 7584 if (validatetLDMRegList(Inst, Operands, 3)) 7585 return true; 7586 } else { 7587 if (validatetSTMRegList(Inst, Operands, 3)) 7588 return true; 7589 } 7590 break; 7591 7592 case ARM::sysLDMIA_UPD: 7593 case ARM::sysLDMDA_UPD: 7594 case ARM::sysLDMDB_UPD: 7595 case ARM::sysLDMIB_UPD: 7596 if (!listContainsReg(Inst, 3, ARM::PC)) 7597 return Error(Operands[4]->getStartLoc(), 7598 "writeback register only allowed on system LDM " 7599 "if PC in register-list"); 7600 break; 7601 case ARM::sysSTMIA_UPD: 7602 case ARM::sysSTMDA_UPD: 7603 case ARM::sysSTMDB_UPD: 7604 case ARM::sysSTMIB_UPD: 7605 return Error(Operands[2]->getStartLoc(), 7606 "system STM cannot have writeback register"); 7607 case ARM::tMUL: 7608 // The second source operand must be the same register as the destination 7609 // operand. 7610 // 7611 // In this case, we must directly check the parsed operands because the 7612 // cvtThumbMultiply() function is written in such a way that it guarantees 7613 // this first statement is always true for the new Inst. Essentially, the 7614 // destination is unconditionally copied into the second source operand 7615 // without checking to see if it matches what we actually parsed. 7616 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 7617 ((ARMOperand &)*Operands[5]).getReg()) && 7618 (((ARMOperand &)*Operands[3]).getReg() != 7619 ((ARMOperand &)*Operands[4]).getReg())) { 7620 return Error(Operands[3]->getStartLoc(), 7621 "destination register must match source register"); 7622 } 7623 break; 7624 7625 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 7626 // so only issue a diagnostic for thumb1. The instructions will be 7627 // switched to the t2 encodings in processInstruction() if necessary. 7628 case ARM::tPOP: { 7629 bool ListContainsBase; 7630 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 7631 !isThumbTwo()) 7632 return Error(Operands[2]->getStartLoc(), 7633 "registers must be in range r0-r7 or pc"); 7634 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) 7635 return true; 7636 break; 7637 } 7638 case ARM::tPUSH: { 7639 bool ListContainsBase; 7640 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 7641 !isThumbTwo()) 7642 return Error(Operands[2]->getStartLoc(), 7643 "registers must be in range r0-r7 or lr"); 7644 if (validatetSTMRegList(Inst, Operands, 2)) 7645 return true; 7646 break; 7647 } 7648 case ARM::tSTMIA_UPD: { 7649 bool ListContainsBase, InvalidLowList; 7650 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 7651 0, ListContainsBase); 7652 if (InvalidLowList && !isThumbTwo()) 7653 return Error(Operands[4]->getStartLoc(), 7654 "registers must be in range r0-r7"); 7655 7656 // This would be converted to a 32-bit stm, but that's not valid if the 7657 // writeback register is in the list. 7658 if (InvalidLowList && ListContainsBase) 7659 return Error(Operands[4]->getStartLoc(), 7660 "writeback operator '!' not allowed when base register " 7661 "in register list"); 7662 7663 if (validatetSTMRegList(Inst, Operands, 4)) 7664 return true; 7665 break; 7666 } 7667 case ARM::tADDrSP: 7668 // If the non-SP source operand and the destination operand are not the 7669 // same, we need thumb2 (for the wide encoding), or we have an error. 7670 if (!isThumbTwo() && 7671 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7672 return Error(Operands[4]->getStartLoc(), 7673 "source register must be the same as destination"); 7674 } 7675 break; 7676 7677 case ARM::t2ADDri: 7678 case ARM::t2ADDri12: 7679 case ARM::t2ADDrr: 7680 case ARM::t2ADDrs: 7681 case ARM::t2SUBri: 7682 case ARM::t2SUBri12: 7683 case ARM::t2SUBrr: 7684 case ARM::t2SUBrs: 7685 if (Inst.getOperand(0).getReg() == ARM::SP && 7686 Inst.getOperand(1).getReg() != ARM::SP) 7687 return Error(Operands[4]->getStartLoc(), 7688 "source register must be sp if destination is sp"); 7689 break; 7690 7691 // Final range checking for Thumb unconditional branch instructions. 7692 case ARM::tB: 7693 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) 7694 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7695 break; 7696 case ARM::t2B: { 7697 int op = (Operands[2]->isImm()) ? 2 : 3; 7698 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) 7699 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 7700 break; 7701 } 7702 // Final range checking for Thumb conditional branch instructions. 7703 case ARM::tBcc: 7704 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) 7705 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7706 break; 7707 case ARM::t2Bcc: { 7708 int Op = (Operands[2]->isImm()) ? 2 : 3; 7709 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) 7710 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 7711 break; 7712 } 7713 case ARM::tCBZ: 7714 case ARM::tCBNZ: { 7715 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) 7716 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 7717 break; 7718 } 7719 case ARM::MOVi16: 7720 case ARM::MOVTi16: 7721 case ARM::t2MOVi16: 7722 case ARM::t2MOVTi16: 7723 { 7724 // We want to avoid misleadingly allowing something like "mov r0, <symbol>" 7725 // especially when we turn it into a movw and the expression <symbol> does 7726 // not have a :lower16: or :upper16 as part of the expression. We don't 7727 // want the behavior of silently truncating, which can be unexpected and 7728 // lead to bugs that are difficult to find since this is an easy mistake 7729 // to make. 7730 int i = (Operands[3]->isImm()) ? 3 : 4; 7731 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); 7732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()); 7733 if (CE) break; 7734 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm()); 7735 if (!E) break; 7736 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E); 7737 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && 7738 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) 7739 return Error( 7740 Op.getStartLoc(), 7741 "immediate expression for mov requires :lower16: or :upper16"); 7742 break; 7743 } 7744 case ARM::HINT: 7745 case ARM::t2HINT: { 7746 unsigned Imm8 = Inst.getOperand(0).getImm(); 7747 unsigned Pred = Inst.getOperand(1).getImm(); 7748 // ESB is not predicable (pred must be AL). Without the RAS extension, this 7749 // behaves as any other unallocated hint. 7750 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS()) 7751 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " 7752 "predicable, but condition " 7753 "code specified"); 7754 if (Imm8 == 0x14 && Pred != ARMCC::AL) 7755 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " 7756 "predicable, but condition " 7757 "code specified"); 7758 break; 7759 } 7760 case ARM::t2BFi: 7761 case ARM::t2BFr: 7762 case ARM::t2BFLi: 7763 case ARM::t2BFLr: { 7764 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || 7765 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7766 return Error(Operands[2]->getStartLoc(), 7767 "branch location out of range or not a multiple of 2"); 7768 7769 if (Opcode == ARM::t2BFi) { 7770 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) 7771 return Error(Operands[3]->getStartLoc(), 7772 "branch target out of range or not a multiple of 2"); 7773 } else if (Opcode == ARM::t2BFLi) { 7774 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) 7775 return Error(Operands[3]->getStartLoc(), 7776 "branch target out of range or not a multiple of 2"); 7777 } 7778 break; 7779 } 7780 case ARM::t2BFic: { 7781 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || 7782 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0)) 7783 return Error(Operands[1]->getStartLoc(), 7784 "branch location out of range or not a multiple of 2"); 7785 7786 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) 7787 return Error(Operands[2]->getStartLoc(), 7788 "branch target out of range or not a multiple of 2"); 7789 7790 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() && 7791 "branch location and else branch target should either both be " 7792 "immediates or both labels"); 7793 7794 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) { 7795 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm(); 7796 if (Diff != 4 && Diff != 2) 7797 return Error( 7798 Operands[3]->getStartLoc(), 7799 "else branch target must be 2 or 4 greater than the branch location"); 7800 } 7801 break; 7802 } 7803 case ARM::t2CLRM: { 7804 for (unsigned i = 2; i < Inst.getNumOperands(); i++) { 7805 if (Inst.getOperand(i).isReg() && 7806 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains( 7807 Inst.getOperand(i).getReg())) { 7808 return Error(Operands[2]->getStartLoc(), 7809 "invalid register in register list. Valid registers are " 7810 "r0-r12, lr/r14 and APSR."); 7811 } 7812 } 7813 break; 7814 } 7815 case ARM::DSB: 7816 case ARM::t2DSB: { 7817 7818 if (Inst.getNumOperands() < 2) 7819 break; 7820 7821 unsigned Option = Inst.getOperand(0).getImm(); 7822 unsigned Pred = Inst.getOperand(1).getImm(); 7823 7824 // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL). 7825 if (Option == 0 && Pred != ARMCC::AL) 7826 return Error(Operands[1]->getStartLoc(), 7827 "instruction 'ssbb' is not predicable, but condition code " 7828 "specified"); 7829 if (Option == 4 && Pred != ARMCC::AL) 7830 return Error(Operands[1]->getStartLoc(), 7831 "instruction 'pssbb' is not predicable, but condition code " 7832 "specified"); 7833 break; 7834 } 7835 case ARM::VMOVRRS: { 7836 // Source registers must be sequential. 7837 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 7838 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 7839 if (Sm1 != Sm + 1) 7840 return Error(Operands[5]->getStartLoc(), 7841 "source operands must be sequential"); 7842 break; 7843 } 7844 case ARM::VMOVSRR: { 7845 // Destination registers must be sequential. 7846 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 7847 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 7848 if (Sm1 != Sm + 1) 7849 return Error(Operands[3]->getStartLoc(), 7850 "destination operands must be sequential"); 7851 break; 7852 } 7853 case ARM::VLDMDIA: 7854 case ARM::VSTMDIA: { 7855 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); 7856 auto &RegList = Op.getRegList(); 7857 if (RegList.size() < 1 || RegList.size() > 16) 7858 return Error(Operands[3]->getStartLoc(), 7859 "list of registers must be at least 1 and at most 16"); 7860 break; 7861 } 7862 case ARM::MVE_VQDMULLs32bh: 7863 case ARM::MVE_VQDMULLs32th: 7864 case ARM::MVE_VCMULf32: 7865 case ARM::MVE_VMULLs32bh: 7866 case ARM::MVE_VMULLs32th: 7867 case ARM::MVE_VMULLu32bh: 7868 case ARM::MVE_VMULLu32th: { 7869 if (Operands[3]->getReg() == Operands[4]->getReg()) { 7870 return Error (Operands[3]->getStartLoc(), 7871 "Qd register and Qn register can't be identical"); 7872 } 7873 if (Operands[3]->getReg() == Operands[5]->getReg()) { 7874 return Error (Operands[3]->getStartLoc(), 7875 "Qd register and Qm register can't be identical"); 7876 } 7877 break; 7878 } 7879 case ARM::MVE_VMOV_rr_q: { 7880 if (Operands[4]->getReg() != Operands[6]->getReg()) 7881 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); 7882 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != 7883 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) 7884 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); 7885 break; 7886 } 7887 case ARM::MVE_VMOV_q_rr: { 7888 if (Operands[2]->getReg() != Operands[4]->getReg()) 7889 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); 7890 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != 7891 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) 7892 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); 7893 break; 7894 } 7895 } 7896 7897 return false; 7898 } 7899 7900 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 7901 switch(Opc) { 7902 default: llvm_unreachable("unexpected opcode!"); 7903 // VST1LN 7904 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 7905 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 7906 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 7907 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 7908 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 7909 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 7910 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 7911 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 7912 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 7913 7914 // VST2LN 7915 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 7916 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 7917 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 7918 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 7919 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 7920 7921 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 7922 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 7923 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 7924 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 7925 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 7926 7927 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 7928 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 7929 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 7930 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 7931 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 7932 7933 // VST3LN 7934 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 7935 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 7936 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 7937 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 7938 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 7939 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 7940 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 7941 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 7942 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 7943 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 7944 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 7945 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 7946 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 7947 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 7948 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 7949 7950 // VST3 7951 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 7952 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 7953 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 7954 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 7955 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 7956 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 7957 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 7958 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 7959 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 7960 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 7961 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 7962 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 7963 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 7964 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 7965 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 7966 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 7967 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 7968 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 7969 7970 // VST4LN 7971 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 7972 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 7973 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 7974 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 7975 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 7976 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 7977 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 7978 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 7979 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 7980 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 7981 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 7982 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 7983 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 7984 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 7985 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 7986 7987 // VST4 7988 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 7989 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 7990 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 7991 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 7992 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 7993 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 7994 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 7995 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 7996 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 7997 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 7998 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 7999 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 8000 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 8001 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 8002 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 8003 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 8004 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 8005 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 8006 } 8007 } 8008 8009 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 8010 switch(Opc) { 8011 default: llvm_unreachable("unexpected opcode!"); 8012 // VLD1LN 8013 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 8014 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 8015 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 8016 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 8017 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 8018 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 8019 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 8020 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 8021 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 8022 8023 // VLD2LN 8024 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 8025 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 8026 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 8027 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 8028 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 8029 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 8030 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 8031 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 8032 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 8033 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 8034 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 8035 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 8036 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 8037 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 8038 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 8039 8040 // VLD3DUP 8041 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 8042 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 8043 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 8044 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 8045 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 8046 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 8047 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 8048 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 8049 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 8050 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 8051 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 8052 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 8053 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 8054 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 8055 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 8056 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 8057 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 8058 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 8059 8060 // VLD3LN 8061 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 8062 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 8063 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 8064 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 8065 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 8066 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 8067 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 8068 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 8069 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 8070 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 8071 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 8072 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 8073 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 8074 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 8075 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 8076 8077 // VLD3 8078 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 8079 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 8080 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 8081 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 8082 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 8083 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 8084 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 8085 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 8086 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 8087 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 8088 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 8089 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 8090 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 8091 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 8092 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 8093 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 8094 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 8095 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 8096 8097 // VLD4LN 8098 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 8099 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 8100 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 8101 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 8102 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 8103 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 8104 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 8105 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 8106 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 8107 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 8108 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 8109 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 8110 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 8111 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 8112 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 8113 8114 // VLD4DUP 8115 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 8116 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 8117 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 8118 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 8119 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 8120 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 8121 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 8122 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 8123 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 8124 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 8125 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 8126 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 8127 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 8128 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 8129 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 8130 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 8131 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 8132 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 8133 8134 // VLD4 8135 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 8136 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 8137 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 8138 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 8139 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 8140 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 8141 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 8142 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 8143 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 8144 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 8145 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 8146 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 8147 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 8148 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 8149 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 8150 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 8151 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 8152 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 8153 } 8154 } 8155 8156 bool ARMAsmParser::processInstruction(MCInst &Inst, 8157 const OperandVector &Operands, 8158 MCStreamer &Out) { 8159 // Check if we have the wide qualifier, because if it's present we 8160 // must avoid selecting a 16-bit thumb instruction. 8161 bool HasWideQualifier = false; 8162 for (auto &Op : Operands) { 8163 ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op); 8164 if (ARMOp.isToken() && ARMOp.getToken() == ".w") { 8165 HasWideQualifier = true; 8166 break; 8167 } 8168 } 8169 8170 switch (Inst.getOpcode()) { 8171 case ARM::MVE_VORNIZ0v4i32: 8172 case ARM::MVE_VORNIZ0v8i16: 8173 case ARM::MVE_VORNIZ8v4i32: 8174 case ARM::MVE_VORNIZ8v8i16: 8175 case ARM::MVE_VORNIZ16v4i32: 8176 case ARM::MVE_VORNIZ24v4i32: 8177 case ARM::MVE_VANDIZ0v4i32: 8178 case ARM::MVE_VANDIZ0v8i16: 8179 case ARM::MVE_VANDIZ8v4i32: 8180 case ARM::MVE_VANDIZ8v8i16: 8181 case ARM::MVE_VANDIZ16v4i32: 8182 case ARM::MVE_VANDIZ24v4i32: { 8183 unsigned Opcode; 8184 bool imm16 = false; 8185 switch(Inst.getOpcode()) { 8186 case ARM::MVE_VORNIZ0v4i32: Opcode = ARM::MVE_VORRIZ0v4i32; break; 8187 case ARM::MVE_VORNIZ0v8i16: Opcode = ARM::MVE_VORRIZ0v8i16; imm16 = true; break; 8188 case ARM::MVE_VORNIZ8v4i32: Opcode = ARM::MVE_VORRIZ8v4i32; break; 8189 case ARM::MVE_VORNIZ8v8i16: Opcode = ARM::MVE_VORRIZ8v8i16; imm16 = true; break; 8190 case ARM::MVE_VORNIZ16v4i32: Opcode = ARM::MVE_VORRIZ16v4i32; break; 8191 case ARM::MVE_VORNIZ24v4i32: Opcode = ARM::MVE_VORRIZ24v4i32; break; 8192 case ARM::MVE_VANDIZ0v4i32: Opcode = ARM::MVE_VBICIZ0v4i32; break; 8193 case ARM::MVE_VANDIZ0v8i16: Opcode = ARM::MVE_VBICIZ0v8i16; imm16 = true; break; 8194 case ARM::MVE_VANDIZ8v4i32: Opcode = ARM::MVE_VBICIZ8v4i32; break; 8195 case ARM::MVE_VANDIZ8v8i16: Opcode = ARM::MVE_VBICIZ8v8i16; imm16 = true; break; 8196 case ARM::MVE_VANDIZ16v4i32: Opcode = ARM::MVE_VBICIZ16v4i32; break; 8197 case ARM::MVE_VANDIZ24v4i32: Opcode = ARM::MVE_VBICIZ24v4i32; break; 8198 default: llvm_unreachable("unexpected opcode"); 8199 } 8200 8201 MCInst TmpInst; 8202 TmpInst.setOpcode(Opcode); 8203 TmpInst.addOperand(Inst.getOperand(0)); 8204 TmpInst.addOperand(Inst.getOperand(1)); 8205 8206 // invert immediate 8207 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff); 8208 TmpInst.addOperand(MCOperand::createImm(imm)); 8209 8210 TmpInst.addOperand(Inst.getOperand(3)); 8211 TmpInst.addOperand(Inst.getOperand(4)); 8212 Inst = TmpInst; 8213 return true; 8214 } 8215 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 8216 case ARM::LDRT_POST: 8217 case ARM::LDRBT_POST: { 8218 const unsigned Opcode = 8219 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 8220 : ARM::LDRBT_POST_IMM; 8221 MCInst TmpInst; 8222 TmpInst.setOpcode(Opcode); 8223 TmpInst.addOperand(Inst.getOperand(0)); 8224 TmpInst.addOperand(Inst.getOperand(1)); 8225 TmpInst.addOperand(Inst.getOperand(1)); 8226 TmpInst.addOperand(MCOperand::createReg(0)); 8227 TmpInst.addOperand(MCOperand::createImm(0)); 8228 TmpInst.addOperand(Inst.getOperand(2)); 8229 TmpInst.addOperand(Inst.getOperand(3)); 8230 Inst = TmpInst; 8231 return true; 8232 } 8233 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 8234 case ARM::STRT_POST: 8235 case ARM::STRBT_POST: { 8236 const unsigned Opcode = 8237 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 8238 : ARM::STRBT_POST_IMM; 8239 MCInst TmpInst; 8240 TmpInst.setOpcode(Opcode); 8241 TmpInst.addOperand(Inst.getOperand(1)); 8242 TmpInst.addOperand(Inst.getOperand(0)); 8243 TmpInst.addOperand(Inst.getOperand(1)); 8244 TmpInst.addOperand(MCOperand::createReg(0)); 8245 TmpInst.addOperand(MCOperand::createImm(0)); 8246 TmpInst.addOperand(Inst.getOperand(2)); 8247 TmpInst.addOperand(Inst.getOperand(3)); 8248 Inst = TmpInst; 8249 return true; 8250 } 8251 // Alias for alternate form of 'ADR Rd, #imm' instruction. 8252 case ARM::ADDri: { 8253 if (Inst.getOperand(1).getReg() != ARM::PC || 8254 Inst.getOperand(5).getReg() != 0 || 8255 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 8256 return false; 8257 MCInst TmpInst; 8258 TmpInst.setOpcode(ARM::ADR); 8259 TmpInst.addOperand(Inst.getOperand(0)); 8260 if (Inst.getOperand(2).isImm()) { 8261 // Immediate (mod_imm) will be in its encoded form, we must unencode it 8262 // before passing it to the ADR instruction. 8263 unsigned Enc = Inst.getOperand(2).getImm(); 8264 TmpInst.addOperand(MCOperand::createImm( 8265 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); 8266 } else { 8267 // Turn PC-relative expression into absolute expression. 8268 // Reading PC provides the start of the current instruction + 8 and 8269 // the transform to adr is biased by that. 8270 MCSymbol *Dot = getContext().createTempSymbol(); 8271 Out.EmitLabel(Dot); 8272 const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); 8273 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot, 8274 MCSymbolRefExpr::VK_None, 8275 getContext()); 8276 const MCExpr *Const8 = MCConstantExpr::create(8, getContext()); 8277 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8, 8278 getContext()); 8279 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr, 8280 getContext()); 8281 TmpInst.addOperand(MCOperand::createExpr(FixupAddr)); 8282 } 8283 TmpInst.addOperand(Inst.getOperand(3)); 8284 TmpInst.addOperand(Inst.getOperand(4)); 8285 Inst = TmpInst; 8286 return true; 8287 } 8288 // Aliases for alternate PC+imm syntax of LDR instructions. 8289 case ARM::t2LDRpcrel: 8290 // Select the narrow version if the immediate will fit. 8291 if (Inst.getOperand(1).getImm() > 0 && 8292 Inst.getOperand(1).getImm() <= 0xff && 8293 !HasWideQualifier) 8294 Inst.setOpcode(ARM::tLDRpci); 8295 else 8296 Inst.setOpcode(ARM::t2LDRpci); 8297 return true; 8298 case ARM::t2LDRBpcrel: 8299 Inst.setOpcode(ARM::t2LDRBpci); 8300 return true; 8301 case ARM::t2LDRHpcrel: 8302 Inst.setOpcode(ARM::t2LDRHpci); 8303 return true; 8304 case ARM::t2LDRSBpcrel: 8305 Inst.setOpcode(ARM::t2LDRSBpci); 8306 return true; 8307 case ARM::t2LDRSHpcrel: 8308 Inst.setOpcode(ARM::t2LDRSHpci); 8309 return true; 8310 case ARM::LDRConstPool: 8311 case ARM::tLDRConstPool: 8312 case ARM::t2LDRConstPool: { 8313 // Pseudo instruction ldr rt, =immediate is converted to a 8314 // MOV rt, immediate if immediate is known and representable 8315 // otherwise we create a constant pool entry that we load from. 8316 MCInst TmpInst; 8317 if (Inst.getOpcode() == ARM::LDRConstPool) 8318 TmpInst.setOpcode(ARM::LDRi12); 8319 else if (Inst.getOpcode() == ARM::tLDRConstPool) 8320 TmpInst.setOpcode(ARM::tLDRpci); 8321 else if (Inst.getOpcode() == ARM::t2LDRConstPool) 8322 TmpInst.setOpcode(ARM::t2LDRpci); 8323 const ARMOperand &PoolOperand = 8324 (HasWideQualifier ? 8325 static_cast<ARMOperand &>(*Operands[4]) : 8326 static_cast<ARMOperand &>(*Operands[3])); 8327 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm(); 8328 // If SubExprVal is a constant we may be able to use a MOV 8329 if (isa<MCConstantExpr>(SubExprVal) && 8330 Inst.getOperand(0).getReg() != ARM::PC && 8331 Inst.getOperand(0).getReg() != ARM::SP) { 8332 int64_t Value = 8333 (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue(); 8334 bool UseMov = true; 8335 bool MovHasS = true; 8336 if (Inst.getOpcode() == ARM::LDRConstPool) { 8337 // ARM Constant 8338 if (ARM_AM::getSOImmVal(Value) != -1) { 8339 Value = ARM_AM::getSOImmVal(Value); 8340 TmpInst.setOpcode(ARM::MOVi); 8341 } 8342 else if (ARM_AM::getSOImmVal(~Value) != -1) { 8343 Value = ARM_AM::getSOImmVal(~Value); 8344 TmpInst.setOpcode(ARM::MVNi); 8345 } 8346 else if (hasV6T2Ops() && 8347 Value >=0 && Value < 65536) { 8348 TmpInst.setOpcode(ARM::MOVi16); 8349 MovHasS = false; 8350 } 8351 else 8352 UseMov = false; 8353 } 8354 else { 8355 // Thumb/Thumb2 Constant 8356 if (hasThumb2() && 8357 ARM_AM::getT2SOImmVal(Value) != -1) 8358 TmpInst.setOpcode(ARM::t2MOVi); 8359 else if (hasThumb2() && 8360 ARM_AM::getT2SOImmVal(~Value) != -1) { 8361 TmpInst.setOpcode(ARM::t2MVNi); 8362 Value = ~Value; 8363 } 8364 else if (hasV8MBaseline() && 8365 Value >=0 && Value < 65536) { 8366 TmpInst.setOpcode(ARM::t2MOVi16); 8367 MovHasS = false; 8368 } 8369 else 8370 UseMov = false; 8371 } 8372 if (UseMov) { 8373 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8374 TmpInst.addOperand(MCOperand::createImm(Value)); // Immediate 8375 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8376 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8377 if (MovHasS) 8378 TmpInst.addOperand(MCOperand::createReg(0)); // S 8379 Inst = TmpInst; 8380 return true; 8381 } 8382 } 8383 // No opportunity to use MOV/MVN create constant pool 8384 const MCExpr *CPLoc = 8385 getTargetStreamer().addConstantPoolEntry(SubExprVal, 8386 PoolOperand.getStartLoc()); 8387 TmpInst.addOperand(Inst.getOperand(0)); // Rt 8388 TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool 8389 if (TmpInst.getOpcode() == ARM::LDRi12) 8390 TmpInst.addOperand(MCOperand::createImm(0)); // unused offset 8391 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8392 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8393 Inst = TmpInst; 8394 return true; 8395 } 8396 // Handle NEON VST complex aliases. 8397 case ARM::VST1LNdWB_register_Asm_8: 8398 case ARM::VST1LNdWB_register_Asm_16: 8399 case ARM::VST1LNdWB_register_Asm_32: { 8400 MCInst TmpInst; 8401 // Shuffle the operands around so the lane index operand is in the 8402 // right place. 8403 unsigned Spacing; 8404 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8405 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8406 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8407 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8408 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8409 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8410 TmpInst.addOperand(Inst.getOperand(1)); // lane 8411 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8412 TmpInst.addOperand(Inst.getOperand(6)); 8413 Inst = TmpInst; 8414 return true; 8415 } 8416 8417 case ARM::VST2LNdWB_register_Asm_8: 8418 case ARM::VST2LNdWB_register_Asm_16: 8419 case ARM::VST2LNdWB_register_Asm_32: 8420 case ARM::VST2LNqWB_register_Asm_16: 8421 case ARM::VST2LNqWB_register_Asm_32: { 8422 MCInst TmpInst; 8423 // Shuffle the operands around so the lane index operand is in the 8424 // right place. 8425 unsigned Spacing; 8426 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8427 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8428 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8429 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8430 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8431 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8432 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8433 Spacing)); 8434 TmpInst.addOperand(Inst.getOperand(1)); // lane 8435 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8436 TmpInst.addOperand(Inst.getOperand(6)); 8437 Inst = TmpInst; 8438 return true; 8439 } 8440 8441 case ARM::VST3LNdWB_register_Asm_8: 8442 case ARM::VST3LNdWB_register_Asm_16: 8443 case ARM::VST3LNdWB_register_Asm_32: 8444 case ARM::VST3LNqWB_register_Asm_16: 8445 case ARM::VST3LNqWB_register_Asm_32: { 8446 MCInst TmpInst; 8447 // Shuffle the operands around so the lane index operand is in the 8448 // right place. 8449 unsigned Spacing; 8450 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8451 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8452 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8453 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8454 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8455 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8456 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8457 Spacing)); 8458 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8459 Spacing * 2)); 8460 TmpInst.addOperand(Inst.getOperand(1)); // lane 8461 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8462 TmpInst.addOperand(Inst.getOperand(6)); 8463 Inst = TmpInst; 8464 return true; 8465 } 8466 8467 case ARM::VST4LNdWB_register_Asm_8: 8468 case ARM::VST4LNdWB_register_Asm_16: 8469 case ARM::VST4LNdWB_register_Asm_32: 8470 case ARM::VST4LNqWB_register_Asm_16: 8471 case ARM::VST4LNqWB_register_Asm_32: { 8472 MCInst TmpInst; 8473 // Shuffle the operands around so the lane index operand is in the 8474 // right place. 8475 unsigned Spacing; 8476 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8477 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8478 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8479 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8480 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8481 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8482 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8483 Spacing)); 8484 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8485 Spacing * 2)); 8486 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8487 Spacing * 3)); 8488 TmpInst.addOperand(Inst.getOperand(1)); // lane 8489 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8490 TmpInst.addOperand(Inst.getOperand(6)); 8491 Inst = TmpInst; 8492 return true; 8493 } 8494 8495 case ARM::VST1LNdWB_fixed_Asm_8: 8496 case ARM::VST1LNdWB_fixed_Asm_16: 8497 case ARM::VST1LNdWB_fixed_Asm_32: { 8498 MCInst TmpInst; 8499 // Shuffle the operands around so the lane index operand is in the 8500 // right place. 8501 unsigned Spacing; 8502 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8503 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8504 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8505 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8506 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8507 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8508 TmpInst.addOperand(Inst.getOperand(1)); // lane 8509 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8510 TmpInst.addOperand(Inst.getOperand(5)); 8511 Inst = TmpInst; 8512 return true; 8513 } 8514 8515 case ARM::VST2LNdWB_fixed_Asm_8: 8516 case ARM::VST2LNdWB_fixed_Asm_16: 8517 case ARM::VST2LNdWB_fixed_Asm_32: 8518 case ARM::VST2LNqWB_fixed_Asm_16: 8519 case ARM::VST2LNqWB_fixed_Asm_32: { 8520 MCInst TmpInst; 8521 // Shuffle the operands around so the lane index operand is in the 8522 // right place. 8523 unsigned Spacing; 8524 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8525 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8526 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8527 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8528 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8529 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8530 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8531 Spacing)); 8532 TmpInst.addOperand(Inst.getOperand(1)); // lane 8533 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8534 TmpInst.addOperand(Inst.getOperand(5)); 8535 Inst = TmpInst; 8536 return true; 8537 } 8538 8539 case ARM::VST3LNdWB_fixed_Asm_8: 8540 case ARM::VST3LNdWB_fixed_Asm_16: 8541 case ARM::VST3LNdWB_fixed_Asm_32: 8542 case ARM::VST3LNqWB_fixed_Asm_16: 8543 case ARM::VST3LNqWB_fixed_Asm_32: { 8544 MCInst TmpInst; 8545 // Shuffle the operands around so the lane index operand is in the 8546 // right place. 8547 unsigned Spacing; 8548 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8549 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8550 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8551 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8552 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8553 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8554 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8555 Spacing)); 8556 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8557 Spacing * 2)); 8558 TmpInst.addOperand(Inst.getOperand(1)); // lane 8559 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8560 TmpInst.addOperand(Inst.getOperand(5)); 8561 Inst = TmpInst; 8562 return true; 8563 } 8564 8565 case ARM::VST4LNdWB_fixed_Asm_8: 8566 case ARM::VST4LNdWB_fixed_Asm_16: 8567 case ARM::VST4LNdWB_fixed_Asm_32: 8568 case ARM::VST4LNqWB_fixed_Asm_16: 8569 case ARM::VST4LNqWB_fixed_Asm_32: { 8570 MCInst TmpInst; 8571 // Shuffle the operands around so the lane index operand is in the 8572 // right place. 8573 unsigned Spacing; 8574 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8575 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8576 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8577 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8578 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8579 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8580 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8581 Spacing)); 8582 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8583 Spacing * 2)); 8584 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8585 Spacing * 3)); 8586 TmpInst.addOperand(Inst.getOperand(1)); // lane 8587 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8588 TmpInst.addOperand(Inst.getOperand(5)); 8589 Inst = TmpInst; 8590 return true; 8591 } 8592 8593 case ARM::VST1LNdAsm_8: 8594 case ARM::VST1LNdAsm_16: 8595 case ARM::VST1LNdAsm_32: { 8596 MCInst TmpInst; 8597 // Shuffle the operands around so the lane index operand is in the 8598 // right place. 8599 unsigned Spacing; 8600 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8601 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8602 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8603 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8604 TmpInst.addOperand(Inst.getOperand(1)); // lane 8605 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8606 TmpInst.addOperand(Inst.getOperand(5)); 8607 Inst = TmpInst; 8608 return true; 8609 } 8610 8611 case ARM::VST2LNdAsm_8: 8612 case ARM::VST2LNdAsm_16: 8613 case ARM::VST2LNdAsm_32: 8614 case ARM::VST2LNqAsm_16: 8615 case ARM::VST2LNqAsm_32: { 8616 MCInst TmpInst; 8617 // Shuffle the operands around so the lane index operand is in the 8618 // right place. 8619 unsigned Spacing; 8620 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8621 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8622 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8623 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8624 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8625 Spacing)); 8626 TmpInst.addOperand(Inst.getOperand(1)); // lane 8627 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8628 TmpInst.addOperand(Inst.getOperand(5)); 8629 Inst = TmpInst; 8630 return true; 8631 } 8632 8633 case ARM::VST3LNdAsm_8: 8634 case ARM::VST3LNdAsm_16: 8635 case ARM::VST3LNdAsm_32: 8636 case ARM::VST3LNqAsm_16: 8637 case ARM::VST3LNqAsm_32: { 8638 MCInst TmpInst; 8639 // Shuffle the operands around so the lane index operand is in the 8640 // right place. 8641 unsigned Spacing; 8642 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8643 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8644 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8645 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8646 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8647 Spacing)); 8648 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8649 Spacing * 2)); 8650 TmpInst.addOperand(Inst.getOperand(1)); // lane 8651 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8652 TmpInst.addOperand(Inst.getOperand(5)); 8653 Inst = TmpInst; 8654 return true; 8655 } 8656 8657 case ARM::VST4LNdAsm_8: 8658 case ARM::VST4LNdAsm_16: 8659 case ARM::VST4LNdAsm_32: 8660 case ARM::VST4LNqAsm_16: 8661 case ARM::VST4LNqAsm_32: { 8662 MCInst TmpInst; 8663 // Shuffle the operands around so the lane index operand is in the 8664 // right place. 8665 unsigned Spacing; 8666 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 8667 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8668 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8669 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8670 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8671 Spacing)); 8672 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8673 Spacing * 2)); 8674 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8675 Spacing * 3)); 8676 TmpInst.addOperand(Inst.getOperand(1)); // lane 8677 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8678 TmpInst.addOperand(Inst.getOperand(5)); 8679 Inst = TmpInst; 8680 return true; 8681 } 8682 8683 // Handle NEON VLD complex aliases. 8684 case ARM::VLD1LNdWB_register_Asm_8: 8685 case ARM::VLD1LNdWB_register_Asm_16: 8686 case ARM::VLD1LNdWB_register_Asm_32: { 8687 MCInst TmpInst; 8688 // Shuffle the operands around so the lane index operand is in the 8689 // right place. 8690 unsigned Spacing; 8691 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8692 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8693 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8694 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8695 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8696 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8697 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8698 TmpInst.addOperand(Inst.getOperand(1)); // lane 8699 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8700 TmpInst.addOperand(Inst.getOperand(6)); 8701 Inst = TmpInst; 8702 return true; 8703 } 8704 8705 case ARM::VLD2LNdWB_register_Asm_8: 8706 case ARM::VLD2LNdWB_register_Asm_16: 8707 case ARM::VLD2LNdWB_register_Asm_32: 8708 case ARM::VLD2LNqWB_register_Asm_16: 8709 case ARM::VLD2LNqWB_register_Asm_32: { 8710 MCInst TmpInst; 8711 // Shuffle the operands around so the lane index operand is in the 8712 // right place. 8713 unsigned Spacing; 8714 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8715 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8716 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8717 Spacing)); 8718 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8719 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8720 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8721 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8722 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8723 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8724 Spacing)); 8725 TmpInst.addOperand(Inst.getOperand(1)); // lane 8726 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8727 TmpInst.addOperand(Inst.getOperand(6)); 8728 Inst = TmpInst; 8729 return true; 8730 } 8731 8732 case ARM::VLD3LNdWB_register_Asm_8: 8733 case ARM::VLD3LNdWB_register_Asm_16: 8734 case ARM::VLD3LNdWB_register_Asm_32: 8735 case ARM::VLD3LNqWB_register_Asm_16: 8736 case ARM::VLD3LNqWB_register_Asm_32: { 8737 MCInst TmpInst; 8738 // Shuffle the operands around so the lane index operand is in the 8739 // right place. 8740 unsigned Spacing; 8741 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8742 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8743 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8744 Spacing)); 8745 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8746 Spacing * 2)); 8747 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8748 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8749 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8750 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8751 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8752 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8753 Spacing)); 8754 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8755 Spacing * 2)); 8756 TmpInst.addOperand(Inst.getOperand(1)); // lane 8757 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8758 TmpInst.addOperand(Inst.getOperand(6)); 8759 Inst = TmpInst; 8760 return true; 8761 } 8762 8763 case ARM::VLD4LNdWB_register_Asm_8: 8764 case ARM::VLD4LNdWB_register_Asm_16: 8765 case ARM::VLD4LNdWB_register_Asm_32: 8766 case ARM::VLD4LNqWB_register_Asm_16: 8767 case ARM::VLD4LNqWB_register_Asm_32: { 8768 MCInst TmpInst; 8769 // Shuffle the operands around so the lane index operand is in the 8770 // right place. 8771 unsigned Spacing; 8772 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8773 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8774 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8775 Spacing)); 8776 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8777 Spacing * 2)); 8778 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8779 Spacing * 3)); 8780 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8781 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8782 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8783 TmpInst.addOperand(Inst.getOperand(4)); // Rm 8784 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8786 Spacing)); 8787 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8788 Spacing * 2)); 8789 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8790 Spacing * 3)); 8791 TmpInst.addOperand(Inst.getOperand(1)); // lane 8792 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 8793 TmpInst.addOperand(Inst.getOperand(6)); 8794 Inst = TmpInst; 8795 return true; 8796 } 8797 8798 case ARM::VLD1LNdWB_fixed_Asm_8: 8799 case ARM::VLD1LNdWB_fixed_Asm_16: 8800 case ARM::VLD1LNdWB_fixed_Asm_32: { 8801 MCInst TmpInst; 8802 // Shuffle the operands around so the lane index operand is in the 8803 // right place. 8804 unsigned Spacing; 8805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8806 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8807 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8808 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8809 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8810 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8811 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8812 TmpInst.addOperand(Inst.getOperand(1)); // lane 8813 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8814 TmpInst.addOperand(Inst.getOperand(5)); 8815 Inst = TmpInst; 8816 return true; 8817 } 8818 8819 case ARM::VLD2LNdWB_fixed_Asm_8: 8820 case ARM::VLD2LNdWB_fixed_Asm_16: 8821 case ARM::VLD2LNdWB_fixed_Asm_32: 8822 case ARM::VLD2LNqWB_fixed_Asm_16: 8823 case ARM::VLD2LNqWB_fixed_Asm_32: { 8824 MCInst TmpInst; 8825 // Shuffle the operands around so the lane index operand is in the 8826 // right place. 8827 unsigned Spacing; 8828 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8829 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8830 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8831 Spacing)); 8832 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8833 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8834 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8835 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8836 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8837 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8838 Spacing)); 8839 TmpInst.addOperand(Inst.getOperand(1)); // lane 8840 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8841 TmpInst.addOperand(Inst.getOperand(5)); 8842 Inst = TmpInst; 8843 return true; 8844 } 8845 8846 case ARM::VLD3LNdWB_fixed_Asm_8: 8847 case ARM::VLD3LNdWB_fixed_Asm_16: 8848 case ARM::VLD3LNdWB_fixed_Asm_32: 8849 case ARM::VLD3LNqWB_fixed_Asm_16: 8850 case ARM::VLD3LNqWB_fixed_Asm_32: { 8851 MCInst TmpInst; 8852 // Shuffle the operands around so the lane index operand is in the 8853 // right place. 8854 unsigned Spacing; 8855 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8856 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8857 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8858 Spacing)); 8859 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8860 Spacing * 2)); 8861 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8862 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8863 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8864 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8865 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8866 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8867 Spacing)); 8868 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8869 Spacing * 2)); 8870 TmpInst.addOperand(Inst.getOperand(1)); // lane 8871 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8872 TmpInst.addOperand(Inst.getOperand(5)); 8873 Inst = TmpInst; 8874 return true; 8875 } 8876 8877 case ARM::VLD4LNdWB_fixed_Asm_8: 8878 case ARM::VLD4LNdWB_fixed_Asm_16: 8879 case ARM::VLD4LNdWB_fixed_Asm_32: 8880 case ARM::VLD4LNqWB_fixed_Asm_16: 8881 case ARM::VLD4LNqWB_fixed_Asm_32: { 8882 MCInst TmpInst; 8883 // Shuffle the operands around so the lane index operand is in the 8884 // right place. 8885 unsigned Spacing; 8886 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8887 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8888 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8889 Spacing)); 8890 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8891 Spacing * 2)); 8892 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8893 Spacing * 3)); 8894 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 8895 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8896 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8897 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 8898 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8899 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8900 Spacing)); 8901 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8902 Spacing * 2)); 8903 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8904 Spacing * 3)); 8905 TmpInst.addOperand(Inst.getOperand(1)); // lane 8906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8907 TmpInst.addOperand(Inst.getOperand(5)); 8908 Inst = TmpInst; 8909 return true; 8910 } 8911 8912 case ARM::VLD1LNdAsm_8: 8913 case ARM::VLD1LNdAsm_16: 8914 case ARM::VLD1LNdAsm_32: { 8915 MCInst TmpInst; 8916 // Shuffle the operands around so the lane index operand is in the 8917 // right place. 8918 unsigned Spacing; 8919 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8920 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8921 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8922 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8923 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8924 TmpInst.addOperand(Inst.getOperand(1)); // lane 8925 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8926 TmpInst.addOperand(Inst.getOperand(5)); 8927 Inst = TmpInst; 8928 return true; 8929 } 8930 8931 case ARM::VLD2LNdAsm_8: 8932 case ARM::VLD2LNdAsm_16: 8933 case ARM::VLD2LNdAsm_32: 8934 case ARM::VLD2LNqAsm_16: 8935 case ARM::VLD2LNqAsm_32: { 8936 MCInst TmpInst; 8937 // Shuffle the operands around so the lane index operand is in the 8938 // right place. 8939 unsigned Spacing; 8940 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8941 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8942 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8943 Spacing)); 8944 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8945 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8946 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8947 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8948 Spacing)); 8949 TmpInst.addOperand(Inst.getOperand(1)); // lane 8950 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8951 TmpInst.addOperand(Inst.getOperand(5)); 8952 Inst = TmpInst; 8953 return true; 8954 } 8955 8956 case ARM::VLD3LNdAsm_8: 8957 case ARM::VLD3LNdAsm_16: 8958 case ARM::VLD3LNdAsm_32: 8959 case ARM::VLD3LNqAsm_16: 8960 case ARM::VLD3LNqAsm_32: { 8961 MCInst TmpInst; 8962 // Shuffle the operands around so the lane index operand is in the 8963 // right place. 8964 unsigned Spacing; 8965 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8966 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8967 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8968 Spacing)); 8969 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8970 Spacing * 2)); 8971 TmpInst.addOperand(Inst.getOperand(2)); // Rn 8972 TmpInst.addOperand(Inst.getOperand(3)); // alignment 8973 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 8974 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8975 Spacing)); 8976 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8977 Spacing * 2)); 8978 TmpInst.addOperand(Inst.getOperand(1)); // lane 8979 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 8980 TmpInst.addOperand(Inst.getOperand(5)); 8981 Inst = TmpInst; 8982 return true; 8983 } 8984 8985 case ARM::VLD4LNdAsm_8: 8986 case ARM::VLD4LNdAsm_16: 8987 case ARM::VLD4LNdAsm_32: 8988 case ARM::VLD4LNqAsm_16: 8989 case ARM::VLD4LNqAsm_32: { 8990 MCInst TmpInst; 8991 // Shuffle the operands around so the lane index operand is in the 8992 // right place. 8993 unsigned Spacing; 8994 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 8995 TmpInst.addOperand(Inst.getOperand(0)); // Vd 8996 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8997 Spacing)); 8998 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 8999 Spacing * 2)); 9000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9001 Spacing * 3)); 9002 TmpInst.addOperand(Inst.getOperand(2)); // Rn 9003 TmpInst.addOperand(Inst.getOperand(3)); // alignment 9004 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 9005 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9006 Spacing)); 9007 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9008 Spacing * 2)); 9009 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9010 Spacing * 3)); 9011 TmpInst.addOperand(Inst.getOperand(1)); // lane 9012 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9013 TmpInst.addOperand(Inst.getOperand(5)); 9014 Inst = TmpInst; 9015 return true; 9016 } 9017 9018 // VLD3DUP single 3-element structure to all lanes instructions. 9019 case ARM::VLD3DUPdAsm_8: 9020 case ARM::VLD3DUPdAsm_16: 9021 case ARM::VLD3DUPdAsm_32: 9022 case ARM::VLD3DUPqAsm_8: 9023 case ARM::VLD3DUPqAsm_16: 9024 case ARM::VLD3DUPqAsm_32: { 9025 MCInst TmpInst; 9026 unsigned Spacing; 9027 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9028 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9029 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9030 Spacing)); 9031 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9032 Spacing * 2)); 9033 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9034 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9035 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9036 TmpInst.addOperand(Inst.getOperand(4)); 9037 Inst = TmpInst; 9038 return true; 9039 } 9040 9041 case ARM::VLD3DUPdWB_fixed_Asm_8: 9042 case ARM::VLD3DUPdWB_fixed_Asm_16: 9043 case ARM::VLD3DUPdWB_fixed_Asm_32: 9044 case ARM::VLD3DUPqWB_fixed_Asm_8: 9045 case ARM::VLD3DUPqWB_fixed_Asm_16: 9046 case ARM::VLD3DUPqWB_fixed_Asm_32: { 9047 MCInst TmpInst; 9048 unsigned Spacing; 9049 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9050 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9051 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9052 Spacing)); 9053 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9054 Spacing * 2)); 9055 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9056 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9057 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9058 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9059 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9060 TmpInst.addOperand(Inst.getOperand(4)); 9061 Inst = TmpInst; 9062 return true; 9063 } 9064 9065 case ARM::VLD3DUPdWB_register_Asm_8: 9066 case ARM::VLD3DUPdWB_register_Asm_16: 9067 case ARM::VLD3DUPdWB_register_Asm_32: 9068 case ARM::VLD3DUPqWB_register_Asm_8: 9069 case ARM::VLD3DUPqWB_register_Asm_16: 9070 case ARM::VLD3DUPqWB_register_Asm_32: { 9071 MCInst TmpInst; 9072 unsigned Spacing; 9073 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9074 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9075 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9076 Spacing)); 9077 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9078 Spacing * 2)); 9079 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9080 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9081 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9082 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9083 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9084 TmpInst.addOperand(Inst.getOperand(5)); 9085 Inst = TmpInst; 9086 return true; 9087 } 9088 9089 // VLD3 multiple 3-element structure instructions. 9090 case ARM::VLD3dAsm_8: 9091 case ARM::VLD3dAsm_16: 9092 case ARM::VLD3dAsm_32: 9093 case ARM::VLD3qAsm_8: 9094 case ARM::VLD3qAsm_16: 9095 case ARM::VLD3qAsm_32: { 9096 MCInst TmpInst; 9097 unsigned Spacing; 9098 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9099 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9100 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9101 Spacing)); 9102 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9103 Spacing * 2)); 9104 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9105 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9106 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9107 TmpInst.addOperand(Inst.getOperand(4)); 9108 Inst = TmpInst; 9109 return true; 9110 } 9111 9112 case ARM::VLD3dWB_fixed_Asm_8: 9113 case ARM::VLD3dWB_fixed_Asm_16: 9114 case ARM::VLD3dWB_fixed_Asm_32: 9115 case ARM::VLD3qWB_fixed_Asm_8: 9116 case ARM::VLD3qWB_fixed_Asm_16: 9117 case ARM::VLD3qWB_fixed_Asm_32: { 9118 MCInst TmpInst; 9119 unsigned Spacing; 9120 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9121 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9122 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9123 Spacing)); 9124 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9125 Spacing * 2)); 9126 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9127 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9128 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9129 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9130 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9131 TmpInst.addOperand(Inst.getOperand(4)); 9132 Inst = TmpInst; 9133 return true; 9134 } 9135 9136 case ARM::VLD3dWB_register_Asm_8: 9137 case ARM::VLD3dWB_register_Asm_16: 9138 case ARM::VLD3dWB_register_Asm_32: 9139 case ARM::VLD3qWB_register_Asm_8: 9140 case ARM::VLD3qWB_register_Asm_16: 9141 case ARM::VLD3qWB_register_Asm_32: { 9142 MCInst TmpInst; 9143 unsigned Spacing; 9144 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9145 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9146 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9147 Spacing)); 9148 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9149 Spacing * 2)); 9150 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9151 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9152 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9153 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9154 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9155 TmpInst.addOperand(Inst.getOperand(5)); 9156 Inst = TmpInst; 9157 return true; 9158 } 9159 9160 // VLD4DUP single 3-element structure to all lanes instructions. 9161 case ARM::VLD4DUPdAsm_8: 9162 case ARM::VLD4DUPdAsm_16: 9163 case ARM::VLD4DUPdAsm_32: 9164 case ARM::VLD4DUPqAsm_8: 9165 case ARM::VLD4DUPqAsm_16: 9166 case ARM::VLD4DUPqAsm_32: { 9167 MCInst TmpInst; 9168 unsigned Spacing; 9169 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9170 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9171 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9172 Spacing)); 9173 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9174 Spacing * 2)); 9175 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9176 Spacing * 3)); 9177 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9178 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9179 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9180 TmpInst.addOperand(Inst.getOperand(4)); 9181 Inst = TmpInst; 9182 return true; 9183 } 9184 9185 case ARM::VLD4DUPdWB_fixed_Asm_8: 9186 case ARM::VLD4DUPdWB_fixed_Asm_16: 9187 case ARM::VLD4DUPdWB_fixed_Asm_32: 9188 case ARM::VLD4DUPqWB_fixed_Asm_8: 9189 case ARM::VLD4DUPqWB_fixed_Asm_16: 9190 case ARM::VLD4DUPqWB_fixed_Asm_32: { 9191 MCInst TmpInst; 9192 unsigned Spacing; 9193 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9194 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9195 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9196 Spacing)); 9197 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9198 Spacing * 2)); 9199 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9200 Spacing * 3)); 9201 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9202 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9203 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9204 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9205 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9206 TmpInst.addOperand(Inst.getOperand(4)); 9207 Inst = TmpInst; 9208 return true; 9209 } 9210 9211 case ARM::VLD4DUPdWB_register_Asm_8: 9212 case ARM::VLD4DUPdWB_register_Asm_16: 9213 case ARM::VLD4DUPdWB_register_Asm_32: 9214 case ARM::VLD4DUPqWB_register_Asm_8: 9215 case ARM::VLD4DUPqWB_register_Asm_16: 9216 case ARM::VLD4DUPqWB_register_Asm_32: { 9217 MCInst TmpInst; 9218 unsigned Spacing; 9219 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9220 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9221 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9222 Spacing)); 9223 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9224 Spacing * 2)); 9225 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9226 Spacing * 3)); 9227 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9228 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9229 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9230 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9231 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9232 TmpInst.addOperand(Inst.getOperand(5)); 9233 Inst = TmpInst; 9234 return true; 9235 } 9236 9237 // VLD4 multiple 4-element structure instructions. 9238 case ARM::VLD4dAsm_8: 9239 case ARM::VLD4dAsm_16: 9240 case ARM::VLD4dAsm_32: 9241 case ARM::VLD4qAsm_8: 9242 case ARM::VLD4qAsm_16: 9243 case ARM::VLD4qAsm_32: { 9244 MCInst TmpInst; 9245 unsigned Spacing; 9246 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9247 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9248 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9249 Spacing)); 9250 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9251 Spacing * 2)); 9252 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9253 Spacing * 3)); 9254 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9255 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9256 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9257 TmpInst.addOperand(Inst.getOperand(4)); 9258 Inst = TmpInst; 9259 return true; 9260 } 9261 9262 case ARM::VLD4dWB_fixed_Asm_8: 9263 case ARM::VLD4dWB_fixed_Asm_16: 9264 case ARM::VLD4dWB_fixed_Asm_32: 9265 case ARM::VLD4qWB_fixed_Asm_8: 9266 case ARM::VLD4qWB_fixed_Asm_16: 9267 case ARM::VLD4qWB_fixed_Asm_32: { 9268 MCInst TmpInst; 9269 unsigned Spacing; 9270 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9271 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9272 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9273 Spacing)); 9274 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9275 Spacing * 2)); 9276 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9277 Spacing * 3)); 9278 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9279 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9280 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9281 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9282 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9283 TmpInst.addOperand(Inst.getOperand(4)); 9284 Inst = TmpInst; 9285 return true; 9286 } 9287 9288 case ARM::VLD4dWB_register_Asm_8: 9289 case ARM::VLD4dWB_register_Asm_16: 9290 case ARM::VLD4dWB_register_Asm_32: 9291 case ARM::VLD4qWB_register_Asm_8: 9292 case ARM::VLD4qWB_register_Asm_16: 9293 case ARM::VLD4qWB_register_Asm_32: { 9294 MCInst TmpInst; 9295 unsigned Spacing; 9296 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 9297 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9298 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9299 Spacing)); 9300 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9301 Spacing * 2)); 9302 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9303 Spacing * 3)); 9304 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9305 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9306 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9307 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9308 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9309 TmpInst.addOperand(Inst.getOperand(5)); 9310 Inst = TmpInst; 9311 return true; 9312 } 9313 9314 // VST3 multiple 3-element structure instructions. 9315 case ARM::VST3dAsm_8: 9316 case ARM::VST3dAsm_16: 9317 case ARM::VST3dAsm_32: 9318 case ARM::VST3qAsm_8: 9319 case ARM::VST3qAsm_16: 9320 case ARM::VST3qAsm_32: { 9321 MCInst TmpInst; 9322 unsigned Spacing; 9323 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9324 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9325 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9326 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9327 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9328 Spacing)); 9329 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9330 Spacing * 2)); 9331 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9332 TmpInst.addOperand(Inst.getOperand(4)); 9333 Inst = TmpInst; 9334 return true; 9335 } 9336 9337 case ARM::VST3dWB_fixed_Asm_8: 9338 case ARM::VST3dWB_fixed_Asm_16: 9339 case ARM::VST3dWB_fixed_Asm_32: 9340 case ARM::VST3qWB_fixed_Asm_8: 9341 case ARM::VST3qWB_fixed_Asm_16: 9342 case ARM::VST3qWB_fixed_Asm_32: { 9343 MCInst TmpInst; 9344 unsigned Spacing; 9345 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9346 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9347 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9348 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9349 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9350 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9351 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9352 Spacing)); 9353 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9354 Spacing * 2)); 9355 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9356 TmpInst.addOperand(Inst.getOperand(4)); 9357 Inst = TmpInst; 9358 return true; 9359 } 9360 9361 case ARM::VST3dWB_register_Asm_8: 9362 case ARM::VST3dWB_register_Asm_16: 9363 case ARM::VST3dWB_register_Asm_32: 9364 case ARM::VST3qWB_register_Asm_8: 9365 case ARM::VST3qWB_register_Asm_16: 9366 case ARM::VST3qWB_register_Asm_32: { 9367 MCInst TmpInst; 9368 unsigned Spacing; 9369 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9370 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9371 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9372 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9373 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9374 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9375 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9376 Spacing)); 9377 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9378 Spacing * 2)); 9379 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9380 TmpInst.addOperand(Inst.getOperand(5)); 9381 Inst = TmpInst; 9382 return true; 9383 } 9384 9385 // VST4 multiple 3-element structure instructions. 9386 case ARM::VST4dAsm_8: 9387 case ARM::VST4dAsm_16: 9388 case ARM::VST4dAsm_32: 9389 case ARM::VST4qAsm_8: 9390 case ARM::VST4qAsm_16: 9391 case ARM::VST4qAsm_32: { 9392 MCInst TmpInst; 9393 unsigned Spacing; 9394 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9395 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9396 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9397 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9398 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9399 Spacing)); 9400 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9401 Spacing * 2)); 9402 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9403 Spacing * 3)); 9404 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9405 TmpInst.addOperand(Inst.getOperand(4)); 9406 Inst = TmpInst; 9407 return true; 9408 } 9409 9410 case ARM::VST4dWB_fixed_Asm_8: 9411 case ARM::VST4dWB_fixed_Asm_16: 9412 case ARM::VST4dWB_fixed_Asm_32: 9413 case ARM::VST4qWB_fixed_Asm_8: 9414 case ARM::VST4qWB_fixed_Asm_16: 9415 case ARM::VST4qWB_fixed_Asm_32: { 9416 MCInst TmpInst; 9417 unsigned Spacing; 9418 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9419 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9420 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9421 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9422 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 9423 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9424 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9425 Spacing)); 9426 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9427 Spacing * 2)); 9428 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9429 Spacing * 3)); 9430 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9431 TmpInst.addOperand(Inst.getOperand(4)); 9432 Inst = TmpInst; 9433 return true; 9434 } 9435 9436 case ARM::VST4dWB_register_Asm_8: 9437 case ARM::VST4dWB_register_Asm_16: 9438 case ARM::VST4dWB_register_Asm_32: 9439 case ARM::VST4qWB_register_Asm_8: 9440 case ARM::VST4qWB_register_Asm_16: 9441 case ARM::VST4qWB_register_Asm_32: { 9442 MCInst TmpInst; 9443 unsigned Spacing; 9444 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 9445 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9446 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 9447 TmpInst.addOperand(Inst.getOperand(2)); // alignment 9448 TmpInst.addOperand(Inst.getOperand(3)); // Rm 9449 TmpInst.addOperand(Inst.getOperand(0)); // Vd 9450 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9451 Spacing)); 9452 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9453 Spacing * 2)); 9454 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 9455 Spacing * 3)); 9456 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9457 TmpInst.addOperand(Inst.getOperand(5)); 9458 Inst = TmpInst; 9459 return true; 9460 } 9461 9462 // Handle encoding choice for the shift-immediate instructions. 9463 case ARM::t2LSLri: 9464 case ARM::t2LSRri: 9465 case ARM::t2ASRri: 9466 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9467 isARMLowRegister(Inst.getOperand(1).getReg()) && 9468 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9469 !HasWideQualifier) { 9470 unsigned NewOpc; 9471 switch (Inst.getOpcode()) { 9472 default: llvm_unreachable("unexpected opcode"); 9473 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 9474 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 9475 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 9476 } 9477 // The Thumb1 operands aren't in the same order. Awesome, eh? 9478 MCInst TmpInst; 9479 TmpInst.setOpcode(NewOpc); 9480 TmpInst.addOperand(Inst.getOperand(0)); 9481 TmpInst.addOperand(Inst.getOperand(5)); 9482 TmpInst.addOperand(Inst.getOperand(1)); 9483 TmpInst.addOperand(Inst.getOperand(2)); 9484 TmpInst.addOperand(Inst.getOperand(3)); 9485 TmpInst.addOperand(Inst.getOperand(4)); 9486 Inst = TmpInst; 9487 return true; 9488 } 9489 return false; 9490 9491 // Handle the Thumb2 mode MOV complex aliases. 9492 case ARM::t2MOVsr: 9493 case ARM::t2MOVSsr: { 9494 // Which instruction to expand to depends on the CCOut operand and 9495 // whether we're in an IT block if the register operands are low 9496 // registers. 9497 bool isNarrow = false; 9498 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9499 isARMLowRegister(Inst.getOperand(1).getReg()) && 9500 isARMLowRegister(Inst.getOperand(2).getReg()) && 9501 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 9502 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && 9503 !HasWideQualifier) 9504 isNarrow = true; 9505 MCInst TmpInst; 9506 unsigned newOpc; 9507 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 9508 default: llvm_unreachable("unexpected opcode!"); 9509 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 9510 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 9511 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 9512 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 9513 } 9514 TmpInst.setOpcode(newOpc); 9515 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9516 if (isNarrow) 9517 TmpInst.addOperand(MCOperand::createReg( 9518 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 9519 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9520 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9521 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 9522 TmpInst.addOperand(Inst.getOperand(5)); 9523 if (!isNarrow) 9524 TmpInst.addOperand(MCOperand::createReg( 9525 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 9526 Inst = TmpInst; 9527 return true; 9528 } 9529 case ARM::t2MOVsi: 9530 case ARM::t2MOVSsi: { 9531 // Which instruction to expand to depends on the CCOut operand and 9532 // whether we're in an IT block if the register operands are low 9533 // registers. 9534 bool isNarrow = false; 9535 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9536 isARMLowRegister(Inst.getOperand(1).getReg()) && 9537 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && 9538 !HasWideQualifier) 9539 isNarrow = true; 9540 MCInst TmpInst; 9541 unsigned newOpc; 9542 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 9543 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 9544 bool isMov = false; 9545 // MOV rd, rm, LSL #0 is actually a MOV instruction 9546 if (Shift == ARM_AM::lsl && Amount == 0) { 9547 isMov = true; 9548 // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of 9549 // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is 9550 // unpredictable in an IT block so the 32-bit encoding T3 has to be used 9551 // instead. 9552 if (inITBlock()) { 9553 isNarrow = false; 9554 } 9555 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; 9556 } else { 9557 switch(Shift) { 9558 default: llvm_unreachable("unexpected opcode!"); 9559 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 9560 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 9561 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 9562 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 9563 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 9564 } 9565 } 9566 if (Amount == 32) Amount = 0; 9567 TmpInst.setOpcode(newOpc); 9568 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9569 if (isNarrow && !isMov) 9570 TmpInst.addOperand(MCOperand::createReg( 9571 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 9572 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9573 if (newOpc != ARM::t2RRX && !isMov) 9574 TmpInst.addOperand(MCOperand::createImm(Amount)); 9575 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9576 TmpInst.addOperand(Inst.getOperand(4)); 9577 if (!isNarrow) 9578 TmpInst.addOperand(MCOperand::createReg( 9579 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 9580 Inst = TmpInst; 9581 return true; 9582 } 9583 // Handle the ARM mode MOV complex aliases. 9584 case ARM::ASRr: 9585 case ARM::LSRr: 9586 case ARM::LSLr: 9587 case ARM::RORr: { 9588 ARM_AM::ShiftOpc ShiftTy; 9589 switch(Inst.getOpcode()) { 9590 default: llvm_unreachable("unexpected opcode!"); 9591 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 9592 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 9593 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 9594 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 9595 } 9596 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 9597 MCInst TmpInst; 9598 TmpInst.setOpcode(ARM::MOVsr); 9599 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9600 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9601 TmpInst.addOperand(Inst.getOperand(2)); // Rm 9602 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 9603 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9604 TmpInst.addOperand(Inst.getOperand(4)); 9605 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9606 Inst = TmpInst; 9607 return true; 9608 } 9609 case ARM::ASRi: 9610 case ARM::LSRi: 9611 case ARM::LSLi: 9612 case ARM::RORi: { 9613 ARM_AM::ShiftOpc ShiftTy; 9614 switch(Inst.getOpcode()) { 9615 default: llvm_unreachable("unexpected opcode!"); 9616 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 9617 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 9618 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 9619 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 9620 } 9621 // A shift by zero is a plain MOVr, not a MOVsi. 9622 unsigned Amt = Inst.getOperand(2).getImm(); 9623 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 9624 // A shift by 32 should be encoded as 0 when permitted 9625 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 9626 Amt = 0; 9627 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 9628 MCInst TmpInst; 9629 TmpInst.setOpcode(Opc); 9630 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9631 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9632 if (Opc == ARM::MOVsi) 9633 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 9634 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 9635 TmpInst.addOperand(Inst.getOperand(4)); 9636 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 9637 Inst = TmpInst; 9638 return true; 9639 } 9640 case ARM::RRXi: { 9641 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 9642 MCInst TmpInst; 9643 TmpInst.setOpcode(ARM::MOVsi); 9644 TmpInst.addOperand(Inst.getOperand(0)); // Rd 9645 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9646 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 9647 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9648 TmpInst.addOperand(Inst.getOperand(3)); 9649 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 9650 Inst = TmpInst; 9651 return true; 9652 } 9653 case ARM::t2LDMIA_UPD: { 9654 // If this is a load of a single register, then we should use 9655 // a post-indexed LDR instruction instead, per the ARM ARM. 9656 if (Inst.getNumOperands() != 5) 9657 return false; 9658 MCInst TmpInst; 9659 TmpInst.setOpcode(ARM::t2LDR_POST); 9660 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9661 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9662 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9663 TmpInst.addOperand(MCOperand::createImm(4)); 9664 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9665 TmpInst.addOperand(Inst.getOperand(3)); 9666 Inst = TmpInst; 9667 return true; 9668 } 9669 case ARM::t2STMDB_UPD: { 9670 // If this is a store of a single register, then we should use 9671 // a pre-indexed STR instruction instead, per the ARM ARM. 9672 if (Inst.getNumOperands() != 5) 9673 return false; 9674 MCInst TmpInst; 9675 TmpInst.setOpcode(ARM::t2STR_PRE); 9676 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9677 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9678 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9679 TmpInst.addOperand(MCOperand::createImm(-4)); 9680 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9681 TmpInst.addOperand(Inst.getOperand(3)); 9682 Inst = TmpInst; 9683 return true; 9684 } 9685 case ARM::LDMIA_UPD: 9686 // If this is a load of a single register via a 'pop', then we should use 9687 // a post-indexed LDR instruction instead, per the ARM ARM. 9688 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && 9689 Inst.getNumOperands() == 5) { 9690 MCInst TmpInst; 9691 TmpInst.setOpcode(ARM::LDR_POST_IMM); 9692 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9693 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9694 TmpInst.addOperand(Inst.getOperand(1)); // Rn 9695 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset 9696 TmpInst.addOperand(MCOperand::createImm(4)); 9697 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9698 TmpInst.addOperand(Inst.getOperand(3)); 9699 Inst = TmpInst; 9700 return true; 9701 } 9702 break; 9703 case ARM::STMDB_UPD: 9704 // If this is a store of a single register via a 'push', then we should use 9705 // a pre-indexed STR instruction instead, per the ARM ARM. 9706 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && 9707 Inst.getNumOperands() == 5) { 9708 MCInst TmpInst; 9709 TmpInst.setOpcode(ARM::STR_PRE_IMM); 9710 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 9711 TmpInst.addOperand(Inst.getOperand(4)); // Rt 9712 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 9713 TmpInst.addOperand(MCOperand::createImm(-4)); 9714 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 9715 TmpInst.addOperand(Inst.getOperand(3)); 9716 Inst = TmpInst; 9717 } 9718 break; 9719 case ARM::t2ADDri12: 9720 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 9721 // mnemonic was used (not "addw"), encoding T3 is preferred. 9722 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || 9723 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9724 break; 9725 Inst.setOpcode(ARM::t2ADDri); 9726 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9727 break; 9728 case ARM::t2SUBri12: 9729 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 9730 // mnemonic was used (not "subw"), encoding T3 is preferred. 9731 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || 9732 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 9733 break; 9734 Inst.setOpcode(ARM::t2SUBri); 9735 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9736 break; 9737 case ARM::tADDi8: 9738 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 9739 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 9740 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 9741 // to encoding T1 if <Rd> is omitted." 9742 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9743 Inst.setOpcode(ARM::tADDi3); 9744 return true; 9745 } 9746 break; 9747 case ARM::tSUBi8: 9748 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 9749 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 9750 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 9751 // to encoding T1 if <Rd> is omitted." 9752 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 9753 Inst.setOpcode(ARM::tSUBi3); 9754 return true; 9755 } 9756 break; 9757 case ARM::t2ADDri: 9758 case ARM::t2SUBri: { 9759 // If the destination and first source operand are the same, and 9760 // the flags are compatible with the current IT status, use encoding T2 9761 // instead of T3. For compatibility with the system 'as'. Make sure the 9762 // wide encoding wasn't explicit. 9763 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 9764 !isARMLowRegister(Inst.getOperand(0).getReg()) || 9765 (Inst.getOperand(2).isImm() && 9766 (unsigned)Inst.getOperand(2).getImm() > 255) || 9767 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || 9768 HasWideQualifier) 9769 break; 9770 MCInst TmpInst; 9771 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 9772 ARM::tADDi8 : ARM::tSUBi8); 9773 TmpInst.addOperand(Inst.getOperand(0)); 9774 TmpInst.addOperand(Inst.getOperand(5)); 9775 TmpInst.addOperand(Inst.getOperand(0)); 9776 TmpInst.addOperand(Inst.getOperand(2)); 9777 TmpInst.addOperand(Inst.getOperand(3)); 9778 TmpInst.addOperand(Inst.getOperand(4)); 9779 Inst = TmpInst; 9780 return true; 9781 } 9782 case ARM::t2ADDrr: { 9783 // If the destination and first source operand are the same, and 9784 // there's no setting of the flags, use encoding T2 instead of T3. 9785 // Note that this is only for ADD, not SUB. This mirrors the system 9786 // 'as' behaviour. Also take advantage of ADD being commutative. 9787 // Make sure the wide encoding wasn't explicit. 9788 bool Swap = false; 9789 auto DestReg = Inst.getOperand(0).getReg(); 9790 bool Transform = DestReg == Inst.getOperand(1).getReg(); 9791 if (!Transform && DestReg == Inst.getOperand(2).getReg()) { 9792 Transform = true; 9793 Swap = true; 9794 } 9795 if (!Transform || 9796 Inst.getOperand(5).getReg() != 0 || 9797 HasWideQualifier) 9798 break; 9799 MCInst TmpInst; 9800 TmpInst.setOpcode(ARM::tADDhirr); 9801 TmpInst.addOperand(Inst.getOperand(0)); 9802 TmpInst.addOperand(Inst.getOperand(0)); 9803 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); 9804 TmpInst.addOperand(Inst.getOperand(3)); 9805 TmpInst.addOperand(Inst.getOperand(4)); 9806 Inst = TmpInst; 9807 return true; 9808 } 9809 case ARM::tADDrSP: 9810 // If the non-SP source operand and the destination operand are not the 9811 // same, we need to use the 32-bit encoding if it's available. 9812 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 9813 Inst.setOpcode(ARM::t2ADDrr); 9814 Inst.addOperand(MCOperand::createReg(0)); // cc_out 9815 return true; 9816 } 9817 break; 9818 case ARM::tB: 9819 // A Thumb conditional branch outside of an IT block is a tBcc. 9820 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 9821 Inst.setOpcode(ARM::tBcc); 9822 return true; 9823 } 9824 break; 9825 case ARM::t2B: 9826 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 9827 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 9828 Inst.setOpcode(ARM::t2Bcc); 9829 return true; 9830 } 9831 break; 9832 case ARM::t2Bcc: 9833 // If the conditional is AL or we're in an IT block, we really want t2B. 9834 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 9835 Inst.setOpcode(ARM::t2B); 9836 return true; 9837 } 9838 break; 9839 case ARM::tBcc: 9840 // If the conditional is AL, we really want tB. 9841 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 9842 Inst.setOpcode(ARM::tB); 9843 return true; 9844 } 9845 break; 9846 case ARM::tLDMIA: { 9847 // If the register list contains any high registers, or if the writeback 9848 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 9849 // instead if we're in Thumb2. Otherwise, this should have generated 9850 // an error in validateInstruction(). 9851 unsigned Rn = Inst.getOperand(0).getReg(); 9852 bool hasWritebackToken = 9853 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 9854 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 9855 bool listContainsBase; 9856 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 9857 (!listContainsBase && !hasWritebackToken) || 9858 (listContainsBase && hasWritebackToken)) { 9859 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 9860 assert(isThumbTwo()); 9861 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 9862 // If we're switching to the updating version, we need to insert 9863 // the writeback tied operand. 9864 if (hasWritebackToken) 9865 Inst.insert(Inst.begin(), 9866 MCOperand::createReg(Inst.getOperand(0).getReg())); 9867 return true; 9868 } 9869 break; 9870 } 9871 case ARM::tSTMIA_UPD: { 9872 // If the register list contains any high registers, we need to use 9873 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 9874 // should have generated an error in validateInstruction(). 9875 unsigned Rn = Inst.getOperand(0).getReg(); 9876 bool listContainsBase; 9877 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 9878 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 9879 assert(isThumbTwo()); 9880 Inst.setOpcode(ARM::t2STMIA_UPD); 9881 return true; 9882 } 9883 break; 9884 } 9885 case ARM::tPOP: { 9886 bool listContainsBase; 9887 // If the register list contains any high registers, we need to use 9888 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 9889 // should have generated an error in validateInstruction(). 9890 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 9891 return false; 9892 assert(isThumbTwo()); 9893 Inst.setOpcode(ARM::t2LDMIA_UPD); 9894 // Add the base register and writeback operands. 9895 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9896 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9897 return true; 9898 } 9899 case ARM::tPUSH: { 9900 bool listContainsBase; 9901 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 9902 return false; 9903 assert(isThumbTwo()); 9904 Inst.setOpcode(ARM::t2STMDB_UPD); 9905 // Add the base register and writeback operands. 9906 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9907 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 9908 return true; 9909 } 9910 case ARM::t2MOVi: 9911 // If we can use the 16-bit encoding and the user didn't explicitly 9912 // request the 32-bit variant, transform it here. 9913 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9914 (Inst.getOperand(1).isImm() && 9915 (unsigned)Inst.getOperand(1).getImm() <= 255) && 9916 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 9917 !HasWideQualifier) { 9918 // The operands aren't in the same order for tMOVi8... 9919 MCInst TmpInst; 9920 TmpInst.setOpcode(ARM::tMOVi8); 9921 TmpInst.addOperand(Inst.getOperand(0)); 9922 TmpInst.addOperand(Inst.getOperand(4)); 9923 TmpInst.addOperand(Inst.getOperand(1)); 9924 TmpInst.addOperand(Inst.getOperand(2)); 9925 TmpInst.addOperand(Inst.getOperand(3)); 9926 Inst = TmpInst; 9927 return true; 9928 } 9929 break; 9930 9931 case ARM::t2MOVr: 9932 // If we can use the 16-bit encoding and the user didn't explicitly 9933 // request the 32-bit variant, transform it here. 9934 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9935 isARMLowRegister(Inst.getOperand(1).getReg()) && 9936 Inst.getOperand(2).getImm() == ARMCC::AL && 9937 Inst.getOperand(4).getReg() == ARM::CPSR && 9938 !HasWideQualifier) { 9939 // The operands aren't the same for tMOV[S]r... (no cc_out) 9940 MCInst TmpInst; 9941 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 9942 TmpInst.addOperand(Inst.getOperand(0)); 9943 TmpInst.addOperand(Inst.getOperand(1)); 9944 TmpInst.addOperand(Inst.getOperand(2)); 9945 TmpInst.addOperand(Inst.getOperand(3)); 9946 Inst = TmpInst; 9947 return true; 9948 } 9949 break; 9950 9951 case ARM::t2SXTH: 9952 case ARM::t2SXTB: 9953 case ARM::t2UXTH: 9954 case ARM::t2UXTB: 9955 // If we can use the 16-bit encoding and the user didn't explicitly 9956 // request the 32-bit variant, transform it here. 9957 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 9958 isARMLowRegister(Inst.getOperand(1).getReg()) && 9959 Inst.getOperand(2).getImm() == 0 && 9960 !HasWideQualifier) { 9961 unsigned NewOpc; 9962 switch (Inst.getOpcode()) { 9963 default: llvm_unreachable("Illegal opcode!"); 9964 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 9965 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 9966 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 9967 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 9968 } 9969 // The operands aren't the same for thumb1 (no rotate operand). 9970 MCInst TmpInst; 9971 TmpInst.setOpcode(NewOpc); 9972 TmpInst.addOperand(Inst.getOperand(0)); 9973 TmpInst.addOperand(Inst.getOperand(1)); 9974 TmpInst.addOperand(Inst.getOperand(3)); 9975 TmpInst.addOperand(Inst.getOperand(4)); 9976 Inst = TmpInst; 9977 return true; 9978 } 9979 break; 9980 9981 case ARM::MOVsi: { 9982 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 9983 // rrx shifts and asr/lsr of #32 is encoded as 0 9984 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 9985 return false; 9986 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 9987 // Shifting by zero is accepted as a vanilla 'MOVr' 9988 MCInst TmpInst; 9989 TmpInst.setOpcode(ARM::MOVr); 9990 TmpInst.addOperand(Inst.getOperand(0)); 9991 TmpInst.addOperand(Inst.getOperand(1)); 9992 TmpInst.addOperand(Inst.getOperand(3)); 9993 TmpInst.addOperand(Inst.getOperand(4)); 9994 TmpInst.addOperand(Inst.getOperand(5)); 9995 Inst = TmpInst; 9996 return true; 9997 } 9998 return false; 9999 } 10000 case ARM::ANDrsi: 10001 case ARM::ORRrsi: 10002 case ARM::EORrsi: 10003 case ARM::BICrsi: 10004 case ARM::SUBrsi: 10005 case ARM::ADDrsi: { 10006 unsigned newOpc; 10007 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 10008 if (SOpc == ARM_AM::rrx) return false; 10009 switch (Inst.getOpcode()) { 10010 default: llvm_unreachable("unexpected opcode!"); 10011 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 10012 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 10013 case ARM::EORrsi: newOpc = ARM::EORrr; break; 10014 case ARM::BICrsi: newOpc = ARM::BICrr; break; 10015 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 10016 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 10017 } 10018 // If the shift is by zero, use the non-shifted instruction definition. 10019 // The exception is for right shifts, where 0 == 32 10020 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 10021 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 10022 MCInst TmpInst; 10023 TmpInst.setOpcode(newOpc); 10024 TmpInst.addOperand(Inst.getOperand(0)); 10025 TmpInst.addOperand(Inst.getOperand(1)); 10026 TmpInst.addOperand(Inst.getOperand(2)); 10027 TmpInst.addOperand(Inst.getOperand(4)); 10028 TmpInst.addOperand(Inst.getOperand(5)); 10029 TmpInst.addOperand(Inst.getOperand(6)); 10030 Inst = TmpInst; 10031 return true; 10032 } 10033 return false; 10034 } 10035 case ARM::ITasm: 10036 case ARM::t2IT: { 10037 // Set up the IT block state according to the IT instruction we just 10038 // matched. 10039 assert(!inITBlock() && "nested IT blocks?!"); 10040 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()), 10041 Inst.getOperand(1).getImm()); 10042 break; 10043 } 10044 case ARM::t2LSLrr: 10045 case ARM::t2LSRrr: 10046 case ARM::t2ASRrr: 10047 case ARM::t2SBCrr: 10048 case ARM::t2RORrr: 10049 case ARM::t2BICrr: 10050 // Assemblers should use the narrow encodings of these instructions when permissible. 10051 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10052 isARMLowRegister(Inst.getOperand(2).getReg())) && 10053 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 10054 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10055 !HasWideQualifier) { 10056 unsigned NewOpc; 10057 switch (Inst.getOpcode()) { 10058 default: llvm_unreachable("unexpected opcode"); 10059 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 10060 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 10061 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 10062 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 10063 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 10064 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 10065 } 10066 MCInst TmpInst; 10067 TmpInst.setOpcode(NewOpc); 10068 TmpInst.addOperand(Inst.getOperand(0)); 10069 TmpInst.addOperand(Inst.getOperand(5)); 10070 TmpInst.addOperand(Inst.getOperand(1)); 10071 TmpInst.addOperand(Inst.getOperand(2)); 10072 TmpInst.addOperand(Inst.getOperand(3)); 10073 TmpInst.addOperand(Inst.getOperand(4)); 10074 Inst = TmpInst; 10075 return true; 10076 } 10077 return false; 10078 10079 case ARM::t2ANDrr: 10080 case ARM::t2EORrr: 10081 case ARM::t2ADCrr: 10082 case ARM::t2ORRrr: 10083 // Assemblers should use the narrow encodings of these instructions when permissible. 10084 // These instructions are special in that they are commutable, so shorter encodings 10085 // are available more often. 10086 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 10087 isARMLowRegister(Inst.getOperand(2).getReg())) && 10088 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 10089 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 10090 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 10091 !HasWideQualifier) { 10092 unsigned NewOpc; 10093 switch (Inst.getOpcode()) { 10094 default: llvm_unreachable("unexpected opcode"); 10095 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 10096 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 10097 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 10098 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 10099 } 10100 MCInst TmpInst; 10101 TmpInst.setOpcode(NewOpc); 10102 TmpInst.addOperand(Inst.getOperand(0)); 10103 TmpInst.addOperand(Inst.getOperand(5)); 10104 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 10105 TmpInst.addOperand(Inst.getOperand(1)); 10106 TmpInst.addOperand(Inst.getOperand(2)); 10107 } else { 10108 TmpInst.addOperand(Inst.getOperand(2)); 10109 TmpInst.addOperand(Inst.getOperand(1)); 10110 } 10111 TmpInst.addOperand(Inst.getOperand(3)); 10112 TmpInst.addOperand(Inst.getOperand(4)); 10113 Inst = TmpInst; 10114 return true; 10115 } 10116 return false; 10117 case ARM::MVE_VPST: 10118 case ARM::MVE_VPTv16i8: 10119 case ARM::MVE_VPTv8i16: 10120 case ARM::MVE_VPTv4i32: 10121 case ARM::MVE_VPTv16u8: 10122 case ARM::MVE_VPTv8u16: 10123 case ARM::MVE_VPTv4u32: 10124 case ARM::MVE_VPTv16s8: 10125 case ARM::MVE_VPTv8s16: 10126 case ARM::MVE_VPTv4s32: 10127 case ARM::MVE_VPTv4f32: 10128 case ARM::MVE_VPTv8f16: 10129 case ARM::MVE_VPTv16i8r: 10130 case ARM::MVE_VPTv8i16r: 10131 case ARM::MVE_VPTv4i32r: 10132 case ARM::MVE_VPTv16u8r: 10133 case ARM::MVE_VPTv8u16r: 10134 case ARM::MVE_VPTv4u32r: 10135 case ARM::MVE_VPTv16s8r: 10136 case ARM::MVE_VPTv8s16r: 10137 case ARM::MVE_VPTv4s32r: 10138 case ARM::MVE_VPTv4f32r: 10139 case ARM::MVE_VPTv8f16r: { 10140 assert(!inVPTBlock() && "Nested VPT blocks are not allowed"); 10141 MCOperand &MO = Inst.getOperand(0); 10142 VPTState.Mask = MO.getImm(); 10143 VPTState.CurPosition = 0; 10144 break; 10145 } 10146 } 10147 return false; 10148 } 10149 10150 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 10151 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 10152 // suffix depending on whether they're in an IT block or not. 10153 unsigned Opc = Inst.getOpcode(); 10154 const MCInstrDesc &MCID = MII.get(Opc); 10155 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 10156 assert(MCID.hasOptionalDef() && 10157 "optionally flag setting instruction missing optional def operand"); 10158 assert(MCID.NumOperands == Inst.getNumOperands() && 10159 "operand count mismatch!"); 10160 // Find the optional-def operand (cc_out). 10161 unsigned OpNo; 10162 for (OpNo = 0; 10163 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 10164 ++OpNo) 10165 ; 10166 // If we're parsing Thumb1, reject it completely. 10167 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 10168 return Match_RequiresFlagSetting; 10169 // If we're parsing Thumb2, which form is legal depends on whether we're 10170 // in an IT block. 10171 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 10172 !inITBlock()) 10173 return Match_RequiresITBlock; 10174 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 10175 inITBlock()) 10176 return Match_RequiresNotITBlock; 10177 // LSL with zero immediate is not allowed in an IT block 10178 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) 10179 return Match_RequiresNotITBlock; 10180 } else if (isThumbOne()) { 10181 // Some high-register supporting Thumb1 encodings only allow both registers 10182 // to be from r0-r7 when in Thumb2. 10183 if (Opc == ARM::tADDhirr && !hasV6MOps() && 10184 isARMLowRegister(Inst.getOperand(1).getReg()) && 10185 isARMLowRegister(Inst.getOperand(2).getReg())) 10186 return Match_RequiresThumb2; 10187 // Others only require ARMv6 or later. 10188 else if (Opc == ARM::tMOVr && !hasV6Ops() && 10189 isARMLowRegister(Inst.getOperand(0).getReg()) && 10190 isARMLowRegister(Inst.getOperand(1).getReg())) 10191 return Match_RequiresV6; 10192 } 10193 10194 // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex 10195 // than the loop below can handle, so it uses the GPRnopc register class and 10196 // we do SP handling here. 10197 if (Opc == ARM::t2MOVr && !hasV8Ops()) 10198 { 10199 // SP as both source and destination is not allowed 10200 if (Inst.getOperand(0).getReg() == ARM::SP && 10201 Inst.getOperand(1).getReg() == ARM::SP) 10202 return Match_RequiresV8; 10203 // When flags-setting SP as either source or destination is not allowed 10204 if (Inst.getOperand(4).getReg() == ARM::CPSR && 10205 (Inst.getOperand(0).getReg() == ARM::SP || 10206 Inst.getOperand(1).getReg() == ARM::SP)) 10207 return Match_RequiresV8; 10208 } 10209 10210 switch (Inst.getOpcode()) { 10211 case ARM::VMRS: 10212 case ARM::VMSR: 10213 case ARM::VMRS_FPCXTS: 10214 case ARM::VMRS_FPCXTNS: 10215 case ARM::VMSR_FPCXTS: 10216 case ARM::VMSR_FPCXTNS: 10217 case ARM::VMRS_FPSCR_NZCVQC: 10218 case ARM::VMSR_FPSCR_NZCVQC: 10219 case ARM::FMSTAT: 10220 case ARM::VMRS_VPR: 10221 case ARM::VMRS_P0: 10222 case ARM::VMSR_VPR: 10223 case ARM::VMSR_P0: 10224 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of 10225 // ARMv8-A. 10226 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && 10227 (isThumb() && !hasV8Ops())) 10228 return Match_InvalidOperand; 10229 break; 10230 default: 10231 break; 10232 } 10233 10234 for (unsigned I = 0; I < MCID.NumOperands; ++I) 10235 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { 10236 // rGPRRegClass excludes PC, and also excluded SP before ARMv8 10237 const auto &Op = Inst.getOperand(I); 10238 if (!Op.isReg()) { 10239 // This can happen in awkward cases with tied operands, e.g. a 10240 // writeback load/store with a complex addressing mode in 10241 // which there's an output operand corresponding to the 10242 // updated written-back base register: the Tablegen-generated 10243 // AsmMatcher will have written a placeholder operand to that 10244 // slot in the form of an immediate 0, because it can't 10245 // generate the register part of the complex addressing-mode 10246 // operand ahead of time. 10247 continue; 10248 } 10249 10250 unsigned Reg = Op.getReg(); 10251 if ((Reg == ARM::SP) && !hasV8Ops()) 10252 return Match_RequiresV8; 10253 else if (Reg == ARM::PC) 10254 return Match_InvalidOperand; 10255 } 10256 10257 return Match_Success; 10258 } 10259 10260 namespace llvm { 10261 10262 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) { 10263 return true; // In an assembly source, no need to second-guess 10264 } 10265 10266 } // end namespace llvm 10267 10268 // Returns true if Inst is unpredictable if it is in and IT block, but is not 10269 // the last instruction in the block. 10270 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const { 10271 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 10272 10273 // All branch & call instructions terminate IT blocks with the exception of 10274 // SVC. 10275 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || 10276 MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch()) 10277 return true; 10278 10279 // Any arithmetic instruction which writes to the PC also terminates the IT 10280 // block. 10281 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) 10282 return true; 10283 10284 return false; 10285 } 10286 10287 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, 10288 SmallVectorImpl<NearMissInfo> &NearMisses, 10289 bool MatchingInlineAsm, 10290 bool &EmitInITBlock, 10291 MCStreamer &Out) { 10292 // If we can't use an implicit IT block here, just match as normal. 10293 if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb()) 10294 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); 10295 10296 // Try to match the instruction in an extension of the current IT block (if 10297 // there is one). 10298 if (inImplicitITBlock()) { 10299 extendImplicitITBlock(ITState.Cond); 10300 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == 10301 Match_Success) { 10302 // The match succeded, but we still have to check that the instruction is 10303 // valid in this implicit IT block. 10304 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 10305 if (MCID.isPredicable()) { 10306 ARMCC::CondCodes InstCond = 10307 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) 10308 .getImm(); 10309 ARMCC::CondCodes ITCond = currentITCond(); 10310 if (InstCond == ITCond) { 10311 EmitInITBlock = true; 10312 return Match_Success; 10313 } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) { 10314 invertCurrentITCondition(); 10315 EmitInITBlock = true; 10316 return Match_Success; 10317 } 10318 } 10319 } 10320 rewindImplicitITPosition(); 10321 } 10322 10323 // Finish the current IT block, and try to match outside any IT block. 10324 flushPendingInstructions(Out); 10325 unsigned PlainMatchResult = 10326 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); 10327 if (PlainMatchResult == Match_Success) { 10328 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 10329 if (MCID.isPredicable()) { 10330 ARMCC::CondCodes InstCond = 10331 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) 10332 .getImm(); 10333 // Some forms of the branch instruction have their own condition code 10334 // fields, so can be conditionally executed without an IT block. 10335 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { 10336 EmitInITBlock = false; 10337 return Match_Success; 10338 } 10339 if (InstCond == ARMCC::AL) { 10340 EmitInITBlock = false; 10341 return Match_Success; 10342 } 10343 } else { 10344 EmitInITBlock = false; 10345 return Match_Success; 10346 } 10347 } 10348 10349 // Try to match in a new IT block. The matcher doesn't check the actual 10350 // condition, so we create an IT block with a dummy condition, and fix it up 10351 // once we know the actual condition. 10352 startImplicitITBlock(); 10353 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == 10354 Match_Success) { 10355 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 10356 if (MCID.isPredicable()) { 10357 ITState.Cond = 10358 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx()) 10359 .getImm(); 10360 EmitInITBlock = true; 10361 return Match_Success; 10362 } 10363 } 10364 discardImplicitITBlock(); 10365 10366 // If none of these succeed, return the error we got when trying to match 10367 // outside any IT blocks. 10368 EmitInITBlock = false; 10369 return PlainMatchResult; 10370 } 10371 10372 static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 10373 unsigned VariantID = 0); 10374 10375 static const char *getSubtargetFeatureName(uint64_t Val); 10376 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 10377 OperandVector &Operands, 10378 MCStreamer &Out, uint64_t &ErrorInfo, 10379 bool MatchingInlineAsm) { 10380 MCInst Inst; 10381 unsigned MatchResult; 10382 bool PendConditionalInstruction = false; 10383 10384 SmallVector<NearMissInfo, 4> NearMisses; 10385 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, 10386 PendConditionalInstruction, Out); 10387 10388 switch (MatchResult) { 10389 case Match_Success: 10390 LLVM_DEBUG(dbgs() << "Parsed as: "; 10391 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode())); 10392 dbgs() << "\n"); 10393 10394 // Context sensitive operand constraints aren't handled by the matcher, 10395 // so check them here. 10396 if (validateInstruction(Inst, Operands)) { 10397 // Still progress the IT block, otherwise one wrong condition causes 10398 // nasty cascading errors. 10399 forwardITPosition(); 10400 forwardVPTPosition(); 10401 return true; 10402 } 10403 10404 { // processInstruction() updates inITBlock state, we need to save it away 10405 bool wasInITBlock = inITBlock(); 10406 10407 // Some instructions need post-processing to, for example, tweak which 10408 // encoding is selected. Loop on it while changes happen so the 10409 // individual transformations can chain off each other. E.g., 10410 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 10411 while (processInstruction(Inst, Operands, Out)) 10412 LLVM_DEBUG(dbgs() << "Changed to: "; 10413 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode())); 10414 dbgs() << "\n"); 10415 10416 // Only after the instruction is fully processed, we can validate it 10417 if (wasInITBlock && hasV8Ops() && isThumb() && 10418 !isV8EligibleForIT(&Inst)) { 10419 Warning(IDLoc, "deprecated instruction in IT block"); 10420 } 10421 } 10422 10423 // Only move forward at the very end so that everything in validate 10424 // and process gets a consistent answer about whether we're in an IT 10425 // block. 10426 forwardITPosition(); 10427 forwardVPTPosition(); 10428 10429 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 10430 // doesn't actually encode. 10431 if (Inst.getOpcode() == ARM::ITasm) 10432 return false; 10433 10434 Inst.setLoc(IDLoc); 10435 if (PendConditionalInstruction) { 10436 PendingConditionalInsts.push_back(Inst); 10437 if (isITBlockFull() || isITBlockTerminator(Inst)) 10438 flushPendingInstructions(Out); 10439 } else { 10440 Out.EmitInstruction(Inst, getSTI()); 10441 } 10442 return false; 10443 case Match_NearMisses: 10444 ReportNearMisses(NearMisses, IDLoc, Operands); 10445 return true; 10446 case Match_MnemonicFail: { 10447 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 10448 std::string Suggestion = ARMMnemonicSpellCheck( 10449 ((ARMOperand &)*Operands[0]).getToken(), FBS); 10450 return Error(IDLoc, "invalid instruction" + Suggestion, 10451 ((ARMOperand &)*Operands[0]).getLocRange()); 10452 } 10453 } 10454 10455 llvm_unreachable("Implement any new match types added!"); 10456 } 10457 10458 /// parseDirective parses the arm specific directives 10459 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 10460 const MCObjectFileInfo::Environment Format = 10461 getContext().getObjectFileInfo()->getObjectFileType(); 10462 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 10463 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF; 10464 10465 StringRef IDVal = DirectiveID.getIdentifier(); 10466 if (IDVal == ".word") 10467 parseLiteralValues(4, DirectiveID.getLoc()); 10468 else if (IDVal == ".short" || IDVal == ".hword") 10469 parseLiteralValues(2, DirectiveID.getLoc()); 10470 else if (IDVal == ".thumb") 10471 parseDirectiveThumb(DirectiveID.getLoc()); 10472 else if (IDVal == ".arm") 10473 parseDirectiveARM(DirectiveID.getLoc()); 10474 else if (IDVal == ".thumb_func") 10475 parseDirectiveThumbFunc(DirectiveID.getLoc()); 10476 else if (IDVal == ".code") 10477 parseDirectiveCode(DirectiveID.getLoc()); 10478 else if (IDVal == ".syntax") 10479 parseDirectiveSyntax(DirectiveID.getLoc()); 10480 else if (IDVal == ".unreq") 10481 parseDirectiveUnreq(DirectiveID.getLoc()); 10482 else if (IDVal == ".fnend") 10483 parseDirectiveFnEnd(DirectiveID.getLoc()); 10484 else if (IDVal == ".cantunwind") 10485 parseDirectiveCantUnwind(DirectiveID.getLoc()); 10486 else if (IDVal == ".personality") 10487 parseDirectivePersonality(DirectiveID.getLoc()); 10488 else if (IDVal == ".handlerdata") 10489 parseDirectiveHandlerData(DirectiveID.getLoc()); 10490 else if (IDVal == ".setfp") 10491 parseDirectiveSetFP(DirectiveID.getLoc()); 10492 else if (IDVal == ".pad") 10493 parseDirectivePad(DirectiveID.getLoc()); 10494 else if (IDVal == ".save") 10495 parseDirectiveRegSave(DirectiveID.getLoc(), false); 10496 else if (IDVal == ".vsave") 10497 parseDirectiveRegSave(DirectiveID.getLoc(), true); 10498 else if (IDVal == ".ltorg" || IDVal == ".pool") 10499 parseDirectiveLtorg(DirectiveID.getLoc()); 10500 else if (IDVal == ".even") 10501 parseDirectiveEven(DirectiveID.getLoc()); 10502 else if (IDVal == ".personalityindex") 10503 parseDirectivePersonalityIndex(DirectiveID.getLoc()); 10504 else if (IDVal == ".unwind_raw") 10505 parseDirectiveUnwindRaw(DirectiveID.getLoc()); 10506 else if (IDVal == ".movsp") 10507 parseDirectiveMovSP(DirectiveID.getLoc()); 10508 else if (IDVal == ".arch_extension") 10509 parseDirectiveArchExtension(DirectiveID.getLoc()); 10510 else if (IDVal == ".align") 10511 return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure. 10512 else if (IDVal == ".thumb_set") 10513 parseDirectiveThumbSet(DirectiveID.getLoc()); 10514 else if (IDVal == ".inst") 10515 parseDirectiveInst(DirectiveID.getLoc()); 10516 else if (IDVal == ".inst.n") 10517 parseDirectiveInst(DirectiveID.getLoc(), 'n'); 10518 else if (IDVal == ".inst.w") 10519 parseDirectiveInst(DirectiveID.getLoc(), 'w'); 10520 else if (!IsMachO && !IsCOFF) { 10521 if (IDVal == ".arch") 10522 parseDirectiveArch(DirectiveID.getLoc()); 10523 else if (IDVal == ".cpu") 10524 parseDirectiveCPU(DirectiveID.getLoc()); 10525 else if (IDVal == ".eabi_attribute") 10526 parseDirectiveEabiAttr(DirectiveID.getLoc()); 10527 else if (IDVal == ".fpu") 10528 parseDirectiveFPU(DirectiveID.getLoc()); 10529 else if (IDVal == ".fnstart") 10530 parseDirectiveFnStart(DirectiveID.getLoc()); 10531 else if (IDVal == ".object_arch") 10532 parseDirectiveObjectArch(DirectiveID.getLoc()); 10533 else if (IDVal == ".tlsdescseq") 10534 parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 10535 else 10536 return true; 10537 } else 10538 return true; 10539 return false; 10540 } 10541 10542 /// parseLiteralValues 10543 /// ::= .hword expression [, expression]* 10544 /// ::= .short expression [, expression]* 10545 /// ::= .word expression [, expression]* 10546 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 10547 auto parseOne = [&]() -> bool { 10548 const MCExpr *Value; 10549 if (getParser().parseExpression(Value)) 10550 return true; 10551 getParser().getStreamer().EmitValue(Value, Size, L); 10552 return false; 10553 }; 10554 return (parseMany(parseOne)); 10555 } 10556 10557 /// parseDirectiveThumb 10558 /// ::= .thumb 10559 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 10560 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") || 10561 check(!hasThumb(), L, "target does not support Thumb mode")) 10562 return true; 10563 10564 if (!isThumb()) 10565 SwitchMode(); 10566 10567 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 10568 return false; 10569 } 10570 10571 /// parseDirectiveARM 10572 /// ::= .arm 10573 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 10574 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") || 10575 check(!hasARM(), L, "target does not support ARM mode")) 10576 return true; 10577 10578 if (isThumb()) 10579 SwitchMode(); 10580 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 10581 return false; 10582 } 10583 10584 void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) { 10585 // We need to flush the current implicit IT block on a label, because it is 10586 // not legal to branch into an IT block. 10587 flushPendingInstructions(getStreamer()); 10588 } 10589 10590 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 10591 if (NextSymbolIsThumb) { 10592 getParser().getStreamer().EmitThumbFunc(Symbol); 10593 NextSymbolIsThumb = false; 10594 } 10595 } 10596 10597 /// parseDirectiveThumbFunc 10598 /// ::= .thumbfunc symbol_name 10599 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 10600 MCAsmParser &Parser = getParser(); 10601 const auto Format = getContext().getObjectFileInfo()->getObjectFileType(); 10602 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 10603 10604 // Darwin asm has (optionally) function name after .thumb_func direction 10605 // ELF doesn't 10606 10607 if (IsMachO) { 10608 if (Parser.getTok().is(AsmToken::Identifier) || 10609 Parser.getTok().is(AsmToken::String)) { 10610 MCSymbol *Func = getParser().getContext().getOrCreateSymbol( 10611 Parser.getTok().getIdentifier()); 10612 getParser().getStreamer().EmitThumbFunc(Func); 10613 Parser.Lex(); 10614 if (parseToken(AsmToken::EndOfStatement, 10615 "unexpected token in '.thumb_func' directive")) 10616 return true; 10617 return false; 10618 } 10619 } 10620 10621 if (parseToken(AsmToken::EndOfStatement, 10622 "unexpected token in '.thumb_func' directive")) 10623 return true; 10624 10625 NextSymbolIsThumb = true; 10626 return false; 10627 } 10628 10629 /// parseDirectiveSyntax 10630 /// ::= .syntax unified | divided 10631 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 10632 MCAsmParser &Parser = getParser(); 10633 const AsmToken &Tok = Parser.getTok(); 10634 if (Tok.isNot(AsmToken::Identifier)) { 10635 Error(L, "unexpected token in .syntax directive"); 10636 return false; 10637 } 10638 10639 StringRef Mode = Tok.getString(); 10640 Parser.Lex(); 10641 if (check(Mode == "divided" || Mode == "DIVIDED", L, 10642 "'.syntax divided' arm assembly not supported") || 10643 check(Mode != "unified" && Mode != "UNIFIED", L, 10644 "unrecognized syntax mode in .syntax directive") || 10645 parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) 10646 return true; 10647 10648 // TODO tell the MC streamer the mode 10649 // getParser().getStreamer().Emit???(); 10650 return false; 10651 } 10652 10653 /// parseDirectiveCode 10654 /// ::= .code 16 | 32 10655 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 10656 MCAsmParser &Parser = getParser(); 10657 const AsmToken &Tok = Parser.getTok(); 10658 if (Tok.isNot(AsmToken::Integer)) 10659 return Error(L, "unexpected token in .code directive"); 10660 int64_t Val = Parser.getTok().getIntVal(); 10661 if (Val != 16 && Val != 32) { 10662 Error(L, "invalid operand to .code directive"); 10663 return false; 10664 } 10665 Parser.Lex(); 10666 10667 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) 10668 return true; 10669 10670 if (Val == 16) { 10671 if (!hasThumb()) 10672 return Error(L, "target does not support Thumb mode"); 10673 10674 if (!isThumb()) 10675 SwitchMode(); 10676 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 10677 } else { 10678 if (!hasARM()) 10679 return Error(L, "target does not support ARM mode"); 10680 10681 if (isThumb()) 10682 SwitchMode(); 10683 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 10684 } 10685 10686 return false; 10687 } 10688 10689 /// parseDirectiveReq 10690 /// ::= name .req registername 10691 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 10692 MCAsmParser &Parser = getParser(); 10693 Parser.Lex(); // Eat the '.req' token. 10694 unsigned Reg; 10695 SMLoc SRegLoc, ERegLoc; 10696 if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc, 10697 "register name expected") || 10698 parseToken(AsmToken::EndOfStatement, 10699 "unexpected input in .req directive.")) 10700 return true; 10701 10702 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) 10703 return Error(SRegLoc, 10704 "redefinition of '" + Name + "' does not match original."); 10705 10706 return false; 10707 } 10708 10709 /// parseDirectiveUneq 10710 /// ::= .unreq registername 10711 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 10712 MCAsmParser &Parser = getParser(); 10713 if (Parser.getTok().isNot(AsmToken::Identifier)) 10714 return Error(L, "unexpected input in .unreq directive."); 10715 RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); 10716 Parser.Lex(); // Eat the identifier. 10717 if (parseToken(AsmToken::EndOfStatement, 10718 "unexpected input in '.unreq' directive")) 10719 return true; 10720 return false; 10721 } 10722 10723 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was 10724 // before, if supported by the new target, or emit mapping symbols for the mode 10725 // switch. 10726 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) { 10727 if (WasThumb != isThumb()) { 10728 if (WasThumb && hasThumb()) { 10729 // Stay in Thumb mode 10730 SwitchMode(); 10731 } else if (!WasThumb && hasARM()) { 10732 // Stay in ARM mode 10733 SwitchMode(); 10734 } else { 10735 // Mode switch forced, because the new arch doesn't support the old mode. 10736 getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16 10737 : MCAF_Code32); 10738 // Warn about the implcit mode switch. GAS does not switch modes here, 10739 // but instead stays in the old mode, reporting an error on any following 10740 // instructions as the mode does not exist on the target. 10741 Warning(Loc, Twine("new target does not support ") + 10742 (WasThumb ? "thumb" : "arm") + " mode, switching to " + 10743 (!WasThumb ? "thumb" : "arm") + " mode"); 10744 } 10745 } 10746 } 10747 10748 /// parseDirectiveArch 10749 /// ::= .arch token 10750 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 10751 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 10752 ARM::ArchKind ID = ARM::parseArch(Arch); 10753 10754 if (ID == ARM::ArchKind::INVALID) 10755 return Error(L, "Unknown arch name"); 10756 10757 bool WasThumb = isThumb(); 10758 Triple T; 10759 MCSubtargetInfo &STI = copySTI(); 10760 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str()); 10761 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 10762 FixModeAfterArchChange(WasThumb, L); 10763 10764 getTargetStreamer().emitArch(ID); 10765 return false; 10766 } 10767 10768 /// parseDirectiveEabiAttr 10769 /// ::= .eabi_attribute int, int [, "str"] 10770 /// ::= .eabi_attribute Tag_name, int [, "str"] 10771 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 10772 MCAsmParser &Parser = getParser(); 10773 int64_t Tag; 10774 SMLoc TagLoc; 10775 TagLoc = Parser.getTok().getLoc(); 10776 if (Parser.getTok().is(AsmToken::Identifier)) { 10777 StringRef Name = Parser.getTok().getIdentifier(); 10778 Tag = ARMBuildAttrs::AttrTypeFromString(Name); 10779 if (Tag == -1) { 10780 Error(TagLoc, "attribute name not recognised: " + Name); 10781 return false; 10782 } 10783 Parser.Lex(); 10784 } else { 10785 const MCExpr *AttrExpr; 10786 10787 TagLoc = Parser.getTok().getLoc(); 10788 if (Parser.parseExpression(AttrExpr)) 10789 return true; 10790 10791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 10792 if (check(!CE, TagLoc, "expected numeric constant")) 10793 return true; 10794 10795 Tag = CE->getValue(); 10796 } 10797 10798 if (Parser.parseToken(AsmToken::Comma, "comma expected")) 10799 return true; 10800 10801 StringRef StringValue = ""; 10802 bool IsStringValue = false; 10803 10804 int64_t IntegerValue = 0; 10805 bool IsIntegerValue = false; 10806 10807 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 10808 IsStringValue = true; 10809 else if (Tag == ARMBuildAttrs::compatibility) { 10810 IsStringValue = true; 10811 IsIntegerValue = true; 10812 } else if (Tag < 32 || Tag % 2 == 0) 10813 IsIntegerValue = true; 10814 else if (Tag % 2 == 1) 10815 IsStringValue = true; 10816 else 10817 llvm_unreachable("invalid tag type"); 10818 10819 if (IsIntegerValue) { 10820 const MCExpr *ValueExpr; 10821 SMLoc ValueExprLoc = Parser.getTok().getLoc(); 10822 if (Parser.parseExpression(ValueExpr)) 10823 return true; 10824 10825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 10826 if (!CE) 10827 return Error(ValueExprLoc, "expected numeric constant"); 10828 IntegerValue = CE->getValue(); 10829 } 10830 10831 if (Tag == ARMBuildAttrs::compatibility) { 10832 if (Parser.parseToken(AsmToken::Comma, "comma expected")) 10833 return true; 10834 } 10835 10836 if (IsStringValue) { 10837 if (Parser.getTok().isNot(AsmToken::String)) 10838 return Error(Parser.getTok().getLoc(), "bad string constant"); 10839 10840 StringValue = Parser.getTok().getStringContents(); 10841 Parser.Lex(); 10842 } 10843 10844 if (Parser.parseToken(AsmToken::EndOfStatement, 10845 "unexpected token in '.eabi_attribute' directive")) 10846 return true; 10847 10848 if (IsIntegerValue && IsStringValue) { 10849 assert(Tag == ARMBuildAttrs::compatibility); 10850 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 10851 } else if (IsIntegerValue) 10852 getTargetStreamer().emitAttribute(Tag, IntegerValue); 10853 else if (IsStringValue) 10854 getTargetStreamer().emitTextAttribute(Tag, StringValue); 10855 return false; 10856 } 10857 10858 /// parseDirectiveCPU 10859 /// ::= .cpu str 10860 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 10861 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 10862 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 10863 10864 // FIXME: This is using table-gen data, but should be moved to 10865 // ARMTargetParser once that is table-gen'd. 10866 if (!getSTI().isCPUStringValid(CPU)) 10867 return Error(L, "Unknown CPU name"); 10868 10869 bool WasThumb = isThumb(); 10870 MCSubtargetInfo &STI = copySTI(); 10871 STI.setDefaultFeatures(CPU, ""); 10872 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 10873 FixModeAfterArchChange(WasThumb, L); 10874 10875 return false; 10876 } 10877 10878 /// parseDirectiveFPU 10879 /// ::= .fpu str 10880 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 10881 SMLoc FPUNameLoc = getTok().getLoc(); 10882 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 10883 10884 unsigned ID = ARM::parseFPU(FPU); 10885 std::vector<StringRef> Features; 10886 if (!ARM::getFPUFeatures(ID, Features)) 10887 return Error(FPUNameLoc, "Unknown FPU name"); 10888 10889 MCSubtargetInfo &STI = copySTI(); 10890 for (auto Feature : Features) 10891 STI.ApplyFeatureFlag(Feature); 10892 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 10893 10894 getTargetStreamer().emitFPU(ID); 10895 return false; 10896 } 10897 10898 /// parseDirectiveFnStart 10899 /// ::= .fnstart 10900 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 10901 if (parseToken(AsmToken::EndOfStatement, 10902 "unexpected token in '.fnstart' directive")) 10903 return true; 10904 10905 if (UC.hasFnStart()) { 10906 Error(L, ".fnstart starts before the end of previous one"); 10907 UC.emitFnStartLocNotes(); 10908 return true; 10909 } 10910 10911 // Reset the unwind directives parser state 10912 UC.reset(); 10913 10914 getTargetStreamer().emitFnStart(); 10915 10916 UC.recordFnStart(L); 10917 return false; 10918 } 10919 10920 /// parseDirectiveFnEnd 10921 /// ::= .fnend 10922 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 10923 if (parseToken(AsmToken::EndOfStatement, 10924 "unexpected token in '.fnend' directive")) 10925 return true; 10926 // Check the ordering of unwind directives 10927 if (!UC.hasFnStart()) 10928 return Error(L, ".fnstart must precede .fnend directive"); 10929 10930 // Reset the unwind directives parser state 10931 getTargetStreamer().emitFnEnd(); 10932 10933 UC.reset(); 10934 return false; 10935 } 10936 10937 /// parseDirectiveCantUnwind 10938 /// ::= .cantunwind 10939 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 10940 if (parseToken(AsmToken::EndOfStatement, 10941 "unexpected token in '.cantunwind' directive")) 10942 return true; 10943 10944 UC.recordCantUnwind(L); 10945 // Check the ordering of unwind directives 10946 if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive")) 10947 return true; 10948 10949 if (UC.hasHandlerData()) { 10950 Error(L, ".cantunwind can't be used with .handlerdata directive"); 10951 UC.emitHandlerDataLocNotes(); 10952 return true; 10953 } 10954 if (UC.hasPersonality()) { 10955 Error(L, ".cantunwind can't be used with .personality directive"); 10956 UC.emitPersonalityLocNotes(); 10957 return true; 10958 } 10959 10960 getTargetStreamer().emitCantUnwind(); 10961 return false; 10962 } 10963 10964 /// parseDirectivePersonality 10965 /// ::= .personality name 10966 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 10967 MCAsmParser &Parser = getParser(); 10968 bool HasExistingPersonality = UC.hasPersonality(); 10969 10970 // Parse the name of the personality routine 10971 if (Parser.getTok().isNot(AsmToken::Identifier)) 10972 return Error(L, "unexpected input in .personality directive."); 10973 StringRef Name(Parser.getTok().getIdentifier()); 10974 Parser.Lex(); 10975 10976 if (parseToken(AsmToken::EndOfStatement, 10977 "unexpected token in '.personality' directive")) 10978 return true; 10979 10980 UC.recordPersonality(L); 10981 10982 // Check the ordering of unwind directives 10983 if (!UC.hasFnStart()) 10984 return Error(L, ".fnstart must precede .personality directive"); 10985 if (UC.cantUnwind()) { 10986 Error(L, ".personality can't be used with .cantunwind directive"); 10987 UC.emitCantUnwindLocNotes(); 10988 return true; 10989 } 10990 if (UC.hasHandlerData()) { 10991 Error(L, ".personality must precede .handlerdata directive"); 10992 UC.emitHandlerDataLocNotes(); 10993 return true; 10994 } 10995 if (HasExistingPersonality) { 10996 Error(L, "multiple personality directives"); 10997 UC.emitPersonalityLocNotes(); 10998 return true; 10999 } 11000 11001 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name); 11002 getTargetStreamer().emitPersonality(PR); 11003 return false; 11004 } 11005 11006 /// parseDirectiveHandlerData 11007 /// ::= .handlerdata 11008 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 11009 if (parseToken(AsmToken::EndOfStatement, 11010 "unexpected token in '.handlerdata' directive")) 11011 return true; 11012 11013 UC.recordHandlerData(L); 11014 // Check the ordering of unwind directives 11015 if (!UC.hasFnStart()) 11016 return Error(L, ".fnstart must precede .personality directive"); 11017 if (UC.cantUnwind()) { 11018 Error(L, ".handlerdata can't be used with .cantunwind directive"); 11019 UC.emitCantUnwindLocNotes(); 11020 return true; 11021 } 11022 11023 getTargetStreamer().emitHandlerData(); 11024 return false; 11025 } 11026 11027 /// parseDirectiveSetFP 11028 /// ::= .setfp fpreg, spreg [, offset] 11029 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 11030 MCAsmParser &Parser = getParser(); 11031 // Check the ordering of unwind directives 11032 if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") || 11033 check(UC.hasHandlerData(), L, 11034 ".setfp must precede .handlerdata directive")) 11035 return true; 11036 11037 // Parse fpreg 11038 SMLoc FPRegLoc = Parser.getTok().getLoc(); 11039 int FPReg = tryParseRegister(); 11040 11041 if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") || 11042 Parser.parseToken(AsmToken::Comma, "comma expected")) 11043 return true; 11044 11045 // Parse spreg 11046 SMLoc SPRegLoc = Parser.getTok().getLoc(); 11047 int SPReg = tryParseRegister(); 11048 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") || 11049 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, 11050 "register should be either $sp or the latest fp register")) 11051 return true; 11052 11053 // Update the frame pointer register 11054 UC.saveFPReg(FPReg); 11055 11056 // Parse offset 11057 int64_t Offset = 0; 11058 if (Parser.parseOptionalToken(AsmToken::Comma)) { 11059 if (Parser.getTok().isNot(AsmToken::Hash) && 11060 Parser.getTok().isNot(AsmToken::Dollar)) 11061 return Error(Parser.getTok().getLoc(), "'#' expected"); 11062 Parser.Lex(); // skip hash token. 11063 11064 const MCExpr *OffsetExpr; 11065 SMLoc ExLoc = Parser.getTok().getLoc(); 11066 SMLoc EndLoc; 11067 if (getParser().parseExpression(OffsetExpr, EndLoc)) 11068 return Error(ExLoc, "malformed setfp offset"); 11069 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 11070 if (check(!CE, ExLoc, "setfp offset must be an immediate")) 11071 return true; 11072 Offset = CE->getValue(); 11073 } 11074 11075 if (Parser.parseToken(AsmToken::EndOfStatement)) 11076 return true; 11077 11078 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 11079 static_cast<unsigned>(SPReg), Offset); 11080 return false; 11081 } 11082 11083 /// parseDirective 11084 /// ::= .pad offset 11085 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 11086 MCAsmParser &Parser = getParser(); 11087 // Check the ordering of unwind directives 11088 if (!UC.hasFnStart()) 11089 return Error(L, ".fnstart must precede .pad directive"); 11090 if (UC.hasHandlerData()) 11091 return Error(L, ".pad must precede .handlerdata directive"); 11092 11093 // Parse the offset 11094 if (Parser.getTok().isNot(AsmToken::Hash) && 11095 Parser.getTok().isNot(AsmToken::Dollar)) 11096 return Error(Parser.getTok().getLoc(), "'#' expected"); 11097 Parser.Lex(); // skip hash token. 11098 11099 const MCExpr *OffsetExpr; 11100 SMLoc ExLoc = Parser.getTok().getLoc(); 11101 SMLoc EndLoc; 11102 if (getParser().parseExpression(OffsetExpr, EndLoc)) 11103 return Error(ExLoc, "malformed pad offset"); 11104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 11105 if (!CE) 11106 return Error(ExLoc, "pad offset must be an immediate"); 11107 11108 if (parseToken(AsmToken::EndOfStatement, 11109 "unexpected token in '.pad' directive")) 11110 return true; 11111 11112 getTargetStreamer().emitPad(CE->getValue()); 11113 return false; 11114 } 11115 11116 /// parseDirectiveRegSave 11117 /// ::= .save { registers } 11118 /// ::= .vsave { registers } 11119 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 11120 // Check the ordering of unwind directives 11121 if (!UC.hasFnStart()) 11122 return Error(L, ".fnstart must precede .save or .vsave directives"); 11123 if (UC.hasHandlerData()) 11124 return Error(L, ".save or .vsave must precede .handlerdata directive"); 11125 11126 // RAII object to make sure parsed operands are deleted. 11127 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; 11128 11129 // Parse the register list 11130 if (parseRegisterList(Operands) || 11131 parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) 11132 return true; 11133 ARMOperand &Op = (ARMOperand &)*Operands[0]; 11134 if (!IsVector && !Op.isRegList()) 11135 return Error(L, ".save expects GPR registers"); 11136 if (IsVector && !Op.isDPRRegList()) 11137 return Error(L, ".vsave expects DPR registers"); 11138 11139 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); 11140 return false; 11141 } 11142 11143 /// parseDirectiveInst 11144 /// ::= .inst opcode [, ...] 11145 /// ::= .inst.n opcode [, ...] 11146 /// ::= .inst.w opcode [, ...] 11147 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 11148 int Width = 4; 11149 11150 if (isThumb()) { 11151 switch (Suffix) { 11152 case 'n': 11153 Width = 2; 11154 break; 11155 case 'w': 11156 break; 11157 default: 11158 Width = 0; 11159 break; 11160 } 11161 } else { 11162 if (Suffix) 11163 return Error(Loc, "width suffixes are invalid in ARM mode"); 11164 } 11165 11166 auto parseOne = [&]() -> bool { 11167 const MCExpr *Expr; 11168 if (getParser().parseExpression(Expr)) 11169 return true; 11170 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 11171 if (!Value) { 11172 return Error(Loc, "expected constant expression"); 11173 } 11174 11175 char CurSuffix = Suffix; 11176 switch (Width) { 11177 case 2: 11178 if (Value->getValue() > 0xffff) 11179 return Error(Loc, "inst.n operand is too big, use inst.w instead"); 11180 break; 11181 case 4: 11182 if (Value->getValue() > 0xffffffff) 11183 return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") + 11184 " operand is too big"); 11185 break; 11186 case 0: 11187 // Thumb mode, no width indicated. Guess from the opcode, if possible. 11188 if (Value->getValue() < 0xe800) 11189 CurSuffix = 'n'; 11190 else if (Value->getValue() >= 0xe8000000) 11191 CurSuffix = 'w'; 11192 else 11193 return Error(Loc, "cannot determine Thumb instruction size, " 11194 "use inst.n/inst.w instead"); 11195 break; 11196 default: 11197 llvm_unreachable("only supported widths are 2 and 4"); 11198 } 11199 11200 getTargetStreamer().emitInst(Value->getValue(), CurSuffix); 11201 return false; 11202 }; 11203 11204 if (parseOptionalToken(AsmToken::EndOfStatement)) 11205 return Error(Loc, "expected expression following directive"); 11206 if (parseMany(parseOne)) 11207 return true; 11208 return false; 11209 } 11210 11211 /// parseDirectiveLtorg 11212 /// ::= .ltorg | .pool 11213 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 11214 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) 11215 return true; 11216 getTargetStreamer().emitCurrentConstantPool(); 11217 return false; 11218 } 11219 11220 bool ARMAsmParser::parseDirectiveEven(SMLoc L) { 11221 const MCSection *Section = getStreamer().getCurrentSectionOnly(); 11222 11223 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) 11224 return true; 11225 11226 if (!Section) { 11227 getStreamer().InitSections(false); 11228 Section = getStreamer().getCurrentSectionOnly(); 11229 } 11230 11231 assert(Section && "must have section to emit alignment"); 11232 if (Section->UseCodeAlign()) 11233 getStreamer().EmitCodeAlignment(2); 11234 else 11235 getStreamer().EmitValueToAlignment(2); 11236 11237 return false; 11238 } 11239 11240 /// parseDirectivePersonalityIndex 11241 /// ::= .personalityindex index 11242 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 11243 MCAsmParser &Parser = getParser(); 11244 bool HasExistingPersonality = UC.hasPersonality(); 11245 11246 const MCExpr *IndexExpression; 11247 SMLoc IndexLoc = Parser.getTok().getLoc(); 11248 if (Parser.parseExpression(IndexExpression) || 11249 parseToken(AsmToken::EndOfStatement, 11250 "unexpected token in '.personalityindex' directive")) { 11251 return true; 11252 } 11253 11254 UC.recordPersonalityIndex(L); 11255 11256 if (!UC.hasFnStart()) { 11257 return Error(L, ".fnstart must precede .personalityindex directive"); 11258 } 11259 if (UC.cantUnwind()) { 11260 Error(L, ".personalityindex cannot be used with .cantunwind"); 11261 UC.emitCantUnwindLocNotes(); 11262 return true; 11263 } 11264 if (UC.hasHandlerData()) { 11265 Error(L, ".personalityindex must precede .handlerdata directive"); 11266 UC.emitHandlerDataLocNotes(); 11267 return true; 11268 } 11269 if (HasExistingPersonality) { 11270 Error(L, "multiple personality directives"); 11271 UC.emitPersonalityLocNotes(); 11272 return true; 11273 } 11274 11275 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 11276 if (!CE) 11277 return Error(IndexLoc, "index must be a constant number"); 11278 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) 11279 return Error(IndexLoc, 11280 "personality routine index should be in range [0-3]"); 11281 11282 getTargetStreamer().emitPersonalityIndex(CE->getValue()); 11283 return false; 11284 } 11285 11286 /// parseDirectiveUnwindRaw 11287 /// ::= .unwind_raw offset, opcode [, opcode...] 11288 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 11289 MCAsmParser &Parser = getParser(); 11290 int64_t StackOffset; 11291 const MCExpr *OffsetExpr; 11292 SMLoc OffsetLoc = getLexer().getLoc(); 11293 11294 if (!UC.hasFnStart()) 11295 return Error(L, ".fnstart must precede .unwind_raw directives"); 11296 if (getParser().parseExpression(OffsetExpr)) 11297 return Error(OffsetLoc, "expected expression"); 11298 11299 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 11300 if (!CE) 11301 return Error(OffsetLoc, "offset must be a constant"); 11302 11303 StackOffset = CE->getValue(); 11304 11305 if (Parser.parseToken(AsmToken::Comma, "expected comma")) 11306 return true; 11307 11308 SmallVector<uint8_t, 16> Opcodes; 11309 11310 auto parseOne = [&]() -> bool { 11311 const MCExpr *OE; 11312 SMLoc OpcodeLoc = getLexer().getLoc(); 11313 if (check(getLexer().is(AsmToken::EndOfStatement) || 11314 Parser.parseExpression(OE), 11315 OpcodeLoc, "expected opcode expression")) 11316 return true; 11317 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 11318 if (!OC) 11319 return Error(OpcodeLoc, "opcode value must be a constant"); 11320 const int64_t Opcode = OC->getValue(); 11321 if (Opcode & ~0xff) 11322 return Error(OpcodeLoc, "invalid opcode"); 11323 Opcodes.push_back(uint8_t(Opcode)); 11324 return false; 11325 }; 11326 11327 // Must have at least 1 element 11328 SMLoc OpcodeLoc = getLexer().getLoc(); 11329 if (parseOptionalToken(AsmToken::EndOfStatement)) 11330 return Error(OpcodeLoc, "expected opcode expression"); 11331 if (parseMany(parseOne)) 11332 return true; 11333 11334 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 11335 return false; 11336 } 11337 11338 /// parseDirectiveTLSDescSeq 11339 /// ::= .tlsdescseq tls-variable 11340 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 11341 MCAsmParser &Parser = getParser(); 11342 11343 if (getLexer().isNot(AsmToken::Identifier)) 11344 return TokError("expected variable after '.tlsdescseq' directive"); 11345 11346 const MCSymbolRefExpr *SRE = 11347 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(), 11348 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 11349 Lex(); 11350 11351 if (parseToken(AsmToken::EndOfStatement, 11352 "unexpected token in '.tlsdescseq' directive")) 11353 return true; 11354 11355 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 11356 return false; 11357 } 11358 11359 /// parseDirectiveMovSP 11360 /// ::= .movsp reg [, #offset] 11361 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 11362 MCAsmParser &Parser = getParser(); 11363 if (!UC.hasFnStart()) 11364 return Error(L, ".fnstart must precede .movsp directives"); 11365 if (UC.getFPReg() != ARM::SP) 11366 return Error(L, "unexpected .movsp directive"); 11367 11368 SMLoc SPRegLoc = Parser.getTok().getLoc(); 11369 int SPReg = tryParseRegister(); 11370 if (SPReg == -1) 11371 return Error(SPRegLoc, "register expected"); 11372 if (SPReg == ARM::SP || SPReg == ARM::PC) 11373 return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 11374 11375 int64_t Offset = 0; 11376 if (Parser.parseOptionalToken(AsmToken::Comma)) { 11377 if (Parser.parseToken(AsmToken::Hash, "expected #constant")) 11378 return true; 11379 11380 const MCExpr *OffsetExpr; 11381 SMLoc OffsetLoc = Parser.getTok().getLoc(); 11382 11383 if (Parser.parseExpression(OffsetExpr)) 11384 return Error(OffsetLoc, "malformed offset expression"); 11385 11386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 11387 if (!CE) 11388 return Error(OffsetLoc, "offset must be an immediate constant"); 11389 11390 Offset = CE->getValue(); 11391 } 11392 11393 if (parseToken(AsmToken::EndOfStatement, 11394 "unexpected token in '.movsp' directive")) 11395 return true; 11396 11397 getTargetStreamer().emitMovSP(SPReg, Offset); 11398 UC.saveFPReg(SPReg); 11399 11400 return false; 11401 } 11402 11403 /// parseDirectiveObjectArch 11404 /// ::= .object_arch name 11405 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 11406 MCAsmParser &Parser = getParser(); 11407 if (getLexer().isNot(AsmToken::Identifier)) 11408 return Error(getLexer().getLoc(), "unexpected token"); 11409 11410 StringRef Arch = Parser.getTok().getString(); 11411 SMLoc ArchLoc = Parser.getTok().getLoc(); 11412 Lex(); 11413 11414 ARM::ArchKind ID = ARM::parseArch(Arch); 11415 11416 if (ID == ARM::ArchKind::INVALID) 11417 return Error(ArchLoc, "unknown architecture '" + Arch + "'"); 11418 if (parseToken(AsmToken::EndOfStatement)) 11419 return true; 11420 11421 getTargetStreamer().emitObjectArch(ID); 11422 return false; 11423 } 11424 11425 /// parseDirectiveAlign 11426 /// ::= .align 11427 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 11428 // NOTE: if this is not the end of the statement, fall back to the target 11429 // agnostic handling for this directive which will correctly handle this. 11430 if (parseOptionalToken(AsmToken::EndOfStatement)) { 11431 // '.align' is target specifically handled to mean 2**2 byte alignment. 11432 const MCSection *Section = getStreamer().getCurrentSectionOnly(); 11433 assert(Section && "must have section to emit alignment"); 11434 if (Section->UseCodeAlign()) 11435 getStreamer().EmitCodeAlignment(4, 0); 11436 else 11437 getStreamer().EmitValueToAlignment(4, 0, 1, 0); 11438 return false; 11439 } 11440 return true; 11441 } 11442 11443 /// parseDirectiveThumbSet 11444 /// ::= .thumb_set name, value 11445 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { 11446 MCAsmParser &Parser = getParser(); 11447 11448 StringRef Name; 11449 if (check(Parser.parseIdentifier(Name), 11450 "expected identifier after '.thumb_set'") || 11451 parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'")) 11452 return true; 11453 11454 MCSymbol *Sym; 11455 const MCExpr *Value; 11456 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, 11457 Parser, Sym, Value)) 11458 return true; 11459 11460 getTargetStreamer().emitThumbSet(Sym, Value); 11461 return false; 11462 } 11463 11464 /// Force static initialization. 11465 extern "C" void LLVMInitializeARMAsmParser() { 11466 RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget()); 11467 RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget()); 11468 RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget()); 11469 RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget()); 11470 } 11471 11472 #define GET_REGISTER_MATCHER 11473 #define GET_SUBTARGET_FEATURE_NAME 11474 #define GET_MATCHER_IMPLEMENTATION 11475 #define GET_MNEMONIC_SPELL_CHECKER 11476 #include "ARMGenAsmMatcher.inc" 11477 11478 // Some diagnostics need to vary with subtarget features, so they are handled 11479 // here. For example, the DPR class has either 16 or 32 registers, depending 11480 // on the FPU available. 11481 const char * 11482 ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) { 11483 switch (MatchError) { 11484 // rGPR contains sp starting with ARMv8. 11485 case Match_rGPR: 11486 return hasV8Ops() ? "operand must be a register in range [r0, r14]" 11487 : "operand must be a register in range [r0, r12] or r14"; 11488 // DPR contains 16 registers for some FPUs, and 32 for others. 11489 case Match_DPR: 11490 return hasD32() ? "operand must be a register in range [d0, d31]" 11491 : "operand must be a register in range [d0, d15]"; 11492 case Match_DPR_RegList: 11493 return hasD32() ? "operand must be a list of registers in range [d0, d31]" 11494 : "operand must be a list of registers in range [d0, d15]"; 11495 11496 // For all other diags, use the static string from tablegen. 11497 default: 11498 return getMatchKindDiag(MatchError); 11499 } 11500 } 11501 11502 // Process the list of near-misses, throwing away ones we don't want to report 11503 // to the user, and converting the rest to a source location and string that 11504 // should be reported. 11505 void 11506 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, 11507 SmallVectorImpl<NearMissMessage> &NearMissesOut, 11508 SMLoc IDLoc, OperandVector &Operands) { 11509 // TODO: If operand didn't match, sub in a dummy one and run target 11510 // predicate, so that we can avoid reporting near-misses that are invalid? 11511 // TODO: Many operand types dont have SuperClasses set, so we report 11512 // redundant ones. 11513 // TODO: Some operands are superclasses of registers (e.g. 11514 // MCK_RegShiftedImm), we don't have any way to represent that currently. 11515 // TODO: This is not all ARM-specific, can some of it be factored out? 11516 11517 // Record some information about near-misses that we have already seen, so 11518 // that we can avoid reporting redundant ones. For example, if there are 11519 // variants of an instruction that take 8- and 16-bit immediates, we want 11520 // to only report the widest one. 11521 std::multimap<unsigned, unsigned> OperandMissesSeen; 11522 SmallSet<FeatureBitset, 4> FeatureMissesSeen; 11523 bool ReportedTooFewOperands = false; 11524 11525 // Process the near-misses in reverse order, so that we see more general ones 11526 // first, and so can avoid emitting more specific ones. 11527 for (NearMissInfo &I : reverse(NearMissesIn)) { 11528 switch (I.getKind()) { 11529 case NearMissInfo::NearMissOperand: { 11530 SMLoc OperandLoc = 11531 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); 11532 const char *OperandDiag = 11533 getCustomOperandDiag((ARMMatchResultTy)I.getOperandError()); 11534 11535 // If we have already emitted a message for a superclass, don't also report 11536 // the sub-class. We consider all operand classes that we don't have a 11537 // specialised diagnostic for to be equal for the propose of this check, 11538 // so that we don't report the generic error multiple times on the same 11539 // operand. 11540 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U; 11541 auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex()); 11542 if (std::any_of(PrevReports.first, PrevReports.second, 11543 [DupCheckMatchClass]( 11544 const std::pair<unsigned, unsigned> Pair) { 11545 if (DupCheckMatchClass == ~0U || Pair.second == ~0U) 11546 return Pair.second == DupCheckMatchClass; 11547 else 11548 return isSubclass((MatchClassKind)DupCheckMatchClass, 11549 (MatchClassKind)Pair.second); 11550 })) 11551 break; 11552 OperandMissesSeen.insert( 11553 std::make_pair(I.getOperandIndex(), DupCheckMatchClass)); 11554 11555 NearMissMessage Message; 11556 Message.Loc = OperandLoc; 11557 if (OperandDiag) { 11558 Message.Message = OperandDiag; 11559 } else if (I.getOperandClass() == InvalidMatchClass) { 11560 Message.Message = "too many operands for instruction"; 11561 } else { 11562 Message.Message = "invalid operand for instruction"; 11563 LLVM_DEBUG( 11564 dbgs() << "Missing diagnostic string for operand class " 11565 << getMatchClassName((MatchClassKind)I.getOperandClass()) 11566 << I.getOperandClass() << ", error " << I.getOperandError() 11567 << ", opcode " << MII.getName(I.getOpcode()) << "\n"); 11568 } 11569 NearMissesOut.emplace_back(Message); 11570 break; 11571 } 11572 case NearMissInfo::NearMissFeature: { 11573 const FeatureBitset &MissingFeatures = I.getFeatures(); 11574 // Don't report the same set of features twice. 11575 if (FeatureMissesSeen.count(MissingFeatures)) 11576 break; 11577 FeatureMissesSeen.insert(MissingFeatures); 11578 11579 // Special case: don't report a feature set which includes arm-mode for 11580 // targets that don't have ARM mode. 11581 if (MissingFeatures.test(Feature_IsARMBit) && !hasARM()) 11582 break; 11583 // Don't report any near-misses that both require switching instruction 11584 // set, and adding other subtarget features. 11585 if (isThumb() && MissingFeatures.test(Feature_IsARMBit) && 11586 MissingFeatures.count() > 1) 11587 break; 11588 if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) && 11589 MissingFeatures.count() > 1) 11590 break; 11591 if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) && 11592 (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit, 11593 Feature_IsThumbBit})).any()) 11594 break; 11595 if (isMClass() && MissingFeatures.test(Feature_HasNEONBit)) 11596 break; 11597 11598 NearMissMessage Message; 11599 Message.Loc = IDLoc; 11600 raw_svector_ostream OS(Message.Message); 11601 11602 OS << "instruction requires:"; 11603 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 11604 if (MissingFeatures.test(i)) 11605 OS << ' ' << getSubtargetFeatureName(i); 11606 11607 NearMissesOut.emplace_back(Message); 11608 11609 break; 11610 } 11611 case NearMissInfo::NearMissPredicate: { 11612 NearMissMessage Message; 11613 Message.Loc = IDLoc; 11614 switch (I.getPredicateError()) { 11615 case Match_RequiresNotITBlock: 11616 Message.Message = "flag setting instruction only valid outside IT block"; 11617 break; 11618 case Match_RequiresITBlock: 11619 Message.Message = "instruction only valid inside IT block"; 11620 break; 11621 case Match_RequiresV6: 11622 Message.Message = "instruction variant requires ARMv6 or later"; 11623 break; 11624 case Match_RequiresThumb2: 11625 Message.Message = "instruction variant requires Thumb2"; 11626 break; 11627 case Match_RequiresV8: 11628 Message.Message = "instruction variant requires ARMv8 or later"; 11629 break; 11630 case Match_RequiresFlagSetting: 11631 Message.Message = "no flag-preserving variant of this instruction available"; 11632 break; 11633 case Match_InvalidOperand: 11634 Message.Message = "invalid operand for instruction"; 11635 break; 11636 default: 11637 llvm_unreachable("Unhandled target predicate error"); 11638 break; 11639 } 11640 NearMissesOut.emplace_back(Message); 11641 break; 11642 } 11643 case NearMissInfo::NearMissTooFewOperands: { 11644 if (!ReportedTooFewOperands) { 11645 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); 11646 NearMissesOut.emplace_back(NearMissMessage{ 11647 EndLoc, StringRef("too few operands for instruction")}); 11648 ReportedTooFewOperands = true; 11649 } 11650 break; 11651 } 11652 case NearMissInfo::NoNearMiss: 11653 // This should never leave the matcher. 11654 llvm_unreachable("not a near-miss"); 11655 break; 11656 } 11657 } 11658 } 11659 11660 void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, 11661 SMLoc IDLoc, OperandVector &Operands) { 11662 SmallVector<NearMissMessage, 4> Messages; 11663 FilterNearMisses(NearMisses, Messages, IDLoc, Operands); 11664 11665 if (Messages.size() == 0) { 11666 // No near-misses were found, so the best we can do is "invalid 11667 // instruction". 11668 Error(IDLoc, "invalid instruction"); 11669 } else if (Messages.size() == 1) { 11670 // One near miss was found, report it as the sole error. 11671 Error(Messages[0].Loc, Messages[0].Message); 11672 } else { 11673 // More than one near miss, so report a generic "invalid instruction" 11674 // error, followed by notes for each of the near-misses. 11675 Error(IDLoc, "invalid instruction, any one of the following would fix this:"); 11676 for (auto &M : Messages) { 11677 Note(M.Loc, M.Message); 11678 } 11679 } 11680 } 11681 11682 /// parseDirectiveArchExtension 11683 /// ::= .arch_extension [no]feature 11684 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 11685 // FIXME: This structure should be moved inside ARMTargetParser 11686 // when we start to table-generate them, and we can use the ARM 11687 // flags below, that were generated by table-gen. 11688 static const struct { 11689 const unsigned Kind; 11690 const FeatureBitset ArchCheck; 11691 const FeatureBitset Features; 11692 } Extensions[] = { 11693 { ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC} }, 11694 { ARM::AEK_CRYPTO, {Feature_HasV8Bit}, 11695 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, 11696 { ARM::AEK_FP, {Feature_HasV8Bit}, 11697 {ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} }, 11698 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), 11699 {Feature_HasV7Bit, Feature_IsNotMClassBit}, 11700 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} }, 11701 { ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit}, 11702 {ARM::FeatureMP} }, 11703 { ARM::AEK_SIMD, {Feature_HasV8Bit}, 11704 {ARM::FeatureNEON, ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} }, 11705 { ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} }, 11706 // FIXME: Only available in A-class, isel not predicated 11707 { ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} }, 11708 { ARM::AEK_FP16, {Feature_HasV8_2aBit}, 11709 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} }, 11710 { ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS} }, 11711 { ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB} }, 11712 // FIXME: Unsupported extensions. 11713 { ARM::AEK_OS, {}, {} }, 11714 { ARM::AEK_IWMMXT, {}, {} }, 11715 { ARM::AEK_IWMMXT2, {}, {} }, 11716 { ARM::AEK_MAVERICK, {}, {} }, 11717 { ARM::AEK_XSCALE, {}, {} }, 11718 }; 11719 11720 MCAsmParser &Parser = getParser(); 11721 11722 if (getLexer().isNot(AsmToken::Identifier)) 11723 return Error(getLexer().getLoc(), "expected architecture extension name"); 11724 11725 StringRef Name = Parser.getTok().getString(); 11726 SMLoc ExtLoc = Parser.getTok().getLoc(); 11727 Lex(); 11728 11729 if (parseToken(AsmToken::EndOfStatement, 11730 "unexpected token in '.arch_extension' directive")) 11731 return true; 11732 11733 bool EnableFeature = true; 11734 if (Name.startswith_lower("no")) { 11735 EnableFeature = false; 11736 Name = Name.substr(2); 11737 } 11738 unsigned FeatureKind = ARM::parseArchExt(Name); 11739 if (FeatureKind == ARM::AEK_INVALID) 11740 return Error(ExtLoc, "unknown architectural extension: " + Name); 11741 11742 for (const auto &Extension : Extensions) { 11743 if (Extension.Kind != FeatureKind) 11744 continue; 11745 11746 if (Extension.Features.none()) 11747 return Error(ExtLoc, "unsupported architectural extension: " + Name); 11748 11749 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) 11750 return Error(ExtLoc, "architectural extension '" + Name + 11751 "' is not " 11752 "allowed for the current base architecture"); 11753 11754 MCSubtargetInfo &STI = copySTI(); 11755 if (EnableFeature) { 11756 STI.SetFeatureBitsTransitively(Extension.Features); 11757 } else { 11758 STI.ClearFeatureBitsTransitively(Extension.Features); 11759 } 11760 FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits()); 11761 setAvailableFeatures(Features); 11762 return false; 11763 } 11764 11765 return Error(ExtLoc, "unknown architectural extension: " + Name); 11766 } 11767 11768 // Define this matcher function after the auto-generated include so we 11769 // have the match class enum definitions. 11770 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 11771 unsigned Kind) { 11772 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp); 11773 // If the kind is a token for a literal immediate, check if our asm 11774 // operand matches. This is for InstAliases which have a fixed-value 11775 // immediate in the syntax. 11776 switch (Kind) { 11777 default: break; 11778 case MCK__35_0: 11779 if (Op.isImm()) 11780 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 11781 if (CE->getValue() == 0) 11782 return Match_Success; 11783 break; 11784 case MCK__35_8: 11785 if (Op.isImm()) 11786 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 11787 if (CE->getValue() == 8) 11788 return Match_Success; 11789 break; 11790 case MCK__35_16: 11791 if (Op.isImm()) 11792 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 11793 if (CE->getValue() == 16) 11794 return Match_Success; 11795 break; 11796 case MCK_ModImm: 11797 if (Op.isImm()) { 11798 const MCExpr *SOExpr = Op.getImm(); 11799 int64_t Value; 11800 if (!SOExpr->evaluateAsAbsolute(Value)) 11801 return Match_Success; 11802 assert((Value >= std::numeric_limits<int32_t>::min() && 11803 Value <= std::numeric_limits<uint32_t>::max()) && 11804 "expression value must be representable in 32 bits"); 11805 } 11806 break; 11807 case MCK_rGPR: 11808 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) 11809 return Match_Success; 11810 return Match_rGPR; 11811 case MCK_GPRPair: 11812 if (Op.isReg() && 11813 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) 11814 return Match_Success; 11815 break; 11816 } 11817 return Match_InvalidOperand; 11818 } 11819 11820 bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic, 11821 StringRef ExtraToken) { 11822 if (!hasMVE()) 11823 return false; 11824 11825 return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") || 11826 Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") || 11827 Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") || 11828 Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") || 11829 Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") || 11830 Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") || 11831 Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") || 11832 Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") || 11833 Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") || 11834 Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") || 11835 Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") || 11836 Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") || 11837 Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") || 11838 Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") || 11839 Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") || 11840 Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") || 11841 Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") || 11842 Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") || 11843 Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") || 11844 Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") || 11845 Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") || 11846 Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") || 11847 Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") || 11848 Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") || 11849 Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") || 11850 Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") || 11851 Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") || 11852 Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") || 11853 Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") || 11854 Mnemonic.startswith("vqabs") || 11855 (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") || 11856 Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") || 11857 Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") || 11858 Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") || 11859 Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") || 11860 Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") || 11861 Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") || 11862 Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") || 11863 Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") || 11864 Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") || 11865 Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") || 11866 Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") || 11867 Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") || 11868 Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") || 11869 Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") || 11870 Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") || 11871 Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") || 11872 Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") || 11873 Mnemonic.startswith("vldrb") || 11874 (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") || 11875 (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") || 11876 Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") || 11877 Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") || 11878 Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") || 11879 Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") || 11880 Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") || 11881 Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") || 11882 Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") || 11883 Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") || 11884 Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") || 11885 Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") || 11886 Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") || 11887 Mnemonic.startswith("vcvt") || 11888 (Mnemonic.startswith("vmov") && 11889 !(ExtraToken == ".f16" || ExtraToken == ".32" || 11890 ExtraToken == ".16" || ExtraToken == ".8")); 11891 } 11892