1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include <memory>
19 #include <string>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInstrInfo;
27 class MCInstPrinter;
28 class MCObjectTargetWriter;
29 class MCObjectWriter;
30 class MCRegisterInfo;
31 class MCSubtargetInfo;
32 class MCStreamer;
33 class MCTargetOptions;
34 class MCRelocationInfo;
35 class MCTargetStreamer;
36 class StringRef;
37 class Target;
38 class Triple;
39 class raw_ostream;
40 class raw_pwrite_stream;
41 
42 namespace ARM_MC {
43 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
44 
45 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
46 /// do not need to go through TargetRegistry.
47 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
48                                           StringRef FS);
49 }
50 
51 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
52 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
53                                              formatted_raw_ostream &OS,
54                                              MCInstPrinter *InstPrint,
55                                              bool isVerboseAsm);
56 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
57                                                 const MCSubtargetInfo &STI);
58 
59 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
60                                         const MCRegisterInfo &MRI,
61                                         MCContext &Ctx);
62 
63 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
64                                         const MCRegisterInfo &MRI,
65                                         MCContext &Ctx);
66 
67 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
68                                     const MCRegisterInfo &MRI,
69                                     const MCTargetOptions &Options);
70 
71 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
72                                     const MCRegisterInfo &MRI,
73                                     const MCTargetOptions &Options);
74 
75 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
76 // object file.
77 MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
78                                      std::unique_ptr<MCAsmBackend> &&MAB,
79                                      std::unique_ptr<MCObjectWriter> &&OW,
80                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
81                                      bool RelaxAll,
82                                      bool IncrementalLinkerCompatible);
83 
84 /// Construct an ELF Mach-O object writer.
85 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
86 
87 /// Construct an ARM Mach-O object writer.
88 std::unique_ptr<MCObjectTargetWriter>
89 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
90                           uint32_t CPUSubtype);
91 
92 /// Construct an ARM PE/COFF object writer.
93 std::unique_ptr<MCObjectTargetWriter>
94 createARMWinCOFFObjectWriter(bool Is64Bit);
95 
96 /// Construct ARM Mach-O relocation info.
97 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
98 
99 namespace ARM {
100 enum OperandType {
101   OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
102   OPERAND_VPRED_N,
103 };
104 inline bool isVpred(OperandType op) {
105   return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
106 }
107 inline bool isVpred(uint8_t op) {
108   return isVpred(static_cast<OperandType>(op));
109 }
110 
111 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
112 
113 } // end namespace ARM
114 
115 } // End llvm namespace
116 
117 // Defines symbolic names for ARM registers.  This defines a mapping from
118 // register name to register number.
119 //
120 #define GET_REGINFO_ENUM
121 #include "ARMGenRegisterInfo.inc"
122 
123 // Defines symbolic names for the ARM instructions.
124 //
125 #define GET_INSTRINFO_ENUM
126 #include "ARMGenInstrInfo.inc"
127 
128 #define GET_SUBTARGETINFO_ENUM
129 #include "ARMGenSubtargetInfo.inc"
130 
131 #endif
132