1//===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class AddrMode<bits<5> val> {
10  bits<5> Value = val;
11}
12
13def AddrModeNone : AddrMode<0>;
14def AddrMode32B : AddrMode<1>;   // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
15def AddrMode32H : AddrMode<2>;   // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
16def AddrMode32WD : AddrMode<3>;  // ld32.w, st32.w, ld32.d, st32.d, +16kb
17def AddrMode16B : AddrMode<4>;   // ld16.b, +32b
18def AddrMode16H : AddrMode<5>;   // ld16.h, +64b
19def AddrMode16W : AddrMode<6>;   // ld16.w, +128b or +1kb
20def AddrMode32SDF : AddrMode<7>; // flds, fldd, +1kb
21
22class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
23               list<dag> pattern> : Instruction {
24  let Namespace = "CSKY";
25  int Size = sz;
26  AddrMode AM = am;
27
28  let OutOperandList = outs;
29  let InOperandList = ins;
30  let AsmString = asmstr;
31  let Pattern = pattern;
32  let Itinerary = NoItinerary;
33  let TSFlags{4 - 0} = AM.Value;
34}
35
36class CSKYPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
37    : CSKYInst<AddrModeNone, 0, outs, ins, asmstr, pattern> {
38  let isCodeGenOnly = 1;
39  let isPseudo = 1;
40}
41
42class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
43                 list<dag> pattern>
44    : CSKYInst<am, 4, outs, ins, asmstr, pattern> {
45  field bits<32> Inst;
46  let Inst{31 - 26} = opcode;
47}
48
49// CSKY 32-bit instruction
50// Format< OP[6] | Offset[26] >
51// Instruction(1): bsr32
52class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
53    : CSKY32Inst<AddrModeNone, opcode, outs, ins, !strconcat(op, "\t$offset"),
54                 pattern> {
55  bits<26> offset;
56  let Inst{25 - 0} = offset;
57}
58
59// Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
60// Instructions(7): grs, lrs32.b, lrs32.h, lrs32.w, srs32.b, srs32.h, srs32.w
61class I_18_Z_L<bits<3> sop, string op, Operand operand, list<dag> pattern>
62    : CSKY32Inst<AddrModeNone, 0x33, (outs GPR:$rz), (ins operand:$offset),
63                 !strconcat(op, "\t$rz, $offset"), pattern> {
64  bits<5> rz;
65  bits<18> offset;
66  let Inst{25 - 21} = rz;
67  let Inst{20 - 18} = sop;
68  let Inst{17 - 0} = offset;
69}
70
71// Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
72// Instructions(1): ori32
73class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
74    : CSKY32Inst<AddrModeNone, 0x3b,
75                 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
76                 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
77  bits<5> rz;
78  bits<5> rx;
79  bits<16> imm16;
80  let Inst{25 - 21} = rz;
81  let Inst{20 - 16} = rx;
82  let Inst{15 - 0} = imm16;
83}
84
85// Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
86// Instructions(3): movi32, movih32, (bgeni32)
87class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
88    : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
89                 !strconcat(op, "\t$rz, $imm16"),
90                 [(set GPR:$rz, ImmType:$imm16)]> {
91  bits<5> rz;
92  bits<16> imm16;
93  let Inst{25 - 21} = sop;
94  let Inst{20 - 16} = rz;
95  let Inst{15 - 0} = imm16;
96  let isReMaterializable = 1;
97  let isAsCheapAsAMove = 1;
98  let isMoveImm = 1;
99}
100
101// Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
102// Instructions(1): lrw32
103class I_16_Z_L<bits<5> sop, string op, Operand operand, list<dag> pattern>
104    : CSKY32Inst<AddrModeNone, 0x3a,
105                 (outs GPR:$rz), (ins operand:$imm16),
106                 !strconcat(op, "\t$rz, [$imm16]"), pattern> {
107  bits<5> rz;
108  bits<16> imm16;
109  let Inst{25 - 21} = sop;
110  let Inst{20 - 16} = rz;
111  let Inst{15 - 0} = imm16;
112}
113
114// Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
115// Instructions(5): bt32, bf32, br32, jmpi32, jsri32
116class I_16_L<bits<5> sop, dag outs, dag ins, string op, list<dag> pattern>
117    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$imm16"),
118                 pattern> {
119  bits<16> imm16;
120  let Inst{25 - 21} = sop;
121  let Inst{20 - 16} = 0;
122  let Inst{15 - 0} = imm16;
123}
124
125// bt32, bf32, br32, jmpi32
126class I_16_L_B<bits<5> sop, string op, Operand operand, list<dag> pattern>
127    : I_16_L<sop, (outs), (ins operand:$imm16, CARRY:$ca), op, pattern> {
128  let isBranch = 1;
129  let isTerminator = 1;
130}
131
132// Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
133// Instructions(2): jmp32, jsr32
134class I_16_JX<bits<5> sop, string op, list<dag> pattern>
135    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
136                 !strconcat(op, "\t$rx"), pattern> {
137  bits<5> rx;
138  bits<16> imm16;
139  let Inst{25 - 21} = sop;
140  let Inst{20 - 16} = rx;
141  let Inst{15 - 0} = 0;
142}
143
144// Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
145// Instructions(1): jmpix32
146class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
147    : CSKY32Inst<AddrModeNone, 0x3a, (outs),
148                 (ins GPR:$rx, operand:$imm2),
149                 !strconcat(op, "\t$rx, $imm2"), pattern> {
150  bits<5> rx;
151  bits<2> imm2;
152  let Inst{25 - 21} = sop;
153  let Inst{20 - 16} = rx;
154  let Inst{15 - 2} = 0;
155  let Inst{1 - 0} = imm2;
156}
157
158// Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
159// Instructions(1): rts32
160class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
161    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins), op, pattern> {
162  let Inst{25 - 21} = sop;
163  let Inst{20 - 16} = pcode;
164  let Inst{15 - 0} = 0;
165  let isTerminator = 1;
166  let isReturn = 1;
167  let isBarrier = 1;
168}
169
170// Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
171// Instructions(3): cmpnei32, cmphsi32, cmplti32
172class I_16_X<bits<5> sop, string op>
173    : CSKY32Inst<AddrModeNone, 0x3a, (outs CARRY:$ca),
174    (ins GPR:$rx, i32imm:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
175  bits<16> imm16;
176  bits<5> rx;
177  let Inst{25 - 21} = sop;
178  let Inst{20 - 16} = rx;
179  let Inst{15 - 0} = imm16;
180  let isCompare = 1;
181}
182
183// Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
184// Instructions(7): bez32, bnez32, bnezad32, bhz32, blsz32, blz32, bhsz32
185class I_16_X_L<bits<5> sop, string op, Operand operand>
186    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
187                 !strconcat(op, "\t$rx, $imm16"), []> {
188  bits<5> rx;
189  bits<16> imm16;
190  let Inst{25 - 21} = sop;
191  let Inst{20 - 16} = rx;
192  let Inst{15 - 0} = imm16;
193  let isBranch = 1;
194  let isTerminator = 1;
195}
196
197// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
198// Instructions(5): addi32, subi32, andi32, andni32, xori32
199class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
200    : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
201    (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
202    [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
203  bits<5> rz;
204  bits<5> rx;
205  bits<12> imm12;
206  let Inst{25 - 21} = rz;
207  let Inst{20 - 16} = rx;
208  let Inst{15 - 12} = sop;
209  let Inst{11 - 0} = imm12;
210}
211
212class I_LDST<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
213             string op, list<dag> pattern>
214    : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, $imm12)"),
215                 pattern> {
216  bits<5> rx;
217  bits<5> rz;
218  bits<12> imm12;
219  let Inst{25 - 21} = rz;
220  let Inst{20 - 16} = rx;
221  let Inst{15 - 12} = sop;
222  let Inst{11 - 0} = imm12;
223}
224
225// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
226// Instructions(6): ld32.b, ld32.bs, ld32.h, ld32.hs, ld32.w, ld32.d
227class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
228    : I_LDST<am, 0x36, sop,
229    (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
230
231// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
232// Instructions(4): st32.b, st32.h, st32.w, st32.d
233class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
234    : I_LDST<am, 0x37, sop, (outs),
235    (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
236
237// Format< OP[6] | SOP[5] | PCODE[5] | 0000[4] | 000 | R28 | LIST2[3] | R15 |
238// LIST1[4] >
239// Instructions(2): push32, pop32
240class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
241    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$regs"), []> {
242  bits<12> regs;
243  let Inst{25 - 21} = sop;
244  let Inst{20 - 16} = pcode;
245  let Inst{15 - 12} = 0;
246  let Inst{11 - 0} = regs;
247}
248
249// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
250// Instructions(4): incf32, inct32, decf32, dect32
251class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
252             list<dag> pattern>
253    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
254    (ins GPR:$false, GPR:$rx, ImmType:$imm5),
255    !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
256  bits<5> rz;
257  bits<5> rx;
258  bits<5> imm5;
259  let Inst{25 - 21} = rz;
260  let Inst{20 - 16} = rx;
261  let Inst{15 - 10} = sop;
262  let Inst{9 - 5} = pcode;
263  let Inst{4 - 0} = imm5;
264  let Constraints = "$rz = $false";
265}
266
267// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
268// Instructions(13): decgt32, declt32, decne32, lsli32, lslc32, lsri32
269//                   lsrc32, asri32, asrc32, rotli32, xsr32, bclri32, bseti32
270class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag ins, dag outs,
271             list<dag> pattern>
272    : CSKY32Inst<AddrModeNone, 0x31, ins, outs,
273                 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
274  bits<5> imm5;
275  bits<5> rx;
276  bits<5> rz;
277  let Inst{25 - 21} = imm5;
278  let Inst{20 - 16} = rx;
279  let Inst{15 - 10} = sop;
280  let Inst{9 - 5} = pcode;
281  let Inst{4 - 0} = rz;
282}
283
284// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
285// Instructions(2): ldm32, (ldq32), stm32, (stq32)
286class I_5_YX<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern,
287             bits<5> imm5>
288    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
289                 op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
290  bits<5> rx;
291  bits<5> ry;
292  let Inst{25 - 21} = ry; // ry
293  let Inst{20 - 16} = rx;
294  let Inst{15 - 10} = 0b000111;
295  let Inst{9 - 5} = 0b00001;
296  let Inst{4 - 0} = imm5{4 - 0}; // imm5
297}
298
299// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
300// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
301class I_5_XZ_U<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
302               string op, list<dag> pattern>
303    : CSKY32Inst<AddrModeNone, 0x31, outs, ins,
304                 op #"\t$rz, $rx, " #!cast<int>(msb) #", " #!cast<int>(lsb),
305                 pattern> {
306  bits<5> rx;
307  bits<5> rz;
308  let Inst{25 - 21} = lsb; // lsb
309  let Inst{20 - 16} = rx;
310  let Inst{15 - 10} = sop;
311  let Inst{9 - 5} = msb; // msb
312  let Inst{4 - 0} = rz;
313}
314
315// sextb, sexth
316class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op, SDNode opnode,
317  ValueType type> : I_5_XZ_U<sop, lsb, msb,
318  (outs GPR:$rz), (ins GPR:$rx),op, [(set GPR:$rz, (opnode GPR:$rx, type))]>;
319
320class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
321    : I_5_XZ_U<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
322    [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
323
324// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]>
325// Instructions(1): ins32
326class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
327    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins operand:$size_lsb),
328                 !strconcat(op, "\t$rz, operand:$size_lsb"), pattern> {
329  bits<10> size_lsb;
330  bits<5> rz;
331  bits<5> rx;
332  let Inst{25 - 21} = rz;
333  let Inst{20 - 16} = rx;
334  let Inst{15 - 10} = sop;
335  let Inst{9 - 5} = size_lsb{9 - 5}; // size
336  let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
337}
338
339// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
340// Instructions(1): btsti32
341class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
342            list<dag> pattern>
343    : CSKY32Inst<AddrModeNone, 0x31,
344    (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
345    !strconcat(op, "\t$rx, $imm5"), pattern> {
346  bits<5> imm5;
347  bits<5> rx;
348  let Inst{25 - 21} = imm5;
349  let Inst{20 - 16} = rx;
350  let Inst{15 - 10} = sop;
351  let Inst{9 - 5} = pcode;
352  let Inst{4 - 0} = 0;
353  let isCompare = 1;
354}
355
356// Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
357// Instructions(1): bmaski32
358class I_5_Z<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
359            list<dag> pattern>
360    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins ImmType:$imm5),
361                 !strconcat(op, "\t$rz, $imm5"), pattern> {
362  bits<5> imm5;
363  bits<5> rz;
364  let Inst{25 - 21} = imm5;
365  let Inst{20 - 16} = 0;
366  let Inst{15 - 10} = sop;
367  let Inst{9 - 5} = pcode;
368  let Inst{4 - 0} = rz;
369}
370
371// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
372// Instructions(24): addu32, addc32, subu32, subc32, (rsub32), ixh32, ixw32,
373// ixd32, and32, andn32, or32, xor32, nor32, lsl32, lsr32, asr32, rotl32
374// mult32, divu32, divs32, mul.(u/s)32, mula.32.l, mula.u32, mulall.s16.s
375class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
376            string op, list<dag> pattern>
377    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
378                 !strconcat(op, "\t$rz, $rx, $ry"), pattern> {
379  bits<5> ry;
380  bits<5> rx;
381  bits<5> rz;
382  let Inst{25 - 21} = ry;
383  let Inst{20 - 16} = rx;
384  let Inst{15 - 10} = sop;
385  let Inst{9 - 5} = pcode;
386  let Inst{4 - 0} = rz;
387}
388
389// R_YXZ instructions with simple pattern
390// Output: GPR:rz
391// Input: GPR:rx, GPR:ry
392// Asm string: op rz, rx, ry
393// Instructions: addu32, subu32, ixh32, ixw32, ixd32, and32, andn32, or32,
394// xor32, nor32, lsl32, lsr32, asr32, mult32, divu32, divs32
395class R_YXZ_SP_F1<bits<6> sop, bits<5> pcode, PatFrag opnode, string op,
396  bit Commutable = 0> : R_YXZ<0x31, sop, pcode, (outs GPR:$rz),
397  (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
398  let isCommutable = Commutable;
399}
400
401// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
402// Instructions:(8) ldr32.b, ldr32.h, ldr32.bs, ldr32.hs, ldr32.w,
403//                  str32.b, str32.h, str32.w
404class R_YXZ_LDST<bits<6> opcode, bits<6> sop, bits<5> pcode, int no, dag outs,
405                 dag ins, string op, list<dag> pattern>
406    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
407                 op #"\t$rz, ($rx, $ry << " #no #")", pattern> {
408  bits<5> rx;
409  bits<5> ry;
410  bits<5> rz;
411  let Inst{25 - 21} = ry; // ry;
412  let Inst{20 - 16} = rx; // rx;
413  let Inst{15 - 10} = sop;
414  let Inst{9 - 5} = pcode; // pcode;
415  let Inst{4 - 0} = rz;
416}
417
418class I_LDR<bits<6> sop, bits<5> pcode, string op, int no>
419    : R_YXZ_LDST<0x34, sop, pcode, no,
420    (outs GPR:$rz), (ins GPR:$rx, GPR:$ry), op, []>;
421
422class I_STR<bits<6> sop, bits<5> pcode, string op, int no>
423    : R_YXZ_LDST<0x35, sop, pcode, no, (outs),
424    (ins GPR:$rz, GPR:$rx, GPR:$ry), op, []>;
425
426// Format< OP[6] | RX[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
427// Instructions:(1) not32
428class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
429            list<dag> pattern>
430    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"),
431                 pattern> {
432  bits<5> rx;
433  bits<5> rz;
434  let Inst{25 - 21} = rx;
435  let Inst{20 - 16} = rx;
436  let Inst{15 - 10} = sop;
437  let Inst{9 - 5} = pcode;
438  let Inst{4 - 0} = rz;
439}
440
441// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
442// Instructions:(4) cmpne32, cmphs32, cmplt32, tst32
443class R_YX<bits<6> sop, bits<5> pcode, string op>
444    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
445                 (ins GPR:$rx, GPR:$ry),
446                 !strconcat(op, "\t$rx, $ry"), []> {
447  bits<5> ry;
448  bits<5> rx;
449  let Inst{25 - 21} = ry;
450  let Inst{20 - 16} = rx;
451  let Inst{15 - 10} = sop;
452  let Inst{9 - 5} = pcode;
453  let Inst{4 - 0} = 0;
454  let isCompare = 1;
455}
456
457// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
458// Instructions:(12)
459//   mov32, xtrb0.32, xtrb1.32, xtrb2.32, xtrb3.32, brev32, revb32
460//   revh32, abs32, ff0.32, ff1.32, bgenr32
461class R_XZ<bits<6> sop, bits<5> pcode, string op>
462    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins GPR:$rx),
463                 !strconcat(op, "\t$rz, $rx"), []> {
464  bits<5> rx;
465  bits<5> rz;
466  let Inst{25 - 21} = 0;
467  let Inst{20 - 16} = rx;
468  let Inst{15 - 10} = sop;
469  let Inst{9 - 5} = pcode;
470  let Inst{4 - 0} = rz;
471}
472
473// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
474// Instructions:(2) movf32, movt32
475class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
476    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
477                 (ins CARRY:$ca, GPR:$rx, GPR:$false),
478                 !strconcat(op, "\t$rz, $rx"), pattern> {
479  bits<5> rz;
480  bits<5> rx;
481  let Inst{25 - 21} = rz;
482  let Inst{20 - 16} = rx;
483  let Inst{15 - 10} = sop;
484  let Inst{9 - 5} = pcode;
485  let Inst{4 - 0} = 0;
486  let Constraints = "$rz = $false";
487  let isSelect = 1;
488}
489
490// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
491// Instructions:(1) tstnbz32
492class R_X<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
493    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),(ins GPR:$rx),
494                 !strconcat(op, "\t$rx"), pattern> {
495  bits<5> rx;
496  let Inst{25 - 21} = 0;
497  let Inst{20 - 16} = rx;
498  let Inst{15 - 10} = sop;
499  let Inst{9 - 5} = pcode;
500  let Inst{4 - 0} = 0;
501}
502
503// Format< OP[6] | 00000[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5] >
504// Instructions:(2) mvc32, mvcv32
505class R_Z_1<bits<6> sop, bits<5> pcode, string op>
506    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
507                 (ins CARRY:$ca), !strconcat(op, "\t$rz"), []> {
508  bits<5> rz;
509  let Inst{25 - 21} = 0;
510  let Inst{20 - 16} = 0;
511  let Inst{15 - 10} = sop;
512  let Inst{9 - 5} = pcode;
513  let Inst{4 - 0} = rz;
514}
515
516// Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
517// Instructions:(2) clrf32, clrt32
518class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
519    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
520    (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
521  bits<5> rz;
522  let Inst{25 - 21} = rz;
523  let Inst{20 - 16} = 0;
524  let Inst{15 - 10} = sop;
525  let Inst{9 - 5} = pcode;
526  let Inst{4 - 0} = 0;
527  let Constraints = "$rz = $false";
528}
529