10b57cec5SDimitry Andric //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric // This pass replaces transfer instructions by combine instructions.
90b57cec5SDimitry Andric // We walk along a basic block and look for two combinable instructions and try
100b57cec5SDimitry Andric // to move them together. If we can move them next to each other we do so and
110b57cec5SDimitry Andric // replace them with a combine instruction.
120b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
13e8d8bef9SDimitry Andric
140b57cec5SDimitry Andric #include "HexagonInstrInfo.h"
150b57cec5SDimitry Andric #include "HexagonSubtarget.h"
160b57cec5SDimitry Andric #include "llvm/ADT/DenseMap.h"
170b57cec5SDimitry Andric #include "llvm/ADT/DenseSet.h"
180b57cec5SDimitry Andric #include "llvm/CodeGen/MachineBasicBlock.h"
190b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
200b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h"
210b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstr.h"
220b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
230b57cec5SDimitry Andric #include "llvm/CodeGen/Passes.h"
240b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h"
255ffd83dbSDimitry Andric #include "llvm/Pass.h"
260b57cec5SDimitry Andric #include "llvm/Support/CodeGen.h"
270b57cec5SDimitry Andric #include "llvm/Support/CommandLine.h"
280b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
290b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
30e8d8bef9SDimitry Andric #include "llvm/Target/TargetMachine.h"
310b57cec5SDimitry Andric
320b57cec5SDimitry Andric using namespace llvm;
330b57cec5SDimitry Andric
340b57cec5SDimitry Andric #define DEBUG_TYPE "hexagon-copy-combine"
350b57cec5SDimitry Andric
3681ad6265SDimitry Andric static cl::opt<bool>
3781ad6265SDimitry Andric IsCombinesDisabled("disable-merge-into-combines", cl::Hidden,
3881ad6265SDimitry Andric
390b57cec5SDimitry Andric cl::desc("Disable merging into combines"));
4081ad6265SDimitry Andric static cl::opt<bool>
4181ad6265SDimitry Andric IsConst64Disabled("disable-const64", cl::Hidden,
4281ad6265SDimitry Andric
430b57cec5SDimitry Andric cl::desc("Disable generation of const64"));
440b57cec5SDimitry Andric static
450b57cec5SDimitry Andric cl::opt<unsigned>
460b57cec5SDimitry Andric MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
470b57cec5SDimitry Andric cl::Hidden, cl::init(4),
480b57cec5SDimitry Andric cl::desc("Maximum distance between a tfr feeding a store we "
490b57cec5SDimitry Andric "consider the store still to be newifiable"));
500b57cec5SDimitry Andric
510b57cec5SDimitry Andric namespace llvm {
520b57cec5SDimitry Andric FunctionPass *createHexagonCopyToCombine();
530b57cec5SDimitry Andric void initializeHexagonCopyToCombinePass(PassRegistry&);
540b57cec5SDimitry Andric }
550b57cec5SDimitry Andric
560b57cec5SDimitry Andric
570b57cec5SDimitry Andric namespace {
580b57cec5SDimitry Andric
590b57cec5SDimitry Andric class HexagonCopyToCombine : public MachineFunctionPass {
600b57cec5SDimitry Andric const HexagonInstrInfo *TII;
610b57cec5SDimitry Andric const TargetRegisterInfo *TRI;
620b57cec5SDimitry Andric const HexagonSubtarget *ST;
630b57cec5SDimitry Andric bool ShouldCombineAggressively;
640b57cec5SDimitry Andric
650b57cec5SDimitry Andric DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
660b57cec5SDimitry Andric SmallVector<MachineInstr *, 8> DbgMItoMove;
670b57cec5SDimitry Andric
680b57cec5SDimitry Andric public:
690b57cec5SDimitry Andric static char ID;
700b57cec5SDimitry Andric
HexagonCopyToCombine()7104eeddc0SDimitry Andric HexagonCopyToCombine() : MachineFunctionPass(ID) {}
720b57cec5SDimitry Andric
getAnalysisUsage(AnalysisUsage & AU) const730b57cec5SDimitry Andric void getAnalysisUsage(AnalysisUsage &AU) const override {
740b57cec5SDimitry Andric MachineFunctionPass::getAnalysisUsage(AU);
750b57cec5SDimitry Andric }
760b57cec5SDimitry Andric
getPassName() const770b57cec5SDimitry Andric StringRef getPassName() const override {
780b57cec5SDimitry Andric return "Hexagon Copy-To-Combine Pass";
790b57cec5SDimitry Andric }
800b57cec5SDimitry Andric
810b57cec5SDimitry Andric bool runOnMachineFunction(MachineFunction &Fn) override;
820b57cec5SDimitry Andric
getRequiredProperties() const830b57cec5SDimitry Andric MachineFunctionProperties getRequiredProperties() const override {
840b57cec5SDimitry Andric return MachineFunctionProperties().set(
850b57cec5SDimitry Andric MachineFunctionProperties::Property::NoVRegs);
860b57cec5SDimitry Andric }
870b57cec5SDimitry Andric
880b57cec5SDimitry Andric private:
890b57cec5SDimitry Andric MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
900b57cec5SDimitry Andric bool AllowC64);
910b57cec5SDimitry Andric
920b57cec5SDimitry Andric void findPotentialNewifiableTFRs(MachineBasicBlock &);
930b57cec5SDimitry Andric
940b57cec5SDimitry Andric void combine(MachineInstr &I1, MachineInstr &I2,
950b57cec5SDimitry Andric MachineBasicBlock::iterator &MI, bool DoInsertAtI1,
960b57cec5SDimitry Andric bool OptForSize);
970b57cec5SDimitry Andric
980b57cec5SDimitry Andric bool isSafeToMoveTogether(MachineInstr &I1, MachineInstr &I2,
990b57cec5SDimitry Andric unsigned I1DestReg, unsigned I2DestReg,
1000b57cec5SDimitry Andric bool &DoInsertAtI1);
1010b57cec5SDimitry Andric
1020b57cec5SDimitry Andric void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
1030b57cec5SDimitry Andric MachineOperand &HiOperand, MachineOperand &LoOperand);
1040b57cec5SDimitry Andric
1050b57cec5SDimitry Andric void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
1060b57cec5SDimitry Andric MachineOperand &HiOperand, MachineOperand &LoOperand);
1070b57cec5SDimitry Andric
1080b57cec5SDimitry Andric void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
1090b57cec5SDimitry Andric MachineOperand &HiOperand, MachineOperand &LoOperand);
1100b57cec5SDimitry Andric
1110b57cec5SDimitry Andric void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
1120b57cec5SDimitry Andric MachineOperand &HiOperand, MachineOperand &LoOperand);
1130b57cec5SDimitry Andric
1140b57cec5SDimitry Andric void emitConst64(MachineBasicBlock::iterator &Before, unsigned DestReg,
1150b57cec5SDimitry Andric MachineOperand &HiOperand, MachineOperand &LoOperand);
1160b57cec5SDimitry Andric };
1170b57cec5SDimitry Andric
1180b57cec5SDimitry Andric } // End anonymous namespace.
1190b57cec5SDimitry Andric
1200b57cec5SDimitry Andric char HexagonCopyToCombine::ID = 0;
1210b57cec5SDimitry Andric
1220b57cec5SDimitry Andric INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
1230b57cec5SDimitry Andric "Hexagon Copy-To-Combine Pass", false, false)
1240b57cec5SDimitry Andric
isCombinableInstType(MachineInstr & MI,const HexagonInstrInfo * TII,bool ShouldCombineAggressively)1250b57cec5SDimitry Andric static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
1260b57cec5SDimitry Andric bool ShouldCombineAggressively) {
1270b57cec5SDimitry Andric switch (MI.getOpcode()) {
1280b57cec5SDimitry Andric case Hexagon::A2_tfr: {
1290b57cec5SDimitry Andric // A COPY instruction can be combined if its arguments are IntRegs (32bit).
1300b57cec5SDimitry Andric const MachineOperand &Op0 = MI.getOperand(0);
1310b57cec5SDimitry Andric const MachineOperand &Op1 = MI.getOperand(1);
1320b57cec5SDimitry Andric assert(Op0.isReg() && Op1.isReg());
1330b57cec5SDimitry Andric
1348bcb0991SDimitry Andric Register DestReg = Op0.getReg();
1358bcb0991SDimitry Andric Register SrcReg = Op1.getReg();
1360b57cec5SDimitry Andric return Hexagon::IntRegsRegClass.contains(DestReg) &&
1370b57cec5SDimitry Andric Hexagon::IntRegsRegClass.contains(SrcReg);
1380b57cec5SDimitry Andric }
1390b57cec5SDimitry Andric
1400b57cec5SDimitry Andric case Hexagon::A2_tfrsi: {
1410b57cec5SDimitry Andric // A transfer-immediate can be combined if its argument is a signed 8bit
1420b57cec5SDimitry Andric // value.
1430b57cec5SDimitry Andric const MachineOperand &Op0 = MI.getOperand(0);
1440b57cec5SDimitry Andric const MachineOperand &Op1 = MI.getOperand(1);
1450b57cec5SDimitry Andric assert(Op0.isReg());
1460b57cec5SDimitry Andric
1478bcb0991SDimitry Andric Register DestReg = Op0.getReg();
1480b57cec5SDimitry Andric // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
1490b57cec5SDimitry Andric // workaround for an ABI bug that prevents GOT relocations on combine
1500b57cec5SDimitry Andric // instructions
1510b57cec5SDimitry Andric if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
1520b57cec5SDimitry Andric return false;
1530b57cec5SDimitry Andric
1540b57cec5SDimitry Andric // Only combine constant extended A2_tfrsi if we are in aggressive mode.
1550b57cec5SDimitry Andric bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
1560b57cec5SDimitry Andric return Hexagon::IntRegsRegClass.contains(DestReg) &&
1570b57cec5SDimitry Andric (ShouldCombineAggressively || NotExt);
1580b57cec5SDimitry Andric }
1590b57cec5SDimitry Andric
1600b57cec5SDimitry Andric case Hexagon::V6_vassign:
1610b57cec5SDimitry Andric return true;
1620b57cec5SDimitry Andric
1630b57cec5SDimitry Andric default:
1640b57cec5SDimitry Andric break;
1650b57cec5SDimitry Andric }
1660b57cec5SDimitry Andric
1670b57cec5SDimitry Andric return false;
1680b57cec5SDimitry Andric }
1690b57cec5SDimitry Andric
isGreaterThanNBitTFRI(const MachineInstr & I)1700b57cec5SDimitry Andric template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
1710b57cec5SDimitry Andric if (I.getOpcode() == Hexagon::TFRI64_V4 ||
1720b57cec5SDimitry Andric I.getOpcode() == Hexagon::A2_tfrsi) {
1730b57cec5SDimitry Andric const MachineOperand &Op = I.getOperand(1);
1740b57cec5SDimitry Andric return !Op.isImm() || !isInt<N>(Op.getImm());
1750b57cec5SDimitry Andric }
1760b57cec5SDimitry Andric return false;
1770b57cec5SDimitry Andric }
1780b57cec5SDimitry Andric
1790b57cec5SDimitry Andric /// areCombinableOperations - Returns true if the two instruction can be merge
1800b57cec5SDimitry Andric /// into a combine (ignoring register constraints).
areCombinableOperations(const TargetRegisterInfo * TRI,MachineInstr & HighRegInst,MachineInstr & LowRegInst,bool AllowC64)1810b57cec5SDimitry Andric static bool areCombinableOperations(const TargetRegisterInfo *TRI,
1820b57cec5SDimitry Andric MachineInstr &HighRegInst,
1830b57cec5SDimitry Andric MachineInstr &LowRegInst, bool AllowC64) {
1840b57cec5SDimitry Andric unsigned HiOpc = HighRegInst.getOpcode();
1850b57cec5SDimitry Andric unsigned LoOpc = LowRegInst.getOpcode();
1860b57cec5SDimitry Andric
1870b57cec5SDimitry Andric auto verifyOpc = [](unsigned Opc) -> void {
1880b57cec5SDimitry Andric switch (Opc) {
1890b57cec5SDimitry Andric case Hexagon::A2_tfr:
1900b57cec5SDimitry Andric case Hexagon::A2_tfrsi:
1910b57cec5SDimitry Andric case Hexagon::V6_vassign:
1920b57cec5SDimitry Andric break;
1930b57cec5SDimitry Andric default:
1940b57cec5SDimitry Andric llvm_unreachable("Unexpected opcode");
1950b57cec5SDimitry Andric }
1960b57cec5SDimitry Andric };
1970b57cec5SDimitry Andric verifyOpc(HiOpc);
1980b57cec5SDimitry Andric verifyOpc(LoOpc);
1990b57cec5SDimitry Andric
2000b57cec5SDimitry Andric if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign)
2010b57cec5SDimitry Andric return HiOpc == LoOpc;
2020b57cec5SDimitry Andric
2030b57cec5SDimitry Andric if (!AllowC64) {
2040b57cec5SDimitry Andric // There is no combine of two constant extended values.
2050b57cec5SDimitry Andric if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
2060b57cec5SDimitry Andric isGreaterThanNBitTFRI<6>(LowRegInst))
2070b57cec5SDimitry Andric return false;
2080b57cec5SDimitry Andric }
2090b57cec5SDimitry Andric
2100b57cec5SDimitry Andric // There is a combine of two constant extended values into CONST64,
2110b57cec5SDimitry Andric // provided both constants are true immediates.
2120b57cec5SDimitry Andric if (isGreaterThanNBitTFRI<16>(HighRegInst) &&
2135ffd83dbSDimitry Andric isGreaterThanNBitTFRI<16>(LowRegInst) && !IsConst64Disabled)
2140b57cec5SDimitry Andric return (HighRegInst.getOperand(1).isImm() &&
2150b57cec5SDimitry Andric LowRegInst.getOperand(1).isImm());
2160b57cec5SDimitry Andric
2170b57cec5SDimitry Andric // There is no combine of two constant extended values, unless handled above
2180b57cec5SDimitry Andric // Make both 8-bit size checks to allow both combine (#,##) and combine(##,#)
2190b57cec5SDimitry Andric if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
2200b57cec5SDimitry Andric isGreaterThanNBitTFRI<8>(LowRegInst))
2210b57cec5SDimitry Andric return false;
2220b57cec5SDimitry Andric
2230b57cec5SDimitry Andric return true;
2240b57cec5SDimitry Andric }
2250b57cec5SDimitry Andric
isEvenReg(unsigned Reg)2260b57cec5SDimitry Andric static bool isEvenReg(unsigned Reg) {
2278bcb0991SDimitry Andric assert(Register::isPhysicalRegister(Reg));
2280b57cec5SDimitry Andric if (Hexagon::IntRegsRegClass.contains(Reg))
2290b57cec5SDimitry Andric return (Reg - Hexagon::R0) % 2 == 0;
2300b57cec5SDimitry Andric if (Hexagon::HvxVRRegClass.contains(Reg))
2310b57cec5SDimitry Andric return (Reg - Hexagon::V0) % 2 == 0;
2320b57cec5SDimitry Andric llvm_unreachable("Invalid register");
2330b57cec5SDimitry Andric }
2340b57cec5SDimitry Andric
removeKillInfo(MachineInstr & MI,unsigned RegNotKilled)2350b57cec5SDimitry Andric static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
2364824e7fdSDimitry Andric for (MachineOperand &Op : MI.operands())
2374824e7fdSDimitry Andric if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill())
2380b57cec5SDimitry Andric Op.setIsKill(false);
2390b57cec5SDimitry Andric }
2400b57cec5SDimitry Andric
2410b57cec5SDimitry Andric /// Returns true if it is unsafe to move a copy instruction from \p UseReg to
2420b57cec5SDimitry Andric /// \p DestReg over the instruction \p MI.
isUnsafeToMoveAcross(MachineInstr & MI,unsigned UseReg,unsigned DestReg,const TargetRegisterInfo * TRI)2430b57cec5SDimitry Andric static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
2440b57cec5SDimitry Andric unsigned DestReg,
2450b57cec5SDimitry Andric const TargetRegisterInfo *TRI) {
2460b57cec5SDimitry Andric return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
2470b57cec5SDimitry Andric MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
2480b57cec5SDimitry Andric MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
2490b57cec5SDimitry Andric MI.isMetaInstruction();
2500b57cec5SDimitry Andric }
2510b57cec5SDimitry Andric
UseReg(const MachineOperand & MO)2520b57cec5SDimitry Andric static Register UseReg(const MachineOperand& MO) {
2530b57cec5SDimitry Andric return MO.isReg() ? MO.getReg() : Register();
2540b57cec5SDimitry Andric }
2550b57cec5SDimitry Andric
2560b57cec5SDimitry Andric /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
2570b57cec5SDimitry Andric /// that the two instructions can be paired in a combine.
isSafeToMoveTogether(MachineInstr & I1,MachineInstr & I2,unsigned I1DestReg,unsigned I2DestReg,bool & DoInsertAtI1)2580b57cec5SDimitry Andric bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
2590b57cec5SDimitry Andric MachineInstr &I2,
2600b57cec5SDimitry Andric unsigned I1DestReg,
2610b57cec5SDimitry Andric unsigned I2DestReg,
2620b57cec5SDimitry Andric bool &DoInsertAtI1) {
2638bcb0991SDimitry Andric Register I2UseReg = UseReg(I2.getOperand(1));
2640b57cec5SDimitry Andric
2650b57cec5SDimitry Andric // It is not safe to move I1 and I2 into one combine if I2 has a true
2660b57cec5SDimitry Andric // dependence on I1.
2670b57cec5SDimitry Andric if (I2UseReg && I1.modifiesRegister(I2UseReg, TRI))
2680b57cec5SDimitry Andric return false;
2690b57cec5SDimitry Andric
2700b57cec5SDimitry Andric bool isSafe = true;
2710b57cec5SDimitry Andric
2720b57cec5SDimitry Andric // First try to move I2 towards I1.
2730b57cec5SDimitry Andric {
2740b57cec5SDimitry Andric // A reverse_iterator instantiated like below starts before I2, and I1
2750b57cec5SDimitry Andric // respectively.
2760b57cec5SDimitry Andric // Look at instructions I in between I2 and (excluding) I1.
2775ffd83dbSDimitry Andric MachineBasicBlock::reverse_iterator I = ++I2.getIterator().getReverse();
2785ffd83dbSDimitry Andric MachineBasicBlock::reverse_iterator End = I1.getIterator().getReverse();
2790b57cec5SDimitry Andric // At 03 we got better results (dhrystone!) by being more conservative.
2800b57cec5SDimitry Andric if (!ShouldCombineAggressively)
2815ffd83dbSDimitry Andric End = ++I1.getIterator().getReverse();
2820b57cec5SDimitry Andric // If I2 kills its operand and we move I2 over an instruction that also
2830b57cec5SDimitry Andric // uses I2's use reg we need to modify that (first) instruction to now kill
2840b57cec5SDimitry Andric // this reg.
2850b57cec5SDimitry Andric unsigned KilledOperand = 0;
2860b57cec5SDimitry Andric if (I2.killsRegister(I2UseReg))
2870b57cec5SDimitry Andric KilledOperand = I2UseReg;
2880b57cec5SDimitry Andric MachineInstr *KillingInstr = nullptr;
2890b57cec5SDimitry Andric
2900b57cec5SDimitry Andric for (; I != End; ++I) {
2910b57cec5SDimitry Andric // If the intervening instruction I:
2920b57cec5SDimitry Andric // * modifies I2's use reg
2930b57cec5SDimitry Andric // * modifies I2's def reg
2940b57cec5SDimitry Andric // * reads I2's def reg
2950b57cec5SDimitry Andric // * or has unmodelled side effects
2960b57cec5SDimitry Andric // we can't move I2 across it.
2970b57cec5SDimitry Andric if (I->isDebugInstr())
2980b57cec5SDimitry Andric continue;
2990b57cec5SDimitry Andric
3000b57cec5SDimitry Andric if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
3010b57cec5SDimitry Andric isSafe = false;
3020b57cec5SDimitry Andric break;
3030b57cec5SDimitry Andric }
3040b57cec5SDimitry Andric
3050b57cec5SDimitry Andric // Update first use of the killed operand.
3060b57cec5SDimitry Andric if (!KillingInstr && KilledOperand &&
3070b57cec5SDimitry Andric I->readsRegister(KilledOperand, TRI))
3080b57cec5SDimitry Andric KillingInstr = &*I;
3090b57cec5SDimitry Andric }
3100b57cec5SDimitry Andric if (isSafe) {
3110b57cec5SDimitry Andric // Update the intermediate instruction to with the kill flag.
3120b57cec5SDimitry Andric if (KillingInstr) {
3130b57cec5SDimitry Andric bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
3140b57cec5SDimitry Andric (void)Added; // suppress compiler warning
3150b57cec5SDimitry Andric assert(Added && "Must successfully update kill flag");
3160b57cec5SDimitry Andric removeKillInfo(I2, KilledOperand);
3170b57cec5SDimitry Andric }
3180b57cec5SDimitry Andric DoInsertAtI1 = true;
3190b57cec5SDimitry Andric return true;
3200b57cec5SDimitry Andric }
3210b57cec5SDimitry Andric }
3220b57cec5SDimitry Andric
3230b57cec5SDimitry Andric // Try to move I1 towards I2.
3240b57cec5SDimitry Andric {
3250b57cec5SDimitry Andric // Look at instructions I in between I1 and (excluding) I2.
3260b57cec5SDimitry Andric MachineBasicBlock::iterator I(I1), End(I2);
3270b57cec5SDimitry Andric // At O3 we got better results (dhrystone) by being more conservative here.
3280b57cec5SDimitry Andric if (!ShouldCombineAggressively)
3290b57cec5SDimitry Andric End = std::next(MachineBasicBlock::iterator(I2));
3308bcb0991SDimitry Andric Register I1UseReg = UseReg(I1.getOperand(1));
3310b57cec5SDimitry Andric // Track killed operands. If we move across an instruction that kills our
3320b57cec5SDimitry Andric // operand, we need to update the kill information on the moved I1. It kills
3330b57cec5SDimitry Andric // the operand now.
3340b57cec5SDimitry Andric MachineInstr *KillingInstr = nullptr;
3350b57cec5SDimitry Andric unsigned KilledOperand = 0;
3360b57cec5SDimitry Andric
3370b57cec5SDimitry Andric while(++I != End) {
3380b57cec5SDimitry Andric MachineInstr &MI = *I;
3390b57cec5SDimitry Andric // If the intervening instruction MI:
3400b57cec5SDimitry Andric // * modifies I1's use reg
3410b57cec5SDimitry Andric // * modifies I1's def reg
3420b57cec5SDimitry Andric // * reads I1's def reg
3430b57cec5SDimitry Andric // * or has unmodelled side effects
3440b57cec5SDimitry Andric // We introduce this special case because llvm has no api to remove a
3450b57cec5SDimitry Andric // kill flag for a register (a removeRegisterKilled() analogous to
3460b57cec5SDimitry Andric // addRegisterKilled) that handles aliased register correctly.
3470b57cec5SDimitry Andric // * or has a killed aliased register use of I1's use reg
3480b57cec5SDimitry Andric // %d4 = A2_tfrpi 16
3490b57cec5SDimitry Andric // %r6 = A2_tfr %r9
3500b57cec5SDimitry Andric // %r8 = KILL %r8, implicit killed %d4
3510b57cec5SDimitry Andric // If we want to move R6 = across the KILL instruction we would have
3520b57cec5SDimitry Andric // to remove the implicit killed %d4 operand. For now, we are
3530b57cec5SDimitry Andric // conservative and disallow the move.
3540b57cec5SDimitry Andric // we can't move I1 across it.
3550b57cec5SDimitry Andric if (MI.isDebugInstr()) {
3560b57cec5SDimitry Andric if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
3570b57cec5SDimitry Andric DbgMItoMove.push_back(&MI);
3580b57cec5SDimitry Andric continue;
3590b57cec5SDimitry Andric }
3600b57cec5SDimitry Andric
3610b57cec5SDimitry Andric if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) ||
3620b57cec5SDimitry Andric // Check for an aliased register kill. Bail out if we see one.
3630b57cec5SDimitry Andric (!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI)))
3640b57cec5SDimitry Andric return false;
3650b57cec5SDimitry Andric
3660b57cec5SDimitry Andric // Check for an exact kill (registers match).
3670b57cec5SDimitry Andric if (I1UseReg && MI.killsRegister(I1UseReg)) {
3680b57cec5SDimitry Andric assert(!KillingInstr && "Should only see one killing instruction");
3690b57cec5SDimitry Andric KilledOperand = I1UseReg;
3700b57cec5SDimitry Andric KillingInstr = &MI;
3710b57cec5SDimitry Andric }
3720b57cec5SDimitry Andric }
3730b57cec5SDimitry Andric if (KillingInstr) {
3740b57cec5SDimitry Andric removeKillInfo(*KillingInstr, KilledOperand);
3750b57cec5SDimitry Andric // Update I1 to set the kill flag. This flag will later be picked up by
3760b57cec5SDimitry Andric // the new COMBINE instruction.
3770b57cec5SDimitry Andric bool Added = I1.addRegisterKilled(KilledOperand, TRI);
3780b57cec5SDimitry Andric (void)Added; // suppress compiler warning
3790b57cec5SDimitry Andric assert(Added && "Must successfully update kill flag");
3800b57cec5SDimitry Andric }
3810b57cec5SDimitry Andric DoInsertAtI1 = false;
3820b57cec5SDimitry Andric }
3830b57cec5SDimitry Andric
3840b57cec5SDimitry Andric return true;
3850b57cec5SDimitry Andric }
3860b57cec5SDimitry Andric
3870b57cec5SDimitry Andric /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
3880b57cec5SDimitry Andric /// newified. (A use of a 64 bit register define can not be newified)
3890b57cec5SDimitry Andric void
findPotentialNewifiableTFRs(MachineBasicBlock & BB)3900b57cec5SDimitry Andric HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
3910b57cec5SDimitry Andric DenseMap<unsigned, MachineInstr *> LastDef;
3920b57cec5SDimitry Andric for (MachineInstr &MI : BB) {
3930b57cec5SDimitry Andric if (MI.isDebugInstr())
3940b57cec5SDimitry Andric continue;
3950b57cec5SDimitry Andric
3960b57cec5SDimitry Andric // Mark TFRs that feed a potential new value store as such.
3970b57cec5SDimitry Andric if (TII->mayBeNewStore(MI)) {
3980b57cec5SDimitry Andric // Look for uses of TFR instructions.
3994824e7fdSDimitry Andric for (const MachineOperand &Op : MI.operands()) {
4000b57cec5SDimitry Andric // Skip over anything except register uses.
4010b57cec5SDimitry Andric if (!Op.isReg() || !Op.isUse() || !Op.getReg())
4020b57cec5SDimitry Andric continue;
4030b57cec5SDimitry Andric
4040b57cec5SDimitry Andric // Look for the defining instruction.
4058bcb0991SDimitry Andric Register Reg = Op.getReg();
4060b57cec5SDimitry Andric MachineInstr *DefInst = LastDef[Reg];
4070b57cec5SDimitry Andric if (!DefInst)
4080b57cec5SDimitry Andric continue;
4090b57cec5SDimitry Andric if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
4100b57cec5SDimitry Andric continue;
4110b57cec5SDimitry Andric
4120b57cec5SDimitry Andric // Only close newifiable stores should influence the decision.
4130b57cec5SDimitry Andric // Ignore the debug instructions in between.
4140b57cec5SDimitry Andric MachineBasicBlock::iterator It(DefInst);
4150b57cec5SDimitry Andric unsigned NumInstsToDef = 0;
4160b57cec5SDimitry Andric while (&*It != &MI) {
4170b57cec5SDimitry Andric if (!It->isDebugInstr())
4180b57cec5SDimitry Andric ++NumInstsToDef;
4190b57cec5SDimitry Andric ++It;
4200b57cec5SDimitry Andric }
4210b57cec5SDimitry Andric
4220b57cec5SDimitry Andric if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
4230b57cec5SDimitry Andric continue;
4240b57cec5SDimitry Andric
4250b57cec5SDimitry Andric PotentiallyNewifiableTFR.insert(DefInst);
4260b57cec5SDimitry Andric }
4270b57cec5SDimitry Andric // Skip to next instruction.
4280b57cec5SDimitry Andric continue;
4290b57cec5SDimitry Andric }
4300b57cec5SDimitry Andric
4310b57cec5SDimitry Andric // Put instructions that last defined integer or double registers into the
4320b57cec5SDimitry Andric // map.
4330b57cec5SDimitry Andric for (MachineOperand &Op : MI.operands()) {
4340b57cec5SDimitry Andric if (Op.isReg()) {
4350b57cec5SDimitry Andric if (!Op.isDef() || !Op.getReg())
4360b57cec5SDimitry Andric continue;
4378bcb0991SDimitry Andric Register Reg = Op.getReg();
4380b57cec5SDimitry Andric if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
43906c3fb27SDimitry Andric for (MCPhysReg SubReg : TRI->subregs(Reg))
44006c3fb27SDimitry Andric LastDef[SubReg] = &MI;
4410b57cec5SDimitry Andric } else if (Hexagon::IntRegsRegClass.contains(Reg))
4420b57cec5SDimitry Andric LastDef[Reg] = &MI;
4430b57cec5SDimitry Andric } else if (Op.isRegMask()) {
4440b57cec5SDimitry Andric for (unsigned Reg : Hexagon::IntRegsRegClass)
4450b57cec5SDimitry Andric if (Op.clobbersPhysReg(Reg))
4460b57cec5SDimitry Andric LastDef[Reg] = &MI;
4470b57cec5SDimitry Andric }
4480b57cec5SDimitry Andric }
4490b57cec5SDimitry Andric }
4500b57cec5SDimitry Andric }
4510b57cec5SDimitry Andric
runOnMachineFunction(MachineFunction & MF)4520b57cec5SDimitry Andric bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
4530b57cec5SDimitry Andric if (skipFunction(MF.getFunction()))
4540b57cec5SDimitry Andric return false;
4550b57cec5SDimitry Andric
4560b57cec5SDimitry Andric if (IsCombinesDisabled) return false;
4570b57cec5SDimitry Andric
4580b57cec5SDimitry Andric bool HasChanged = false;
4590b57cec5SDimitry Andric
4600b57cec5SDimitry Andric // Get target info.
4610b57cec5SDimitry Andric ST = &MF.getSubtarget<HexagonSubtarget>();
4620b57cec5SDimitry Andric TRI = ST->getRegisterInfo();
4630b57cec5SDimitry Andric TII = ST->getInstrInfo();
4640b57cec5SDimitry Andric
4650b57cec5SDimitry Andric const Function &F = MF.getFunction();
4660b57cec5SDimitry Andric bool OptForSize = F.hasFnAttribute(Attribute::OptimizeForSize);
4670b57cec5SDimitry Andric
4680b57cec5SDimitry Andric // Combine aggressively (for code size)
4690b57cec5SDimitry Andric ShouldCombineAggressively =
4705f757f3fSDimitry Andric MF.getTarget().getOptLevel() <= CodeGenOptLevel::Default;
4710b57cec5SDimitry Andric
4725ffd83dbSDimitry Andric // Disable CONST64 for tiny core since it takes a LD resource.
4735ffd83dbSDimitry Andric if (!OptForSize && ST->isTinyCore())
4745ffd83dbSDimitry Andric IsConst64Disabled = true;
4755ffd83dbSDimitry Andric
4760b57cec5SDimitry Andric // Traverse basic blocks.
4774824e7fdSDimitry Andric for (MachineBasicBlock &MBB : MF) {
4780b57cec5SDimitry Andric PotentiallyNewifiableTFR.clear();
4794824e7fdSDimitry Andric findPotentialNewifiableTFRs(MBB);
4800b57cec5SDimitry Andric
4810b57cec5SDimitry Andric // Traverse instructions in basic block.
4824824e7fdSDimitry Andric for (MachineBasicBlock::iterator MI = MBB.begin(), End = MBB.end();
4830b57cec5SDimitry Andric MI != End;) {
4840b57cec5SDimitry Andric MachineInstr &I1 = *MI++;
4850b57cec5SDimitry Andric
4860b57cec5SDimitry Andric if (I1.isDebugInstr())
4870b57cec5SDimitry Andric continue;
4880b57cec5SDimitry Andric
4890b57cec5SDimitry Andric // Don't combine a TFR whose user could be newified (instructions that
4900b57cec5SDimitry Andric // define double registers can not be newified - Programmer's Ref Manual
4910b57cec5SDimitry Andric // 5.4.2 New-value stores).
4920b57cec5SDimitry Andric if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&I1))
4930b57cec5SDimitry Andric continue;
4940b57cec5SDimitry Andric
4950b57cec5SDimitry Andric // Ignore instructions that are not combinable.
4960b57cec5SDimitry Andric if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
4970b57cec5SDimitry Andric continue;
4980b57cec5SDimitry Andric
4990b57cec5SDimitry Andric // Find a second instruction that can be merged into a combine
5000b57cec5SDimitry Andric // instruction. In addition, also find all the debug instructions that
5010b57cec5SDimitry Andric // need to be moved along with it.
5020b57cec5SDimitry Andric bool DoInsertAtI1 = false;
5030b57cec5SDimitry Andric DbgMItoMove.clear();
5040b57cec5SDimitry Andric MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize);
5050b57cec5SDimitry Andric if (I2) {
5060b57cec5SDimitry Andric HasChanged = true;
5070b57cec5SDimitry Andric combine(I1, *I2, MI, DoInsertAtI1, OptForSize);
5080b57cec5SDimitry Andric }
5090b57cec5SDimitry Andric }
5100b57cec5SDimitry Andric }
5110b57cec5SDimitry Andric
5120b57cec5SDimitry Andric return HasChanged;
5130b57cec5SDimitry Andric }
5140b57cec5SDimitry Andric
5150b57cec5SDimitry Andric /// findPairable - Returns an instruction that can be merged with \p I1 into a
5160b57cec5SDimitry Andric /// COMBINE instruction or 0 if no such instruction can be found. Returns true
5170b57cec5SDimitry Andric /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
5180b57cec5SDimitry Andric /// false if the combine must be inserted at the returned instruction.
findPairable(MachineInstr & I1,bool & DoInsertAtI1,bool AllowC64)5190b57cec5SDimitry Andric MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
5200b57cec5SDimitry Andric bool &DoInsertAtI1,
5210b57cec5SDimitry Andric bool AllowC64) {
5220b57cec5SDimitry Andric MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
5230b57cec5SDimitry Andric while (I2 != I1.getParent()->end() && I2->isDebugInstr())
5240b57cec5SDimitry Andric ++I2;
5250b57cec5SDimitry Andric
5268bcb0991SDimitry Andric Register I1DestReg = I1.getOperand(0).getReg();
5270b57cec5SDimitry Andric
5280b57cec5SDimitry Andric for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
5290b57cec5SDimitry Andric ++I2) {
5300b57cec5SDimitry Andric // Bail out early if we see a second definition of I1DestReg.
5310b57cec5SDimitry Andric if (I2->modifiesRegister(I1DestReg, TRI))
5320b57cec5SDimitry Andric break;
5330b57cec5SDimitry Andric
5340b57cec5SDimitry Andric // Ignore non-combinable instructions.
5350b57cec5SDimitry Andric if (!isCombinableInstType(*I2, TII, ShouldCombineAggressively))
5360b57cec5SDimitry Andric continue;
5370b57cec5SDimitry Andric
5380b57cec5SDimitry Andric // Don't combine a TFR whose user could be newified.
5390b57cec5SDimitry Andric if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&*I2))
5400b57cec5SDimitry Andric continue;
5410b57cec5SDimitry Andric
5428bcb0991SDimitry Andric Register I2DestReg = I2->getOperand(0).getReg();
5430b57cec5SDimitry Andric
5440b57cec5SDimitry Andric // Check that registers are adjacent and that the first destination register
5450b57cec5SDimitry Andric // is even.
5460b57cec5SDimitry Andric bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
5470b57cec5SDimitry Andric bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
5480b57cec5SDimitry Andric unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
5490b57cec5SDimitry Andric if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
5500b57cec5SDimitry Andric continue;
5510b57cec5SDimitry Andric
5520b57cec5SDimitry Andric // Check that the two instructions are combinable.
5530b57cec5SDimitry Andric // The order matters because in a A2_tfrsi we might can encode a int8 as
5540b57cec5SDimitry Andric // the hi reg operand but only a uint6 as the low reg operand.
5550b57cec5SDimitry Andric if ((IsI2LowReg && !areCombinableOperations(TRI, I1, *I2, AllowC64)) ||
5560b57cec5SDimitry Andric (IsI1LowReg && !areCombinableOperations(TRI, *I2, I1, AllowC64)))
5570b57cec5SDimitry Andric break;
5580b57cec5SDimitry Andric
5590b57cec5SDimitry Andric if (isSafeToMoveTogether(I1, *I2, I1DestReg, I2DestReg, DoInsertAtI1))
5600b57cec5SDimitry Andric return &*I2;
5610b57cec5SDimitry Andric
5620b57cec5SDimitry Andric // Not safe. Stop searching.
5630b57cec5SDimitry Andric break;
5640b57cec5SDimitry Andric }
5650b57cec5SDimitry Andric return nullptr;
5660b57cec5SDimitry Andric }
5670b57cec5SDimitry Andric
combine(MachineInstr & I1,MachineInstr & I2,MachineBasicBlock::iterator & MI,bool DoInsertAtI1,bool OptForSize)5680b57cec5SDimitry Andric void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
5690b57cec5SDimitry Andric MachineBasicBlock::iterator &MI,
5700b57cec5SDimitry Andric bool DoInsertAtI1, bool OptForSize) {
5710b57cec5SDimitry Andric // We are going to delete I2. If MI points to I2 advance it to the next
5720b57cec5SDimitry Andric // instruction.
5730b57cec5SDimitry Andric if (MI == I2.getIterator())
5740b57cec5SDimitry Andric ++MI;
5750b57cec5SDimitry Andric
5760b57cec5SDimitry Andric // Figure out whether I1 or I2 goes into the lowreg part.
5778bcb0991SDimitry Andric Register I1DestReg = I1.getOperand(0).getReg();
5788bcb0991SDimitry Andric Register I2DestReg = I2.getOperand(0).getReg();
5790b57cec5SDimitry Andric bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
5800b57cec5SDimitry Andric unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
5810b57cec5SDimitry Andric unsigned SubLo;
5820b57cec5SDimitry Andric
5830b57cec5SDimitry Andric const TargetRegisterClass *SuperRC = nullptr;
5840b57cec5SDimitry Andric if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
5850b57cec5SDimitry Andric SuperRC = &Hexagon::DoubleRegsRegClass;
5860b57cec5SDimitry Andric SubLo = Hexagon::isub_lo;
5870b57cec5SDimitry Andric } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {
5880b57cec5SDimitry Andric assert(ST->useHVXOps());
5890b57cec5SDimitry Andric SuperRC = &Hexagon::HvxWRRegClass;
5900b57cec5SDimitry Andric SubLo = Hexagon::vsub_lo;
5910b57cec5SDimitry Andric } else
5920b57cec5SDimitry Andric llvm_unreachable("Unexpected register class");
5930b57cec5SDimitry Andric
5940b57cec5SDimitry Andric // Get the double word register.
5950b57cec5SDimitry Andric unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
5960b57cec5SDimitry Andric assert(DoubleRegDest != 0 && "Expect a valid register");
5970b57cec5SDimitry Andric
5980b57cec5SDimitry Andric // Setup source operands.
5990b57cec5SDimitry Andric MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
6000b57cec5SDimitry Andric MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
6010b57cec5SDimitry Andric
6020b57cec5SDimitry Andric // Figure out which source is a register and which a constant.
6030b57cec5SDimitry Andric bool IsHiReg = HiOperand.isReg();
6040b57cec5SDimitry Andric bool IsLoReg = LoOperand.isReg();
6050b57cec5SDimitry Andric
6060b57cec5SDimitry Andric // There is a combine of two constant extended values into CONST64.
6070b57cec5SDimitry Andric bool IsC64 = OptForSize && LoOperand.isImm() && HiOperand.isImm() &&
6080b57cec5SDimitry Andric isGreaterThanNBitTFRI<16>(I1) && isGreaterThanNBitTFRI<16>(I2);
6090b57cec5SDimitry Andric
6100b57cec5SDimitry Andric MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
6110b57cec5SDimitry Andric // Emit combine.
6120b57cec5SDimitry Andric if (IsHiReg && IsLoReg)
6130b57cec5SDimitry Andric emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
6140b57cec5SDimitry Andric else if (IsHiReg)
6150b57cec5SDimitry Andric emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
6160b57cec5SDimitry Andric else if (IsLoReg)
6170b57cec5SDimitry Andric emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
6180b57cec5SDimitry Andric else if (IsC64 && !IsConst64Disabled)
6190b57cec5SDimitry Andric emitConst64(InsertPt, DoubleRegDest, HiOperand, LoOperand);
6200b57cec5SDimitry Andric else
6210b57cec5SDimitry Andric emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
6220b57cec5SDimitry Andric
6230b57cec5SDimitry Andric // Move debug instructions along with I1 if it's being
6240b57cec5SDimitry Andric // moved towards I2.
6250b57cec5SDimitry Andric if (!DoInsertAtI1 && DbgMItoMove.size() != 0) {
6260b57cec5SDimitry Andric // Insert debug instructions at the new location before I2.
6270b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
628bdd1243dSDimitry Andric for (auto *NewMI : DbgMItoMove) {
6290b57cec5SDimitry Andric // If iterator MI is pointing to DEBUG_VAL, make sure
6300b57cec5SDimitry Andric // MI now points to next relevant instruction.
6310b57cec5SDimitry Andric if (NewMI == MI)
6320b57cec5SDimitry Andric ++MI;
6330b57cec5SDimitry Andric BB->splice(InsertPt, BB, NewMI);
6340b57cec5SDimitry Andric }
6350b57cec5SDimitry Andric }
6360b57cec5SDimitry Andric
6370b57cec5SDimitry Andric I1.eraseFromParent();
6380b57cec5SDimitry Andric I2.eraseFromParent();
6390b57cec5SDimitry Andric }
6400b57cec5SDimitry Andric
emitConst64(MachineBasicBlock::iterator & InsertPt,unsigned DoubleDestReg,MachineOperand & HiOperand,MachineOperand & LoOperand)6410b57cec5SDimitry Andric void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt,
6420b57cec5SDimitry Andric unsigned DoubleDestReg,
6430b57cec5SDimitry Andric MachineOperand &HiOperand,
6440b57cec5SDimitry Andric MachineOperand &LoOperand) {
6450b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << "Found a CONST64\n");
6460b57cec5SDimitry Andric
6470b57cec5SDimitry Andric DebugLoc DL = InsertPt->getDebugLoc();
6480b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
6490b57cec5SDimitry Andric assert(LoOperand.isImm() && HiOperand.isImm() &&
6500b57cec5SDimitry Andric "Both operands must be immediate");
6510b57cec5SDimitry Andric
6520b57cec5SDimitry Andric int64_t V = HiOperand.getImm();
6530b57cec5SDimitry Andric V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm());
6540b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
6550b57cec5SDimitry Andric .addImm(V);
6560b57cec5SDimitry Andric }
6570b57cec5SDimitry Andric
emitCombineII(MachineBasicBlock::iterator & InsertPt,unsigned DoubleDestReg,MachineOperand & HiOperand,MachineOperand & LoOperand)6580b57cec5SDimitry Andric void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
6590b57cec5SDimitry Andric unsigned DoubleDestReg,
6600b57cec5SDimitry Andric MachineOperand &HiOperand,
6610b57cec5SDimitry Andric MachineOperand &LoOperand) {
6620b57cec5SDimitry Andric DebugLoc DL = InsertPt->getDebugLoc();
6630b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
6640b57cec5SDimitry Andric
6650b57cec5SDimitry Andric // Handle globals.
6660b57cec5SDimitry Andric if (HiOperand.isGlobal()) {
6670b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
6680b57cec5SDimitry Andric .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
6690b57cec5SDimitry Andric HiOperand.getTargetFlags())
6700b57cec5SDimitry Andric .addImm(LoOperand.getImm());
6710b57cec5SDimitry Andric return;
6720b57cec5SDimitry Andric }
6730b57cec5SDimitry Andric if (LoOperand.isGlobal()) {
6740b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
6750b57cec5SDimitry Andric .addImm(HiOperand.getImm())
6760b57cec5SDimitry Andric .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
6770b57cec5SDimitry Andric LoOperand.getTargetFlags());
6780b57cec5SDimitry Andric return;
6790b57cec5SDimitry Andric }
6800b57cec5SDimitry Andric
6810b57cec5SDimitry Andric // Handle block addresses.
6820b57cec5SDimitry Andric if (HiOperand.isBlockAddress()) {
6830b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
6840b57cec5SDimitry Andric .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
6850b57cec5SDimitry Andric HiOperand.getTargetFlags())
6860b57cec5SDimitry Andric .addImm(LoOperand.getImm());
6870b57cec5SDimitry Andric return;
6880b57cec5SDimitry Andric }
6890b57cec5SDimitry Andric if (LoOperand.isBlockAddress()) {
6900b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
6910b57cec5SDimitry Andric .addImm(HiOperand.getImm())
6920b57cec5SDimitry Andric .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
6930b57cec5SDimitry Andric LoOperand.getTargetFlags());
6940b57cec5SDimitry Andric return;
6950b57cec5SDimitry Andric }
6960b57cec5SDimitry Andric
6970b57cec5SDimitry Andric // Handle jump tables.
6980b57cec5SDimitry Andric if (HiOperand.isJTI()) {
6990b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
7000b57cec5SDimitry Andric .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
7010b57cec5SDimitry Andric .addImm(LoOperand.getImm());
7020b57cec5SDimitry Andric return;
7030b57cec5SDimitry Andric }
7040b57cec5SDimitry Andric if (LoOperand.isJTI()) {
7050b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
7060b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7070b57cec5SDimitry Andric .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
7080b57cec5SDimitry Andric return;
7090b57cec5SDimitry Andric }
7100b57cec5SDimitry Andric
7110b57cec5SDimitry Andric // Handle constant pools.
7120b57cec5SDimitry Andric if (HiOperand.isCPI()) {
7130b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
7140b57cec5SDimitry Andric .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
7150b57cec5SDimitry Andric HiOperand.getTargetFlags())
7160b57cec5SDimitry Andric .addImm(LoOperand.getImm());
7170b57cec5SDimitry Andric return;
7180b57cec5SDimitry Andric }
7190b57cec5SDimitry Andric if (LoOperand.isCPI()) {
7200b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
7210b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7220b57cec5SDimitry Andric .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
7230b57cec5SDimitry Andric LoOperand.getTargetFlags());
7240b57cec5SDimitry Andric return;
7250b57cec5SDimitry Andric }
7260b57cec5SDimitry Andric
7270b57cec5SDimitry Andric // First preference should be given to Hexagon::A2_combineii instruction
7280b57cec5SDimitry Andric // as it can include U6 (in Hexagon::A4_combineii) as well.
7290b57cec5SDimitry Andric // In this instruction, HiOperand is const extended, if required.
7300b57cec5SDimitry Andric if (isInt<8>(LoOperand.getImm())) {
7310b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
7320b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7330b57cec5SDimitry Andric .addImm(LoOperand.getImm());
7340b57cec5SDimitry Andric return;
7350b57cec5SDimitry Andric }
7360b57cec5SDimitry Andric
7370b57cec5SDimitry Andric // In this instruction, LoOperand is const extended, if required.
7380b57cec5SDimitry Andric if (isInt<8>(HiOperand.getImm())) {
7390b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
7400b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7410b57cec5SDimitry Andric .addImm(LoOperand.getImm());
7420b57cec5SDimitry Andric return;
7430b57cec5SDimitry Andric }
7440b57cec5SDimitry Andric
7450b57cec5SDimitry Andric // Insert new combine instruction.
7460b57cec5SDimitry Andric // DoubleRegDest = combine #HiImm, #LoImm
7470b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
7480b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7490b57cec5SDimitry Andric .addImm(LoOperand.getImm());
7500b57cec5SDimitry Andric }
7510b57cec5SDimitry Andric
emitCombineIR(MachineBasicBlock::iterator & InsertPt,unsigned DoubleDestReg,MachineOperand & HiOperand,MachineOperand & LoOperand)7520b57cec5SDimitry Andric void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
7530b57cec5SDimitry Andric unsigned DoubleDestReg,
7540b57cec5SDimitry Andric MachineOperand &HiOperand,
7550b57cec5SDimitry Andric MachineOperand &LoOperand) {
7568bcb0991SDimitry Andric Register LoReg = LoOperand.getReg();
7570b57cec5SDimitry Andric unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
7580b57cec5SDimitry Andric
7590b57cec5SDimitry Andric DebugLoc DL = InsertPt->getDebugLoc();
7600b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
7610b57cec5SDimitry Andric
7620b57cec5SDimitry Andric // Handle globals.
7630b57cec5SDimitry Andric if (HiOperand.isGlobal()) {
7640b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
7650b57cec5SDimitry Andric .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
7660b57cec5SDimitry Andric HiOperand.getTargetFlags())
7670b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
7680b57cec5SDimitry Andric return;
7690b57cec5SDimitry Andric }
7700b57cec5SDimitry Andric // Handle block addresses.
7710b57cec5SDimitry Andric if (HiOperand.isBlockAddress()) {
7720b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
7730b57cec5SDimitry Andric .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
7740b57cec5SDimitry Andric HiOperand.getTargetFlags())
7750b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
7760b57cec5SDimitry Andric return;
7770b57cec5SDimitry Andric }
7780b57cec5SDimitry Andric // Handle jump tables.
7790b57cec5SDimitry Andric if (HiOperand.isJTI()) {
7800b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
7810b57cec5SDimitry Andric .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
7820b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
7830b57cec5SDimitry Andric return;
7840b57cec5SDimitry Andric }
7850b57cec5SDimitry Andric // Handle constant pools.
7860b57cec5SDimitry Andric if (HiOperand.isCPI()) {
7870b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
7880b57cec5SDimitry Andric .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
7890b57cec5SDimitry Andric HiOperand.getTargetFlags())
7900b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
7910b57cec5SDimitry Andric return;
7920b57cec5SDimitry Andric }
7930b57cec5SDimitry Andric // Insert new combine instruction.
7940b57cec5SDimitry Andric // DoubleRegDest = combine #HiImm, LoReg
7950b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
7960b57cec5SDimitry Andric .addImm(HiOperand.getImm())
7970b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
7980b57cec5SDimitry Andric }
7990b57cec5SDimitry Andric
emitCombineRI(MachineBasicBlock::iterator & InsertPt,unsigned DoubleDestReg,MachineOperand & HiOperand,MachineOperand & LoOperand)8000b57cec5SDimitry Andric void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
8010b57cec5SDimitry Andric unsigned DoubleDestReg,
8020b57cec5SDimitry Andric MachineOperand &HiOperand,
8030b57cec5SDimitry Andric MachineOperand &LoOperand) {
8040b57cec5SDimitry Andric unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
8058bcb0991SDimitry Andric Register HiReg = HiOperand.getReg();
8060b57cec5SDimitry Andric
8070b57cec5SDimitry Andric DebugLoc DL = InsertPt->getDebugLoc();
8080b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
8090b57cec5SDimitry Andric
8100b57cec5SDimitry Andric // Handle global.
8110b57cec5SDimitry Andric if (LoOperand.isGlobal()) {
8120b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
8130b57cec5SDimitry Andric .addReg(HiReg, HiRegKillFlag)
8140b57cec5SDimitry Andric .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
8150b57cec5SDimitry Andric LoOperand.getTargetFlags());
8160b57cec5SDimitry Andric return;
8170b57cec5SDimitry Andric }
8180b57cec5SDimitry Andric // Handle block addresses.
8190b57cec5SDimitry Andric if (LoOperand.isBlockAddress()) {
8200b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
8210b57cec5SDimitry Andric .addReg(HiReg, HiRegKillFlag)
8220b57cec5SDimitry Andric .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
8230b57cec5SDimitry Andric LoOperand.getTargetFlags());
8240b57cec5SDimitry Andric return;
8250b57cec5SDimitry Andric }
8260b57cec5SDimitry Andric // Handle jump tables.
8270b57cec5SDimitry Andric if (LoOperand.isJTI()) {
8280b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
8290b57cec5SDimitry Andric .addReg(HiOperand.getReg(), HiRegKillFlag)
8300b57cec5SDimitry Andric .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
8310b57cec5SDimitry Andric return;
8320b57cec5SDimitry Andric }
8330b57cec5SDimitry Andric // Handle constant pools.
8340b57cec5SDimitry Andric if (LoOperand.isCPI()) {
8350b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
8360b57cec5SDimitry Andric .addReg(HiOperand.getReg(), HiRegKillFlag)
8370b57cec5SDimitry Andric .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
8380b57cec5SDimitry Andric LoOperand.getTargetFlags());
8390b57cec5SDimitry Andric return;
8400b57cec5SDimitry Andric }
8410b57cec5SDimitry Andric
8420b57cec5SDimitry Andric // Insert new combine instruction.
8430b57cec5SDimitry Andric // DoubleRegDest = combine HiReg, #LoImm
8440b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
8450b57cec5SDimitry Andric .addReg(HiReg, HiRegKillFlag)
8460b57cec5SDimitry Andric .addImm(LoOperand.getImm());
8470b57cec5SDimitry Andric }
8480b57cec5SDimitry Andric
emitCombineRR(MachineBasicBlock::iterator & InsertPt,unsigned DoubleDestReg,MachineOperand & HiOperand,MachineOperand & LoOperand)8490b57cec5SDimitry Andric void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
8500b57cec5SDimitry Andric unsigned DoubleDestReg,
8510b57cec5SDimitry Andric MachineOperand &HiOperand,
8520b57cec5SDimitry Andric MachineOperand &LoOperand) {
8530b57cec5SDimitry Andric unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
8540b57cec5SDimitry Andric unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
8558bcb0991SDimitry Andric Register LoReg = LoOperand.getReg();
8568bcb0991SDimitry Andric Register HiReg = HiOperand.getReg();
8570b57cec5SDimitry Andric
8580b57cec5SDimitry Andric DebugLoc DL = InsertPt->getDebugLoc();
8590b57cec5SDimitry Andric MachineBasicBlock *BB = InsertPt->getParent();
8600b57cec5SDimitry Andric
8610b57cec5SDimitry Andric // Insert new combine instruction.
8620b57cec5SDimitry Andric // DoubleRegDest = combine HiReg, LoReg
8630b57cec5SDimitry Andric unsigned NewOpc;
8640b57cec5SDimitry Andric if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
8650b57cec5SDimitry Andric NewOpc = Hexagon::A2_combinew;
8660b57cec5SDimitry Andric } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {
8670b57cec5SDimitry Andric assert(ST->useHVXOps());
8680b57cec5SDimitry Andric NewOpc = Hexagon::V6_vcombine;
8690b57cec5SDimitry Andric } else
8700b57cec5SDimitry Andric llvm_unreachable("Unexpected register");
8710b57cec5SDimitry Andric
8720b57cec5SDimitry Andric BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
8730b57cec5SDimitry Andric .addReg(HiReg, HiRegKillFlag)
8740b57cec5SDimitry Andric .addReg(LoReg, LoRegKillFlag);
8750b57cec5SDimitry Andric }
8760b57cec5SDimitry Andric
createHexagonCopyToCombine()8770b57cec5SDimitry Andric FunctionPass *llvm::createHexagonCopyToCombine() {
8780b57cec5SDimitry Andric return new HexagonCopyToCombine();
8790b57cec5SDimitry Andric }
880