10b57cec5SDimitry Andric //===--- HexagonHazardRecognizer.h - Hexagon Post RA Hazard Recognizer ----===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // This file defines the hazard recognizer for scheduling on Hexagon. 90b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 100b57cec5SDimitry Andric 110b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H 120b57cec5SDimitry Andric #define LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #include "HexagonInstrInfo.h" 150b57cec5SDimitry Andric #include "HexagonSubtarget.h" 160b57cec5SDimitry Andric #include "llvm/ADT/SmallSet.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/DFAPacketizer.h" 180b57cec5SDimitry Andric #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric namespace llvm { 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric class HexagonHazardRecognizer : public ScheduleHazardRecognizer { 230b57cec5SDimitry Andric DFAPacketizer *Resources; 240b57cec5SDimitry Andric const HexagonInstrInfo *TII; 250b57cec5SDimitry Andric unsigned PacketNum = 0; 260b57cec5SDimitry Andric // If the packet contains a potential dot cur instruction. This is 270b57cec5SDimitry Andric // used for the scheduling priority function. 280b57cec5SDimitry Andric SUnit *UsesDotCur = nullptr; 290b57cec5SDimitry Andric // The packet number when a dor cur is emitted. If its use is not generated 300b57cec5SDimitry Andric // in the same packet, then try to wait another cycle before emitting. 310b57cec5SDimitry Andric int DotCurPNum = -1; 320b57cec5SDimitry Andric // Does the packet contain a load. Used to restrict another load, if possible. 330b57cec5SDimitry Andric bool UsesLoad = false; 340b57cec5SDimitry Andric // Check if we should prefer a vector store that will become a .new version. 350b57cec5SDimitry Andric // The .new store uses different resources than a normal store, and the 360b57cec5SDimitry Andric // packetizer will not generate the .new if the regular store does not have 370b57cec5SDimitry Andric // resources available (even if the .new version does). To help, the schedule 380b57cec5SDimitry Andric // attempts to schedule the .new as soon as possible in the packet. 390b57cec5SDimitry Andric SUnit *PrefVectorStoreNew = nullptr; 400b57cec5SDimitry Andric // The set of registers defined by instructions in the current packet. 410b57cec5SDimitry Andric SmallSet<unsigned, 8> RegDefs; 420b57cec5SDimitry Andric 4304eeddc0SDimitry Andric // Return true if the instruction is a store that is converted to a new value 4404eeddc0SDimitry Andric // store because its value is defined in the same packet. 4504eeddc0SDimitry Andric bool isNewStore(MachineInstr &MI); 4604eeddc0SDimitry Andric 470b57cec5SDimitry Andric public: HexagonHazardRecognizer(const InstrItineraryData * II,const HexagonInstrInfo * HII,const HexagonSubtarget & ST)480b57cec5SDimitry Andric HexagonHazardRecognizer(const InstrItineraryData *II, 490b57cec5SDimitry Andric const HexagonInstrInfo *HII, 500b57cec5SDimitry Andric const HexagonSubtarget &ST) 510b57cec5SDimitry Andric : Resources(ST.createDFAPacketizer(II)), TII(HII) { } 520b57cec5SDimitry Andric ~HexagonHazardRecognizer()530b57cec5SDimitry Andric ~HexagonHazardRecognizer() override { 540b57cec5SDimitry Andric if (Resources) 550b57cec5SDimitry Andric delete Resources; 560b57cec5SDimitry Andric } 570b57cec5SDimitry Andric 580b57cec5SDimitry Andric /// This callback is invoked when a new block of instructions is about to be 590b57cec5SDimitry Andric /// scheduled. The hazard state is set to an initialized state. 600b57cec5SDimitry Andric void Reset() override; 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric /// Return the hazard type of emitting this node. There are three 630b57cec5SDimitry Andric /// possible results. Either: 640b57cec5SDimitry Andric /// * NoHazard: it is legal to issue this instruction on this cycle. 650b57cec5SDimitry Andric /// * Hazard: issuing this instruction would stall the machine. If some 660b57cec5SDimitry Andric /// other instruction is available, issue it first. 670b57cec5SDimitry Andric HazardType getHazardType(SUnit *SU, int stalls) override; 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric /// This callback is invoked when an instruction is emitted to be scheduled, 700b57cec5SDimitry Andric /// to advance the hazard state. 710b57cec5SDimitry Andric void EmitInstruction(SUnit *) override; 720b57cec5SDimitry Andric 730b57cec5SDimitry Andric /// This callback may be invoked if getHazardType returns NoHazard. If, even 740b57cec5SDimitry Andric /// though there is no hazard, it would be better to schedule another 750b57cec5SDimitry Andric /// available instruction, this callback should return true. 760b57cec5SDimitry Andric bool ShouldPreferAnother(SUnit *) override; 770b57cec5SDimitry Andric 780b57cec5SDimitry Andric /// This callback is invoked whenever the next top-down instruction to be 790b57cec5SDimitry Andric /// scheduled cannot issue in the current cycle, either because of latency 800b57cec5SDimitry Andric /// or resource conflicts. This should increment the internal state of the 810b57cec5SDimitry Andric /// hazard recognizer so that previously "Hazard" instructions will now not 820b57cec5SDimitry Andric /// be hazards. 830b57cec5SDimitry Andric void AdvanceCycle() override; 840b57cec5SDimitry Andric }; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric } // end namespace llvm 870b57cec5SDimitry Andric 880b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H 89