1def SDTVecBinOp:
2  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;
3
4def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
5  [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
6def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
7
8def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
9  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
10def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
11
12def SDTHexagonVSPLATW: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
13def HexagonVSPLATW: SDNode<"HexagonISD::VSPLATW", SDTHexagonVSPLATW>;
14
15def HwLen2: SDNodeXForm<imm, [{
16  const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
17  return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
18}]>;
19
20def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
21
22def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
23  (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
24
25def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
26  (V6_vandvrt
27    (V6_vor
28      (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),
29               (A2_tfrsi (HwLen2 (i32 0)))),  // Half the vector length
30      (V6_vpackeb (V6_vd0), (Q2V $Qt))),
31    (A2_tfrsi -1))>;
32
33def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
34def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
35
36def HexagonVZERO:      SDNode<"HexagonISD::VZERO",      SDTVecLeaf>;
37def HexagonQCAT:       SDNode<"HexagonISD::QCAT",       SDTVecBinOp>;
38def HexagonQTRUE:      SDNode<"HexagonISD::QTRUE",      SDTVecLeaf>;
39def HexagonQFALSE:     SDNode<"HexagonISD::QFALSE",     SDTVecLeaf>;
40
41def vzero:  PatFrag<(ops), (HexagonVZERO)>;
42def qtrue:  PatFrag<(ops), (HexagonQTRUE)>;
43def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
44def qcat:   PatFrag<(ops node:$Qs, node:$Qt),
45                    (HexagonQCAT node:$Qs, node:$Qt)>;
46
47def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
48
49def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb  $Vs)>;
50def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh  $Vs)>;
51def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
52def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
53
54def SplatB: SDNodeXForm<imm, [{
55  uint32_t V = N->getZExtValue();
56  assert(isUInt<8>(V));
57  uint32_t S = V << 24 | V << 16 | V << 8 | V;
58  return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
59}]>;
60
61def SplatH: SDNodeXForm<imm, [{
62  uint32_t V = N->getZExtValue();
63  assert(isUInt<16>(V));
64  return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
65}]>;
66
67def IsVecOff : PatLeaf<(i32 imm), [{
68  int32_t V = N->getSExtValue();
69  int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);
70  assert(isPowerOf2_32(VecSize));
71  if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)
72    return false;
73  int32_t L = Log2_32(VecSize);
74  return isInt<4>(V >> L);
75}]>;
76
77
78def alignedload: PatFrag<(ops node:$a), (load $a), [{
79  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
80}]>;
81
82def unalignedload: PatFrag<(ops node:$a), (load $a), [{
83  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
84}]>;
85
86def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
87  return isAlignedMemNode(dyn_cast<MemSDNode>(N));
88}]>;
89
90def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
91  return !isAlignedMemNode(dyn_cast<MemSDNode>(N));
92}]>;
93
94
95// HVX loads
96
97multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
98                     PatFrag ImmPred> {
99  def: Pat<(ResType (Load I32:$Rt)),
100           (MI I32:$Rt, 0)>;
101  def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
102           (MI I32:$Rt, imm:$s)>;
103  // The HVX selection code for shuffles can generate vector constants.
104  // Calling "Select" on the resulting loads from CP fails without these
105  // patterns.
106  def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
107           (MI (A2_tfrsi imm:$A), 0)>;
108  def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
109           (MI (C4_addipc imm:$A), 0)>;
110}
111
112multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,
113                      PatFrag ImmPred> {
114  let AddedComplexity = 50 in {
115    def: Pat<(ResType (Load (valignaddr I32:$Rt))),
116             (MI I32:$Rt, 0)>;
117    def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
118             (MI I32:$Rt, imm:$Off)>;
119  }
120  defm: HvxLd_pat<MI, Load, ResType, ImmPred>;
121}
122
123let Predicates = [UseHVX] in {
124  defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8,  IsVecOff>;
125  defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;
126  defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;
127
128  defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8,  IsVecOff>;
129  defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;
130  defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;
131
132  defm: HvxLd_pat<V6_vL32Ub_ai,  unalignedload, VecI8,  IsVecOff>;
133  defm: HvxLd_pat<V6_vL32Ub_ai,  unalignedload, VecI16, IsVecOff>;
134  defm: HvxLd_pat<V6_vL32Ub_ai,  unalignedload, VecI32, IsVecOff>;
135}
136
137// HVX stores
138
139multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
140                     PatFrag Value> {
141  def: Pat<(Store Value:$Vs, I32:$Rt),
142           (MI I32:$Rt, 0, Value:$Vs)>;
143  def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
144           (MI I32:$Rt, imm:$s, Value:$Vs)>;
145}
146
147let Predicates = [UseHVX] in {
148  defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI8>;
149  defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI16>;
150  defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, IsVecOff, HVI32>;
151
152  defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI8>;
153  defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI16>;
154  defm: HvxSt_pat<V6_vS32b_ai, alignedstore, IsVecOff, HVI32>;
155
156  defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI8>;
157  defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI16>;
158  defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, IsVecOff, HVI32>;
159}
160
161// Bitcasts between same-size vector types are no-ops, except for the
162// actual type change.
163let Predicates = [UseHVX] in {
164  defm: NopCast_pat<VecI8,   VecI16,  HvxVR>;
165  defm: NopCast_pat<VecI8,   VecI32,  HvxVR>;
166  defm: NopCast_pat<VecI16,  VecI32,  HvxVR>;
167
168  defm: NopCast_pat<VecPI8,  VecPI16, HvxWR>;
169  defm: NopCast_pat<VecPI8,  VecPI32, HvxWR>;
170  defm: NopCast_pat<VecPI16, VecPI32, HvxWR>;
171}
172
173let Predicates = [UseHVX] in {
174  def: Pat<(VecI8   vzero), (V6_vd0)>;
175  def: Pat<(VecI16  vzero), (V6_vd0)>;
176  def: Pat<(VecI32  vzero), (V6_vd0)>;
177  def: Pat<(VecPI8  vzero), (PS_vdd0)>;
178  def: Pat<(VecPI16 vzero), (PS_vdd0)>;
179  def: Pat<(VecPI32 vzero), (PS_vdd0)>;
180
181  def: Pat<(concat_vectors  (VecI8 vzero),  (VecI8 vzero)), (PS_vdd0)>;
182  def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;
183  def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;
184
185  def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
186           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
187  def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
188           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
189  def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
190           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
191
192  def: Pat<(VecQ8  (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qt, $Qs)>;
193  def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qt, $Qs)>;
194
195  def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
196           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
197  def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
198           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
199  def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
200           (V6_extractw HvxVR:$Vu, I32:$Rs)>;
201
202  def: Pat<(HexagonVINSERTW0 HVI8:$Vu,  I32:$Rt),
203           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
204  def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
205           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
206  def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
207           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
208}
209
210def Vsplatib: OutPatFrag<(ops node:$V),  (V6_lvsplatw (ToI32 (SplatB $V)))>;
211def Vsplatih: OutPatFrag<(ops node:$V),  (V6_lvsplatw (ToI32 (SplatH $V)))>;
212def Vsplatiw: OutPatFrag<(ops node:$V),  (V6_lvsplatw (ToI32 $V))>;
213
214def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
215def Vsplatrh: OutPatFrag<(ops node:$Rs),
216                         (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
217def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
218
219def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>;
220
221let Predicates = [UseHVX] in {
222  let AddedComplexity = 10 in {
223    def: Pat<(VecI8   (HexagonVSPLAT u8_0ImmPred:$V)),  (Vsplatib $V)>;
224    def: Pat<(VecI16  (HexagonVSPLAT u16_0ImmPred:$V)), (Vsplatih $V)>;
225    def: Pat<(VecI32  (HexagonVSPLAT anyimm:$V)),       (Vsplatiw $V)>;
226    def: Pat<(VecPI8  (HexagonVSPLAT u8_0ImmPred:$V)),  (Rep (Vsplatib $V))>;
227    def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)), (Rep (Vsplatih $V))>;
228    def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)),       (Rep (Vsplatiw $V))>;
229  }
230  def: Pat<(VecI8   (HexagonVSPLAT I32:$Rs)), (Vsplatrb $Rs)>;
231  def: Pat<(VecI16  (HexagonVSPLAT I32:$Rs)), (Vsplatrh $Rs)>;
232  def: Pat<(VecI32  (HexagonVSPLAT I32:$Rs)), (Vsplatrw $Rs)>;
233  def: Pat<(VecPI8  (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrb $Rs))>;
234  def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrh $Rs))>;
235  def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrw $Rs))>;
236
237  def: Pat<(VecI8   (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
238  def: Pat<(VecI16  (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
239  def: Pat<(VecI32  (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
240  def: Pat<(VecPI8  (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
241  def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
242  def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
243}
244
245class Vneg1<ValueType VecTy>
246  : PatFrag<(ops), (VecTy (HexagonVSPLATW (i32 -1)))>;
247
248class Vnot<ValueType VecTy>
249  : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1<VecTy>)>;
250
251let Predicates = [UseHVX] in {
252  let AddedComplexity = 220 in {
253    defm: MinMax_pats<V6_vminb,  V6_vmaxb,  vselect,  setgt,  VecQ8,  HVI8>;
254    defm: MinMax_pats<V6_vminb,  V6_vmaxb,  vselect,  setge,  VecQ8,  HVI8>;
255    defm: MinMax_pats<V6_vminub, V6_vmaxub, vselect, setugt,  VecQ8,  HVI8>;
256    defm: MinMax_pats<V6_vminub, V6_vmaxub, vselect, setuge,  VecQ8,  HVI8>;
257    defm: MinMax_pats<V6_vminh,  V6_vmaxh,  vselect,  setgt, VecQ16, HVI16>;
258    defm: MinMax_pats<V6_vminh,  V6_vmaxh,  vselect,  setge, VecQ16, HVI16>;
259    defm: MinMax_pats<V6_vminuh, V6_vmaxuh, vselect, setugt, VecQ16, HVI16>;
260    defm: MinMax_pats<V6_vminuh, V6_vmaxuh, vselect, setuge, VecQ16, HVI16>;
261    defm: MinMax_pats<V6_vminw,  V6_vmaxw,  vselect,  setgt, VecQ32, HVI32>;
262    defm: MinMax_pats<V6_vminw,  V6_vmaxw,  vselect,  setge, VecQ32, HVI32>;
263  }
264}
265
266let Predicates = [UseHVX] in {
267  let AddedComplexity = 200 in {
268    def: Pat<(Vnot<VecI8>   HVI8:$Vs), (V6_vnot HvxVR:$Vs)>;
269    def: Pat<(Vnot<VecI16> HVI16:$Vs), (V6_vnot HvxVR:$Vs)>;
270    def: Pat<(Vnot<VecI32> HVI32:$Vs), (V6_vnot HvxVR:$Vs)>;
271  }
272
273  def: OpR_RR_pat<V6_vaddb,    Add,   VecI8,  HVI8>;
274  def: OpR_RR_pat<V6_vaddh,    Add,  VecI16, HVI16>;
275  def: OpR_RR_pat<V6_vaddw,    Add,  VecI32, HVI32>;
276  def: OpR_RR_pat<V6_vaddb_dv, Add,  VecPI8,  HWI8>;
277  def: OpR_RR_pat<V6_vaddh_dv, Add, VecPI16, HWI16>;
278  def: OpR_RR_pat<V6_vaddw_dv, Add, VecPI32, HWI32>;
279  def: OpR_RR_pat<V6_vsubb,    Sub,   VecI8,  HVI8>;
280  def: OpR_RR_pat<V6_vsubh,    Sub,  VecI16, HVI16>;
281  def: OpR_RR_pat<V6_vsubw,    Sub,  VecI32, HVI32>;
282  def: OpR_RR_pat<V6_vsubb_dv, Sub,  VecPI8,  HWI8>;
283  def: OpR_RR_pat<V6_vsubh_dv, Sub, VecPI16, HWI16>;
284  def: OpR_RR_pat<V6_vsubw_dv, Sub, VecPI32, HWI32>;
285  def: OpR_RR_pat<V6_vand,     And,   VecI8,  HVI8>;
286  def: OpR_RR_pat<V6_vand,     And,  VecI16, HVI16>;
287  def: OpR_RR_pat<V6_vand,     And,  VecI32, HVI32>;
288  def: OpR_RR_pat<V6_vor,       Or,   VecI8,  HVI8>;
289  def: OpR_RR_pat<V6_vor,       Or,  VecI16, HVI16>;
290  def: OpR_RR_pat<V6_vor,       Or,  VecI32, HVI32>;
291  def: OpR_RR_pat<V6_vxor,     Xor,   VecI8,  HVI8>;
292  def: OpR_RR_pat<V6_vxor,     Xor,  VecI16, HVI16>;
293  def: OpR_RR_pat<V6_vxor,     Xor,  VecI32, HVI32>;
294
295  def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
296           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
297  def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
298           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
299  def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
300           (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
301
302  def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
303           (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
304  def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
305           (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
306  def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
307           (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
308}
309
310let Predicates = [UseHVX] in {
311  def: Pat<(VecPI16 (sext HVI8:$Vs)),  (VSxtb $Vs)>;
312  def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
313  def: Pat<(VecPI16 (zext HVI8:$Vs)),  (VZxtb $Vs)>;
314  def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
315
316  def: Pat<(VecI16 (sext_invec HVI8:$Vs)),  (LoVec (VSxtb $Vs))>;
317  def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
318  def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
319           (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
320  def: Pat<(VecPI16 (sext_invec HWI8:$Vss)),  (VSxtb (LoVec $Vss))>;
321  def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;
322  def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),
323           (VSxth (LoVec (VSxtb (LoVec $Vss))))>;
324
325  def: Pat<(VecI16 (zext_invec HVI8:$Vs)),  (LoVec (VZxtb $Vs))>;
326  def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
327  def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
328           (LoVec (VZxth (LoVec (VZxtb $Vs))))>;
329  def: Pat<(VecPI16 (zext_invec HWI8:$Vss)),  (VZxtb (LoVec $Vss))>;
330  def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;
331  def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
332           (VZxth (LoVec (VZxtb (LoVec $Vss))))>;
333
334  def: Pat<(VecI8 (trunc HWI16:$Vss)),
335           (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
336  def: Pat<(VecI16 (trunc HWI32:$Vss)),
337           (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
338
339  def: Pat<(VecQ8 (trunc HVI8:$Vs)),
340           (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
341  def: Pat<(VecQ16 (trunc HVI16:$Vs)),
342           (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
343  def: Pat<(VecQ32 (trunc HVI32:$Vs)),
344           (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
345}
346
347let Predicates = [UseHVX] in {
348  // The "source" types are not legal, and there are no parameterized
349  // definitions for them, but they are length-specific.
350  let Predicates = [UseHVX,UseHVX64B] in {
351    def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
352             (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
353    def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
354             (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
355    def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
356             (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
357  }
358  let Predicates = [UseHVX,UseHVX128B] in {
359    def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
360             (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
361    def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
362             (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
363    def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
364             (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
365  }
366
367  def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
368           (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
369                       (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
370  def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
371           (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
372                       (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
373  def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
374           (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
375                       (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
376
377  def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
378  def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
379  def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
380  def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
381  def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
382  def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
383
384  def: Pat<(add HVI32:$Vx, (HexagonVASL HVI32:$Vu, I32:$Rt)),
385           (V6_vaslw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>;
386  def: Pat<(add HVI32:$Vx, (HexagonVASR HVI32:$Vu, I32:$Rt)),
387           (V6_vasrw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>;
388
389  def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
390  def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
391  def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
392  def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
393  def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
394  def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
395
396  def: Pat<(VecI16 (bswap HVI16:$Vs)),
397           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
398  def: Pat<(VecI32 (bswap HVI32:$Vs)),
399           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
400
401  def: Pat<(VecI8 (ctpop HVI8:$Vs)),
402           (V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))),
403                       (V6_vpopcounth (LoVec (V6_vunpackub HvxVR:$Vs))))>;
404  def: Pat<(VecI16 (ctpop HVI16:$Vs)), (V6_vpopcounth HvxVR:$Vs)>;
405  def: Pat<(VecI32 (ctpop HVI32:$Vs)),
406           (V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),
407                     (HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>;
408
409  def: Pat<(VecI8 (ctlz HVI8:$Vs)),
410           (V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
411                                 (V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
412                     (V6_lvsplatw (A2_tfrsi 0x08080808)))>;
413  def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;
414  def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>;
415}
416
417class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
418  : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
419        (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
420
421let Predicates = [UseHVX] in {
422  def: HvxSel_pat<PS_vselect, HVI8>;
423  def: HvxSel_pat<PS_vselect, HVI16>;
424  def: HvxSel_pat<PS_vselect, HVI32>;
425  def: HvxSel_pat<PS_wselect, HWI8>;
426  def: HvxSel_pat<PS_wselect, HWI16>;
427  def: HvxSel_pat<PS_wselect, HWI32>;
428}
429
430let Predicates = [UseHVX] in {
431  def: Pat<(VecQ8   (qtrue)), (PS_qtrue)>;
432  def: Pat<(VecQ16  (qtrue)), (PS_qtrue)>;
433  def: Pat<(VecQ32  (qtrue)), (PS_qtrue)>;
434  def: Pat<(VecQ8  (qfalse)), (PS_qfalse)>;
435  def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
436  def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
437
438  def: Pat<(vnot  HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
439  def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
440  def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
441  def: Pat<(qnot  HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
442  def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
443  def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
444
445  def: OpR_RR_pat<V6_pred_and,         And,  VecQ8,   HQ8>;
446  def: OpR_RR_pat<V6_pred_and,         And, VecQ16,  HQ16>;
447  def: OpR_RR_pat<V6_pred_and,         And, VecQ32,  HQ32>;
448  def: OpR_RR_pat<V6_pred_or,           Or,  VecQ8,   HQ8>;
449  def: OpR_RR_pat<V6_pred_or,           Or, VecQ16,  HQ16>;
450  def: OpR_RR_pat<V6_pred_or,           Or, VecQ32,  HQ32>;
451  def: OpR_RR_pat<V6_pred_xor,         Xor,  VecQ8,   HQ8>;
452  def: OpR_RR_pat<V6_pred_xor,         Xor, VecQ16,  HQ16>;
453  def: OpR_RR_pat<V6_pred_xor,         Xor, VecQ32,  HQ32>;
454
455  def: OpR_RR_pat<V6_pred_and_n, Not2<And>,  VecQ8,   HQ8>;
456  def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ16,  HQ16>;
457  def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ32,  HQ32>;
458  def: OpR_RR_pat<V6_pred_or_n,   Not2<Or>,  VecQ8,   HQ8>;
459  def: OpR_RR_pat<V6_pred_or_n,   Not2<Or>, VecQ16,  HQ16>;
460  def: OpR_RR_pat<V6_pred_or_n,   Not2<Or>, VecQ32,  HQ32>;
461
462  def: OpR_RR_pat<V6_veqb,              seteq,  VecQ8,  HVI8>;
463  def: OpR_RR_pat<V6_veqh,              seteq, VecQ16, HVI16>;
464  def: OpR_RR_pat<V6_veqw,              seteq, VecQ32, HVI32>;
465  def: OpR_RR_pat<V6_vgtb,              setgt,  VecQ8,  HVI8>;
466  def: OpR_RR_pat<V6_vgth,              setgt, VecQ16, HVI16>;
467  def: OpR_RR_pat<V6_vgtw,              setgt, VecQ32, HVI32>;
468  def: OpR_RR_pat<V6_vgtub,            setugt,  VecQ8,  HVI8>;
469  def: OpR_RR_pat<V6_vgtuh,            setugt, VecQ16, HVI16>;
470  def: OpR_RR_pat<V6_vgtuw,            setugt, VecQ32, HVI32>;
471
472  def: AccRRR_pat<V6_veqb_and,    And,  seteq,    HQ8,  HVI8,  HVI8>;
473  def: AccRRR_pat<V6_veqb_or,      Or,  seteq,    HQ8,  HVI8,  HVI8>;
474  def: AccRRR_pat<V6_veqb_xor,    Xor,  seteq,    HQ8,  HVI8,  HVI8>;
475  def: AccRRR_pat<V6_veqh_and,    And,  seteq,   HQ16, HVI16, HVI16>;
476  def: AccRRR_pat<V6_veqh_or,      Or,  seteq,   HQ16, HVI16, HVI16>;
477  def: AccRRR_pat<V6_veqh_xor,    Xor,  seteq,   HQ16, HVI16, HVI16>;
478  def: AccRRR_pat<V6_veqw_and,    And,  seteq,   HQ32, HVI32, HVI32>;
479  def: AccRRR_pat<V6_veqw_or,      Or,  seteq,   HQ32, HVI32, HVI32>;
480  def: AccRRR_pat<V6_veqw_xor,    Xor,  seteq,   HQ32, HVI32, HVI32>;
481
482  def: AccRRR_pat<V6_vgtb_and,    And,  setgt,    HQ8,  HVI8,  HVI8>;
483  def: AccRRR_pat<V6_vgtb_or,      Or,  setgt,    HQ8,  HVI8,  HVI8>;
484  def: AccRRR_pat<V6_vgtb_xor,    Xor,  setgt,    HQ8,  HVI8,  HVI8>;
485  def: AccRRR_pat<V6_vgth_and,    And,  setgt,   HQ16, HVI16, HVI16>;
486  def: AccRRR_pat<V6_vgth_or,      Or,  setgt,   HQ16, HVI16, HVI16>;
487  def: AccRRR_pat<V6_vgth_xor,    Xor,  setgt,   HQ16, HVI16, HVI16>;
488  def: AccRRR_pat<V6_vgtw_and,    And,  setgt,   HQ32, HVI32, HVI32>;
489  def: AccRRR_pat<V6_vgtw_or,      Or,  setgt,   HQ32, HVI32, HVI32>;
490  def: AccRRR_pat<V6_vgtw_xor,    Xor,  setgt,   HQ32, HVI32, HVI32>;
491
492  def: AccRRR_pat<V6_vgtub_and,   And, setugt,    HQ8,  HVI8,  HVI8>;
493  def: AccRRR_pat<V6_vgtub_or,     Or, setugt,    HQ8,  HVI8,  HVI8>;
494  def: AccRRR_pat<V6_vgtub_xor,   Xor, setugt,    HQ8,  HVI8,  HVI8>;
495  def: AccRRR_pat<V6_vgtuh_and,   And, setugt,   HQ16, HVI16, HVI16>;
496  def: AccRRR_pat<V6_vgtuh_or,     Or, setugt,   HQ16, HVI16, HVI16>;
497  def: AccRRR_pat<V6_vgtuh_xor,   Xor, setugt,   HQ16, HVI16, HVI16>;
498  def: AccRRR_pat<V6_vgtuw_and,   And, setugt,   HQ32, HVI32, HVI32>;
499  def: AccRRR_pat<V6_vgtuw_or,     Or, setugt,   HQ32, HVI32, HVI32>;
500  def: AccRRR_pat<V6_vgtuw_xor,   Xor, setugt,   HQ32, HVI32, HVI32>;
501}
502