1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 
12 #include "llvm/CodeGen/DFAPacketizer.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/CodeGen/ScheduleDAG.h"
15 #include <vector>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineBranchProbabilityInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineLoopInfo;
25 class TargetRegisterClass;
26 
27 class HexagonPacketizerList : public VLIWPacketizerList {
28   // Vector of instructions assigned to the packet that has just been created.
29   std::vector<MachineInstr *> OldPacketMIs;
30 
31   // Has the instruction been promoted to a dot-new instruction.
32   bool PromotedToDotNew;
33 
34   // Has the instruction been glued to allocframe.
35   bool GlueAllocframeStore;
36 
37   // Has the feeder instruction been glued to new value jump.
38   bool GlueToNewValueJump;
39 
40   // This holds the offset value, when pruning the dependences.
41   int64_t ChangedOffset;
42 
43   // Check if there is a dependence between some instruction already in this
44   // packet and this instruction.
45   bool Dependence;
46 
47   // Only check for dependence if there are resources available to
48   // schedule this instruction.
49   bool FoundSequentialDependence;
50 
51   bool MemShufDisabled = false;
52 
53   // Track MIs with ignored dependence.
54   std::vector<MachineInstr*> IgnoreDepMIs;
55 
56   // Set to true if the packet contains an instruction that stalls with an
57   // instruction from the previous packet.
58   bool PacketStalls = false;
59 
60   // Set to true if the packet has a duplex pair of sub-instructions.
61   bool PacketHasDuplex = false;
62 
63   // Set to true if the packet has a instruction that can only be executed
64   // in SLOT0.
65   bool PacketHasSLOT0OnlyInsn = false;
66 
67 protected:
68   /// A handle to the branch probability pass.
69   const MachineBranchProbabilityInfo *MBPI;
70   const MachineLoopInfo *MLI;
71 
72 private:
73   const HexagonInstrInfo *HII;
74   const HexagonRegisterInfo *HRI;
75   const bool Minimal;
76 
77 public:
78   HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
79                         AAResults *AA, const MachineBranchProbabilityInfo *MBPI,
80                         bool Minimal);
81 
82   // initPacketizerState - initialize some internal flags.
83   void initPacketizerState() override;
84 
85   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
86   bool ignorePseudoInstruction(const MachineInstr &MI,
87                                const MachineBasicBlock *MBB) override;
88 
89   // isSoloInstruction - return true if instruction MI can not be packetized
90   // with any other instruction, which means that MI itself is a packet.
91   bool isSoloInstruction(const MachineInstr &MI) override;
92 
93   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
94   // together.
95   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
96 
97   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
98   // and SUJ.
99   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
100 
101   bool foundLSInPacket();
102   MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
103   void endPacket(MachineBasicBlock *MBB,
104                  MachineBasicBlock::iterator MI) override;
105   bool shouldAddToPacket(const MachineInstr &MI) override;
106 
107   void unpacketizeSoloInstrs(MachineFunction &MF);
108 
109 protected:
110   bool getmemShufDisabled() {
111     return MemShufDisabled;
112   };
113   void setmemShufDisabled(bool val) {
114     MemShufDisabled = val;
115   };
116   bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
117                        unsigned DepReg);
118   bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
119                        MachineBasicBlock::iterator &MII,
120                        const TargetRegisterClass *RC);
121   bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
122                           unsigned DepReg, MachineBasicBlock::iterator &MII,
123                           const TargetRegisterClass *RC);
124   void cleanUpDotCur();
125 
126   bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
127                        MachineBasicBlock::iterator &MII,
128                        const TargetRegisterClass *RC);
129   bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
130                           unsigned DepReg, MachineBasicBlock::iterator &MII,
131                           const TargetRegisterClass *RC);
132   bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
133                             unsigned DepReg, MachineBasicBlock::iterator &MII);
134   bool canPromoteToNewValueStore(const MachineInstr &MI,
135                                  const MachineInstr &PacketMI, unsigned DepReg);
136   bool demoteToDotOld(MachineInstr &MI);
137   bool useCallersSP(MachineInstr &MI);
138   void useCalleesSP(MachineInstr &MI);
139   bool updateOffset(SUnit *SUI, SUnit *SUJ);
140   void undoChangedOffset(MachineInstr &MI);
141   bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
142   bool restrictingDepExistInPacket(MachineInstr&, unsigned);
143   bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
144   bool isCurifiable(MachineInstr &MI);
145   bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
146 
147   bool isPromotedToDotNew() const {
148     return PromotedToDotNew;
149   }
150 
151   bool tryAllocateResourcesForConstExt(bool Reserve);
152   bool canReserveResourcesForConstExt();
153   void reserveResourcesForConstExt();
154   bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
155   bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
156   bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
157   bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
158   bool producesStall(const MachineInstr &MI);
159   bool isPureSlot0InsnWithNoSlot1Store(const MachineInstr &MI);
160 };
161 
162 } // end namespace llvm
163 
164 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
165