1//===-- M68kInstrFormats.td - M68k Instruction Formats -----*- tablegen -*-===// 2// The LLVM Compiler Infrastructure 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6//===----------------------------------------------------------------------===// 7/// 8/// \file 9/// This file contains M68k instruction formats. 10/// 11/// Since M68k has quite a lot memory addressing modes there are more 12/// instruction prefixes than just i, r and m: 13/// TSF Since Form Letter Description 14/// 00 M68000 Dn or An r any register 15/// 01 M68000 Dn d data register direct 16/// 02 M68000 An a address register direct 17/// 03 M68000 (An) j address register indirect 18/// 04 M68000 (An)+ o address register indirect with postincrement 19/// 05 M68000 -(An) e address register indirect with predecrement 20/// 06 M68000 (i,An) p address register indirect with displacement 21/// 10 M68000 (i,An,Xn.L) f address register indirect with index and scale = 1 22/// 07 M68000 (i,An,Xn.W) F address register indirect with index and scale = 1 23/// 12 M68020 (i,An,Xn.L,SCALE) g address register indirect with index 24/// 11 M68020 (i,An,Xn.W,SCALE) G address register indirect with index 25/// 14 M68020 ([bd,An],Xn.L,SCALE,od) u memory indirect postindexed mode 26/// 13 M68020 ([bd,An],Xn.W,SCALE,od) U memory indirect postindexed mode 27/// 16 M68020 ([bd,An,Xn.L,SCALE],od) v memory indirect preindexed mode 28/// 15 M68020 ([bd,An,Xn.W,SCALE],od) V memory indirect preindexed mode 29/// 20 M68000 abs.L b absolute long address 30/// 17 M68000 abs.W B absolute short address 31/// 21 M68000 (i,PC) q program counter with displacement 32/// 23 M68000 (i,PC,Xn.L) k program counter with index and scale = 1 33/// 22 M68000 (i,PC,Xn.W) K program counter with index and scale = 1 34/// 25 M68020 (i,PC,Xn.L,SCALE) l program counter with index 35/// 24 M68020 (i,PC,Xn.W,SCALE) L program counter with index 36/// 27 M68020 ([bd,PC],Xn.L,SCALE,od) x program counter memory indirect postindexed mode 37/// 26 M68020 ([bd,PC],Xn.W,SCALE,od) X program counter memory indirect postindexed mode 38/// 31 M68020 ([bd,PC,Xn.L,SCALE],od) y program counter memory indirect preindexed mode 39/// 30 M68020 ([bd,PC,Xn.W,SCALE],od) Y program counter memory indirect preindexed mode 40/// 32 M68000 #immediate i immediate data 41/// 42/// NOTE that long form is always lowercase, word variants are capitalized 43/// 44/// Operand can be qualified with size where appropriate to force a particular 45/// instruction encoding, e.g.: 46/// (i8,An,Xn.W) f8 1 extension word 47/// (i16,An,Xn.W) f16 2 extension words 48/// (i32,An,Xn.W) f32 3 extension words 49/// 50/// Form without size qualifier will adapt to operand size automatically, e.g.: 51/// (i,An,Xn.W) f 1, 2 or 3 extension words 52/// 53/// Some forms already imply a particular size of their operands, e.g.: 54/// (i,An) p 1 extension word and i is 16bit 55/// 56/// Operand order follows x86 Intel order(destination before source), e.g.: 57/// MOV8df MOVE (4,A0,D0), D1 58/// 59/// Number after instruction mnemonics determines the size of the data 60/// 61//===----------------------------------------------------------------------===// 62 63/// ??? Is it possible to use this stuff for disassembling? 64/// NOTE 1: In case of conditional beads(DA, DAReg), cond part is able to 65/// consume any bit, though a more general instructions must be chosen, e.g. 66/// d -> r, a -> r 67 68//===----------------------------------------------------------------------===// 69// Encoding primitives 70//===----------------------------------------------------------------------===// 71 72class MxBead<bits<4> type, bit b4 = 0, bit b5 = 0, bit b6 = 0, bit b7 = 0> { 73 bits<8> Value = 0b00000000; 74 let Value{3-0} = type; 75 let Value{4} = b4; 76 let Value{5} = b5; 77 let Value{6} = b6; 78 let Value{7} = b7; 79} 80 81/// System beads, allow to control beading flow 82def MxBeadTerm : MxBead<0x0, 0, 0, 0, 0>; 83def MxBeadIgnore : MxBead<0x0, 1, 0, 0, 0>; 84 85/// Add plain bit to the instruction 86class MxBead1Bit <bits<1> b> : MxBead<0x1, b>; 87class MxBead2Bits <bits<2> b> : MxBead<0x2, b{0}, b{1}>; 88class MxBead3Bits <bits<3> b> : MxBead<0x3, b{0}, b{1}, b{2}>; 89class MxBead4Bits <bits<4> b> : MxBead<0x4, b{0}, b{1}, b{2}, b{3}>; 90 91/// bits<3> o - operand number 92/// bit a - use alternative, used to select index register or 93/// outer displacement/immediate 94/// suffix NP means non-padded 95class MxBeadDAReg <bits<3> o, bit a = 0> : MxBead<0x5, o{0}, o{1}, o{2}, a>; 96class MxBeadDA <bits<3> o, bit a = 0> : MxBead<0x6, o{0}, o{1}, o{2}, a>; 97class MxBeadReg <bits<3> o, bit a = 0> : MxBead<0x7, o{0}, o{1}, o{2}, a>; 98class MxBeadDReg <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>; 99class MxBead8Disp <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>; 100 101/// Add Immediate to the instruction. 8-bit version is padded with zeros to fit 102/// the word. 103class MxBead8Imm <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>; 104class MxBead16Imm <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>; 105class MxBead32Imm <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>; 106 107/// Encodes an immediate 0-7(alt. 1-8) into 3 bit field 108class MxBead3Imm <bits<3> o, bit a = 0> : MxBead<0xD, o{0}, o{1}, o{2}, a>; 109 110 111class MxEncoding<MxBead n0 = MxBeadTerm, MxBead n1 = MxBeadTerm, 112 MxBead n2 = MxBeadTerm, MxBead n3 = MxBeadTerm, 113 MxBead n4 = MxBeadTerm, MxBead n5 = MxBeadTerm, 114 MxBead n6 = MxBeadTerm, MxBead n7 = MxBeadTerm, 115 MxBead n8 = MxBeadTerm, MxBead n9 = MxBeadTerm, 116 MxBead n10 = MxBeadTerm, MxBead n11 = MxBeadTerm, 117 MxBead n12 = MxBeadTerm, MxBead n13 = MxBeadTerm, 118 MxBead n14 = MxBeadTerm, MxBead n15 = MxBeadTerm, 119 MxBead n16 = MxBeadTerm, MxBead n17 = MxBeadTerm, 120 MxBead n18 = MxBeadTerm, MxBead n19 = MxBeadTerm, 121 MxBead n20 = MxBeadTerm, MxBead n21 = MxBeadTerm, 122 MxBead n22 = MxBeadTerm, MxBead n23 = MxBeadTerm> { 123 bits <192> Value; 124 let Value{7-0} = n0.Value; 125 let Value{15-8} = n1.Value; 126 let Value{23-16} = n2.Value; 127 let Value{31-24} = n3.Value; 128 let Value{39-32} = n4.Value; 129 let Value{47-40} = n5.Value; 130 let Value{55-48} = n6.Value; 131 let Value{63-56} = n7.Value; 132 let Value{71-64} = n8.Value; 133 let Value{79-72} = n9.Value; 134 let Value{87-80} = n10.Value; 135 let Value{95-88} = n11.Value; 136 let Value{103-96} = n12.Value; 137 let Value{111-104} = n13.Value; 138 let Value{119-112} = n14.Value; 139 let Value{127-120} = n15.Value; 140 let Value{135-128} = n16.Value; 141 let Value{143-136} = n17.Value; 142 let Value{151-144} = n18.Value; 143 let Value{159-152} = n19.Value; 144 let Value{167-160} = n20.Value; 145 let Value{175-168} = n21.Value; 146 let Value{183-176} = n22.Value; 147 let Value{191-184} = n23.Value; 148} 149 150class MxEncFixed<bits<16> value> : MxEncoding { 151 let Value{7-0} = MxBead4Bits<value{3-0}>.Value; 152 let Value{15-8} = MxBead4Bits<value{7-4}>.Value; 153 let Value{23-16} = MxBead4Bits<value{11-8}>.Value; 154 let Value{31-24} = MxBead4Bits<value{15-12}>.Value; 155} 156 157//===----------------------------------------------------------------------===// 158// Encoding composites 159// 160// These must be lowered to MxEncoding by instr specific wrappers 161// 162// HERE BE DRAGONS... 163//===----------------------------------------------------------------------===// 164 165class MxEncByte<bits<8> value> : MxEncoding { 166 MxBead4Bits LO = MxBead4Bits<value{3-0}>; 167 MxBead4Bits HI = MxBead4Bits<value{7-4}>; 168} 169 170def MxEncEmpty : MxEncoding; 171 172 173/// M68k Standard Effective Address layout: 174/// 175/// :-------------------: 176/// | 5 4 3 | 2 1 0 | 177/// | mode | reg | 178/// :-------------------: 179/// 180/// If the EA is a direct register mode, bits 4 and 5 are 0, and the register 181/// number will be encoded in bit 0 - 3. Since the first address register's 182/// (A0) register number is 8, we can easily tell data registers from 183/// address registers by only inspecting bit 3 (i.e. if bit 3 is set, it's an 184/// address register). 185/// 186/// 187/// But MOVE instruction uses reversed layout for destination EA: 188/// 189/// :-------------------: 190/// | 5 4 3 | 2 1 0 | 191/// | reg | mode | 192/// :-------------------: 193/// 194/// And this complicates things a bit because the DA bit is now separated from 195/// the register and we have to encode those separately using MxBeadDA<opN> 196/// 197class MxEncEA<MxBead reg, MxBead mode, MxBead da = MxBeadIgnore> { 198 MxBead Reg = reg; 199 MxBead Mode = mode; 200 MxBead DA = da; 201} 202 203// FIXME: Is there a way to factorize the addressing mode suffix (i.e. 204// 'r', 'd', 'a' etc.) and use something like multiclass to replace? 205def MxEncEAr_0: MxEncEA<MxBeadDAReg<0>, MxBead2Bits<0b00>>; 206def MxEncEAd_0: MxEncEA<MxBeadDReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>; 207def MxEncEAa_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<1>>; 208def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>; 209def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>; 210def MxEncEAe_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<0>>; 211def MxEncEAp_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<1>>; 212def MxEncEAf_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b11>, MxBead1Bit<0>>; 213 214def MxEncEAa_0_reflected : MxEncEA<MxBeadReg<0>, MxBead3Bits<0b001>>; 215def MxEncEAr_0_reflected : MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBeadDA<0>>; 216 217def MxEncEAr_1: MxEncEA<MxBeadDAReg<1>, MxBead2Bits<0b00>>; 218def MxEncEAd_1: MxEncEA<MxBeadDReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>; 219def MxEncEAa_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<1>>; 220def MxEncEAj_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<0>>; 221def MxEncEAo_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<1>>; 222def MxEncEAe_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<0>>; 223def MxEncEAp_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<1>>; 224def MxEncEAf_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b11>, MxBead1Bit<0>>; 225 226def MxEncEAr_2: MxEncEA<MxBeadDAReg<2>, MxBead2Bits<0b00>>; 227def MxEncEAd_2: MxEncEA<MxBeadDReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>; 228def MxEncEAa_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<1>>; 229def MxEncEAj_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<0>>; 230def MxEncEAo_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<1>>; 231def MxEncEAe_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<0>>; 232def MxEncEAp_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<1>>; 233def MxEncEAf_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b11>, MxBead1Bit<0>>; 234 235def MxEncEAb : MxEncEA<MxBead3Bits<0b001>, MxBead2Bits<0b11>, MxBead1Bit<1>>; 236def MxEncEAq : MxEncEA<MxBead3Bits<0b010>, MxBead2Bits<0b11>, MxBead1Bit<1>>; 237def MxEncEAk : MxEncEA<MxBead3Bits<0b011>, MxBead2Bits<0b11>, MxBead1Bit<1>>; 238def MxEncEAi : MxEncEA<MxBead3Bits<0b100>, MxBead2Bits<0b11>, MxBead1Bit<1>>; 239 240// Allows you to specify each bit of opcode 241class MxEncOpMode<MxBead b0, MxBead b1 = MxBeadIgnore, MxBead b2 = MxBeadIgnore> { 242 MxBead B0 = b0; 243 MxBead B1 = b1; 244 MxBead B2 = b2; 245} 246 247// op EA, Dn 248def MxOpMode8dEA : MxEncOpMode<MxBead3Bits<0b000>>; 249def MxOpMode16dEA : MxEncOpMode<MxBead3Bits<0b001>>; 250def MxOpMode32dEA : MxEncOpMode<MxBead3Bits<0b010>>; 251 252// op EA, An 253def MxOpMode16aEA : MxEncOpMode<MxBead3Bits<0b011>>; 254def MxOpMode32aEA : MxEncOpMode<MxBead3Bits<0b111>>; 255 256// op EA, Rn 257// As you might noticed this guy is special... Since M68k differentiates 258// between Data and Address registers we required to use different OPMODE codes 259// for Address registers DST operands. One way of dealing with it is to use 260// separate tablegen instructions, but in this case it would force Register 261// Allocator to use specific Register Classes and eventually will lead to 262// superfluous moves. Another approach is to use reg-variadic encoding which will 263// change OPMODE base on Register Class used. Luckily, all the bits that differ go 264// from 0 to 1 and can be encoded with MxBeadDA. 265// Basically, if the register used is of Data type these encodings will be 266// the same as MxOpMode{16,32}dEA above and used with regular instructions(e.g. ADD, 267// SUB), but if the register is of Address type the appropriate bits will flip and 268// the instructions become of *A type(e.g ADDA, SUBA). 269def MxOpMode16rEA : MxEncOpMode<MxBead1Bit<1>, MxBeadDA<0>, MxBead1Bit<0>>; 270def MxOpMode32rEA : MxEncOpMode<MxBeadDA<0>, MxBead1Bit<1>, MxBeadDA<0>>; 271 272// op Dn, EA 273def MxOpMode8EAd : MxEncOpMode<MxBead3Bits<0b100>>; 274def MxOpMode16EAd : MxEncOpMode<MxBead3Bits<0b101>>; 275def MxOpMode32EAd : MxEncOpMode<MxBead3Bits<0b110>>; 276 277 278// Represents two types of extension word: 279// - Imm extension word 280// - Brief extension word 281class MxEncExt<MxBead imm = MxBeadIgnore, MxBead b8 = MxBeadIgnore, 282 MxBead scale = MxBeadIgnore, MxBead wl = MxBeadIgnore, 283 MxBead daReg = MxBeadIgnore> { 284 MxBead Imm = imm; 285 MxBead B8 = b8; 286 MxBead Scale = scale; 287 MxBead WL = wl; 288 MxBead DAReg = daReg; 289} 290 291def MxExtEmpty : MxEncExt; 292 293// These handle encoding of displacement fields, absolute addresses and 294// immediate values, since encoding for these categories is mainly the same, 295// with exception of some weird immediates. 296def MxExtI8_0 : MxEncExt<MxBead8Imm<0>>; 297def MxExtI16_0 : MxEncExt<MxBead16Imm<0>>; 298def MxExtI32_0 : MxEncExt<MxBead32Imm<0>>; 299 300def MxExtI8_1 : MxEncExt<MxBead8Imm<1>>; 301def MxExtI16_1 : MxEncExt<MxBead16Imm<1>>; 302def MxExtI32_1 : MxEncExt<MxBead32Imm<1>>; 303 304def MxExtI8_2 : MxEncExt<MxBead8Imm<2>>; 305def MxExtI16_2 : MxEncExt<MxBead16Imm<2>>; 306def MxExtI32_2 : MxEncExt<MxBead32Imm<2>>; 307 308// NOTE They are all using Long Xn 309def MxExtBrief_0 : MxEncExt<MxBead8Disp<0>, MxBead1Bit<0b0>, 310 MxBead2Bits<0b00>, MxBead1Bit<1>, 311 MxBeadDAReg<0, 1>>; 312 313def MxExtBrief_1 : MxEncExt<MxBead8Disp<1>, MxBead1Bit<0b0>, 314 MxBead2Bits<0b00>, MxBead1Bit<1>, 315 MxBeadDAReg<1, 1>>; 316 317def MxExtBrief_2 : MxEncExt<MxBead8Disp<2>, MxBead1Bit<0b0>, 318 MxBead2Bits<0b00>, MxBead1Bit<1>, 319 MxBeadDAReg<2, 1>>; 320 321def MxExtBrief_3 : MxEncExt<MxBead8Disp<3>, MxBead1Bit<0b0>, 322 MxBead2Bits<0b00>, MxBead1Bit<1>, 323 MxBeadDAReg<3, 1>>; 324 325def MxExtBrief_4 : MxEncExt<MxBead8Disp<4>, MxBead1Bit<0b0>, 326 MxBead2Bits<0b00>, MxBead1Bit<1>, 327 MxBeadDAReg<4, 1>>; 328 329class MxEncSize<bits<2> value> : MxBead2Bits<value>; 330def MxEncSize8 : MxEncSize<0b00>; 331def MxEncSize16 : MxEncSize<0b01>; 332def MxEncSize32 : MxEncSize<0b10>; 333def MxEncSize64 : MxEncSize<0b11>; 334 335// M68k INSTRUCTION. Most instructions specify the location of an operand by 336// using the effective address field in the operation word. The effective address 337// is composed of two 3-bit fields: the mode field and the register field. The 338// value in the mode field selects the different address modes. The register 339// field contains the number of a register. The effective address field may 340// require additional information to fully specify the operand. This additional 341// information, called the effective address extension, is contained in the 342// following word or words and is considered part of the instruction. The 343// effective address modes are grouped into three categories: register direct, 344// memory addressing, and special. 345class MxInst<dag outs, dag ins, 346 string asmStr = "", 347 list<dag> pattern = [], 348 MxEncoding beads = MxEncEmpty, 349 InstrItinClass itin = NoItinerary> 350 : Instruction { 351 let Namespace = "M68k"; 352 let OutOperandList = outs; 353 let InOperandList = ins; 354 let AsmString = asmStr; 355 let Pattern = pattern; 356 let Itinerary = itin; 357 358 // Byte stream 359 field bits<192> Beads = beads.Value; 360 361 // Number of bytes 362 let Size = 0; 363 364 let UseLogicalOperandMappings = 1; 365} 366 367// M68k PSEUDO INSTRUCTION 368class MxPseudo<dag outs, dag ins, list<dag> pattern = []> 369 : MxInst<outs, ins, "; error: this should not be emitted", pattern> { 370 let isPseudo = 1; 371} 372