1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This is the top level entry point for the Mips target. 9//===----------------------------------------------------------------------===// 10 11//===----------------------------------------------------------------------===// 12// Target-independent interfaces 13//===----------------------------------------------------------------------===// 14 15include "llvm/Target/Target.td" 16 17// The overall idea of the PredicateControl class is to chop the Predicates list 18// into subsets that are usually overridden independently. This allows 19// subclasses to partially override the predicates of their superclasses without 20// having to re-add all the existing predicates. 21class PredicateControl { 22 // Predicates for the encoding scheme in use such as HasStdEnc 23 list<Predicate> EncodingPredicates = []; 24 // Predicates for the GPR size such as IsGP64bit 25 list<Predicate> GPRPredicates = []; 26 // Predicates for the PTR size such as IsPTR64bit 27 list<Predicate> PTRPredicates = []; 28 // Predicates for the FGR size and layout such as IsFP64bit 29 list<Predicate> FGRPredicates = []; 30 // Predicates for the instruction group membership such as ISA's. 31 list<Predicate> InsnPredicates = []; 32 // Predicate for the ASE that an instruction belongs to. 33 list<Predicate> ASEPredicate = []; 34 // Predicate for marking the instruction as usable in hard-float mode only. 35 list<Predicate> HardFloatPredicate = []; 36 // Predicates for anything else 37 list<Predicate> AdditionalPredicates = []; 38 list<Predicate> Predicates = !listconcat(EncodingPredicates, 39 GPRPredicates, 40 PTRPredicates, 41 FGRPredicates, 42 InsnPredicates, 43 HardFloatPredicate, 44 ASEPredicate, 45 AdditionalPredicates); 46} 47 48// Like Requires<> but for the AdditionalPredicates list 49class AdditionalRequires<list<Predicate> preds> { 50 list<Predicate> AdditionalPredicates = preds; 51} 52 53//===----------------------------------------------------------------------===// 54// Register File, Calling Conv, Instruction Descriptions 55//===----------------------------------------------------------------------===// 56 57include "MipsRegisterInfo.td" 58include "MipsSchedule.td" 59include "MipsInstrInfo.td" 60include "MipsCallingConv.td" 61include "MipsRegisterBanks.td" 62 63// Avoid forward declaration issues. 64include "MipsScheduleP5600.td" 65include "MipsScheduleGeneric.td" 66 67def MipsInstrInfo : InstrInfo; 68 69//===----------------------------------------------------------------------===// 70// Mips Subtarget features // 71//===----------------------------------------------------------------------===// 72 73def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", 74 "Disable SVR4-style position-independent code">; 75def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true", 76 "Pointers are 64-bit wide">; 77def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 78 "General Purpose Registers are 64-bit wide">; 79def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 80 "Support 64-bit FP registers">; 81def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true", 82 "Support for FPXX">; 83def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true", 84 "IEEE 754-2008 NaN encoding">; 85def FeatureAbs2008 : SubtargetFeature<"abs2008", "Abs2008", "true", 86 "Disable IEEE 754-2008 abs.fmt mode">; 87def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 88 "true", "Only supports single precision float">; 89def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true", 90 "Does not support floating point instructions">; 91def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", 92 "Disable odd numbered single-precision " 93 "registers">; 94def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 95 "true", "Enable vector FPU instructions">; 96def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", 97 "Mips I ISA Support [highly experimental]">; 98def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", 99 "Mips II ISA Support [highly experimental]", 100 [FeatureMips1]>; 101def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true", 102 "Subset of MIPS-III that is also in MIPS32 " 103 "[highly experimental]">; 104def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true", 105 "Subset of MIPS-III that is also in MIPS32r2 " 106 "[highly experimental]">; 107def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3", 108 "MIPS III ISA Support [highly experimental]", 109 [FeatureMips2, FeatureMips3_32, 110 FeatureMips3_32r2, FeatureGP64Bit, 111 FeatureFP64Bit]>; 112def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true", 113 "Subset of MIPS-IV that is also in MIPS32 " 114 "[highly experimental]">; 115def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true", 116 "Subset of MIPS-IV that is also in MIPS32r2 " 117 "[highly experimental]">; 118def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", 119 "Mips4", "MIPS IV ISA Support", 120 [FeatureMips3, FeatureMips4_32, 121 FeatureMips4_32r2]>; 122def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true", 123 "Subset of MIPS-V that is also in MIPS32r2 " 124 "[highly experimental]">; 125def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5", 126 "MIPS V ISA Support [highly experimental]", 127 [FeatureMips4, FeatureMips5_32r2]>; 128def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 129 "Mips32 ISA Support", 130 [FeatureMips2, FeatureMips3_32, 131 FeatureMips4_32]>; 132def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 133 "Mips32r2", "Mips32r2 ISA Support", 134 [FeatureMips3_32r2, FeatureMips4_32r2, 135 FeatureMips5_32r2, FeatureMips32]>; 136def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion", 137 "Mips32r3", "Mips32r3 ISA Support", 138 [FeatureMips32r2]>; 139def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion", 140 "Mips32r5", "Mips32r5 ISA Support", 141 [FeatureMips32r3]>; 142def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", 143 "Mips32r6", 144 "Mips32r6 ISA Support [experimental]", 145 [FeatureMips32r5, FeatureFP64Bit, 146 FeatureNaN2008, FeatureAbs2008]>; 147def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 148 "Mips64", "Mips64 ISA Support", 149 [FeatureMips5, FeatureMips32]>; 150def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 151 "Mips64r2", "Mips64r2 ISA Support", 152 [FeatureMips64, FeatureMips32r2]>; 153def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion", 154 "Mips64r3", "Mips64r3 ISA Support", 155 [FeatureMips64r2, FeatureMips32r3]>; 156def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion", 157 "Mips64r5", "Mips64r5 ISA Support", 158 [FeatureMips64r3, FeatureMips32r5]>; 159def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion", 160 "Mips64r6", 161 "Mips64r6 ISA Support [experimental]", 162 [FeatureMips32r6, FeatureMips64r5, 163 FeatureNaN2008, FeatureAbs2008]>; 164def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true", 165 "Symbols are 32 bit on Mips64">; 166 167def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 168 "Mips16 mode">; 169 170def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 171def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 172 "Mips DSP-R2 ASE", [FeatureDSP]>; 173def FeatureDSPR3 174 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE", 175 [ FeatureDSP, FeatureDSPR2 ]>; 176 177def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 178 179def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; 180 181def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">; 182 183def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true", 184 "Mips Virtualization ASE">; 185 186def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true", 187 "Mips Global Invalidate ASE">; 188 189def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 190 "microMips mode">; 191 192def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips", 193 "true", "Octeon cnMIPS Support", 194 [FeatureMips64r2]>; 195 196def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP", 197 "true", "Octeon+ cnMIPS Support", 198 [FeatureCnMips]>; 199 200def FeatureUseTCCInDIV : SubtargetFeature< 201 "use-tcc-in-div", 202 "UseTCCInDIV", "false", 203 "Force the assembler to use trapping">; 204 205def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true", 206 "Disable 4-operand madd.fmt and related instructions">; 207 208def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">; 209 210def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true", 211 "Disable use of the jal instruction">; 212 213def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", 214 "UseIndirectJumpsHazard", 215 "true", "Use indirect jump" 216 " guards to prevent certain speculation based attacks">; 217//===----------------------------------------------------------------------===// 218// Mips processors supported. 219//===----------------------------------------------------------------------===// 220 221def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", 222 "MipsSubtarget::CPU::P5600", 223 "The P5600 Processor", [FeatureMips32r5]>; 224 225class Proc<string Name, list<SubtargetFeature> Features> 226 : ProcessorModel<Name, MipsGenericModel, Features>; 227 228def : Proc<"mips1", [FeatureMips1]>; 229def : Proc<"mips2", [FeatureMips2]>; 230def : Proc<"mips32", [FeatureMips32]>; 231def : Proc<"mips32r2", [FeatureMips32r2]>; 232def : Proc<"mips32r3", [FeatureMips32r3]>; 233def : Proc<"mips32r5", [FeatureMips32r5]>; 234def : Proc<"mips32r6", [FeatureMips32r6]>; 235 236def : Proc<"mips3", [FeatureMips3]>; 237def : Proc<"mips4", [FeatureMips4]>; 238def : Proc<"mips5", [FeatureMips5]>; 239def : Proc<"mips64", [FeatureMips64]>; 240def : Proc<"mips64r2", [FeatureMips64r2]>; 241def : Proc<"mips64r3", [FeatureMips64r3]>; 242def : Proc<"mips64r5", [FeatureMips64r5]>; 243def : Proc<"mips64r6", [FeatureMips64r6]>; 244def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>; 245def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>; 246def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>; 247 248def MipsAsmParser : AsmParser { 249 let ShouldEmitMatchRegisterName = 0; 250} 251 252def MipsAsmParserVariant : AsmParserVariant { 253 int Variant = 0; 254 255 // Recognize hard coded registers. 256 string RegisterPrefix = "$"; 257} 258 259def Mips : Target { 260 let InstructionSet = MipsInstrInfo; 261 let AssemblyParsers = [MipsAsmParser]; 262 let AssemblyParserVariants = [MipsAsmParserVariant]; 263 let AllowRegisterRenaming = 1; 264} 265