1 //===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips16 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
14 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
15 
16 #include "Mips16RegisterInfo.h"
17 #include "MipsInstrInfo.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Support/MathExtras.h"
20 #include <cstdint>
21 
22 namespace llvm {
23 
24 class MCInstrDesc;
25 class MipsSubtarget;
26 
27 class Mips16InstrInfo : public MipsInstrInfo {
28   const Mips16RegisterInfo RI;
29 
30 public:
31   explicit Mips16InstrInfo(const MipsSubtarget &STI);
32 
33   const MipsRegisterInfo &getRegisterInfo() const override;
34 
35   /// isLoadFromStackSlot - If the specified machine instruction is a direct
36   /// load from a stack slot, return the virtual or physical register number of
37   /// the destination along with the FrameIndex of the loaded stack slot.  If
38   /// not, return 0.  This predicate must return 0 if the instruction has
39   /// any side effects other than loading from the stack slot.
40   unsigned isLoadFromStackSlot(const MachineInstr &MI,
41                                int &FrameIndex) const override;
42 
43   /// isStoreToStackSlot - If the specified machine instruction is a direct
44   /// store to a stack slot, return the virtual or physical register number of
45   /// the source reg along with the FrameIndex of the loaded stack slot.  If
46   /// not, return 0.  This predicate must return 0 if the instruction has
47   /// any side effects other than storing to the stack slot.
48   unsigned isStoreToStackSlot(const MachineInstr &MI,
49                               int &FrameIndex) const override;
50 
51   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
52                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
53                    bool KillSrc) const override;
54 
55   void storeRegToStack(MachineBasicBlock &MBB,
56                        MachineBasicBlock::iterator MBBI,
57                        Register SrcReg, bool isKill, int FrameIndex,
58                        const TargetRegisterClass *RC,
59                        const TargetRegisterInfo *TRI,
60                        int64_t Offset) const override;
61 
62   void loadRegFromStack(MachineBasicBlock &MBB,
63                         MachineBasicBlock::iterator MBBI,
64                         Register DestReg, int FrameIndex,
65                         const TargetRegisterClass *RC,
66                         const TargetRegisterInfo *TRI,
67                         int64_t Offset) const override;
68 
69   bool expandPostRAPseudo(MachineInstr &MI) const override;
70 
71   unsigned getOppositeBranchOpc(unsigned Opc) const override;
72 
73   // Adjust SP by FrameSize bytes. Save RA, S0, S1
74   void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
75                  MachineBasicBlock::iterator I) const;
76 
77   // Adjust SP by FrameSize bytes. Restore RA, S0, S1
78   void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
79                       MachineBasicBlock::iterator I) const;
80 
81   /// Adjust SP by Amount bytes.
82   void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
83                       MachineBasicBlock::iterator I) const override;
84 
85   /// Emit a series of instructions to load an immediate.
86   // This is to adjust some FrameReg. We return the new register to be used
87   // in place of FrameReg and the adjusted immediate field (&NewImm)
88   unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
89                          MachineBasicBlock::iterator II, const DebugLoc &DL,
90                          unsigned &NewImm) const;
91 
92   static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
93 
94   static bool validSpImm8(int offset) {
95     return ((offset & 7) == 0) && isInt<11>(offset);
96   }
97 
98   // build the proper one based on the Imm field
99 
100   const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
101 
102   void BuildAddiuSpImm
103     (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
104 
105 protected:
106   /// If the specific machine instruction is a instruction that moves/copies
107   /// value from one register to another register return destination and source
108   /// registers as machine operands.
109   Optional<DestSourcePair> isCopyInstrImpl(const MachineInstr &MI) const override;
110 
111 private:
112   unsigned getAnalyzableBrOpc(unsigned Opc) const override;
113 
114   void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115                    unsigned Opc) const;
116 
117   // Adjust SP by Amount bytes where bytes can be up to 32bit number.
118   void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
119                          MachineBasicBlock::iterator I,
120                          unsigned Reg1, unsigned Reg2) const;
121 
122   // Adjust SP by Amount bytes where bytes can be up to 32bit number.
123   void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
124                                      MachineBasicBlock &MBB,
125                                      MachineBasicBlock::iterator I) const;
126 };
127 
128 } // end namespace llvm
129 
130 #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
131